[linux-2.6-block.git] / drivers / staging / rtl8712 / rtl871x_mp.h

#ifndef __RTL871X_MP_H_
#define __RTL871X_MP_H_

/*	00 - Success */
/*	11 - Error */
#define STATUS_SUCCESS			(0x00000000L)
#define STATUS_PENDING			(0x00000103L)
#define STATUS_UNSUCCESSFUL		(0xC0000001L)
#define STATUS_INSUFFICIENT_RESOURCES	(0xC000009AL)
#define STATUS_NOT_SUPPORTED		(0xC00000BBL)
#define NDIS_STATUS_SUCCESS		((uint)STATUS_SUCCESS)
#define NDIS_STATUS_PENDING		((uint) STATUS_PENDING)
#define NDIS_STATUS_NOT_RECOGNIZED	((uint)0x00010001L)
#define NDIS_STATUS_NOT_COPIED		((uint)0x00010002L)
#define NDIS_STATUS_NOT_ACCEPTED	((uint)0x00010003L)
#define NDIS_STATUS_CALL_ACTIVE		((uint)0x00010007L)
#define NDIS_STATUS_FAILURE		((uint) STATUS_UNSUCCESSFUL)
#define NDIS_STATUS_RESOURCES		((uint)\
					STATUS_INSUFFICIENT_RESOURCES)
#define NDIS_STATUS_CLOSING		((uint)0xC0010002L)
#define NDIS_STATUS_BAD_VERSION		((uint)0xC0010004L)
#define NDIS_STATUS_BAD_CHARACTERISTICS	((uint)0xC0010005L)
#define NDIS_STATUS_ADAPTER_NOT_FOUND	((uint)0xC0010006L)
#define NDIS_STATUS_OPEN_FAILED		((uint)0xC0010007L)
#define NDIS_STATUS_DEVICE_FAILED	((uint)0xC0010008L)
#define NDIS_STATUS_MULTICAST_FULL	((uint)0xC0010009L)
#define NDIS_STATUS_MULTICAST_EXISTS	((uint)0xC001000AL)
#define NDIS_STATUS_MULTICAST_NOT_FOUND	((uint)0xC001000BL)
#define NDIS_STATUS_REQUEST_ABORTED	((uint)0xC001000CL)
#define NDIS_STATUS_RESET_IN_PROGRESS	((uint)0xC001000DL)
#define NDIS_STATUS_CLOSING_INDICATING	((uint)0xC001000EL)
#define NDIS_STATUS_NOT_SUPPORTED	((uint)STATUS_NOT_SUPPORTED)
#define NDIS_STATUS_INVALID_PACKET	((uint)0xC001000FL)
#define NDIS_STATUS_OPEN_LIST_FULL	((uint)0xC0010010L)
#define NDIS_STATUS_ADAPTER_NOT_READY	((uint)0xC0010011L)
#define NDIS_STATUS_ADAPTER_NOT_OPEN	((uint)0xC0010012L)
#define NDIS_STATUS_NOT_INDICATING	((uint)0xC0010013L)
#define NDIS_STATUS_INVALID_LENGTH	((uint)0xC0010014L)
#define NDIS_STATUS_INVALID_DATA	((uint)0xC0010015L)
#define NDIS_STATUS_BUFFER_TOO_SHORT	((uint)0xC0010016L)
#define NDIS_STATUS_INVALID_OID		((uint)0xC0010017L)
#define NDIS_STATUS_ADAPTER_REMOVED	((uint)0xC0010018L)
#define NDIS_STATUS_UNSUPPORTED_MEDIA	((uint)0xC0010019L)
#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((uint)0xC001001AL)
#define NDIS_STATUS_FILE_NOT_FOUND	((uint)0xC001001BL)
#define NDIS_STATUS_ERROR_READING_FILE	((uint)0xC001001CL)
#define NDIS_STATUS_ALREADY_MAPPED	((uint)0xC001001DL)
#define NDIS_STATUS_RESOURCE_CONFLICT	((uint)0xC001001EL)
#define NDIS_STATUS_NO_CABLE		((uint)0xC001001FL)
#define NDIS_STATUS_INVALID_SAP		((uint)0xC0010020L)
#define NDIS_STATUS_SAP_IN_USE		((uint)0xC0010021L)
#define NDIS_STATUS_INVALID_ADDRESS	((uint)0xC0010022L)
#define NDIS_STATUS_VC_NOT_ACTIVATED	((uint)0xC0010023L)
#define NDIS_STATUS_DEST_OUT_OF_ORDER	((uint)0xC0010024L) /* cause 27*/
#define NDIS_STATUS_VC_NOT_AVAILABLE	((uint)0xC0010025L) /* 35,45*/
#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((uint)0xC0010026L) /* 37*/
#define NDIS_STATUS_INCOMPATABLE_QOS	((uint)0xC0010027L)  /* 49*/
#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((uint)0xC0010028L)  /*  93*/
#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((uint)0xC0010029L)  /*  3*/
#define MPT_NOOP			0
#define MPT_READ_MAC_1BYTE		1
#define MPT_READ_MAC_2BYTE		2
#define MPT_READ_MAC_4BYTE		3
#define MPT_WRITE_MAC_1BYTE		4
#define MPT_WRITE_MAC_2BYTE		5
#define MPT_WRITE_MAC_4BYTE		6
#define MPT_READ_BB_CCK			7
#define MPT_WRITE_BB_CCK		8
#define MPT_READ_BB_OFDM		9
#define MPT_WRITE_BB_OFDM		10
#define MPT_READ_RF			11
#define MPT_WRITE_RF			12
#define MPT_READ_EEPROM_1BYTE		13
#define MPT_WRITE_EEPROM_1BYTE		14
#define MPT_READ_EEPROM_2BYTE		15
#define MPT_WRITE_EEPROM_2BYTE		16
#define MPT_SET_CSTHRESHOLD		21
#define MPT_SET_INITGAIN		22
#define MPT_SWITCH_BAND			23
#define MPT_SWITCH_CHANNEL		24
#define MPT_SET_DATARATE		25
#define MPT_SWITCH_ANTENNA		26
#define MPT_SET_TX_POWER		27
#define MPT_SET_CONT_TX			28
#define MPT_SET_SINGLE_CARRIER		29
#define MPT_SET_CARRIER_SUPPRESSION	30
#define MPT_GET_RATE_TABLE		31
#define MPT_READ_TSSI			32
#define MPT_GET_THERMAL_METER		33
#define MAX_MP_XMITBUF_SZ	2048
#define NR_MP_XMITFRAME		8

struct mp_xmit_frame {
	struct list_head list;
	struct pkt_attrib attrib;
	_pkt *pkt;
	int frame_tag;
	struct _adapter *padapter;
	u8 *mem_addr;
	u16 sz[8];
	struct urb *pxmit_urb[8];
	u8 bpending[8];
	u8 last[8];
	uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
};

struct mp_wiparam {
	u32 bcompleted;
	u32 act_type;
	u32 io_offset;
	u32 io_value;
};

struct mp_priv {
	struct _adapter *papdater;
	/*OID cmd handler*/
	struct mp_wiparam workparam;
	u8 act_in_progress;
	/*Tx Section*/
	u8 TID;
	u32 tx_pktcount;
	/*Rx Section*/
	u32 rx_pktcount;
	u32 rx_crcerrpktcount;
	u32 rx_pktloss;
	struct recv_stat rxstat;
	/*RF/BB relative*/
	u32 curr_ch;
	u32 curr_rateidx;
	u8 curr_bandwidth;
	u8 curr_modem;
	u8 curr_txpoweridx;
	u32 curr_crystalcap;
	u16 antenna_tx;
	u16 antenna_rx;
	u8 curr_rfpath;
	u8 check_mp_pkt;
	uint ForcedDataRate;
	struct wlan_network mp_network;
	unsigned char network_macaddr[6];
	/*Testing Flag*/
	u32 mode;/*0 for normal type packet,
		  * 1 for loopback packet (16bytes TXCMD)*/
	sint prev_fw_state;
	u8 *pallocated_mp_xmitframe_buf;
	u8 *pmp_xmtframe_buf;
	struct  __queue free_mp_xmitqueue;
	u32 free_mp_xmitframe_cnt;
};

struct IOCMD_STRUCT {
	u8	cmdclass;
	u16	value;
	u8	index;
};

struct rf_reg_param {
	u32 path;
	u32 offset;
	u32 value;
};

struct bb_reg_param {
	u32 offset;
	u32 value;
};
/* ======================================================================= */

#define LOWER	true
#define RAISE	false
#define IOCMD_CTRL_REG			0x10250370
#define IOCMD_DATA_REG			0x10250374
#define IOCMD_GET_THERMAL_METER		0xFD000028
#define IOCMD_CLASS_BB_RF		0xF0
#define IOCMD_BB_READ_IDX		0x00
#define IOCMD_BB_WRITE_IDX		0x01
#define IOCMD_RF_READ_IDX		0x02
#define IOCMD_RF_WRIT_IDX		0x03
#define BB_REG_BASE_ADDR		0x800
#define RF_PATH_A	0
#define RF_PATH_B	1
#define RF_PATH_C	2
#define RF_PATH_D	3
#define MAX_RF_PATH_NUMS	2
#define _2MAC_MODE_	0
#define _LOOPBOOK_MODE_	1

/* MP set force data rate base on the definition. */
enum {
	/* CCK rate. */
	MPT_RATE_1M,	/* 0 */
	MPT_RATE_2M,
	MPT_RATE_55M,
	MPT_RATE_11M,	/* 3 */

	/* OFDM rate. */
	MPT_RATE_6M,	/* 4 */
	MPT_RATE_9M,
	MPT_RATE_12M,
	MPT_RATE_18M,
	MPT_RATE_24M,
	MPT_RATE_36M,
	MPT_RATE_48M,
	MPT_RATE_54M,	/* 11 */

	/* HT rate. */
	MPT_RATE_MCS0,	/* 12 */
	MPT_RATE_MCS1,
	MPT_RATE_MCS2,
	MPT_RATE_MCS3,
	MPT_RATE_MCS4,
	MPT_RATE_MCS5,
	MPT_RATE_MCS6,
	MPT_RATE_MCS7,	/* 19 */
	MPT_RATE_MCS8,
	MPT_RATE_MCS9,
	MPT_RATE_MCS10,
	MPT_RATE_MCS11,
	MPT_RATE_MCS12,
	MPT_RATE_MCS13,
	MPT_RATE_MCS14,
	MPT_RATE_MCS15,	/* 27 */
	MPT_RATE_LAST
};

/* Represent Channel Width in HT Capabilities */
enum HT_CHANNEL_WIDTH {
	HT_CHANNEL_WIDTH_20 = 0,
	HT_CHANNEL_WIDTH_40 = 1,
};

#define MAX_TX_PWR_INDEX_N_MODE 64	/* 0x3F */

enum POWER_MODE {
	POWER_LOW = 0,
	POWER_NORMAL
};

#define RX_PKT_BROADCAST	1
#define RX_PKT_DEST_ADDR	2
#define RX_PKT_PHY_MATCH	3

#define RPTMaxCount 0x000FFFFF;

/* parameter 1 : BitMask
 *	bit 0  : OFDM PPDU
 *	bit 1  : OFDM False Alarm
 *	bit 2  : OFDM MPDU OK
 *	bit 3  : OFDM MPDU Fail
 *	bit 4  : CCK PPDU
 *	bit 5  : CCK False Alarm
 *	bit 6  : CCK MPDU ok
 *	bit 7  : CCK MPDU fail
 *	bit 8  : HT PPDU counter
 *	bit 9  : HT false alarm
 *	bit 10 : HT MPDU total
 *	bit 11 : HT MPDU OK
 *	bit 12 : HT MPDU fail
 *	bit 15 : RX full drop
 */
enum RXPHY_BITMASK {
	OFDM_PPDU_BIT = 0,
	OFDM_MPDU_OK_BIT,
	OFDM_MPDU_FAIL_BIT,
	CCK_PPDU_BIT,
	CCK_MPDU_OK_BIT,
	CCK_MPDU_FAIL_BIT,
	HT_PPDU_BIT,
	HT_MPDU_BIT,
	HT_MPDU_OK_BIT,
	HT_MPDU_FAIL_BIT,
};

enum ENCRY_CTRL_STATE {
	HW_CONTROL,		/*hw encryption& decryption*/
	SW_CONTROL,		/*sw encryption& decryption*/
	HW_ENCRY_SW_DECRY,	/*hw encryption & sw decryption*/
	SW_ENCRY_HW_DECRY	/*sw encryption & hw decryption*/
};

/* Bandwidth Offset */
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE	0
#define HAL_PRIME_CHNL_OFFSET_LOWER	1
#define HAL_PRIME_CHNL_OFFSET_UPPER	2
/*=======================================================================*/
void mp871xinit(struct _adapter *padapter);
void mp871xdeinit(struct _adapter *padapter);
u32 r8712_bb_reg_read(struct _adapter *Adapter, u16 offset);
u8 r8712_bb_reg_write(struct _adapter *Adapter, u16 offset, u32 value);
u32 r8712_rf_reg_read(struct _adapter *Adapter, u8 path, u8 offset);
u8 r8712_rf_reg_write(struct _adapter *Adapter, u8 path,
		      u8 offset, u32 value);
u32 r8712_get_bb_reg(struct _adapter *Adapter, u16 offset, u32 bitmask);
u8 r8712_set_bb_reg(struct _adapter *Adapter, u16 offset,
		    u32 bitmask, u32 value);
u32 r8712_get_rf_reg(struct _adapter *Adapter, u8 path, u8 offset,
		     u32 bitmask);
u8 r8712_set_rf_reg(struct _adapter *Adapter, u8 path, u8 offset,
		    u32 bitmask, u32 value);

void r8712_SetChannel(struct _adapter *pAdapter);
void r8712_SetTxPower(struct _adapter *pAdapte);
void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset);
void r8712_SetDataRate(struct _adapter *pAdapter);
void r8712_SwitchBandwidth(struct _adapter *pAdapter);
void r8712_SwitchAntenna(struct _adapter *pAdapter);
void r8712_SetCrystalCap(struct _adapter *pAdapter);
void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value);
void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart);
void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart);
void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart);
void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart);
void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter);
u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter);
u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter);

#endif /*__RTL871X_MP_H_*/
Commit	Line	Data
2865d42c LF	1	#ifndef __RTL871X_MP_H_
	2	#define __RTL871X_MP_H_
	3
	4	/* 00 - Success */
	5	/* 11 - Error */
	6	#define STATUS_SUCCESS (0x00000000L)
	7	#define STATUS_PENDING (0x00000103L)
	8	#define STATUS_UNSUCCESSFUL (0xC0000001L)
	9	#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL)
	10	#define STATUS_NOT_SUPPORTED (0xC00000BBL)
	11	#define NDIS_STATUS_SUCCESS ((uint)STATUS_SUCCESS)
	12	#define NDIS_STATUS_PENDING ((uint) STATUS_PENDING)
	13	#define NDIS_STATUS_NOT_RECOGNIZED ((uint)0x00010001L)
	14	#define NDIS_STATUS_NOT_COPIED ((uint)0x00010002L)
	15	#define NDIS_STATUS_NOT_ACCEPTED ((uint)0x00010003L)
	16	#define NDIS_STATUS_CALL_ACTIVE ((uint)0x00010007L)
	17	#define NDIS_STATUS_FAILURE ((uint) STATUS_UNSUCCESSFUL)
	18	#define NDIS_STATUS_RESOURCES ((uint)\
	19	STATUS_INSUFFICIENT_RESOURCES)
	20	#define NDIS_STATUS_CLOSING ((uint)0xC0010002L)
	21	#define NDIS_STATUS_BAD_VERSION ((uint)0xC0010004L)
	22	#define NDIS_STATUS_BAD_CHARACTERISTICS ((uint)0xC0010005L)
	23	#define NDIS_STATUS_ADAPTER_NOT_FOUND ((uint)0xC0010006L)
	24	#define NDIS_STATUS_OPEN_FAILED ((uint)0xC0010007L)
	25	#define NDIS_STATUS_DEVICE_FAILED ((uint)0xC0010008L)
	26	#define NDIS_STATUS_MULTICAST_FULL ((uint)0xC0010009L)
	27	#define NDIS_STATUS_MULTICAST_EXISTS ((uint)0xC001000AL)
	28	#define NDIS_STATUS_MULTICAST_NOT_FOUND ((uint)0xC001000BL)
	29	#define NDIS_STATUS_REQUEST_ABORTED ((uint)0xC001000CL)
	30	#define NDIS_STATUS_RESET_IN_PROGRESS ((uint)0xC001000DL)
	31	#define NDIS_STATUS_CLOSING_INDICATING ((uint)0xC001000EL)
	32	#define NDIS_STATUS_NOT_SUPPORTED ((uint)STATUS_NOT_SUPPORTED)
	33	#define NDIS_STATUS_INVALID_PACKET ((uint)0xC001000FL)
	34	#define NDIS_STATUS_OPEN_LIST_FULL ((uint)0xC0010010L)
	35	#define NDIS_STATUS_ADAPTER_NOT_READY ((uint)0xC0010011L)
	36	#define NDIS_STATUS_ADAPTER_NOT_OPEN ((uint)0xC0010012L)
	37	#define NDIS_STATUS_NOT_INDICATING ((uint)0xC0010013L)
	38	#define NDIS_STATUS_INVALID_LENGTH ((uint)0xC0010014L)
	39	#define NDIS_STATUS_INVALID_DATA ((uint)0xC0010015L)
	40	#define NDIS_STATUS_BUFFER_TOO_SHORT ((uint)0xC0010016L)
	41	#define NDIS_STATUS_INVALID_OID ((uint)0xC0010017L)
	42	#define NDIS_STATUS_ADAPTER_REMOVED ((uint)0xC0010018L)
	43	#define NDIS_STATUS_UNSUPPORTED_MEDIA ((uint)0xC0010019L)
	44	#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((uint)0xC001001AL)
	45	#define NDIS_STATUS_FILE_NOT_FOUND ((uint)0xC001001BL)
	46	#define NDIS_STATUS_ERROR_READING_FILE ((uint)0xC001001CL)
	47	#define NDIS_STATUS_ALREADY_MAPPED ((uint)0xC001001DL)
	48	#define NDIS_STATUS_RESOURCE_CONFLICT ((uint)0xC001001EL)
	49	#define NDIS_STATUS_NO_CABLE ((uint)0xC001001FL)
	50	#define NDIS_STATUS_INVALID_SAP ((uint)0xC0010020L)
	51	#define NDIS_STATUS_SAP_IN_USE ((uint)0xC0010021L)
	52	#define NDIS_STATUS_INVALID_ADDRESS ((uint)0xC0010022L)
	53	#define NDIS_STATUS_VC_NOT_ACTIVATED ((uint)0xC0010023L)
	54	#define NDIS_STATUS_DEST_OUT_OF_ORDER ((uint)0xC0010024L) /* cause 27*/
	55	#define NDIS_STATUS_VC_NOT_AVAILABLE ((uint)0xC0010025L) /* 35,45*/
	56	#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((uint)0xC0010026L) /* 37*/
	57	#define NDIS_STATUS_INCOMPATABLE_QOS ((uint)0xC0010027L) /* 49*/
	58	#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((uint)0xC0010028L) /* 93*/
	59	#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((uint)0xC0010029L) /* 3*/
	60	#define MPT_NOOP 0
	61	#define MPT_READ_MAC_1BYTE 1
	62	#define MPT_READ_MAC_2BYTE 2
	63	#define MPT_READ_MAC_4BYTE 3
	64	#define MPT_WRITE_MAC_1BYTE 4
65	#define MPT_WRITE_MAC_2BYTE 5
66	#define MPT_WRITE_MAC_4BYTE 6
67	#define MPT_READ_BB_CCK 7
68	#define MPT_WRITE_BB_CCK 8
69	#define MPT_READ_BB_OFDM 9
70	#define MPT_WRITE_BB_OFDM 10
71	#define MPT_READ_RF 11
72	#define MPT_WRITE_RF 12
73	#define MPT_READ_EEPROM_1BYTE 13
74	#define MPT_WRITE_EEPROM_1BYTE 14
75	#define MPT_READ_EEPROM_2BYTE 15
76	#define MPT_WRITE_EEPROM_2BYTE 16
77	#define MPT_SET_CSTHRESHOLD 21
78	#define MPT_SET_INITGAIN 22
79	#define MPT_SWITCH_BAND 23
80	#define MPT_SWITCH_CHANNEL 24
81	#define MPT_SET_DATARATE 25
82	#define MPT_SWITCH_ANTENNA 26
83	#define MPT_SET_TX_POWER 27
84	#define MPT_SET_CONT_TX 28
85	#define MPT_SET_SINGLE_CARRIER 29
86	#define MPT_SET_CARRIER_SUPPRESSION 30
87	#define MPT_GET_RATE_TABLE 31
88	#define MPT_READ_TSSI 32
89	#define MPT_GET_THERMAL_METER 33
90	#define MAX_MP_XMITBUF_SZ 2048
91	#define NR_MP_XMITFRAME 8
92
93	struct mp_xmit_frame {
94	struct list_head list;
95	struct pkt_attrib attrib;
96	_pkt *pkt;
97	int frame_tag;
98	struct _adapter *padapter;
99	u8 *mem_addr;
100	u16 sz[8];
101	struct urb *pxmit_urb[8];
102	u8 bpending[8];
103	u8 last[8];
104	uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
105	};
106
107	struct mp_wiparam {
108	u32 bcompleted;
109	u32 act_type;
110	u32 io_offset;
111	u32 io_value;
112	};
113
114	struct mp_priv {
115	struct _adapter *papdater;
116	/OID cmd handler/
117	struct mp_wiparam workparam;
118	u8 act_in_progress;
119	/Tx Section/
120	u8 TID;
121	u32 tx_pktcount;
122	/Rx Section/
123	u32 rx_pktcount;
124	u32 rx_crcerrpktcount;
125	u32 rx_pktloss;
126	struct recv_stat rxstat;
127	/RF/BB relative/
128	u32 curr_ch;
129	u32 curr_rateidx;
130	u8 curr_bandwidth;
131	u8 curr_modem;
132	u8 curr_txpoweridx;
133	u32 curr_crystalcap;
134	u16 antenna_tx;
135	u16 antenna_rx;
136	u8 curr_rfpath;
137	u8 check_mp_pkt;
138	uint ForcedDataRate;
139	struct wlan_network mp_network;
140	unsigned char network_macaddr[6];
141	/Testing Flag/
142	u32 mode;/*0 for normal type packet,
143	* 1 for loopback packet (16bytes TXCMD)*/
144	sint prev_fw_state;
145	u8 *pallocated_mp_xmitframe_buf;
146	u8 *pmp_xmtframe_buf;
147	struct __queue free_mp_xmitqueue;
148	u32 free_mp_xmitframe_cnt;
149	};
150
151	struct IOCMD_STRUCT {
152	u8 cmdclass;
153	u16 value;
154	u8 index;
155	};
156
157	struct rf_reg_param {
158	u32 path;
159	u32 offset;
160	u32 value;
161	};
162
163	struct bb_reg_param {
164	u32 offset;
165	u32 value;
166	};
167	/* ======================================================================= */
168
169	#define LOWER true
170	#define RAISE false
171	#define IOCMD_CTRL_REG 0x10250370
172	#define IOCMD_DATA_REG 0x10250374
173	#define IOCMD_GET_THERMAL_METER 0xFD000028
174	#define IOCMD_CLASS_BB_RF 0xF0
175	#define IOCMD_BB_READ_IDX 0x00
176	#define IOCMD_BB_WRITE_IDX 0x01
177	#define IOCMD_RF_READ_IDX 0x02
178	#define IOCMD_RF_WRIT_IDX 0x03
179	#define BB_REG_BASE_ADDR 0x800
180	#define RF_PATH_A 0
181	#define RF_PATH_B 1
182	#define RF_PATH_C 2
183	#define RF_PATH_D 3
184	#define MAX_RF_PATH_NUMS 2
185	#define _2MAC_MODE_ 0
186	#define _LOOPBOOK_MODE_ 1
187
188	/* MP set force data rate base on the definition. */
189	enum {
190	/* CCK rate. */
191	MPT_RATE_1M, /* 0 */
192	MPT_RATE_2M,
193	MPT_RATE_55M,
194	MPT_RATE_11M, /* 3 */
195
196	/* OFDM rate. */
197	MPT_RATE_6M, /* 4 */
198	MPT_RATE_9M,
199	MPT_RATE_12M,
200	MPT_RATE_18M,
201	MPT_RATE_24M,
202	MPT_RATE_36M,
203	MPT_RATE_48M,
204	MPT_RATE_54M, /* 11 */
205
206	/* HT rate. */
207	MPT_RATE_MCS0, /* 12 */
208	MPT_RATE_MCS1,
209	MPT_RATE_MCS2,
210	MPT_RATE_MCS3,
211	MPT_RATE_MCS4,
212	MPT_RATE_MCS5,
213	MPT_RATE_MCS6,
214	MPT_RATE_MCS7, /* 19 */
215	MPT_RATE_MCS8,
216	MPT_RATE_MCS9,
217	MPT_RATE_MCS10,
218	MPT_RATE_MCS11,
219	MPT_RATE_MCS12,
220	MPT_RATE_MCS13,
221	MPT_RATE_MCS14,
222	MPT_RATE_MCS15, /* 27 */
223	MPT_RATE_LAST
224	};
225
226	/* Represent Channel Width in HT Capabilities */
227	enum HT_CHANNEL_WIDTH {
228	HT_CHANNEL_WIDTH_20 = 0,
229	HT_CHANNEL_WIDTH_40 = 1,
230	};
231
232	#define MAX_TX_PWR_INDEX_N_MODE 64 /* 0x3F */
233
234	enum POWER_MODE {
235	POWER_LOW = 0,
236	POWER_NORMAL
237	};
238
239	#define RX_PKT_BROADCAST 1
240	#define RX_PKT_DEST_ADDR 2
241	#define RX_PKT_PHY_MATCH 3
242
243	#define RPTMaxCount 0x000FFFFF;
244
245	/* parameter 1 : BitMask
246	* bit 0 : OFDM PPDU
247	* bit 1 : OFDM False Alarm
248	* bit 2 : OFDM MPDU OK
249	* bit 3 : OFDM MPDU Fail
250	* bit 4 : CCK PPDU
251	* bit 5 : CCK False Alarm
252	* bit 6 : CCK MPDU ok
253	* bit 7 : CCK MPDU fail
254	* bit 8 : HT PPDU counter
255	* bit 9 : HT false alarm
256	* bit 10 : HT MPDU total
257	* bit 11 : HT MPDU OK
258	* bit 12 : HT MPDU fail
259	* bit 15 : RX full drop
260	*/
261	enum RXPHY_BITMASK {
262	OFDM_PPDU_BIT = 0,
263	OFDM_MPDU_OK_BIT,
264	OFDM_MPDU_FAIL_BIT,
265	CCK_PPDU_BIT,
266	CCK_MPDU_OK_BIT,
267	CCK_MPDU_FAIL_BIT,
268	HT_PPDU_BIT,
269	HT_MPDU_BIT,
270	HT_MPDU_OK_BIT,
271	HT_MPDU_FAIL_BIT,
272	};
273
274	enum ENCRY_CTRL_STATE {
275	HW_CONTROL, /hw encryption& decryption/
276	SW_CONTROL, /sw encryption& decryption/
277	HW_ENCRY_SW_DECRY, /hw encryption & sw decryption/
278	SW_ENCRY_HW_DECRY /sw encryption & hw decryption/
279	};
280
281	/* Bandwidth Offset */
282	#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
283	#define HAL_PRIME_CHNL_OFFSET_LOWER 1
284	#define HAL_PRIME_CHNL_OFFSET_UPPER 2
285	/=======================================================================/
286	void mp871xinit(struct _adapter *padapter);
287	void mp871xdeinit(struct _adapter *padapter);
288	u32 r8712_bb_reg_read(struct _adapter *Adapter, u16 offset);
289	u8 r8712_bb_reg_write(struct _adapter *Adapter, u16 offset, u32 value);
290	u32 r8712_rf_reg_read(struct _adapter *Adapter, u8 path, u8 offset);
291	u8 r8712_rf_reg_write(struct _adapter *Adapter, u8 path,
292	u8 offset, u32 value);
293	u32 r8712_get_bb_reg(struct _adapter *Adapter, u16 offset, u32 bitmask);
294	u8 r8712_set_bb_reg(struct _adapter *Adapter, u16 offset,
295	u32 bitmask, u32 value);
296	u32 r8712_get_rf_reg(struct _adapter *Adapter, u8 path, u8 offset,
297	u32 bitmask);
298	u8 r8712_set_rf_reg(struct _adapter *Adapter, u8 path, u8 offset,
299	u32 bitmask, u32 value);
300
301	void r8712_SetChannel(struct _adapter *pAdapter);
302	void r8712_SetTxPower(struct _adapter *pAdapte);
303	void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset);
304	void r8712_SetDataRate(struct _adapter *pAdapter);
305	void r8712_SwitchBandwidth(struct _adapter *pAdapter);
306	void r8712_SwitchAntenna(struct _adapter *pAdapter);
307	void r8712_SetCrystalCap(struct _adapter *pAdapter);
308	void r8712_GetThermalMeter(struct _adapter pAdapter, u32 value);
309	void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart);
310	void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart);
311	void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart);
312	void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart);
313	void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter);
314	u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter);
315	u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter);
316
317	#endif /__RTL871X_MP_H_/
318