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Merge branch 'core-objtool-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / staging / rtl8192u / r819xU_phy.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
8fc8598e
JC		 2#include "r8192U.h"
3#include "r8192U_hw.h"
4#include "r819xU_phy.h"
5#include "r819xU_phyreg.h"
6#include "r8190_rtl8256.h"
7#include "r8192U_dm.h"
8#include "r819xU_firmware_img.h"
9
71fe5953 10#include "ieee80211/dot11d.h"
391c72a3
XR		 11#include <linux/bitops.h>
12
8fc8598e
JC		 13static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
14 0,
5f2392b8
XR		 15 0x085c, /* 2412 1 */
16 0x08dc, /* 2417 2 */
17 0x095c, /* 2422 3 */
18 0x09dc, /* 2427 4 */
19 0x0a5c, /* 2432 5 */
20 0x0adc, /* 2437 6 */
21 0x0b5c, /* 2442 7 */
22 0x0bdc, /* 2447 8 */
23 0x0c5c, /* 2452 9 */
24 0x0cdc, /* 2457 10 */
25 0x0d5c, /* 2462 11 */
26 0x0ddc, /* 2467 12 */
27 0x0e5c, /* 2472 13 */
28 0x0f72, /* 2484 */
8fc8598e
JC		 29};
30
8fc8598e 31#define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
8fc8598e 32
8fc8598e 33/******************************************************************************
5f2392b8
XR		 34 * function: This function checks different RF type to execute legal judgement.
35 * If RF Path is illegal, we will return false.
36 * input: net_device *dev
cc29db86 37 * u32 e_rfpath
5f2392b8
XR		 38 * output: none
39 * return: 0(illegal, false), 1(legal, true)
40 *****************************************************************************/
cc29db86 41u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 e_rfpath)
8fc8598e
JC		 42{
43 u8 ret = 1;
44 struct r8192_priv *priv = ieee80211_priv(dev);
0081fcc6 45
4a6094c3 46 if (priv->rf_type == RF_2T4R) {
8fc8598e 47 ret = 0;
4a6094c3 48 } else if (priv->rf_type == RF_1T2R) {
cc29db86 49 if (e_rfpath == RF90_PATH_A || e_rfpath == RF90_PATH_B)
8fc8598e 50 ret = 1;
cc29db86 51 else if (e_rfpath == RF90_PATH_C || e_rfpath == RF90_PATH_D)
8fc8598e
JC		 52 ret = 0;
53 }
54 return ret;
55}
0081fcc6 56
8fc8598e 57/******************************************************************************
5f2392b8
XR		 58 * function: This function sets specific bits to BB register
59 * input: net_device *dev
60 * u32 reg_addr //target addr to be modified
61 * u32 bitmask //taget bit pos to be modified
62 * u32 data //value to be write
63 * output: none
64 * return: none
65 * notice:
66 ******************************************************************************/
79931639
XR		 67void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
68 u32 data)
8fc8598e
JC		 69{
70
79931639 71 u32 reg, bitshift;
8fc8598e 72
5f2392b8 73 if (bitmask != bMaskDWord) {
79931639 74 read_nic_dword(dev, reg_addr, &reg);
d2071984 75 bitshift = ffs(bitmask) - 1;
9f66ddb5 76 reg &= ~bitmask;
79931639
XR		 77 reg |= data << bitshift;
78 write_nic_dword(dev, reg_addr, reg);
4a6094c3 79 } else {
79931639 80 write_nic_dword(dev, reg_addr, data);
4a6094c3 81 }
8fc8598e 82}
0081fcc6 83
8fc8598e 84/******************************************************************************
5f2392b8
XR		 85 * function: This function reads specific bits from BB register
86 * input: net_device *dev
98bedd77
KS		 87 * u32 reg_addr //target addr to be readback
88 * u32 bitmask //taget bit pos to be readback
5f2392b8 89 * output: none
98bedd77 90 * return: u32 data //the readback register value
5f2392b8
XR		 91 * notice:
92 ******************************************************************************/
79931639 93u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
8fc8598e 94{
c4b5eb8c 95 u32 reg, bitshift;
8fc8598e 96
79931639 97 read_nic_dword(dev, reg_addr, &reg);
d2071984 98 bitshift = ffs(bitmask) - 1;
8fc8598e 99
c4b5eb8c 100 return (reg & bitmask) >> bitshift;
8fc8598e 101}
0081fcc6 102
8b5c53e6 103static u32 phy_FwRFSerialRead(struct net_device *dev,
cc29db86 104 enum rf90_radio_path_e e_rfpath,
79931639 105 u32 offset);
8fc8598e 106
442543d7 107static void phy_FwRFSerialWrite(struct net_device *dev,
cc29db86 108 enum rf90_radio_path_e e_rfpath,
8b5c53e6 109 u32 offset,
79931639 110 u32 data);
8fc8598e
JC		 111
112/******************************************************************************
5f2392b8
XR		 113 * function: This function reads register from RF chip
114 * input: net_device *dev
cc29db86 115 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D
5f2392b8
XR		 116 * u32 offset //target address to be read
117 * output: none
118 * return: u32 readback value
119 * notice: There are three types of serial operations:
120 * (1) Software serial write.
121 * (2)Hardware LSSI-Low Speed Serial Interface.
122 * (3)Hardware HSSI-High speed serial write.
123 * Driver here need to implement (1) and (2)
124 * ---need more spec for this information.
125 ******************************************************************************/
c92f473d 126static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
cc29db86 127 enum rf90_radio_path_e e_rfpath, u32 offset)
8fc8598e
JC		 128{
129 struct r8192_priv *priv = ieee80211_priv(dev);
130 u32 ret = 0;
79931639 131 u32 new_offset = 0;
cc29db86 132 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath];
0081fcc6 133
8fc8598e 134 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
5f2392b8 135 /* Make sure RF register offset is correct */
79931639 136 offset &= 0x3f;
8fc8598e 137
5f2392b8 138 /* Switch page for 8256 RF IC */
4a6094c3 139 if (priv->rf_chip == RF_8256) {
79931639 140 if (offset >= 31) {
cc29db86 141 priv->RfReg0Value[e_rfpath] |= 0x140;
5f2392b8 142 /* Switch to Reg_Mode2 for Reg 31-45 */
1db5aa05
XR		 143 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
144 bMaskDWord,
cc29db86 145 priv->RfReg0Value[e_rfpath]<<16);
5f2392b8 146 /* Modify offset */
79931639
XR		 147 new_offset = offset - 30;
148 } else if (offset >= 16) {
cc29db86
JW		 149 priv->RfReg0Value[e_rfpath] |= 0x100;
150 priv->RfReg0Value[e_rfpath] &= (~0x40);
5f2392b8 151 /* Switch to Reg_Mode1 for Reg16-30 */
1db5aa05
XR		 152 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
153 bMaskDWord,
cc29db86 154 priv->RfReg0Value[e_rfpath]<<16);
8fc8598e 155
79931639 156 new_offset = offset - 15;
4a6094c3 157 } else {
79931639 158 new_offset = offset;
4a6094c3
XR		 159 }
160 } else {
1db5aa05
XR		 161 RT_TRACE((COMP_PHY|COMP_ERR),
162 "check RF type here, need to be 8256\n");
79931639 163 new_offset = offset;
8fc8598e 164 }
5f2392b8 165 /* Put desired read addr to LSSI control Register */
1db5aa05
XR		 166 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
167 new_offset);
5f2392b8 168 /* Issue a posedge trigger */
8fc8598e
JC		 169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
170 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
171
172
5f2392b8 173 /* TODO: we should not delay such a long time. Ask for help from SD3 */
26f3561d 174 usleep_range(1000, 1000);
8fc8598e 175
1db5aa05
XR		 176 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
177 bLSSIReadBackData);
8fc8598e
JC		 178
179
5f2392b8 180 /* Switch back to Reg_Mode0 */
1111b876 181 if (priv->rf_chip == RF_8256) {
cc29db86 182 priv->RfReg0Value[e_rfpath] &= 0xebf;
8fc8598e 183
1db5aa05 184 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
cc29db86 185 priv->RfReg0Value[e_rfpath] << 16);
8fc8598e
JC		 186 }
187
188 return ret;
8fc8598e
JC		 189}
190
191/******************************************************************************
5f2392b8
XR		 192 * function: This function writes data to RF register
193 * input: net_device *dev
cc29db86 194 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D
5f2392b8
XR		 195 * u32 offset //target address to be written
196 * u32 data //the new register data to be written
197 * output: none
198 * return: none
199 * notice: For RF8256 only.
200 * ===========================================================================
201 * Reg Mode RegCTL[1] RegCTL[0] Note
8fc8598e 202 * (Reg00[12]) (Reg00[10])
5f2392b8
XR		 203 * ===========================================================================
204 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf)
205 * ---------------------------------------------------------------------------
206 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf)
207 * ---------------------------------------------------------------------------
8fc8598e 208 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
5f2392b8
XR		 209 * ---------------------------------------------------------------------------
210 *****************************************************************************/
c92f473d 211static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
cc29db86 212 enum rf90_radio_path_e e_rfpath,
8b5c53e6 213 u32 offset,
c92f473d 214 u32 data)
8fc8598e
JC		 215{
216 struct r8192_priv *priv = ieee80211_priv(dev);
79931639 217 u32 DataAndAddr = 0, new_offset = 0;
cc29db86 218 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath];
8fc8598e 219
79931639 220 offset &= 0x3f;
4a6094c3 221 if (priv->rf_chip == RF_8256) {
8fc8598e 222
79931639 223 if (offset >= 31) {
cc29db86 224 priv->RfReg0Value[e_rfpath] |= 0x140;
1db5aa05
XR		 225 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
226 bMaskDWord,
cc29db86 227 priv->RfReg0Value[e_rfpath] << 16);
79931639
XR		 228 new_offset = offset - 30;
229 } else if (offset >= 16) {
cc29db86
JW		 230 priv->RfReg0Value[e_rfpath] |= 0x100;
231 priv->RfReg0Value[e_rfpath] &= (~0x40);
1db5aa05
XR		 232 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
233 bMaskDWord,
cc29db86 234 priv->RfReg0Value[e_rfpath]<<16);
79931639 235 new_offset = offset - 15;
4a6094c3 236 } else {
79931639 237 new_offset = offset;
4a6094c3
XR		 238 }
239 } else {
1db5aa05
XR		 240 RT_TRACE((COMP_PHY|COMP_ERR),
241 "check RF type here, need to be 8256\n");
79931639 242 new_offset = offset;
8fc8598e
JC		 243 }
244
5f2392b8 245 /* Put write addr in [5:0] and write data in [31:16] */
79931639 246 DataAndAddr = (data<<16) | (new_offset&0x3f);
8fc8598e 247
5f2392b8 248 /* Write operation */
8fc8598e
JC		 249 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
250
251
79931639 252 if (offset == 0x0)
cc29db86 253 priv->RfReg0Value[e_rfpath] = data;
8fc8598e 254
5f2392b8 255 /* Switch back to Reg_Mode0 */
1111b876 256 if (priv->rf_chip == RF_8256) {
79931639 257 if (offset != 0) {
cc29db86 258 priv->RfReg0Value[e_rfpath] &= 0xebf;
1db5aa05
XR		 259 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
260 bMaskDWord,
cc29db86 261 priv->RfReg0Value[e_rfpath] << 16);
8fc8598e
JC		 262 }
263 }
8fc8598e
JC		 264}
265
266/******************************************************************************
5f2392b8
XR		 267 * function: This function set specific bits to RF register
268 * input: net_device dev
cc29db86 269 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D
5f2392b8
XR		 270 * u32 reg_addr //target addr to be modified
271 * u32 bitmask //taget bit pos to be modified
272 * u32 data //value to be written
273 * output: none
274 * return: none
275 * notice:
276 *****************************************************************************/
8b5c53e6 277void rtl8192_phy_SetRFReg(struct net_device *dev,
cc29db86 278 enum rf90_radio_path_e e_rfpath,
79931639 279 u32 reg_addr, u32 bitmask, u32 data)
8fc8598e
JC		 280{
281 struct r8192_priv *priv = ieee80211_priv(dev);
79931639 282 u32 reg, bitshift;
8fc8598e 283
cc29db86 284 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
8fc8598e
JC		 285 return;
286
4a6094c3 287 if (priv->Rf_Mode == RF_OP_By_FW) {
5f2392b8
XR		 288 if (bitmask != bMask12Bits) {
289 /* RF data is 12 bits only */
cc29db86 290 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
d2071984 291 bitshift = ffs(bitmask) - 1;
9f66ddb5 292 reg &= ~bitmask;
79931639 293 reg |= data << bitshift;
8fc8598e 294
cc29db86 295 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, reg);
4a6094c3 296 } else {
cc29db86 297 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, data);
4a6094c3 298 }
8fc8598e
JC		 299
300 udelay(200);
301
4a6094c3 302 } else {
5f2392b8
XR		 303 if (bitmask != bMask12Bits) {
304 /* RF data is 12 bits only */
cc29db86 305 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
d2071984 306 bitshift = ffs(bitmask) - 1;
9f66ddb5 307 reg &= ~bitmask;
79931639 308 reg |= data << bitshift;
8fc8598e 309
cc29db86 310 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, reg);
4a6094c3 311 } else {
cc29db86 312 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, data);
4a6094c3 313 }
8fc8598e 314 }
8fc8598e
JC		 315}
316
317/******************************************************************************
5f2392b8
XR		 318 * function: This function reads specific bits from RF register
319 * input: net_device *dev
320 * u32 reg_addr //target addr to be readback
321 * u32 bitmask //taget bit pos to be readback
322 * output: none
323 * return: u32 data //the readback register value
324 * notice:
325 *****************************************************************************/
8b5c53e6 326u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
cc29db86 327 enum rf90_radio_path_e e_rfpath,
79931639 328 u32 reg_addr, u32 bitmask)
8fc8598e 329{
79931639 330 u32 reg, bitshift;
8fc8598e
JC		 331 struct r8192_priv *priv = ieee80211_priv(dev);
332
333
cc29db86 334 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
8fc8598e 335 return 0;
4a6094c3 336 if (priv->Rf_Mode == RF_OP_By_FW) {
cc29db86 337 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
8fc8598e 338 udelay(200);
4a6094c3 339 } else {
cc29db86 340 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
8fc8598e 341 }
d2071984 342 bitshift = ffs(bitmask) - 1;
d0049dfc
KS		 343 reg = (reg & bitmask) >> bitshift;
344 return reg;
345
8fc8598e 346}
0081fcc6 347
8fc8598e 348/******************************************************************************
5f2392b8
XR		 349 * function: We support firmware to execute RF-R/W.
350 * input: net_device *dev
cc29db86 351 * rf90_radio_path_e e_rfpath
5f2392b8
XR		 352 * u32 offset
353 * output: none
354 * return: u32
355 * notice:
356 ****************************************************************************/
8b5c53e6 357static u32 phy_FwRFSerialRead(struct net_device *dev,
cc29db86 358 enum rf90_radio_path_e e_rfpath,
79931639 359 u32 offset)
8fc8598e 360{
07ecbbf1 361 u32 reg = 0;
79931639 362 u32 data = 0;
8fc8598e 363 u8 time = 0;
b3d42bf1 364 u32 tmp;
0081fcc6 365
5f2392b8
XR		 366 /* Firmware RF Write control.
367 * We can not execute the scheme in the initial step.
368 * Otherwise, RF-R/W will waste much time.
991397d1
DR		 369 * This is only for site survey.
370 */
5f2392b8
XR		 371 /* 1. Read operation need not insert data. bit 0-11 */
372 /* 2. Write RF register address. bit 12-19 */
79931639 373 data |= ((offset&0xFF)<<12);
5f2392b8 374 /* 3. Write RF path. bit 20-21 */
cc29db86 375 data |= ((e_rfpath&0x3)<<20);
5f2392b8
XR		 376 /* 4. Set RF read indicator. bit 22=0 */
377 /* 5. Trigger Fw to operate the command. bit 31 */
79931639 378 data |= 0x80000000;
5f2392b8 379 /* 6. We can not execute read operation if bit 31 is 1. */
b3d42bf1 380 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 381 while (tmp & 0x80000000) {
5f2392b8 382 /* If FW can not finish RF-R/W for more than ?? times.
991397d1
DR		 383 * We must reset FW.
384 */
4a6094c3 385 if (time++ < 100) {
8fc8598e 386 udelay(10);
b3d42bf1 387 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 388 } else {
8fc8598e 389 break;
4a6094c3 390 }
8fc8598e 391 }
5f2392b8 392 /* 7. Execute read operation. */
79931639 393 write_nic_dword(dev, QPNR, data);
5f2392b8 394 /* 8. Check if firmware send back RF content. */
b3d42bf1 395 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 396 while (tmp & 0x80000000) {
5f2392b8 397 /* If FW can not finish RF-R/W for more than ?? times.
991397d1
DR		 398 * We must reset FW.
399 */
4a6094c3 400 if (time++ < 100) {
8fc8598e 401 udelay(10);
b3d42bf1 402 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 403 } else {
4c8dd926 404 return 0;
4a6094c3 405 }
8fc8598e 406 }
07ecbbf1 407 read_nic_dword(dev, RF_DATA, &reg);
8fc8598e 408
07ecbbf1 409 return reg;
5f2392b8 410}
8fc8598e
JC		 411
412/******************************************************************************
5f2392b8
XR		 413 * function: We support firmware to execute RF-R/W.
414 * input: net_device *dev
cc29db86 415 * rf90_radio_path_e e_rfpath
5f2392b8
XR		 416 * u32 offset
417 * u32 data
418 * output: none
419 * return: none
420 * notice:
421 ****************************************************************************/
442543d7 422static void phy_FwRFSerialWrite(struct net_device *dev,
cc29db86 423 enum rf90_radio_path_e e_rfpath,
8b5c53e6 424 u32 offset, u32 data)
8fc8598e
JC		 425{
426 u8 time = 0;
b3d42bf1 427 u32 tmp;
8fc8598e 428
5f2392b8
XR		 429 /* Firmware RF Write control.
430 * We can not execute the scheme in the initial step.
431 * Otherwise, RF-R/W will waste much time.
991397d1
DR		 432 * This is only for site survey.
433 */
8fc8598e 434
5f2392b8
XR		 435 /* 1. Set driver write bit and 12 bit data. bit 0-11 */
436 /* 2. Write RF register address. bit 12-19 */
79931639 437 data |= ((offset&0xFF)<<12);
5f2392b8 438 /* 3. Write RF path. bit 20-21 */
cc29db86 439 data |= ((e_rfpath&0x3)<<20);
5f2392b8 440 /* 4. Set RF write indicator. bit 22=1 */
79931639 441 data |= 0x400000;
5f2392b8 442 /* 5. Trigger Fw to operate the command. bit 31=1 */
79931639 443 data |= 0x80000000;
8fc8598e 444
5f2392b8 445 /* 6. Write operation. We can not write if bit 31 is 1. */
b3d42bf1 446 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 447 while (tmp & 0x80000000) {
5f2392b8 448 /* If FW can not finish RF-R/W for more than ?? times.
991397d1
DR		 449 * We must reset FW.
450 */
4a6094c3 451 if (time++ < 100) {
8fc8598e 452 udelay(10);
b3d42bf1 453 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 454 } else {
8fc8598e 455 break;
4a6094c3 456 }
8fc8598e 457 }
5f2392b8 458 /* 7. No matter check bit. We always force the write.
991397d1
DR		 459 * Because FW will not accept the command.
460 */
79931639 461 write_nic_dword(dev, QPNR, data);
5f2392b8 462 /* According to test, we must delay 20us to wait firmware
991397d1
DR		 463 * to finish RF write operation.
464 */
5f2392b8 465 /* We support delay in firmware side now. */
5f2392b8 466}
8fc8598e 467
8fc8598e 468/******************************************************************************
5f2392b8
XR		 469 * function: This function reads BB parameters from header file we generate,
470 * and do register read/write
98bedd77 471 * input: net_device *dev
5f2392b8
XR		 472 * output: none
473 * return: none
474 * notice: BB parameters may change all the time, so please make
475 * sure it has been synced with the newest.
476 *****************************************************************************/
88d8fe29 477void rtl8192_phy_configmac(struct net_device *dev)
8fc8598e
JC		 478{
479 u32 dwArrayLen = 0, i;
88d8fe29 480 u32 *pdwArray = NULL;
8fc8598e
JC		 481 struct r8192_priv *priv = ieee80211_priv(dev);
482
1111b876 483 if (priv->btxpowerdata_readfromEEPORM) {
8fc8598e
JC		 484 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
485 dwArrayLen = MACPHY_Array_PGLength;
4531f193 486 pdwArray = Rtl8192UsbMACPHY_Array_PG;
8fc8598e 487
4a6094c3 488 } else {
8fc8598e
JC		 489 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
490 dwArrayLen = MACPHY_ArrayLength;
491 pdwArray = rtl819XMACPHY_Array;
492 }
9d8e79ed 493 for (i = 0; i < dwArrayLen; i = i+3) {
2930d0b9 494 if (pdwArray[i] == 0x318)
8fc8598e 495 pdwArray[i+2] = 0x00000800;
8fc8598e 496
1db5aa05
XR		 497 RT_TRACE(COMP_DBG,
498 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
499 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
500 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
501 pdwArray[i+2]);
8fc8598e 502 }
8fc8598e
JC		 503}
504
505/******************************************************************************
5f2392b8
XR		 506 * function: This function does dirty work
507 * input: net_device *dev
508 * u8 ConfigType
509 * output: none
510 * return: none
511 * notice: BB parameters may change all the time, so please make
512 * sure it has been synced with the newest.
513 *****************************************************************************/
111118af
JW		 514static void rtl8192_phyConfigBB(struct net_device *dev,
515 enum baseband_config_type ConfigType)
8fc8598e
JC		 516{
517 u32 i;
518
111118af 519 if (ConfigType == BASEBAND_CONFIG_PHY_REG) {
9d8e79ed 520 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
22be361a 521 rtl8192_setBBreg(dev, Rtl8192UsbPHY_REG_1T2RArray[i],
1db5aa05 522 bMaskDWord,
22be361a 523 Rtl8192UsbPHY_REG_1T2RArray[i+1]);
1db5aa05
XR		 524 RT_TRACE(COMP_DBG,
525 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
22be361a
JW		 526 i, Rtl8192UsbPHY_REG_1T2RArray[i],
527 Rtl8192UsbPHY_REG_1T2RArray[i+1]);
8fc8598e 528 }
111118af 529 } else if (ConfigType == BASEBAND_CONFIG_AGC_TAB) {
9d8e79ed 530 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
def6b79f
JW		 531 rtl8192_setBBreg(dev, Rtl8192UsbAGCTAB_Array[i],
532 bMaskDWord, Rtl8192UsbAGCTAB_Array[i+1]);
1db5aa05 533 RT_TRACE(COMP_DBG,
def6b79f
JW		 534 "i: %x, Rtl8192UsbAGCTAB_Array[0]=%x Rtl8192UsbAGCTAB_Array[1]=%x\n",
535 i, Rtl8192UsbAGCTAB_Array[i],
536 Rtl8192UsbAGCTAB_Array[i+1]);
8fc8598e
JC		 537 }
538 }
8fc8598e 539}
0081fcc6 540
8fc8598e 541/******************************************************************************
5f2392b8
XR		 542 * function: This function initializes Register definition offset for
543 * Radio Path A/B/C/D
544 * input: net_device *dev
545 * output: none
546 * return: none
547 * notice: Initialization value here is constant and it should never
548 * be changed
549 *****************************************************************************/
c92f473d 550static void rtl8192_InitBBRFRegDef(struct net_device *dev)
8fc8598e
JC		 551{
552 struct r8192_priv *priv = ieee80211_priv(dev);
0081fcc6 553
5f2392b8
XR		 554 /* RF Interface Software Control */
555 /* 16 LSBs if read 32-bit from 0x870 */
556 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
557 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
558 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
559 /* 16 LSBs if read 32-bit from 0x874 */
560 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
561 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
562 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
563
564 /* RF Interface Readback Value */
565 /* 16 LSBs if read 32-bit from 0x8E0 */
566 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
567 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
568 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
569 /* 16 LSBs if read 32-bit from 0x8E4 */
570 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
571 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
572 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
573
574 /* RF Interface Output (and Enable) */
575 /* 16 LSBs if read 32-bit from 0x860 */
576 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
577 /* 16 LSBs if read 32-bit from 0x864 */
578 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
579 /* 16 LSBs if read 32-bit from 0x868 */
580 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
581 /* 16 LSBs if read 32-bit from 0x86C */
582 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
583
584 /* RF Interface (Output and) Enable */
585 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
586 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
587 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
588 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
589 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
590 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
591 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
592 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
593
594 /* Addr of LSSI. Write RF register by driver */
595 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
8fc8598e
JC		 596 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
597 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
598 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
599
5f2392b8
XR		 600 /* RF parameter */
601 /* BB Band Select */
602 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
8fc8598e
JC		 603 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
604 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
605 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
606
5f2392b8
XR		 607 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
608 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
609 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
610 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
611 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
612
613 /* Tranceiver A~D HSSI Parameter-1 */
614 /* wire control parameter1 */
615 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
616 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
617 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
618 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
619
620 /* Tranceiver A~D HSSI Parameter-2 */
621 /* wire control parameter2 */
622 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
623 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
624 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
625 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
626
627 /* RF Switch Control */
628 /* TR/Ant switch control */
629 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
8fc8598e
JC		 630 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
631 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
632 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
633
5f2392b8 634 /* AGC control 1 */
8fc8598e
JC		 635 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
636 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
637 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
638 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
639
5f2392b8 640 /* AGC control 2 */
8fc8598e
JC		 641 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
642 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
643 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
644 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
645
5f2392b8 646 /* RX AFE control 1 */
8fc8598e
JC		 647 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
648 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
649 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
650 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
651
5f2392b8 652 /* RX AFE control 1 */
8fc8598e
JC		 653 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
654 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
655 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
656 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
657
5f2392b8 658 /* Tx AFE control 1 */
8fc8598e
JC		 659 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
660 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
661 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
662 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
663
5f2392b8 664 /* Tx AFE control 2 */
8fc8598e
JC		 665 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
666 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
667 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
668 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
669
5f2392b8 670 /* Tranceiver LSSI Readback */
8fc8598e
JC		 671 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
672 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
673 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
674 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
8fc8598e 675}
0081fcc6 676
8fc8598e 677/******************************************************************************
5f2392b8
XR		 678 * function: This function is to write register and then readback to make
679 * sure whether BB and RF is OK
680 * input: net_device *dev
b714c8c0 681 * hw90_block_e CheckBlock
cc29db86 682 * rf90_radio_path_e e_rfpath //only used when checkblock is
5f2392b8
XR		 683 * //HW90_BLOCK_RF
684 * output: none
685 * return: return whether BB and RF is ok (0:OK, 1:Fail)
686 * notice: This function may be removed in the ASIC
687 ******************************************************************************/
b714c8c0 688u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, enum hw90_block_e CheckBlock,
cc29db86 689 enum rf90_radio_path_e e_rfpath)
8fc8598e 690{
8fc8598e 691 u8 ret = 0;
a60d4d68 692 u32 i, CheckTimes = 4, reg = 0;
8fc8598e
JC		 693 u32 WriteAddr[4];
694 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
0081fcc6 695
5f2392b8 696 /* Initialize register address offset to be checked */
8fc8598e
JC		 697 WriteAddr[HW90_BLOCK_MAC] = 0x100;
698 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
699 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
700 WriteAddr[HW90_BLOCK_RF] = 0x3;
08a4cdea 701 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
111857c9 702 for (i = 0; i < CheckTimes; i++) {
8fc8598e 703
5f2392b8 704 /* Write data to register and readback */
4a6094c3 705 switch (CheckBlock) {
8fc8598e 706 case HW90_BLOCK_MAC:
1db5aa05 707 RT_TRACE(COMP_ERR,
0081fcc6 708 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
8fc8598e
JC		 709 break;
710
711 case HW90_BLOCK_PHY0:
712 case HW90_BLOCK_PHY1:
1db5aa05
XR		 713 write_nic_dword(dev, WriteAddr[CheckBlock],
714 WriteData[i]);
a60d4d68 715 read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
8fc8598e
JC		 716 break;
717
718 case HW90_BLOCK_RF:
719 WriteData[i] &= 0xfff;
cc29db86 720 rtl8192_phy_SetRFReg(dev, e_rfpath,
1db5aa05
XR		 721 WriteAddr[HW90_BLOCK_RF],
722 bMask12Bits, WriteData[i]);
5f2392b8 723 /* TODO: we should not delay for such a long time.
991397d1
DR		 724 * Ask SD3
725 */
26f3561d 726 usleep_range(1000, 1000);
cc29db86 727 reg = rtl8192_phy_QueryRFReg(dev, e_rfpath,
a60d4d68
XR		 728 WriteAddr[HW90_BLOCK_RF],
729 bMask12Bits);
26f3561d 730 usleep_range(1000, 1000);
8fc8598e
JC		 731 break;
732
733 default:
734 ret = 1;
735 break;
736 }
737
738
5f2392b8 739 /* Check whether readback data is correct */
a60d4d68 740 if (reg != WriteData[i]) {
1db5aa05 741 RT_TRACE((COMP_PHY|COMP_ERR),
a60d4d68
XR		 742 "error reg: %x, WriteData: %x\n",
743 reg, WriteData[i]);
8fc8598e
JC		 744 ret = 1;
745 break;
746 }
747 }
748
749 return ret;
750}
751
8fc8598e 752/******************************************************************************
5f2392b8
XR		 753 * function: This function initializes BB&RF
754 * input: net_device *dev
755 * output: none
756 * return: none
757 * notice: Initialization value may change all the time, so please make
758 * sure it has been synced with the newest.
759 ******************************************************************************/
c92f473d 760static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
8fc8598e
JC		 761{
762 struct r8192_priv *priv = ieee80211_priv(dev);
a60d4d68 763 u8 reg_u8 = 0, eCheckItem = 0, status = 0;
07ecbbf1 764 u32 reg_u32 = 0;
0081fcc6 765
8fc8598e 766 /**************************************
5f2392b8
XR		 767 * <1> Initialize BaseBand
768 *************************************/
8fc8598e 769
5f2392b8 770 /* --set BB Global Reset-- */
07ecbbf1 771 read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
83e6d9e2 772 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
8fc8598e 773 mdelay(50);
5f2392b8 774 /* ---set BB reset Active--- */
07ecbbf1
XR		 775 read_nic_dword(dev, CPU_GEN, &reg_u32);
776 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
8fc8598e 777
5f2392b8
XR		 778 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
779 /* TODO: this function should be removed on ASIC */
b714c8c0 780 for (eCheckItem = (enum hw90_block_e)HW90_BLOCK_PHY0;
1db5aa05
XR		 781 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
782 /* don't care RF path */
b714c8c0 783 status = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block_e)eCheckItem,
fb37edcf 784 (enum rf90_radio_path_e)0);
a60d4d68 785 if (status != 0) {
1db5aa05 786 RT_TRACE((COMP_ERR | COMP_PHY),
9980fd11 787 "phy_rf8256_config(): Check PHY%d Fail!!\n",
1db5aa05 788 eCheckItem-1);
111857c9 789 return;
8fc8598e
JC		 790 }
791 }
5f2392b8 792 /* ---- Set CCK and OFDM Block "OFF"---- */
8fc8598e 793 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
5f2392b8
XR		 794 /* ----BB Register Initilazation---- */
795 /* ==m==>Set PHY REG From Header<==m== */
111118af 796 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_PHY_REG);
8fc8598e 797
5f2392b8 798 /* ----Set BB reset de-Active---- */
07ecbbf1
XR		 799 read_nic_dword(dev, CPU_GEN, &reg_u32);
800 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
8fc8598e 801
5f2392b8
XR		 802 /* ----BB AGC table Initialization---- */
803 /* ==m==>Set PHY REG From Header<==m== */
111118af 804 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_AGC_TAB);
8fc8598e 805
5f2392b8 806 /* ----Enable XSTAL ---- */
8fc8598e 807 write_nic_byte_E(dev, 0x5e, 0x00);
64749a7e 808 if (priv->card_8192_version == VERSION_819XU_A) {
5f2392b8 809 /* Antenna gain offset from B/C/D to A */
2060f31a
HM		 810 reg_u32 = priv->AntennaTxPwDiff[1]<<4 |
811 priv->AntennaTxPwDiff[0];
1db5aa05
XR		 812 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
813 reg_u32);
8fc8598e 814
5f2392b8 815 /* XSTALLCap */
07ecbbf1 816 reg_u32 = priv->CrystalCap & 0xf;
1db5aa05
XR		 817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
818 reg_u32);
8fc8598e
JC		 819 }
820
5f2392b8 821 /* Check if the CCK HighPower is turned ON.
991397d1
DR		 822 * This is used to calculate PWDB.
823 */
1db5aa05
XR		 824 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
825 rFPGA0_XA_HSSIParameter2,
826 0x200);
8fc8598e 827}
0081fcc6 828
8fc8598e 829/******************************************************************************
5f2392b8
XR		 830 * function: This function initializes BB&RF
831 * input: net_device *dev
832 * output: none
833 * return: none
834 * notice: Initialization value may change all the time, so please make
835 * sure it has been synced with the newest.
836 *****************************************************************************/
88d8fe29 837void rtl8192_BBConfig(struct net_device *dev)
8fc8598e
JC		 838{
839 rtl8192_InitBBRFRegDef(dev);
5f2392b8
XR		 840 /* config BB&RF. As hardCode based initialization has not been well
841 * implemented, so use file first.
991397d1
DR		 842 * FIXME: should implement it for hardcode?
843 */
8fc8598e 844 rtl8192_BB_Config_ParaFile(dev);
8fc8598e
JC		 845}
846
0081fcc6 847
8fc8598e 848/******************************************************************************
5f2392b8
XR		 849 * function: This function obtains the initialization value of Tx power Level
850 * offset
851 * input: net_device *dev
852 * output: none
853 * return: none
854 *****************************************************************************/
88d8fe29 855void rtl8192_phy_getTxPower(struct net_device *dev)
8fc8598e
JC		 856{
857 struct r8192_priv *priv = ieee80211_priv(dev);
b3d42bf1 858 u8 tmp;
0081fcc6 859
1db5aa05
XR		 860 read_nic_dword(dev, rTxAGC_Rate18_06,
861 &priv->MCSTxPowerLevelOriginalOffset[0]);
862 read_nic_dword(dev, rTxAGC_Rate54_24,
863 &priv->MCSTxPowerLevelOriginalOffset[1]);
864 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
865 &priv->MCSTxPowerLevelOriginalOffset[2]);
866 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
867 &priv->MCSTxPowerLevelOriginalOffset[3]);
868 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
869 &priv->MCSTxPowerLevelOriginalOffset[4]);
870 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
871 &priv->MCSTxPowerLevelOriginalOffset[5]);
8fc8598e 872
5f2392b8 873 /* Read rx initial gain */
b3d42bf1
XR		 874 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
875 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
876 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
877 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
1db5aa05
XR		 878 RT_TRACE(COMP_INIT,
879 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
880 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
881 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
8fc8598e 882
5f2392b8 883 /* Read framesync */
b3d42bf1
XR		 884 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
885 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
886 priv->framesyncC34 = tmp;
d5133e75 887 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
8fc8598e
JC		 888 rOFDM0_RxDetector3, priv->framesync);
889
5f2392b8 890 /* Read SIFS (save the value read fome MACPHY_REG.txt) */
b3d42bf1 891 read_nic_word(dev, SIFS, &priv->SifsTime);
8fc8598e
JC		 892}
893
894/******************************************************************************
5f2392b8
XR		 895 * function: This function sets the initialization value of Tx power Level
896 * offset
897 * input: net_device *dev
898 * u8 channel
899 * output: none
900 * return: none
901 ******************************************************************************/
88d8fe29 902void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
8fc8598e
JC		 903{
904 struct r8192_priv *priv = ieee80211_priv(dev);
905 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
906 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
907
4a6094c3 908 switch (priv->rf_chip) {
8fc8598e 909 case RF_8256:
1db5aa05 910 /* need further implement */
3942039a 911 phy_set_rf8256_cck_tx_power(dev, powerlevel);
071327fc 912 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G);
8fc8598e
JC		 913 break;
914 default:
1db5aa05
XR		 915 RT_TRACE((COMP_PHY|COMP_ERR),
916 "error RF chipID(8225 or 8258) in function %s()\n",
08a4cdea 917 __func__);
8fc8598e
JC		 918 break;
919 }
8fc8598e
JC		 920}
921
922/******************************************************************************
5f2392b8
XR		 923 * function: This function checks Rf chip to do RF config
924 * input: net_device *dev
925 * output: none
926 * return: only 8256 is supported
927 ******************************************************************************/
88d8fe29 928void rtl8192_phy_RFConfig(struct net_device *dev)
8fc8598e
JC		 929{
930 struct r8192_priv *priv = ieee80211_priv(dev);
931
4a6094c3 932 switch (priv->rf_chip) {
16ec1a20 933 case RF_8256:
9980fd11 934 phy_rf8256_config(dev);
16ec1a20 935 break;
936 default:
937 RT_TRACE(COMP_ERR, "error chip id\n");
938 break;
8fc8598e 939 }
8fc8598e
JC		 940}
941
942/******************************************************************************
5f2392b8
XR		 943 * function: This function updates Initial gain
944 * input: net_device *dev
945 * output: none
946 * return: As Windows has not implemented this, wait for complement
947 ******************************************************************************/
88d8fe29 948void rtl8192_phy_updateInitGain(struct net_device *dev)
8fc8598e 949{
8fc8598e
JC		 950}
951
952/******************************************************************************
5f2392b8
XR		 953 * function: This function read RF parameters from general head file,
954 * and do RF 3-wire
955 * input: net_device *dev
cc29db86 956 * rf90_radio_path_e e_rfpath
5f2392b8
XR		 957 * output: none
958 * return: return code show if RF configuration is successful(0:pass, 1:fail)
959 * notice: Delay may be required for RF configuration
960 *****************************************************************************/
442543d7 961u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
cc29db86 962 enum rf90_radio_path_e e_rfpath)
8fc8598e
JC		 963{
964
965 int i;
8fc8598e 966
cc29db86 967 switch (e_rfpath) {
24fbe875 968 case RF90_PATH_A:
9d8e79ed 969 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
8fc8598e 970
be208c76 971 if (Rtl8192UsbRadioA_Array[i] == 0xfe) {
1db5aa05
XR		 972 mdelay(100);
973 continue;
8fc8598e 974 }
cc29db86 975 rtl8192_phy_SetRFReg(dev, e_rfpath,
be208c76 976 Rtl8192UsbRadioA_Array[i],
1db5aa05 977 bMask12Bits,
be208c76 978 Rtl8192UsbRadioA_Array[i+1]);
24fbe875 979 mdelay(1);
8fc8598e 980
24fbe875
SH		 981 }
982 break;
983 case RF90_PATH_B:
9d8e79ed 984 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
8fc8598e 985
416599d0 986 if (Rtl8192UsbRadioB_Array[i] == 0xfe) {
1db5aa05
XR		 987 mdelay(100);
988 continue;
8fc8598e 989 }
cc29db86 990 rtl8192_phy_SetRFReg(dev, e_rfpath,
416599d0 991 Rtl8192UsbRadioB_Array[i],
1db5aa05 992 bMask12Bits,
416599d0 993 Rtl8192UsbRadioB_Array[i+1]);
24fbe875 994 mdelay(1);
8fc8598e 995
24fbe875
SH		 996 }
997 break;
998 case RF90_PATH_C:
9d8e79ed 999 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
8fc8598e 1000
281da530 1001 if (Rtl8192UsbRadioC_Array[i] == 0xfe) {
1db5aa05
XR		 1002 mdelay(100);
1003 continue;
8fc8598e 1004 }
cc29db86 1005 rtl8192_phy_SetRFReg(dev, e_rfpath,
281da530 1006 Rtl8192UsbRadioC_Array[i],
1db5aa05 1007 bMask12Bits,
281da530 1008 Rtl8192UsbRadioC_Array[i+1]);
24fbe875 1009 mdelay(1);
8fc8598e 1010
24fbe875
SH		 1011 }
1012 break;
1013 case RF90_PATH_D:
9d8e79ed 1014 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
8fc8598e 1015
a99d0240 1016 if (Rtl8192UsbRadioD_Array[i] == 0xfe) {
1db5aa05
XR		 1017 mdelay(100);
1018 continue;
8fc8598e 1019 }
cc29db86 1020 rtl8192_phy_SetRFReg(dev, e_rfpath,
a99d0240 1021 Rtl8192UsbRadioD_Array[i],
1db5aa05 1022 bMask12Bits,
a99d0240 1023 Rtl8192UsbRadioD_Array[i+1]);
24fbe875
SH		 1024 mdelay(1);
1025
1026 }
1027 break;
1028 default:
1029 break;
8fc8598e
JC		 1030 }
1031
4764ca98 1032 return 0;
8fc8598e
JC		 1033
1034}
0081fcc6 1035
8fc8598e 1036/******************************************************************************
5f2392b8
XR		 1037 * function: This function sets Tx Power of the channel
1038 * input: net_device *dev
1039 * u8 channel
1040 * output: none
1041 * return: none
1042 * notice:
1043 ******************************************************************************/
c92f473d 1044static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
8fc8598e
JC		 1045{
1046 struct r8192_priv *priv = ieee80211_priv(dev);
1047 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1048 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1049
4a6094c3 1050 switch (priv->rf_chip) {
8fc8598e 1051 case RF_8225:
8fc8598e
JC		 1052 break;
1053
1054 case RF_8256:
3942039a 1055 phy_set_rf8256_cck_tx_power(dev, powerlevel);
071327fc 1056 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G);
8fc8598e
JC		 1057 break;
1058
1059 case RF_8258:
1060 break;
1061 default:
1db5aa05 1062 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
8fc8598e
JC		 1063 break;
1064 }
8fc8598e
JC		 1065}
1066
1067/******************************************************************************
5f2392b8
XR		 1068 * function: This function sets RF state on or off
1069 * input: net_device *dev
1070 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1071 * output: none
1072 * return: none
1073 * notice:
1074 *****************************************************************************/
442543d7
XR		 1075bool rtl8192_SetRFPowerState(struct net_device *dev,
1076 RT_RF_POWER_STATE eRFPowerState)
8fc8598e
JC		 1077{
1078 bool bResult = true;
8fc8598e
JC		 1079 struct r8192_priv *priv = ieee80211_priv(dev);
1080
1111b876 1081 if (eRFPowerState == priv->ieee80211->eRFPowerState)
8fc8598e
JC		 1082 return false;
1083
a0886f73 1084 if (priv->SetRFPowerStateInProgress)
8fc8598e
JC		 1085 return false;
1086
1087 priv->SetRFPowerStateInProgress = true;
1088
4a6094c3 1089 switch (priv->rf_chip) {
1db5aa05 1090 case RF_8256:
ceb56597 1091 switch (eRFPowerState) {
1db5aa05
XR		 1092 case eRfOn:
1093 /* RF-A, RF-B */
1094 /* enable RF-Chip A/B - 0x860[4] */
56b3152e 1095 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1db5aa05
XR		 1096 0x1);
1097 /* analog to digital on - 0x88c[9:8] */
1098 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1099 0x3);
1100 /* digital to analog on - 0x880[4:3] */
1101 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1102 0x3);
1103 /* rx antenna on - 0xc04[1:0] */
1104 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1105 /* rx antenna on - 0xd04[1:0] */
1106 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1107 /* analog to digital part2 on - 0x880[6:5] */
1108 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1109 0x3);
8fc8598e 1110
1db5aa05 1111 break;
8fc8598e 1112
1db5aa05 1113 case eRfSleep:
8fc8598e 1114
1db5aa05 1115 break;
8fc8598e 1116
1db5aa05
XR		 1117 case eRfOff:
1118 /* RF-A, RF-B */
1119 /* disable RF-Chip A/B - 0x860[4] */
56b3152e 1120 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1db5aa05
XR		 1121 0x0);
1122 /* analog to digital off, for power save */
1123 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1124 0x0); /* 0x88c[11:8] */
1125 /* digital to analog off, for power save - 0x880[4:3] */
1126 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1127 0x0);
1128 /* rx antenna off - 0xc04[3:0] */
1129 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1130 /* rx antenna off - 0xd04[3:0] */
1131 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1132 /* analog to digital part2 off, for power save */
1133 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1134 0x0); /* 0x880[6:5] */
8fc8598e 1135
8fc8598e 1136 break;
1db5aa05 1137
8fc8598e 1138 default:
1db5aa05
XR		 1139 bResult = false;
1140 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1141 __func__, eRFPowerState);
8fc8598e 1142 break;
1db5aa05
XR		 1143 }
1144 break;
1145 default:
1146 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1147 break;
8fc8598e 1148 }
8fc8598e
JC		 1149 priv->SetRFPowerStateInProgress = false;
1150
1151 return bResult;
1152}
1153
5f2392b8 1154/******************************************************************************
a1b34e42
JW		 1155 * function: This function sets command table variable (struct sw_chnl_cmd).
1156 * input: sw_chnl_cmd *CmdTable //table to be set
5f2392b8
XR		 1157 * u32 CmdTableIdx //variable index in table to be set
1158 * u32 CmdTableSz //table size
2dad9cba 1159 * switch_chan_cmd_id CmdID //command ID to set
5f2392b8
XR		 1160 * u32 Para1
1161 * u32 Para2
1162 * u32 msDelay
1163 * output:
1164 * return: true if finished, false otherwise
1165 * notice:
1166 ******************************************************************************/
a1b34e42 1167static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx,
2dad9cba 1168 u32 CmdTableSz, enum switch_chan_cmd_id CmdID,
c92f473d 1169 u32 Para1, u32 Para2, u32 msDelay)
8fc8598e 1170{
a1b34e42 1171 struct sw_chnl_cmd *pCmd;
8fc8598e 1172
1111b876 1173 if (CmdTable == NULL) {
1db5aa05 1174 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
8fc8598e
JC		 1175 return false;
1176 }
1111b876 1177 if (CmdTableIdx >= CmdTableSz) {
1db5aa05
XR		 1178 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1179 __func__, CmdTableIdx, CmdTableSz);
8fc8598e
JC		 1180 return false;
1181 }
1182
1183 pCmd = CmdTable + CmdTableIdx;
d2a5c987 1184 pCmd->cmd_id = CmdID;
33f28ab7 1185 pCmd->para_1 = Para1;
21807031 1186 pCmd->para_2 = Para2;
e918443c 1187 pCmd->ms_delay = msDelay;
8fc8598e
JC		 1188
1189 return true;
1190}
0081fcc6 1191
8fc8598e 1192/******************************************************************************
5f2392b8
XR		 1193 * function: This function sets channel step by step
1194 * input: net_device *dev
1195 * u8 channel
1196 * u8 *stage //3 stages
1197 * u8 *step
1198 * u32 *delay //whether need to delay
1199 * output: store new stage, step and delay for next step
1200 * (combine with function above)
1201 * return: true if finished, false otherwise
1202 * notice: Wait for simpler function to replace it
1203 *****************************************************************************/
c92f473d
AR		 1204static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1205 u8 *stage, u8 *step, u32 *delay)
8fc8598e
JC		 1206{
1207 struct r8192_priv *priv = ieee80211_priv(dev);
a1b34e42 1208 struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT];
9821cb6d 1209 u32 PreCommonCmdCnt;
a1b34e42 1210 struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT];
9821cb6d 1211 u32 PostCommonCmdCnt;
a1b34e42 1212 struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
9821cb6d 1213 u32 RfDependCmdCnt;
a1b34e42 1214 struct sw_chnl_cmd *CurrentCmd = NULL;
cc29db86 1215 u8 e_rfpath;
8fc8598e 1216
1db5aa05 1217 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
08a4cdea 1218 __func__, *stage, *step, channel);
b56b1438 1219 if (!is_legal_channel(priv->ieee80211, channel)) {
1db5aa05 1220 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
5f2392b8 1221 /* return true to tell upper caller function this channel
991397d1
DR		 1222 * setting is finished! Or it will in while loop.
1223 */
5f2392b8 1224 return true;
8fc8598e 1225 }
1db5aa05 1226 /* FIXME: need to check whether channel is legal or not here */
8fc8598e
JC		 1227
1228
1db5aa05
XR		 1229 /* <1> Fill up pre common command. */
1230 PreCommonCmdCnt = 0;
1231 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1be8f4e7 1232 MAX_PRECMD_CNT, CMD_ID_SET_TX_PWR_LEVEL,
1db5aa05
XR		 1233 0, 0, 0);
1234 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
8772da06 1235 MAX_PRECMD_CNT, CMD_ID_END, 0, 0, 0);
8fc8598e 1236
1db5aa05
XR		 1237 /* <2> Fill up post common command. */
1238 PostCommonCmdCnt = 0;
8fc8598e 1239
1db5aa05 1240 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
8772da06 1241 MAX_POSTCMD_CNT, CMD_ID_END, 0, 0, 0);
8fc8598e 1242
1db5aa05
XR		 1243 /* <3> Fill up RF dependent command. */
1244 RfDependCmdCnt = 0;
1245 switch (priv->rf_chip) {
1246 case RF_8225:
1247 if (!(channel >= 1 && channel <= 14)) {
1248 RT_TRACE(COMP_ERR,
1249 "illegal channel for Zebra 8225: %d\n",
1250 channel);
1251 return true;
1252 }
1253 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1254 MAX_RFDEPENDCMD_CNT,
f6e1472a 1255 CMD_ID_RF_WRITE_REG,
1db5aa05
XR		 1256 rZebra1_Channel,
1257 RF_CHANNEL_TABLE_ZEBRA[channel],
1258 10);
1259 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1260 MAX_RFDEPENDCMD_CNT,
8772da06 1261 CMD_ID_END, 0, 0, 0);
1db5aa05 1262 break;
8fc8598e 1263
1db5aa05
XR		 1264 case RF_8256:
1265 /* TEST!! This is not the table for 8256!! */
1266 if (!(channel >= 1 && channel <= 14)) {
1267 RT_TRACE(COMP_ERR,
1268 "illegal channel for Zebra 8256: %d\n",
1269 channel);
8fc8598e 1270 return true;
8fc8598e 1271 }
1db5aa05
XR		 1272 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1273 MAX_RFDEPENDCMD_CNT,
f6e1472a 1274 CMD_ID_RF_WRITE_REG,
1db5aa05
XR		 1275 rZebra1_Channel, channel, 10);
1276 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1277 MAX_RFDEPENDCMD_CNT,
8772da06 1278 CMD_ID_END, 0, 0, 0);
1db5aa05 1279 break;
8fc8598e 1280
1db5aa05
XR		 1281 case RF_8258:
1282 break;
8fc8598e 1283
1db5aa05
XR		 1284 default:
1285 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1286 return true;
1db5aa05 1287 }
8fc8598e 1288
8fc8598e 1289
1db5aa05
XR		 1290 do {
1291 switch (*stage) {
1292 case 0:
1293 CurrentCmd = &PreCommonCmd[*step];
1294 break;
1295 case 1:
1296 CurrentCmd = &RfDependCmd[*step];
1297 break;
1298 case 2:
1299 CurrentCmd = &PostCommonCmd[*step];
1300 break;
1301 }
1302
d2a5c987 1303 if (CurrentCmd->cmd_id == CMD_ID_END) {
1db5aa05 1304 if ((*stage) == 2) {
e918443c 1305 (*delay) = CurrentCmd->ms_delay;
1db5aa05 1306 return true;
8fc8598e 1307 }
bf1c66e8
KS		 1308 (*stage)++;
1309 (*step) = 0;
1310 continue;
1db5aa05 1311 }
8fc8598e 1312
d2a5c987 1313 switch (CurrentCmd->cmd_id) {
1be8f4e7 1314 case CMD_ID_SET_TX_PWR_LEVEL:
64749a7e 1315 if (priv->card_8192_version == VERSION_819XU_A)
1db5aa05
XR		 1316 /* consider it later! */
1317 rtl8192_SetTxPowerLevel(dev, channel);
8fc8598e 1318 break;
3ebdf34f 1319 case CMD_ID_WRITE_PORT_ULONG:
33f28ab7 1320 write_nic_dword(dev, CurrentCmd->para_1,
21807031 1321 CurrentCmd->para_2);
1db5aa05 1322 break;
61c9f41b 1323 case CMD_ID_WRITE_PORT_USHORT:
33f28ab7 1324 write_nic_word(dev, CurrentCmd->para_1,
21807031 1325 (u16)CurrentCmd->para_2);
1db5aa05 1326 break;
64641cf6 1327 case CMD_ID_WRITE_PORT_UCHAR:
33f28ab7 1328 write_nic_byte(dev, CurrentCmd->para_1,
21807031 1329 (u8)CurrentCmd->para_2);
1db5aa05 1330 break;
f6e1472a 1331 case CMD_ID_RF_WRITE_REG:
cc29db86 1332 for (e_rfpath = 0; e_rfpath < RF90_PATH_MAX; e_rfpath++) {
1db5aa05 1333 rtl8192_phy_SetRFReg(dev,
cc29db86 1334 (enum rf90_radio_path_e)e_rfpath,
33f28ab7 1335 CurrentCmd->para_1,
1db5aa05 1336 bZebra1_ChannelNum,
21807031 1337 CurrentCmd->para_2);
1db5aa05
XR		 1338 }
1339 break;
1340 default:
1341 break;
1342 }
1343
1344 break;
1345 } while (true);
8fc8598e 1346
e918443c 1347 (*delay) = CurrentCmd->ms_delay;
8fc8598e
JC		 1348 (*step)++;
1349 return false;
1350}
1351
1352/******************************************************************************
5f2392b8
XR		 1353 * function: This function does actually set channel work
1354 * input: net_device *dev
1355 * u8 channel
1356 * output: none
1357 * return: none
1358 * notice: We should not call this function directly
1359 *****************************************************************************/
c92f473d 1360static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
8fc8598e
JC		 1361{
1362 struct r8192_priv *priv = ieee80211_priv(dev);
1363 u32 delay = 0;
1364
1db5aa05
XR		 1365 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1366 &priv->SwChnlStep, &delay)) {
1111b876 1367 if (!priv->up)
8fc8598e
JC		 1368 break;
1369 }
1370}
0081fcc6 1371
8fc8598e 1372/******************************************************************************
5f2392b8
XR		 1373 * function: Callback routine of the work item for switch channel.
1374 * input: net_device *dev
8fc8598e 1375 *
5f2392b8
XR		 1376 * output: none
1377 * return: none
1378 *****************************************************************************/
8fc8598e
JC		 1379void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1380{
1381
1382 struct r8192_priv *priv = ieee80211_priv(dev);
1383
1db5aa05
XR		 1384 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1385 priv->chan);
8fc8598e
JC		 1386
1387
83e6d9e2 1388 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
8fc8598e
JC		 1389
1390 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1391}
1392
1393/******************************************************************************
5f2392b8
XR		 1394 * function: This function scheduled actual work item to set channel
1395 * input: net_device *dev
1396 * u8 channel //channel to set
1397 * output: none
1398 * return: return code show if workitem is scheduled (1:pass, 0:fail)
1399 * notice: Delay may be required for RF configuration
1400 ******************************************************************************/
88d8fe29 1401u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
8fc8598e
JC		 1402{
1403 struct r8192_priv *priv = ieee80211_priv(dev);
657eb979 1404
08a4cdea 1405 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1db5aa05 1406 priv->SwChnlInProgress);
1111b876 1407 if (!priv->up)
8fc8598e 1408 return false;
1111b876 1409 if (priv->SwChnlInProgress)
8fc8598e
JC		 1410 return false;
1411
5f2392b8 1412 /* -------------------------------------------- */
4a6094c3 1413 switch (priv->ieee80211->mode) {
8fc8598e
JC		 1414 case WIRELESS_MODE_A:
1415 case WIRELESS_MODE_N_5G:
9d8e79ed 1416 if (channel <= 14) {
0081fcc6 1417 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
8fc8598e
JC		 1418 return false;
1419 }
1420 break;
1421 case WIRELESS_MODE_B:
9d8e79ed 1422 if (channel > 14) {
0081fcc6 1423 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
8fc8598e
JC		 1424 return false;
1425 }
1426 break;
1427 case WIRELESS_MODE_G:
1428 case WIRELESS_MODE_N_24G:
9d8e79ed 1429 if (channel > 14) {
0081fcc6 1430 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
8fc8598e
JC		 1431 return false;
1432 }
1433 break;
1434 }
5f2392b8 1435 /* -------------------------------------------- */
8fc8598e
JC		 1436
1437 priv->SwChnlInProgress = true;
1111b876 1438 if (channel == 0)
8fc8598e
JC		 1439 channel = 1;
1440
ec5d319b 1441 priv->chan = channel;
8fc8598e 1442
ec5d319b
XR		 1443 priv->SwChnlStage = 0;
1444 priv->SwChnlStep = 0;
d75340eb 1445 if (priv->up)
1db5aa05 1446 rtl8192_SwChnl_WorkItem(dev);
8fc8598e
JC		 1447
1448 priv->SwChnlInProgress = false;
1449 return true;
1450}
1451
8fc8598e 1452/******************************************************************************
5f2392b8
XR		 1453 * function: Callback routine of the work item for set bandwidth mode.
1454 * input: net_device *dev
1455 * output: none
1456 * return: none
1457 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1458 * test whether current work in the queue or not.//do I?
1459 *****************************************************************************/
8fc8598e
JC		 1460void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1461{
1462
1463 struct r8192_priv *priv = ieee80211_priv(dev);
1464 u8 regBwOpMode;
1465
1db5aa05 1466 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__,
4a8d1135 1467 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
8fc8598e
JC		 1468
1469
1111b876 1470 if (priv->rf_chip == RF_PSEUDO_11N) {
ec5d319b 1471 priv->SetBWModeInProgress = false;
8fc8598e
JC		 1472 return;
1473 }
1474
5f2392b8 1475 /* <1> Set MAC register */
b3d42bf1 1476 read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
8fc8598e 1477
4a6094c3 1478 switch (priv->CurrentChannelBW) {
1db5aa05
XR		 1479 case HT_CHANNEL_WIDTH_20:
1480 regBwOpMode |= BW_OPMODE_20MHZ;
1481 /* We have not verify whether this register works */
1482 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1483 break;
8fc8598e 1484
1db5aa05
XR		 1485 case HT_CHANNEL_WIDTH_20_40:
1486 regBwOpMode &= ~BW_OPMODE_20MHZ;
1487 /* We have not verify whether this register works */
1488 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1489 break;
8fc8598e 1490
1db5aa05
XR		 1491 default:
1492 RT_TRACE(COMP_ERR,
1493 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1494 priv->CurrentChannelBW);
1495 break;
8fc8598e
JC		 1496 }
1497
5f2392b8 1498 /* <2> Set PHY related register */
4a6094c3 1499 switch (priv->CurrentChannelBW) {
1db5aa05
XR		 1500 case HT_CHANNEL_WIDTH_20:
1501 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1502 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1503 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1504 0x00100000, 1);
1505
1506 /* Correct the tx power for CCK rate in 20M. */
f78d7669
CIK		 1507 priv->cck_present_attenuation =
1508 priv->cck_present_attenuation_20Mdefault +
1509 priv->cck_present_attenuation_difference;
1510
1511 if (priv->cck_present_attenuation > 22)
1512 priv->cck_present_attenuation = 22;
1513 if (priv->cck_present_attenuation < 0)
1514 priv->cck_present_attenuation = 0;
1db5aa05
XR		 1515 RT_TRACE(COMP_INIT,
1516 "20M, pHalData->CCKPresentAttentuation = %d\n",
f78d7669 1517 priv->cck_present_attenuation);
1db5aa05
XR		 1518
1519 if (priv->chan == 14 && !priv->bcck_in_ch14) {
4b2faf80 1520 priv->bcck_in_ch14 = true;
1db5aa05
XR		 1521 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1522 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
4b2faf80 1523 priv->bcck_in_ch14 = false;
1db5aa05
XR		 1524 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1525 } else {
1526 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1527 }
8fc8598e 1528
1db5aa05
XR		 1529 break;
1530 case HT_CHANNEL_WIDTH_20_40:
1531 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1532 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1533 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
4ed6aba9 1534 priv->nCur40MhzPrimeSC >> 1);
1db5aa05
XR		 1535 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1536 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1537 priv->nCur40MhzPrimeSC);
f78d7669
CIK		 1538 priv->cck_present_attenuation =
1539 priv->cck_present_attenuation_40Mdefault +
1540 priv->cck_present_attenuation_difference;
1db5aa05 1541
f78d7669
CIK		 1542 if (priv->cck_present_attenuation > 22)
1543 priv->cck_present_attenuation = 22;
1544 if (priv->cck_present_attenuation < 0)
1545 priv->cck_present_attenuation = 0;
1db5aa05
XR		 1546
1547 RT_TRACE(COMP_INIT,
1548 "40M, pHalData->CCKPresentAttentuation = %d\n",
f78d7669 1549 priv->cck_present_attenuation);
1db5aa05
XR		 1550 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1551 priv->bcck_in_ch14 = true;
1552 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1553 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1554 priv->bcck_in_ch14 = false;
1555 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1556 } else {
1557 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1558 }
8fc8598e 1559
1db5aa05
XR		 1560 break;
1561 default:
1562 RT_TRACE(COMP_ERR,
1563 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1564 priv->CurrentChannelBW);
1565 break;
8fc8598e
JC		 1566
1567 }
5f2392b8 1568 /* Skip over setting of J-mode in BB register here.
991397d1
DR		 1569 * Default value is "None J mode".
1570 */
8fc8598e 1571
5f2392b8 1572 /* <3> Set RF related register */
ceb56597 1573 switch (priv->rf_chip) {
1db5aa05 1574 case RF_8225:
1db5aa05 1575 break;
8fc8598e 1576
1db5aa05 1577 case RF_8256:
7c671608 1578 phy_set_rf8256_bandwidth(dev, priv->CurrentChannelBW);
1db5aa05 1579 break;
8fc8598e 1580
1db5aa05
XR		 1581 case RF_8258:
1582 break;
8fc8598e 1583
1db5aa05
XR		 1584 case RF_PSEUDO_11N:
1585 break;
8fc8598e 1586
1db5aa05
XR		 1587 default:
1588 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1589 break;
8fc8598e 1590 }
ec5d319b 1591 priv->SetBWModeInProgress = false;
8fc8598e 1592
0081fcc6 1593 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1db5aa05 1594 atomic_read(&priv->ieee80211->atm_swbw));
8fc8598e
JC		 1595}
1596
1597/******************************************************************************
5f2392b8
XR		 1598 * function: This function schedules bandwidth switch work.
1599 * input: struct net_deviceq *dev
1600 * HT_CHANNEL_WIDTH bandwidth //20M or 40M
1601 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
1602 * output: none
1603 * return: none
1604 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1605 * test whether current work in the queue or not.//do I?
1606 *****************************************************************************/
0bde13ed
JW		 1607void rtl8192_SetBWMode(struct net_device *dev,
1608 enum ht_channel_width bandwidth,
1609 enum ht_extension_chan_offset offset)
8fc8598e
JC		 1610{
1611 struct r8192_priv *priv = ieee80211_priv(dev);
1612
1111b876 1613 if (priv->SetBWModeInProgress)
8fc8598e 1614 return;
ec5d319b 1615 priv->SetBWModeInProgress = true;
8fc8598e 1616
79931639 1617 priv->CurrentChannelBW = bandwidth;
8fc8598e 1618
79931639 1619 if (offset == HT_EXTCHNL_OFFSET_LOWER)
8fc8598e 1620 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
79931639 1621 else if (offset == HT_EXTCHNL_OFFSET_UPPER)
8fc8598e
JC		 1622 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1623 else
1624 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1625
8fc8598e
JC		 1626 rtl8192_SetBWModeWorkItem(dev);
1627
1628}
1629
1630void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1631{
1632 struct r8192_priv *priv = ieee80211_priv(dev);
1633
1634 priv->InitialGainOperateType = Operation;
1635
1111b876 1636 if (priv->up)
83e6d9e2 1637 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
8fc8598e
JC		 1638}
1639
a115ee41 1640void InitialGainOperateWorkItemCallBack(struct work_struct *work)
8fc8598e 1641{
a5959f3f 1642 struct delayed_work *dwork = to_delayed_work(work);
1db5aa05
XR		 1643 struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1644 initialgain_operate_wq);
1645 struct net_device *dev = priv->ieee80211->dev;
8fc8598e
JC		 1646#define SCAN_RX_INITIAL_GAIN 0x17
1647#define POWER_DETECTION_TH 0x08
9f66ddb5 1648 u32 bitmask;
8fc8598e
JC		 1649 u8 initial_gain;
1650 u8 Operation;
1651
1652 Operation = priv->InitialGainOperateType;
1653
4a6094c3 1654 switch (Operation) {
1db5aa05
XR		 1655 case IG_Backup:
1656 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1657 initial_gain = SCAN_RX_INITIAL_GAIN;
1658 bitmask = bMaskByte0;
1659 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1660 /* FW DIG OFF */
1661 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1662 priv->initgain_backup.xaagccore1 =
1663 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1664 priv->initgain_backup.xbagccore1 =
1665 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1666 priv->initgain_backup.xcagccore1 =
1667 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1668 priv->initgain_backup.xdagccore1 =
1669 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1670 bitmask = bMaskByte2;
1671 priv->initgain_backup.cca =
1672 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1673
1674 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1675 priv->initgain_backup.xaagccore1);
1676 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1677 priv->initgain_backup.xbagccore1);
1678 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1679 priv->initgain_backup.xcagccore1);
1680 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1681 priv->initgain_backup.xdagccore1);
1682 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1683 priv->initgain_backup.cca);
1684
d5133e75 1685 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1db5aa05
XR		 1686 initial_gain);
1687 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1688 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1689 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1690 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
d5133e75 1691 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1db5aa05
XR		 1692 POWER_DETECTION_TH);
1693 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1694 break;
1695 case IG_Restore:
1696 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1697 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1698 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1699 /* FW DIG OFF */
1700 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1701
1702 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1703 (u32)priv->initgain_backup.xaagccore1);
1704 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1705 (u32)priv->initgain_backup.xbagccore1);
1706 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1707 (u32)priv->initgain_backup.xcagccore1);
1708 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1709 (u32)priv->initgain_backup.xdagccore1);
1710 bitmask = bMaskByte2;
1711 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1712 (u32)priv->initgain_backup.cca);
1713
1714 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1715 priv->initgain_backup.xaagccore1);
1716 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1717 priv->initgain_backup.xbagccore1);
1718 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1719 priv->initgain_backup.xcagccore1);
1720 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1721 priv->initgain_backup.xdagccore1);
1722 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1723 priv->initgain_backup.cca);
8fc8598e 1724
1db5aa05 1725 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
8fc8598e 1726
1db5aa05
XR		 1727 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1728 /* FW DIG ON */
1729 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1730 break;
1731 default:
d5133e75 1732 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1db5aa05 1733 break;
8fc8598e
JC		 1734 }
1735}
Linux 6.x block layer and io_uring tree(s)