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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
8fc8598e JC |
2 | /*++ |
3 | Copyright-c Realtek Semiconductor Corp. All rights reserved. | |
4 | ||
5 | Module Name: | |
6 | r8192U_dm.c | |
7 | ||
8 | Abstract: | |
9 | HW dynamic mechanism. | |
10 | ||
11 | Major Change History: | |
35997ff0 | 12 | When Who What |
8fc8598e JC |
13 | ---------- --------------- ------------------------------- |
14 | 2008-05-14 amy create version 0 porting from windows code. | |
15 | ||
16 | --*/ | |
17 | #include "r8192U.h" | |
18 | #include "r8192U_dm.h" | |
19 | #include "r8192U_hw.h" | |
20 | #include "r819xU_phy.h" | |
21 | #include "r819xU_phyreg.h" | |
22 | #include "r8190_rtl8256.h" | |
23 | #include "r819xU_cmdpkt.h" | |
24 | /*---------------------------Define Local Constant---------------------------*/ | |
e1da1d57 | 25 | /* Indicate different AP vendor for IOT issue. */ |
04d695d7 LS |
26 | static u32 edca_setting_DL[HT_IOT_PEER_MAX] = { |
27 | 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0x00a44f, 0x5ea44f | |
28 | }; | |
c4309727 | 29 | |
04d695d7 LS |
30 | static u32 edca_setting_UL[HT_IOT_PEER_MAX] = { |
31 | 0x5e4322, 0x00a44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f | |
32 | }; | |
8fc8598e JC |
33 | |
34 | #define RTK_UL_EDCA 0xa44f | |
35 | #define RTK_DL_EDCA 0x5e4322 | |
36 | /*---------------------------Define Local Constant---------------------------*/ | |
37 | ||
38 | ||
39 | /*------------------------Define global variable-----------------------------*/ | |
e1da1d57 | 40 | /* Debug variable ? */ |
70dada1a | 41 | struct dig dm_digtable; |
e1da1d57 | 42 | /* Store current software write register content for MAC PHY. */ |
04d695d7 | 43 | u8 dm_shadow[16][256] = { {0} }; |
e1da1d57 | 44 | /* For Dynamic Rx Path Selection by Signal Strength */ |
916501c8 | 45 | static struct dynamic_rx_path_sel DM_RxPathSelTable; |
70dada1a | 46 | |
8fc8598e | 47 | extern void dm_check_fsync(struct net_device *dev); |
8fc8598e | 48 | |
e1da1d57 | 49 | /* DM --> Rate Adaptive */ |
8fc8598e JC |
50 | static void dm_check_rate_adaptive(struct net_device *dev); |
51 | ||
e1da1d57 | 52 | /* DM --> Bandwidth switch */ |
8fc8598e | 53 | static void dm_init_bandwidth_autoswitch(struct net_device *dev); |
0009631b | 54 | static void dm_bandwidth_autoswitch(struct net_device *dev); |
8fc8598e | 55 | |
e1da1d57 LS |
56 | /* DM --> TX power control */ |
57 | /*static void dm_initialize_txpower_tracking(struct net_device *dev);*/ | |
8fc8598e JC |
58 | |
59 | static void dm_check_txpower_tracking(struct net_device *dev); | |
60 | ||
e1da1d57 | 61 | /*static void dm_txpower_reset_recovery(struct net_device *dev);*/ |
8fc8598e | 62 | |
e1da1d57 | 63 | /* DM --> Dynamic Init Gain by RSSI */ |
8fc8598e JC |
64 | static void dm_dig_init(struct net_device *dev); |
65 | static void dm_ctrl_initgain_byrssi(struct net_device *dev); | |
66 | static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev); | |
0009631b | 67 | static void dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev); |
8fc8598e JC |
68 | static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev); |
69 | static void dm_initial_gain(struct net_device *dev); | |
70 | static void dm_pd_th(struct net_device *dev); | |
71 | static void dm_cs_ratio(struct net_device *dev); | |
72 | ||
73 | static void dm_init_ctstoself(struct net_device *dev); | |
e1da1d57 | 74 | /* DM --> EDCA turbo mode control */ |
8fc8598e JC |
75 | static void dm_check_edca_turbo(struct net_device *dev); |
76 | ||
e1da1d57 LS |
77 | /*static void dm_gpio_change_rf(struct net_device *dev);*/ |
78 | /* DM --> Check PBC */ | |
8fc8598e JC |
79 | static void dm_check_pbc_gpio(struct net_device *dev); |
80 | ||
e1da1d57 | 81 | /* DM --> Check current RX RF path state */ |
8fc8598e | 82 | static void dm_check_rx_path_selection(struct net_device *dev); |
35997ff0 | 83 | static void dm_init_rxpath_selection(struct net_device *dev); |
8fc8598e JC |
84 | static void dm_rxpath_sel_byrssi(struct net_device *dev); |
85 | ||
e1da1d57 | 86 | /* DM --> Fsync for broadcom ap */ |
8fc8598e JC |
87 | static void dm_init_fsync(struct net_device *dev); |
88 | static void dm_deInit_fsync(struct net_device *dev); | |
89 | ||
e1da1d57 | 90 | /* Added by vivi, 20080522 */ |
8fc8598e JC |
91 | static void dm_check_txrateandretrycount(struct net_device *dev); |
92 | ||
93 | /*---------------------Define local function prototype-----------------------*/ | |
94 | ||
e1da1d57 | 95 | /*---------------------Define of Tx Power Control For Near/Far Range --------*/ /*Add by Jacken 2008/02/18 */ |
8fc8598e JC |
96 | static void dm_init_dynamic_txpower(struct net_device *dev); |
97 | static void dm_dynamic_txpower(struct net_device *dev); | |
98 | ||
e1da1d57 | 99 | /* DM --> For rate adaptive and DIG, we must send RSSI to firmware */ |
8fc8598e JC |
100 | static void dm_send_rssi_tofw(struct net_device *dev); |
101 | static void dm_ctstoself(struct net_device *dev); | |
102 | /*---------------------------Define function prototype------------------------*/ | |
d8718e45 | 103 | /* ================================================================================ |
e1da1d57 LS |
104 | * HW Dynamic mechanism interface. |
105 | * ================================================================================ | |
106 | * | |
107 | * | |
108 | * Description: | |
109 | * Prepare SW resource for HW dynamic mechanism. | |
110 | * | |
111 | * Assumption: | |
69e98df7 | 112 | * This function is only invoked at driver initialization once. |
e1da1d57 | 113 | */ |
bf316434 | 114 | void init_hal_dm(struct net_device *dev) |
8fc8598e JC |
115 | { |
116 | struct r8192_priv *priv = ieee80211_priv(dev); | |
117 | ||
e1da1d57 | 118 | /* Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. */ |
8fc8598e JC |
119 | priv->undecorated_smoothed_pwdb = -1; |
120 | ||
e1da1d57 | 121 | /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */ |
8fc8598e JC |
122 | dm_init_dynamic_txpower(dev); |
123 | init_rate_adaptive(dev); | |
e1da1d57 | 124 | /*dm_initialize_txpower_tracking(dev);*/ |
8fc8598e JC |
125 | dm_dig_init(dev); |
126 | dm_init_edca_turbo(dev); | |
127 | dm_init_bandwidth_autoswitch(dev); | |
128 | dm_init_fsync(dev); | |
129 | dm_init_rxpath_selection(dev); | |
130 | dm_init_ctstoself(dev); | |
131 | ||
e1da1d57 | 132 | } /* InitHalDm */ |
8fc8598e | 133 | |
c541fa87 | 134 | void deinit_hal_dm(struct net_device *dev) |
8fc8598e | 135 | { |
8fc8598e | 136 | dm_deInit_fsync(dev); |
8fc8598e JC |
137 | } |
138 | ||
8fc8598e | 139 | #ifdef USB_RX_AGGREGATION_SUPPORT |
04d695d7 LS |
140 | void dm_CheckRxAggregation(struct net_device *dev) |
141 | { | |
efdcb35a | 142 | struct r8192_priv *priv = ieee80211_priv(dev); |
8fc8598e | 143 | PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; |
de13a3da SH |
144 | static unsigned long lastTxOkCnt; |
145 | static unsigned long lastRxOkCnt; | |
8fc8598e JC |
146 | unsigned long curTxOkCnt = 0; |
147 | unsigned long curRxOkCnt = 0; | |
148 | ||
149 | /* | |
150 | if (pHalData->bForcedUsbRxAggr) { | |
151 | if (pHalData->ForcedUsbRxAggrInfo == 0) { | |
152 | if (pHalData->bCurrentRxAggrEnable) { | |
153 | Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE); | |
154 | } | |
155 | } else { | |
156 | if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) { | |
157 | Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE); | |
158 | } | |
159 | } | |
160 | return; | |
161 | } | |
162 | ||
163 | */ | |
164 | curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; | |
165 | curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; | |
166 | ||
2930d0b9 | 167 | if ((curTxOkCnt + curRxOkCnt) < 15000000) |
8fc8598e | 168 | return; |
8fc8598e | 169 | |
04d695d7 | 170 | if (curTxOkCnt > 4*curRxOkCnt) { |
8fc8598e JC |
171 | if (priv->bCurrentRxAggrEnable) { |
172 | write_nic_dword(dev, 0x1a8, 0); | |
173 | priv->bCurrentRxAggrEnable = false; | |
174 | } | |
04d695d7 | 175 | } else { |
8fc8598e JC |
176 | if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) { |
177 | u32 ulValue; | |
04d695d7 | 178 | |
8fc8598e JC |
179 | ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | |
180 | (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); | |
d8718e45 | 181 | /* If usb rx firmware aggregation is enabled, |
8fc8598e JC |
182 | * when anyone of three threshold conditions above is reached, |
183 | * firmware will send aggregated packet to driver. | |
184 | */ | |
185 | write_nic_dword(dev, 0x1a8, ulValue); | |
186 | priv->bCurrentRxAggrEnable = true; | |
187 | } | |
188 | } | |
189 | ||
190 | lastTxOkCnt = priv->stats.txbytesunicast; | |
191 | lastRxOkCnt = priv->stats.rxbytesunicast; | |
e1da1d57 | 192 | } /* dm_CheckEdcaTurbo */ |
8fc8598e JC |
193 | #endif |
194 | ||
bf316434 | 195 | void hal_dm_watchdog(struct net_device *dev) |
8fc8598e | 196 | { |
e1da1d57 | 197 | /*struct r8192_priv *priv = ieee80211_priv(dev);*/ |
8fc8598e | 198 | |
e1da1d57 | 199 | /*static u8 previous_bssid[6] ={0};*/ |
8fc8598e JC |
200 | |
201 | /*Add by amy 2008/05/15 ,porting from windows code.*/ | |
202 | dm_check_rate_adaptive(dev); | |
203 | dm_dynamic_txpower(dev); | |
204 | dm_check_txrateandretrycount(dev); | |
205 | dm_check_txpower_tracking(dev); | |
206 | dm_ctrl_initgain_byrssi(dev); | |
207 | dm_check_edca_turbo(dev); | |
208 | dm_bandwidth_autoswitch(dev); | |
8fc8598e JC |
209 | dm_check_rx_path_selection(dev); |
210 | dm_check_fsync(dev); | |
211 | ||
e1da1d57 | 212 | /* Add by amy 2008-05-15 porting from windows code. */ |
8fc8598e JC |
213 | dm_check_pbc_gpio(dev); |
214 | dm_send_rssi_tofw(dev); | |
215 | dm_ctstoself(dev); | |
216 | #ifdef USB_RX_AGGREGATION_SUPPORT | |
217 | dm_CheckRxAggregation(dev); | |
218 | #endif | |
e1da1d57 | 219 | } /* HalDmWatchDog */ |
8fc8598e | 220 | |
d8718e45 | 221 | /* Decide Rate Adaptive Set according to distance (signal strength) |
e1da1d57 LS |
222 | * 01/11/2008 MHC Modify input arguments and RATR table level. |
223 | * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call | |
224 | * the function after making sure RF_Type. | |
225 | */ | |
c541fa87 | 226 | void init_rate_adaptive(struct net_device *dev) |
8fc8598e | 227 | { |
8fc8598e JC |
228 | struct r8192_priv *priv = ieee80211_priv(dev); |
229 | prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; | |
230 | ||
231 | pra->ratr_state = DM_RATR_STA_MAX; | |
0395a9aa | 232 | pra->high2low_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH; |
c972be9a JW |
233 | pra->low2high_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M + 5; |
234 | pra->low2high_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M + 5; | |
8fc8598e | 235 | |
0395a9aa | 236 | pra->high_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH + 5; |
c972be9a JW |
237 | pra->low_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M; |
238 | pra->low_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M; | |
8fc8598e | 239 | |
04d695d7 | 240 | if (priv->CustomerID == RT_CID_819x_Netcore) |
8fc8598e JC |
241 | pra->ping_rssi_enable = 1; |
242 | else | |
243 | pra->ping_rssi_enable = 0; | |
244 | pra->ping_rssi_thresh_for_ra = 15; | |
245 | ||
04d695d7 | 246 | if (priv->rf_type == RF_2T4R) { |
d8718e45 | 247 | /* 07/10/08 MH Modify for RA smooth scheme. |
e1da1d57 LS |
248 | * 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code. |
249 | */ | |
35997ff0 SH |
250 | pra->upper_rssi_threshold_ratr = 0x8f0f0000; |
251 | pra->middle_rssi_threshold_ratr = 0x8f0ff000; | |
252 | pra->low_rssi_threshold_ratr = 0x8f0ff001; | |
253 | pra->low_rssi_threshold_ratr_40M = 0x8f0ff005; | |
254 | pra->low_rssi_threshold_ratr_20M = 0x8f0ff001; | |
e1da1d57 | 255 | pra->ping_rssi_ratr = 0x0000000d;/* cosa add for test */ |
04d695d7 | 256 | } else if (priv->rf_type == RF_1T2R) { |
35997ff0 SH |
257 | pra->upper_rssi_threshold_ratr = 0x000f0000; |
258 | pra->middle_rssi_threshold_ratr = 0x000ff000; | |
259 | pra->low_rssi_threshold_ratr = 0x000ff001; | |
260 | pra->low_rssi_threshold_ratr_40M = 0x000ff005; | |
261 | pra->low_rssi_threshold_ratr_20M = 0x000ff001; | |
e1da1d57 | 262 | pra->ping_rssi_ratr = 0x0000000d;/* cosa add for test */ |
8fc8598e JC |
263 | } |
264 | ||
e1da1d57 | 265 | } /* InitRateAdaptive */ |
8fc8598e | 266 | |
8fc8598e JC |
267 | /*----------------------------------------------------------------------------- |
268 | * Function: dm_check_rate_adaptive() | |
269 | * | |
270 | * Overview: | |
271 | * | |
272 | * Input: NONE | |
273 | * | |
274 | * Output: NONE | |
275 | * | |
276 | * Return: NONE | |
277 | * | |
278 | * Revised History: | |
279 | * When Who Remark | |
35997ff0 | 280 | * 05/26/08 amy Create version 0 porting from windows code. |
8fc8598e JC |
281 | * |
282 | *---------------------------------------------------------------------------*/ | |
999d594b | 283 | static void dm_check_rate_adaptive(struct net_device *dev) |
8fc8598e JC |
284 | { |
285 | struct r8192_priv *priv = ieee80211_priv(dev); | |
286 | PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; | |
287 | prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; | |
288 | u32 currentRATR, targetRATR = 0; | |
289 | u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0; | |
290 | bool bshort_gi_enabled = false; | |
de13a3da | 291 | static u8 ping_rssi_state; |
8fc8598e | 292 | |
04d695d7 | 293 | if (!priv->up) { |
8fc8598e JC |
294 | RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n"); |
295 | return; | |
296 | } | |
297 | ||
04d695d7 | 298 | if (pra->rate_adaptive_disabled) /* this variable is set by ioctl. */ |
8fc8598e JC |
299 | return; |
300 | ||
e1da1d57 | 301 | /* TODO: Only 11n mode is implemented currently, */ |
04d695d7 LS |
302 | if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G || |
303 | priv->ieee80211->mode == WIRELESS_MODE_N_5G)) | |
304 | return; | |
8fc8598e | 305 | |
04d695d7 | 306 | if (priv->ieee80211->state == IEEE80211_LINKED) { |
e1da1d57 | 307 | /*RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");*/ |
8fc8598e | 308 | |
e1da1d57 | 309 | /* Check whether Short GI is enabled */ |
8fc8598e JC |
310 | bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) || |
311 | (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz); | |
312 | ||
8fc8598e | 313 | pra->upper_rssi_threshold_ratr = |
56b3152e AB |
314 | (pra->upper_rssi_threshold_ratr & (~BIT(31))) | |
315 | ((bshort_gi_enabled) ? BIT(31) : 0); | |
8fc8598e JC |
316 | |
317 | pra->middle_rssi_threshold_ratr = | |
56b3152e AB |
318 | (pra->middle_rssi_threshold_ratr & (~BIT(31))) | |
319 | ((bshort_gi_enabled) ? BIT(31) : 0); | |
8fc8598e | 320 | |
04d695d7 | 321 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
8fc8598e | 322 | pra->low_rssi_threshold_ratr = |
56b3152e AB |
323 | (pra->low_rssi_threshold_ratr_40M & (~BIT(31))) | |
324 | ((bshort_gi_enabled) ? BIT(31) : 0); | |
04d695d7 | 325 | } else { |
8fc8598e | 326 | pra->low_rssi_threshold_ratr = |
56b3152e AB |
327 | (pra->low_rssi_threshold_ratr_20M & (~BIT(31))) | |
328 | ((bshort_gi_enabled) ? BIT(31) : 0); | |
8fc8598e | 329 | } |
e1da1d57 | 330 | /* cosa add for test */ |
8fc8598e | 331 | pra->ping_rssi_ratr = |
56b3152e AB |
332 | (pra->ping_rssi_ratr & (~BIT(31))) | |
333 | ((bshort_gi_enabled) ? BIT(31) : 0); | |
8fc8598e JC |
334 | |
335 | /* 2007/10/08 MH We support RA smooth scheme now. When it is the first | |
0dbc8368 CM |
336 | * time to link with AP. We will not change upper/lower threshold. If |
337 | * STA stay in high or low level, we must change two different threshold | |
338 | * to prevent jumping frequently. | |
339 | */ | |
04d695d7 | 340 | if (pra->ratr_state == DM_RATR_STA_HIGH) { |
35997ff0 | 341 | HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra; |
04d695d7 | 342 | LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? |
8fc8598e | 343 | (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); |
04d695d7 | 344 | } else if (pra->ratr_state == DM_RATR_STA_LOW) { |
8fc8598e | 345 | HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; |
04d695d7 | 346 | LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? |
8fc8598e | 347 | (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M); |
04d695d7 | 348 | } else { |
8fc8598e | 349 | HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; |
04d695d7 | 350 | LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? |
8fc8598e JC |
351 | (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); |
352 | } | |
353 | ||
e1da1d57 | 354 | /*DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);*/ |
04d695d7 | 355 | if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) { |
e1da1d57 | 356 | /*DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);*/ |
8fc8598e JC |
357 | pra->ratr_state = DM_RATR_STA_HIGH; |
358 | targetRATR = pra->upper_rssi_threshold_ratr; | |
04d695d7 | 359 | } else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) { |
e1da1d57 | 360 | /*DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);*/ |
8fc8598e JC |
361 | pra->ratr_state = DM_RATR_STA_MIDDLE; |
362 | targetRATR = pra->middle_rssi_threshold_ratr; | |
04d695d7 | 363 | } else { |
e1da1d57 | 364 | /*DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);*/ |
8fc8598e JC |
365 | pra->ratr_state = DM_RATR_STA_LOW; |
366 | targetRATR = pra->low_rssi_threshold_ratr; | |
367 | } | |
368 | ||
e1da1d57 | 369 | /* cosa add for test */ |
04d695d7 | 370 | if (pra->ping_rssi_enable) { |
e1da1d57 | 371 | /*pHalData->UndecoratedSmoothedPWDB = 19;*/ |
04d695d7 LS |
372 | if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) { |
373 | if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) || | |
374 | ping_rssi_state) { | |
375 | /*DbgPrint("TestRSSI = %d, set RATR to 0x%x\n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);*/ | |
8fc8598e JC |
376 | pra->ratr_state = DM_RATR_STA_LOW; |
377 | targetRATR = pra->ping_rssi_ratr; | |
378 | ping_rssi_state = 1; | |
379 | } | |
e1da1d57 | 380 | /*else |
04d695d7 LS |
381 | DbgPrint("TestRSSI is between the range.\n");*/ |
382 | } else { | |
383 | /*DbgPrint("TestRSSI Recover to 0x%x\n", targetRATR);*/ | |
8fc8598e JC |
384 | ping_rssi_state = 0; |
385 | } | |
386 | } | |
387 | ||
d8718e45 | 388 | /* 2008.04.01 |
e1da1d57 LS |
389 | * For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7. |
390 | */ | |
04d695d7 LS |
391 | if (priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev)) |
392 | targetRATR &= 0xf00fffff; | |
8fc8598e | 393 | |
e1da1d57 | 394 | /* Check whether updating of RATR0 is required */ |
b3d42bf1 | 395 | read_nic_dword(dev, RATR0, ¤tRATR); |
04d695d7 | 396 | if (targetRATR != currentRATR) { |
8fc8598e | 397 | u32 ratr_value; |
04d695d7 | 398 | |
8fc8598e | 399 | ratr_value = targetRATR; |
04d695d7 | 400 | RT_TRACE(COMP_RATE, "currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR); |
16da7808 | 401 | if (priv->rf_type == RF_1T2R) |
8fc8598e | 402 | ratr_value &= ~(RATE_ALL_OFDM_2SS); |
8fc8598e JC |
403 | write_nic_dword(dev, RATR0, ratr_value); |
404 | write_nic_byte(dev, UFWP, 1); | |
405 | ||
406 | pra->last_ratr = targetRATR; | |
407 | } | |
408 | ||
04d695d7 | 409 | } else { |
8fc8598e JC |
410 | pra->ratr_state = DM_RATR_STA_MAX; |
411 | } | |
412 | ||
e1da1d57 | 413 | } /* dm_CheckRateAdaptive */ |
8fc8598e | 414 | |
999d594b | 415 | static void dm_init_bandwidth_autoswitch(struct net_device *dev) |
8fc8598e JC |
416 | { |
417 | struct r8192_priv *priv = ieee80211_priv(dev); | |
418 | ||
419 | priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH; | |
420 | priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW; | |
421 | priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; | |
422 | priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false; | |
423 | ||
e1da1d57 | 424 | } /* dm_init_bandwidth_autoswitch */ |
8fc8598e | 425 | |
999d594b | 426 | static void dm_bandwidth_autoswitch(struct net_device *dev) |
8fc8598e JC |
427 | { |
428 | struct r8192_priv *priv = ieee80211_priv(dev); | |
429 | ||
16da7808 | 430 | if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || !priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable) |
8fc8598e | 431 | return; |
f9bd549a | 432 | if (!priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz) { /* If send packets in 40 Mhz in 20/40 */ |
04d695d7 | 433 | if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz) |
2fd8feab | 434 | priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true; |
04d695d7 LS |
435 | } else { /* in force send packets in 20 Mhz in 20/40 */ |
436 | if (priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz) | |
2fd8feab | 437 | priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; |
8fc8598e | 438 | } |
e1da1d57 | 439 | } /* dm_BandwidthAutoSwitch */ |
8fc8598e | 440 | |
e1da1d57 | 441 | /* OFDM default at 0db, index=6. */ |
8fc8598e | 442 | static u32 OFDMSwingTable[OFDM_Table_Length] = { |
e1da1d57 LS |
443 | 0x7f8001fe, /* 0, +6db */ |
444 | 0x71c001c7, /* 1, +5db */ | |
445 | 0x65400195, /* 2, +4db */ | |
446 | 0x5a400169, /* 3, +3db */ | |
447 | 0x50800142, /* 4, +2db */ | |
448 | 0x47c0011f, /* 5, +1db */ | |
449 | 0x40000100, /* 6, +0db ===> default, upper for higher temperature, lower for low temperature */ | |
450 | 0x390000e4, /* 7, -1db */ | |
451 | 0x32c000cb, /* 8, -2db */ | |
452 | 0x2d4000b5, /* 9, -3db */ | |
453 | 0x288000a2, /* 10, -4db */ | |
454 | 0x24000090, /* 11, -5db */ | |
455 | 0x20000080, /* 12, -6db */ | |
456 | 0x1c800072, /* 13, -7db */ | |
457 | 0x19800066, /* 14, -8db */ | |
458 | 0x26c0005b, /* 15, -9db */ | |
459 | 0x24400051, /* 16, -10db */ | |
460 | 0x12000048, /* 17, -11db */ | |
461 | 0x10000040 /* 18, -12db */ | |
8fc8598e JC |
462 | }; |
463 | ||
464 | static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = { | |
e1da1d57 LS |
465 | {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0db ===> CCK40M default */ |
466 | {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 1, -1db */ | |
467 | {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 2, -2db */ | |
468 | {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 3, -3db */ | |
469 | {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 4, -4db */ | |
470 | {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 5, -5db */ | |
471 | {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 6, -6db ===> CCK20M default */ | |
472 | {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 7, -7db */ | |
473 | {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 8, -8db */ | |
474 | {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 9, -9db */ | |
475 | {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 10, -10db */ | |
476 | {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} /* 11, -11db */ | |
8fc8598e JC |
477 | }; |
478 | ||
479 | static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = { | |
e1da1d57 LS |
480 | {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0db ===> CCK40M default */ |
481 | {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 1, -1db */ | |
482 | {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 2, -2db */ | |
483 | {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 3, -3db */ | |
484 | {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 4, -4db */ | |
485 | {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 5, -5db */ | |
486 | {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 6, -6db ===> CCK20M default */ | |
487 | {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 7, -7db */ | |
488 | {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 8, -8db */ | |
489 | {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 9, -9db */ | |
490 | {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 10, -10db */ | |
491 | {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} /* 11, -11db */ | |
8fc8598e JC |
492 | }; |
493 | ||
999d594b | 494 | static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev) |
8fc8598e JC |
495 | { |
496 | struct r8192_priv *priv = ieee80211_priv(dev); | |
e9d93154 | 497 | bool viviflag = false; |
d3c90eff | 498 | struct tx_config_cmd tx_cmd; |
8fc8598e | 499 | u8 powerlevelOFDM24G; |
04d695d7 LS |
500 | int i = 0, j = 0, k = 0; |
501 | u8 RF_Type, tmp_report[5] = {0, 0, 0, 0, 0}; | |
8fc8598e JC |
502 | u32 Value; |
503 | u8 Pwr_Flag; | |
04d695d7 | 504 | u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0; |
e1da1d57 | 505 | /*RT_STATUS rtStatus = RT_STATUS_SUCCESS;*/ |
8fc8598e | 506 | bool rtStatus = true; |
04d695d7 | 507 | u32 delta = 0; |
8fc8598e JC |
508 | |
509 | write_nic_byte(dev, 0x1ba, 0); | |
510 | ||
511 | priv->ieee80211->bdynamic_txpower_enable = false; | |
8fc8598e JC |
512 | |
513 | powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24); | |
514 | RF_Type = priv->rf_type; | |
515 | Value = (RF_Type<<8) | powerlevelOFDM24G; | |
516 | ||
517 | RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G); | |
518 | ||
04d695d7 | 519 | for (j = 0; j <= 30; j++) { /* fill tx_cmd */ |
d3c90eff JW |
520 | tx_cmd.cmd_op = TXCMD_SET_TX_PWR_TRACKING; |
521 | tx_cmd.cmd_length = sizeof(tx_cmd.cmd_op); | |
522 | tx_cmd.cmd_value = Value; | |
523 | rtStatus = SendTxCommandPacket(dev, &tx_cmd, sizeof(struct tx_config_cmd)); | |
16da7808 | 524 | if (rtStatus == RT_STATUS_FAILURE) |
04d695d7 | 525 | RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n"); |
72cbd314 | 526 | usleep_range(1000, 2000); |
04d695d7 LS |
527 | /*DbgPrint("hi, vivi, strange\n");*/ |
528 | for (i = 0; i <= 30; i++) { | |
529 | read_nic_byte(dev, 0x1ba, &Pwr_Flag); | |
530 | ||
531 | if (Pwr_Flag == 0) { | |
72cbd314 | 532 | usleep_range(1000, 2000); |
04d695d7 LS |
533 | continue; |
534 | } | |
535 | read_nic_word(dev, 0x13c, &Avg_TSSI_Meas); | |
536 | if (Avg_TSSI_Meas == 0) { | |
537 | write_nic_byte(dev, 0x1ba, 0); | |
8fc8598e JC |
538 | break; |
539 | } | |
8fc8598e | 540 | |
04d695d7 LS |
541 | for (k = 0; k < 5; k++) { |
542 | if (k != 4) | |
543 | read_nic_byte(dev, 0x134+k, &tmp_report[k]); | |
544 | else | |
545 | read_nic_byte(dev, 0x13e, &tmp_report[k]); | |
546 | RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]); | |
547 | } | |
8fc8598e | 548 | |
04d695d7 LS |
549 | /* check if the report value is right */ |
550 | for (k = 0; k < 5; k++) { | |
551 | if (tmp_report[k] <= 20) { | |
4b2faf80 | 552 | viviflag = true; |
04d695d7 | 553 | break; |
8fc8598e JC |
554 | } |
555 | } | |
c40753b5 | 556 | if (viviflag) { |
04d695d7 | 557 | write_nic_byte(dev, 0x1ba, 0); |
4b2faf80 | 558 | viviflag = false; |
04d695d7 LS |
559 | RT_TRACE(COMP_POWER_TRACKING, "we filtered the data\n"); |
560 | for (k = 0; k < 5; k++) | |
561 | tmp_report[k] = 0; | |
562 | break; | |
563 | } | |
8fc8598e | 564 | |
16da7808 | 565 | for (k = 0; k < 5; k++) |
04d695d7 | 566 | Avg_TSSI_Meas_from_driver += tmp_report[k]; |
8fc8598e | 567 | |
04d695d7 LS |
568 | Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5; |
569 | RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver); | |
570 | TSSI_13dBm = priv->TSSI_13dBm; | |
571 | RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm); | |
572 | ||
573 | /*if (abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)*/ | |
574 | /* For MacOS-compatible */ | |
575 | if (Avg_TSSI_Meas_from_driver > TSSI_13dBm) | |
576 | delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm; | |
8fc8598e | 577 | else |
04d695d7 LS |
578 | delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver; |
579 | ||
580 | if (delta <= E_FOR_TX_POWER_TRACK) { | |
4b2faf80 | 581 | priv->ieee80211->bdynamic_txpower_enable = true; |
04d695d7 LS |
582 | write_nic_byte(dev, 0x1ba, 0); |
583 | RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n"); | |
584 | RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); | |
585 | RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); | |
f78d7669 CIK |
586 | RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference); |
587 | RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation); | |
04d695d7 | 588 | return; |
16da7808 LS |
589 | } |
590 | if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) { | |
591 | if (priv->rfa_txpowertrackingindex > 0) { | |
592 | priv->rfa_txpowertrackingindex--; | |
593 | if (priv->rfa_txpowertrackingindex_real > 4) { | |
594 | priv->rfa_txpowertrackingindex_real--; | |
04d695d7 | 595 | rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); |
04d695d7 | 596 | } |
8fc8598e | 597 | } |
16da7808 LS |
598 | } else { |
599 | if (priv->rfa_txpowertrackingindex < 36) { | |
600 | priv->rfa_txpowertrackingindex++; | |
601 | priv->rfa_txpowertrackingindex_real++; | |
602 | rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); | |
04d695d7 | 603 | } |
16da7808 | 604 | } |
f78d7669 | 605 | priv->cck_present_attenuation_difference |
16da7808 | 606 | = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default; |
04d695d7 | 607 | |
16da7808 | 608 | if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) |
f78d7669 CIK |
609 | priv->cck_present_attenuation |
610 | = priv->cck_present_attenuation_20Mdefault + priv->cck_present_attenuation_difference; | |
16da7808 | 611 | else |
f78d7669 CIK |
612 | priv->cck_present_attenuation |
613 | = priv->cck_present_attenuation_40Mdefault + priv->cck_present_attenuation_difference; | |
16da7808 | 614 | |
f78d7669 | 615 | if (priv->cck_present_attenuation > -1 && priv->cck_present_attenuation < 23) { |
16da7808 | 616 | if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) { |
4b2faf80 | 617 | priv->bcck_in_ch14 = true; |
16da7808 LS |
618 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
619 | } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) { | |
4b2faf80 | 620 | priv->bcck_in_ch14 = false; |
16da7808 LS |
621 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
622 | } else | |
623 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
624 | } | |
625 | RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); | |
626 | RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); | |
f78d7669 CIK |
627 | RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference); |
628 | RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation); | |
04d695d7 | 629 | |
f78d7669 | 630 | if (priv->cck_present_attenuation_difference <= -12 || priv->cck_present_attenuation_difference >= 24) { |
4b2faf80 | 631 | priv->ieee80211->bdynamic_txpower_enable = true; |
16da7808 LS |
632 | write_nic_byte(dev, 0x1ba, 0); |
633 | RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n"); | |
634 | return; | |
8fc8598e | 635 | } |
16da7808 | 636 | |
8fc8598e | 637 | write_nic_byte(dev, 0x1ba, 0); |
04d695d7 LS |
638 | Avg_TSSI_Meas_from_driver = 0; |
639 | for (k = 0; k < 5; k++) | |
640 | tmp_report[k] = 0; | |
641 | break; | |
8fc8598e | 642 | } |
8fc8598e | 643 | } |
4b2faf80 | 644 | priv->ieee80211->bdynamic_txpower_enable = true; |
04d695d7 | 645 | write_nic_byte(dev, 0x1ba, 0); |
8fc8598e JC |
646 | } |
647 | ||
999d594b | 648 | static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev) |
8fc8598e JC |
649 | { |
650 | #define ThermalMeterVal 9 | |
651 | struct r8192_priv *priv = ieee80211_priv(dev); | |
652 | u32 tmpRegA, TempCCk; | |
653 | u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval; | |
04d695d7 | 654 | int i = 0, CCKSwingNeedUpdate = 0; |
8fc8598e | 655 | |
04d695d7 | 656 | if (!priv->btxpower_trackingInit) { |
e1da1d57 | 657 | /* Query OFDM default setting */ |
04d695d7 LS |
658 | tmpRegA = rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); |
659 | for (i = 0; i < OFDM_Table_Length; i++) { /* find the index */ | |
660 | if (tmpRegA == OFDMSwingTable[i]) { | |
661 | priv->OFDM_index = (u8)i; | |
8fc8598e JC |
662 | RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n", |
663 | rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index); | |
664 | } | |
665 | } | |
666 | ||
e1da1d57 | 667 | /* Query CCK default setting From 0xa22 */ |
8fc8598e | 668 | TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); |
04d695d7 LS |
669 | for (i = 0; i < CCK_Table_length; i++) { |
670 | if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) { | |
671 | priv->CCK_index = (u8) i; | |
8fc8598e JC |
672 | RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n", |
673 | rCCK0_TxFilter1, TempCCk, priv->CCK_index); | |
674 | break; | |
675 | } | |
676 | } | |
4b2faf80 | 677 | priv->btxpower_trackingInit = true; |
e1da1d57 | 678 | /*pHalData->TXPowercount = 0;*/ |
8fc8598e JC |
679 | return; |
680 | } | |
681 | ||
d8718e45 | 682 | /* ========================== |
e1da1d57 LS |
683 | * this is only for test, should be masked |
684 | * ========================== | |
685 | */ | |
8fc8598e | 686 | |
e1da1d57 LS |
687 | /* read and filter out unreasonable value */ |
688 | tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); /* 0x12: RF Reg[10:7] */ | |
04d695d7 LS |
689 | RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA); |
690 | if (tmpRegA < 3 || tmpRegA > 13) | |
8fc8598e | 691 | return; |
04d695d7 | 692 | if (tmpRegA >= 12) /* if over 12, TP will be bad when high temperature */ |
8fc8598e | 693 | tmpRegA = 12; |
04d695d7 | 694 | RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d\n", tmpRegA); |
e1da1d57 LS |
695 | priv->ThermalMeter[0] = ThermalMeterVal; /* We use fixed value by Bryant's suggestion */ |
696 | priv->ThermalMeter[1] = ThermalMeterVal; /* We use fixed value by Bryant's suggestion */ | |
8fc8598e | 697 | |
e1da1d57 | 698 | /* Get current RF-A temperature index */ |
04d695d7 | 699 | if (priv->ThermalMeter[0] >= (u8)tmpRegA) { /* lower temperature */ |
8fc8598e JC |
700 | tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA); |
701 | tmpCCK40Mindex = tmpCCK20Mindex - 6; | |
04d695d7 | 702 | if (tmpOFDMindex >= OFDM_Table_Length) |
8fc8598e | 703 | tmpOFDMindex = OFDM_Table_Length-1; |
04d695d7 | 704 | if (tmpCCK20Mindex >= CCK_Table_length) |
8fc8598e | 705 | tmpCCK20Mindex = CCK_Table_length-1; |
04d695d7 | 706 | if (tmpCCK40Mindex >= CCK_Table_length) |
8fc8598e | 707 | tmpCCK40Mindex = CCK_Table_length-1; |
04d695d7 | 708 | } else { |
2060f31a | 709 | tmpval = (u8)tmpRegA - priv->ThermalMeter[0]; |
04d695d7 | 710 | |
4cad1589 GS |
711 | if (tmpval >= 6) { |
712 | /* higher temperature */ | |
713 | tmpOFDMindex = 0; | |
714 | tmpCCK20Mindex = 0; | |
715 | } else { | |
716 | /* max to +6dB */ | |
717 | tmpOFDMindex = 6 - tmpval; | |
718 | tmpCCK20Mindex = 6 - tmpval; | |
719 | } | |
8fc8598e JC |
720 | tmpCCK40Mindex = 0; |
721 | } | |
e1da1d57 LS |
722 | /*DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d", |
723 | ((u1Byte)tmpRegA - pHalData->ThermalMeter[0]), | |
724 | tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);*/ | |
04d695d7 | 725 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) /* 40M */ |
8fc8598e JC |
726 | tmpCCKindex = tmpCCK40Mindex; |
727 | else | |
728 | tmpCCKindex = tmpCCK20Mindex; | |
729 | ||
04d695d7 | 730 | if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) { |
4b2faf80 | 731 | priv->bcck_in_ch14 = true; |
8fc8598e | 732 | CCKSwingNeedUpdate = 1; |
04d695d7 | 733 | } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) { |
4b2faf80 | 734 | priv->bcck_in_ch14 = false; |
8fc8598e JC |
735 | CCKSwingNeedUpdate = 1; |
736 | } | |
737 | ||
04d695d7 | 738 | if (priv->CCK_index != tmpCCKindex) { |
8fc8598e JC |
739 | priv->CCK_index = tmpCCKindex; |
740 | CCKSwingNeedUpdate = 1; | |
741 | } | |
742 | ||
04d695d7 | 743 | if (CCKSwingNeedUpdate) { |
e1da1d57 | 744 | /*DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);*/ |
8fc8598e JC |
745 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
746 | } | |
04d695d7 | 747 | if (priv->OFDM_index != tmpOFDMindex) { |
8fc8598e JC |
748 | priv->OFDM_index = tmpOFDMindex; |
749 | rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]); | |
750 | RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n", | |
751 | priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]); | |
752 | } | |
753 | priv->txpower_count = 0; | |
754 | } | |
755 | ||
bf316434 | 756 | void dm_txpower_trackingcallback(struct work_struct *work) |
8fc8598e | 757 | { |
a5959f3f | 758 | struct delayed_work *dwork = to_delayed_work(work); |
04d695d7 LS |
759 | struct r8192_priv *priv = container_of(dwork, struct r8192_priv, txpower_tracking_wq); |
760 | struct net_device *dev = priv->ieee80211->dev; | |
8fc8598e | 761 | |
c40753b5 | 762 | if (priv->bDcut) |
8fc8598e JC |
763 | dm_TXPowerTrackingCallback_TSSI(dev); |
764 | else | |
765 | dm_TXPowerTrackingCallback_ThermalMeter(dev); | |
8fc8598e JC |
766 | } |
767 | ||
8fc8598e JC |
768 | static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev) |
769 | { | |
8fc8598e JC |
770 | struct r8192_priv *priv = ieee80211_priv(dev); |
771 | ||
e1da1d57 | 772 | /* Initial the Tx BB index and mapping value */ |
35997ff0 | 773 | priv->txbbgain_table[0].txbb_iq_amplifygain = 12; |
04d695d7 | 774 | priv->txbbgain_table[0].txbbgain_value = 0x7f8001fe; |
35997ff0 | 775 | priv->txbbgain_table[1].txbb_iq_amplifygain = 11; |
04d695d7 | 776 | priv->txbbgain_table[1].txbbgain_value = 0x788001e2; |
35997ff0 | 777 | priv->txbbgain_table[2].txbb_iq_amplifygain = 10; |
04d695d7 | 778 | priv->txbbgain_table[2].txbbgain_value = 0x71c001c7; |
35997ff0 | 779 | priv->txbbgain_table[3].txbb_iq_amplifygain = 9; |
04d695d7 | 780 | priv->txbbgain_table[3].txbbgain_value = 0x6b8001ae; |
35997ff0 | 781 | priv->txbbgain_table[4].txbb_iq_amplifygain = 8; |
04d695d7 | 782 | priv->txbbgain_table[4].txbbgain_value = 0x65400195; |
35997ff0 | 783 | priv->txbbgain_table[5].txbb_iq_amplifygain = 7; |
04d695d7 | 784 | priv->txbbgain_table[5].txbbgain_value = 0x5fc0017f; |
35997ff0 | 785 | priv->txbbgain_table[6].txbb_iq_amplifygain = 6; |
04d695d7 | 786 | priv->txbbgain_table[6].txbbgain_value = 0x5a400169; |
35997ff0 | 787 | priv->txbbgain_table[7].txbb_iq_amplifygain = 5; |
04d695d7 | 788 | priv->txbbgain_table[7].txbbgain_value = 0x55400155; |
35997ff0 | 789 | priv->txbbgain_table[8].txbb_iq_amplifygain = 4; |
04d695d7 | 790 | priv->txbbgain_table[8].txbbgain_value = 0x50800142; |
35997ff0 | 791 | priv->txbbgain_table[9].txbb_iq_amplifygain = 3; |
04d695d7 | 792 | priv->txbbgain_table[9].txbbgain_value = 0x4c000130; |
35997ff0 | 793 | priv->txbbgain_table[10].txbb_iq_amplifygain = 2; |
04d695d7 | 794 | priv->txbbgain_table[10].txbbgain_value = 0x47c0011f; |
35997ff0 | 795 | priv->txbbgain_table[11].txbb_iq_amplifygain = 1; |
04d695d7 | 796 | priv->txbbgain_table[11].txbbgain_value = 0x43c0010f; |
35997ff0 | 797 | priv->txbbgain_table[12].txbb_iq_amplifygain = 0; |
04d695d7 | 798 | priv->txbbgain_table[12].txbbgain_value = 0x40000100; |
35997ff0 | 799 | priv->txbbgain_table[13].txbb_iq_amplifygain = -1; |
04d695d7 | 800 | priv->txbbgain_table[13].txbbgain_value = 0x3c8000f2; |
35997ff0 | 801 | priv->txbbgain_table[14].txbb_iq_amplifygain = -2; |
04d695d7 | 802 | priv->txbbgain_table[14].txbbgain_value = 0x390000e4; |
35997ff0 | 803 | priv->txbbgain_table[15].txbb_iq_amplifygain = -3; |
04d695d7 | 804 | priv->txbbgain_table[15].txbbgain_value = 0x35c000d7; |
35997ff0 | 805 | priv->txbbgain_table[16].txbb_iq_amplifygain = -4; |
04d695d7 | 806 | priv->txbbgain_table[16].txbbgain_value = 0x32c000cb; |
35997ff0 | 807 | priv->txbbgain_table[17].txbb_iq_amplifygain = -5; |
04d695d7 | 808 | priv->txbbgain_table[17].txbbgain_value = 0x300000c0; |
35997ff0 | 809 | priv->txbbgain_table[18].txbb_iq_amplifygain = -6; |
04d695d7 | 810 | priv->txbbgain_table[18].txbbgain_value = 0x2d4000b5; |
35997ff0 | 811 | priv->txbbgain_table[19].txbb_iq_amplifygain = -7; |
04d695d7 | 812 | priv->txbbgain_table[19].txbbgain_value = 0x2ac000ab; |
35997ff0 | 813 | priv->txbbgain_table[20].txbb_iq_amplifygain = -8; |
04d695d7 | 814 | priv->txbbgain_table[20].txbbgain_value = 0x288000a2; |
35997ff0 | 815 | priv->txbbgain_table[21].txbb_iq_amplifygain = -9; |
04d695d7 | 816 | priv->txbbgain_table[21].txbbgain_value = 0x26000098; |
35997ff0 | 817 | priv->txbbgain_table[22].txbb_iq_amplifygain = -10; |
04d695d7 | 818 | priv->txbbgain_table[22].txbbgain_value = 0x24000090; |
35997ff0 | 819 | priv->txbbgain_table[23].txbb_iq_amplifygain = -11; |
04d695d7 | 820 | priv->txbbgain_table[23].txbbgain_value = 0x22000088; |
35997ff0 | 821 | priv->txbbgain_table[24].txbb_iq_amplifygain = -12; |
04d695d7 | 822 | priv->txbbgain_table[24].txbbgain_value = 0x20000080; |
35997ff0 | 823 | priv->txbbgain_table[25].txbb_iq_amplifygain = -13; |
04d695d7 | 824 | priv->txbbgain_table[25].txbbgain_value = 0x1a00006c; |
35997ff0 | 825 | priv->txbbgain_table[26].txbb_iq_amplifygain = -14; |
04d695d7 | 826 | priv->txbbgain_table[26].txbbgain_value = 0x1c800072; |
35997ff0 | 827 | priv->txbbgain_table[27].txbb_iq_amplifygain = -15; |
04d695d7 | 828 | priv->txbbgain_table[27].txbbgain_value = 0x18000060; |
35997ff0 | 829 | priv->txbbgain_table[28].txbb_iq_amplifygain = -16; |
04d695d7 | 830 | priv->txbbgain_table[28].txbbgain_value = 0x19800066; |
35997ff0 | 831 | priv->txbbgain_table[29].txbb_iq_amplifygain = -17; |
04d695d7 | 832 | priv->txbbgain_table[29].txbbgain_value = 0x15800056; |
35997ff0 | 833 | priv->txbbgain_table[30].txbb_iq_amplifygain = -18; |
04d695d7 | 834 | priv->txbbgain_table[30].txbbgain_value = 0x26c0005b; |
35997ff0 | 835 | priv->txbbgain_table[31].txbb_iq_amplifygain = -19; |
04d695d7 | 836 | priv->txbbgain_table[31].txbbgain_value = 0x14400051; |
35997ff0 | 837 | priv->txbbgain_table[32].txbb_iq_amplifygain = -20; |
04d695d7 | 838 | priv->txbbgain_table[32].txbbgain_value = 0x24400051; |
35997ff0 | 839 | priv->txbbgain_table[33].txbb_iq_amplifygain = -21; |
04d695d7 | 840 | priv->txbbgain_table[33].txbbgain_value = 0x1300004c; |
35997ff0 | 841 | priv->txbbgain_table[34].txbb_iq_amplifygain = -22; |
04d695d7 | 842 | priv->txbbgain_table[34].txbbgain_value = 0x12000048; |
35997ff0 | 843 | priv->txbbgain_table[35].txbb_iq_amplifygain = -23; |
04d695d7 | 844 | priv->txbbgain_table[35].txbbgain_value = 0x11000044; |
35997ff0 | 845 | priv->txbbgain_table[36].txbb_iq_amplifygain = -24; |
04d695d7 | 846 | priv->txbbgain_table[36].txbbgain_value = 0x10000040; |
8fc8598e | 847 | |
d8718e45 | 848 | /* ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 |
e1da1d57 LS |
849 | * This Table is for CH1~CH13 |
850 | */ | |
8fc8598e JC |
851 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36; |
852 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35; | |
853 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e; | |
854 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25; | |
855 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c; | |
856 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12; | |
857 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09; | |
858 | priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04; | |
859 | ||
860 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33; | |
861 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32; | |
862 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b; | |
863 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23; | |
864 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a; | |
865 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11; | |
866 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08; | |
867 | priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04; | |
868 | ||
869 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30; | |
870 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f; | |
871 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29; | |
872 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21; | |
873 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19; | |
874 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10; | |
875 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08; | |
876 | priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03; | |
877 | ||
878 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d; | |
879 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d; | |
880 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27; | |
881 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f; | |
882 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18; | |
883 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f; | |
884 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08; | |
885 | priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03; | |
886 | ||
887 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b; | |
888 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a; | |
889 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25; | |
890 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e; | |
891 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16; | |
892 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e; | |
893 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07; | |
894 | priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03; | |
895 | ||
896 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28; | |
897 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28; | |
898 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22; | |
899 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c; | |
900 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15; | |
901 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d; | |
902 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07; | |
903 | priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03; | |
904 | ||
905 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26; | |
906 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25; | |
907 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21; | |
908 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b; | |
909 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14; | |
910 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d; | |
911 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06; | |
912 | priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03; | |
913 | ||
914 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24; | |
915 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23; | |
916 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f; | |
917 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19; | |
918 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13; | |
919 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c; | |
920 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06; | |
921 | priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03; | |
922 | ||
923 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22; | |
924 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21; | |
925 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d; | |
926 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18; | |
927 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11; | |
928 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b; | |
929 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06; | |
930 | priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02; | |
931 | ||
932 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20; | |
933 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20; | |
934 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b; | |
935 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16; | |
936 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11; | |
937 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08; | |
938 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05; | |
939 | priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02; | |
940 | ||
941 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f; | |
942 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e; | |
943 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a; | |
944 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15; | |
945 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10; | |
946 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a; | |
947 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05; | |
948 | priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02; | |
949 | ||
950 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d; | |
951 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c; | |
952 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18; | |
953 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14; | |
954 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f; | |
955 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a; | |
956 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05; | |
957 | priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02; | |
958 | ||
959 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b; | |
960 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a; | |
961 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17; | |
962 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13; | |
963 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e; | |
964 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09; | |
965 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04; | |
966 | priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02; | |
967 | ||
968 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a; | |
969 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19; | |
970 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16; | |
971 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12; | |
972 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d; | |
973 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09; | |
974 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04; | |
975 | priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02; | |
976 | ||
977 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18; | |
978 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17; | |
979 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15; | |
980 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11; | |
981 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c; | |
982 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08; | |
983 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04; | |
984 | priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02; | |
985 | ||
986 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17; | |
987 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16; | |
988 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13; | |
989 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10; | |
990 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c; | |
991 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08; | |
992 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04; | |
993 | priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02; | |
994 | ||
995 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16; | |
996 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15; | |
997 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12; | |
998 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f; | |
999 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b; | |
1000 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07; | |
1001 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04; | |
1002 | priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01; | |
1003 | ||
1004 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14; | |
1005 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14; | |
1006 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11; | |
1007 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e; | |
1008 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b; | |
1009 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07; | |
1010 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03; | |
1011 | priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02; | |
1012 | ||
1013 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13; | |
1014 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13; | |
1015 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10; | |
1016 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d; | |
1017 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a; | |
1018 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06; | |
1019 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03; | |
1020 | priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01; | |
1021 | ||
1022 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12; | |
1023 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12; | |
1024 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f; | |
1025 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c; | |
1026 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09; | |
1027 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06; | |
1028 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03; | |
1029 | priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01; | |
1030 | ||
1031 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11; | |
1032 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11; | |
1033 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f; | |
1034 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c; | |
1035 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09; | |
1036 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06; | |
1037 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03; | |
1038 | priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01; | |
1039 | ||
1040 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10; | |
1041 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10; | |
1042 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e; | |
1043 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b; | |
1044 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08; | |
1045 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05; | |
1046 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03; | |
1047 | priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01; | |
1048 | ||
1049 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f; | |
1050 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f; | |
1051 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d; | |
1052 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b; | |
1053 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08; | |
1054 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05; | |
1055 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03; | |
1056 | priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01; | |
1057 | ||
d8718e45 | 1058 | /* ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 |
e1da1d57 LS |
1059 | * This Table is for CH14 |
1060 | */ | |
8fc8598e JC |
1061 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36; |
1062 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35; | |
1063 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e; | |
1064 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b; | |
1065 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00; | |
1066 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00; | |
1067 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00; | |
1068 | priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00; | |
1069 | ||
1070 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33; | |
1071 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32; | |
1072 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b; | |
1073 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19; | |
1074 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00; | |
1075 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00; | |
1076 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00; | |
1077 | priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00; | |
1078 | ||
1079 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30; | |
1080 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f; | |
1081 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29; | |
1082 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18; | |
1083 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00; | |
1084 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00; | |
1085 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00; | |
1086 | priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00; | |
1087 | ||
1088 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d; | |
1089 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d; | |
1090 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27; | |
1091 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17; | |
1092 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00; | |
1093 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00; | |
1094 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00; | |
1095 | priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00; | |
1096 | ||
1097 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b; | |
1098 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a; | |
1099 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25; | |
1100 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15; | |
1101 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00; | |
1102 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00; | |
1103 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00; | |
1104 | priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00; | |
1105 | ||
1106 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28; | |
1107 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28; | |
1108 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22; | |
1109 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14; | |
1110 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00; | |
1111 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00; | |
1112 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00; | |
1113 | priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00; | |
1114 | ||
1115 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26; | |
1116 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25; | |
1117 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21; | |
1118 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13; | |
1119 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00; | |
1120 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00; | |
1121 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00; | |
1122 | priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00; | |
1123 | ||
1124 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24; | |
1125 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23; | |
1126 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f; | |
1127 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12; | |
1128 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00; | |
1129 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00; | |
1130 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00; | |
1131 | priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00; | |
1132 | ||
1133 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22; | |
1134 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21; | |
1135 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d; | |
1136 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11; | |
1137 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00; | |
1138 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00; | |
1139 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00; | |
1140 | priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00; | |
1141 | ||
1142 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20; | |
1143 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20; | |
1144 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b; | |
1145 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10; | |
1146 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00; | |
1147 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00; | |
1148 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00; | |
1149 | priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00; | |
1150 | ||
1151 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f; | |
1152 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e; | |
1153 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a; | |
1154 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f; | |
1155 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00; | |
1156 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00; | |
1157 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00; | |
1158 | priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00; | |
1159 | ||
1160 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d; | |
1161 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c; | |
1162 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18; | |
1163 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e; | |
1164 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00; | |
1165 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00; | |
1166 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00; | |
1167 | priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00; | |
1168 | ||
1169 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b; | |
1170 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a; | |
1171 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17; | |
1172 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e; | |
1173 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00; | |
1174 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00; | |
1175 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00; | |
1176 | priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00; | |
1177 | ||
1178 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a; | |
1179 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19; | |
1180 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16; | |
1181 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d; | |
1182 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00; | |
1183 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00; | |
1184 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00; | |
1185 | priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00; | |
1186 | ||
1187 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18; | |
1188 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17; | |
1189 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15; | |
1190 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c; | |
1191 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00; | |
1192 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00; | |
1193 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00; | |
1194 | priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00; | |
1195 | ||
1196 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17; | |
1197 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16; | |
1198 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13; | |
1199 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b; | |
1200 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00; | |
1201 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00; | |
1202 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00; | |
1203 | priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00; | |
1204 | ||
1205 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16; | |
1206 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15; | |
1207 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12; | |
1208 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b; | |
1209 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00; | |
1210 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00; | |
1211 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00; | |
1212 | priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00; | |
1213 | ||
1214 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14; | |
1215 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14; | |
1216 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11; | |
1217 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a; | |
1218 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00; | |
1219 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00; | |
1220 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00; | |
1221 | priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00; | |
1222 | ||
1223 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13; | |
1224 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13; | |
1225 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10; | |
1226 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a; | |
1227 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00; | |
1228 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00; | |
1229 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00; | |
1230 | priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00; | |
1231 | ||
1232 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12; | |
1233 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12; | |
1234 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f; | |
1235 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09; | |
1236 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00; | |
1237 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00; | |
1238 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00; | |
1239 | priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00; | |
1240 | ||
1241 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11; | |
1242 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11; | |
1243 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f; | |
1244 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09; | |
1245 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00; | |
1246 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00; | |
1247 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00; | |
1248 | priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00; | |
1249 | ||
1250 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10; | |
1251 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10; | |
1252 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e; | |
1253 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08; | |
1254 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00; | |
1255 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00; | |
1256 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00; | |
1257 | priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00; | |
1258 | ||
1259 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f; | |
1260 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f; | |
1261 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d; | |
1262 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08; | |
1263 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00; | |
1264 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00; | |
1265 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00; | |
1266 | priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00; | |
1267 | ||
4b2faf80 | 1268 | priv->btxpower_tracking = true; |
8fc8598e | 1269 | priv->txpower_count = 0; |
4b2faf80 | 1270 | priv->btxpower_trackingInit = false; |
8fc8598e JC |
1271 | } |
1272 | ||
1273 | static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev) | |
1274 | { | |
1275 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1276 | ||
d8718e45 | 1277 | /* Tx Power tracking by Thermal Meter requires Firmware R/W 3-wire. This mechanism |
e1da1d57 LS |
1278 | * can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w |
1279 | * 3-wire by driver causes RF to go into a wrong state. | |
1280 | */ | |
04d695d7 | 1281 | if (priv->ieee80211->FwRWRF) |
4b2faf80 | 1282 | priv->btxpower_tracking = true; |
8fc8598e | 1283 | else |
4b2faf80 | 1284 | priv->btxpower_tracking = false; |
8fc8598e | 1285 | priv->txpower_count = 0; |
4b2faf80 | 1286 | priv->btxpower_trackingInit = false; |
8fc8598e JC |
1287 | } |
1288 | ||
8fc8598e JC |
1289 | void dm_initialize_txpower_tracking(struct net_device *dev) |
1290 | { | |
1291 | struct r8192_priv *priv = ieee80211_priv(dev); | |
04d695d7 | 1292 | |
c40753b5 | 1293 | if (priv->bDcut) |
8fc8598e JC |
1294 | dm_InitializeTXPowerTracking_TSSI(dev); |
1295 | else | |
1296 | dm_InitializeTXPowerTracking_ThermalMeter(dev); | |
e1da1d57 | 1297 | } /* dm_InitializeTXPowerTracking */ |
8fc8598e | 1298 | |
8fc8598e JC |
1299 | static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev) |
1300 | { | |
1301 | struct r8192_priv *priv = ieee80211_priv(dev); | |
de13a3da | 1302 | static u32 tx_power_track_counter; |
8fc8598e | 1303 | |
04d695d7 | 1304 | if (!priv->btxpower_tracking) |
8fc8598e | 1305 | return; |
16da7808 LS |
1306 | if ((tx_power_track_counter % 30 == 0) && (tx_power_track_counter != 0)) |
1307 | queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0); | |
1308 | tx_power_track_counter++; | |
8fc8598e JC |
1309 | } |
1310 | ||
8fc8598e JC |
1311 | static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev) |
1312 | { | |
1313 | struct r8192_priv *priv = ieee80211_priv(dev); | |
de13a3da | 1314 | static u8 TM_Trigger; |
04d695d7 LS |
1315 | /*DbgPrint("dm_CheckTXPowerTracking()\n");*/ |
1316 | if (!priv->btxpower_tracking) | |
8fc8598e | 1317 | return; |
16da7808 LS |
1318 | if (priv->txpower_count <= 2) { |
1319 | priv->txpower_count++; | |
1320 | return; | |
8fc8598e JC |
1321 | } |
1322 | ||
04d695d7 | 1323 | if (!TM_Trigger) { |
d8718e45 | 1324 | /* Attention!! You have to write all 12bits of data to RF, or it may cause RF to crash |
e1da1d57 LS |
1325 | * actually write reg0x02 bit1=0, then bit1=1. |
1326 | * DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n"); | |
1327 | */ | |
8fc8598e JC |
1328 | rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); |
1329 | rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); | |
1330 | rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); | |
1331 | rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); | |
1332 | TM_Trigger = 1; | |
1333 | return; | |
8fc8598e | 1334 | } |
16da7808 | 1335 | /*DbgPrint("Schedule TxPowerTrackingWorkItem\n");*/ |
4b2c85ca | 1336 | queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0); |
16da7808 | 1337 | TM_Trigger = 0; |
8fc8598e JC |
1338 | } |
1339 | ||
8fc8598e JC |
1340 | static void dm_check_txpower_tracking(struct net_device *dev) |
1341 | { | |
1342 | struct r8192_priv *priv = ieee80211_priv(dev); | |
e1da1d57 | 1343 | /*static u32 tx_power_track_counter = 0;*/ |
8fc8598e | 1344 | |
04d695d7 | 1345 | #ifdef RTL8190P |
8fc8598e JC |
1346 | dm_CheckTXPowerTracking_TSSI(dev); |
1347 | #else | |
c40753b5 | 1348 | if (priv->bDcut) |
8fc8598e JC |
1349 | dm_CheckTXPowerTracking_TSSI(dev); |
1350 | else | |
1351 | dm_CheckTXPowerTracking_ThermalMeter(dev); | |
1352 | #endif | |
1353 | ||
e1da1d57 | 1354 | } /* dm_CheckTXPowerTracking */ |
8fc8598e | 1355 | |
8fc8598e JC |
1356 | static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14) |
1357 | { | |
1358 | u32 TempVal; | |
1359 | struct r8192_priv *priv = ieee80211_priv(dev); | |
04d695d7 | 1360 | |
e1da1d57 | 1361 | /* Write 0xa22 0xa23 */ |
8fc8598e | 1362 | TempVal = 0; |
04d695d7 | 1363 | if (!bInCH14) { |
e1da1d57 | 1364 | /* Write 0xa22 0xa23 */ |
f78d7669 CIK |
1365 | TempVal = priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] + |
1366 | (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8); | |
8fc8598e | 1367 | |
0b4ef0a6 | 1368 | rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); |
e1da1d57 | 1369 | /* Write 0xa24 ~ 0xa27 */ |
f78d7669 CIK |
1370 | TempVal = priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] + |
1371 | (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) + | |
1372 | (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+ | |
1373 | (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24); | |
0b4ef0a6 | 1374 | rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); |
e1da1d57 | 1375 | /* Write 0xa28 0xa29 */ |
f78d7669 CIK |
1376 | TempVal = priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] + |
1377 | (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8); | |
8fc8598e | 1378 | |
0b4ef0a6 | 1379 | rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); |
04d695d7 | 1380 | } else { |
f78d7669 CIK |
1381 | TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] + |
1382 | (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8); | |
8fc8598e | 1383 | |
0b4ef0a6 | 1384 | rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); |
e1da1d57 | 1385 | /* Write 0xa24 ~ 0xa27 */ |
f78d7669 CIK |
1386 | TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] + |
1387 | (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) + | |
1388 | (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+ | |
1389 | (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24); | |
0b4ef0a6 | 1390 | rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); |
e1da1d57 | 1391 | /* Write 0xa28 0xa29 */ |
f78d7669 CIK |
1392 | TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] + |
1393 | (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8); | |
8fc8598e | 1394 | |
0b4ef0a6 | 1395 | rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); |
8fc8598e | 1396 | } |
8fc8598e JC |
1397 | } |
1398 | ||
04d695d7 | 1399 | static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14) |
8fc8598e JC |
1400 | { |
1401 | u32 TempVal; | |
1402 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1403 | ||
1404 | TempVal = 0; | |
04d695d7 | 1405 | if (!bInCH14) { |
e1da1d57 | 1406 | /* Write 0xa22 0xa23 */ |
35997ff0 | 1407 | TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + |
04d695d7 | 1408 | (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8); |
8fc8598e JC |
1409 | rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); |
1410 | RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", | |
1411 | rCCK0_TxFilter1, TempVal); | |
e1da1d57 | 1412 | /* Write 0xa24 ~ 0xa27 */ |
35997ff0 | 1413 | TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] + |
8fc8598e | 1414 | (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) + |
0009631b | 1415 | (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+ |
8fc8598e JC |
1416 | (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24); |
1417 | rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); | |
1418 | RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", | |
1419 | rCCK0_TxFilter2, TempVal); | |
e1da1d57 | 1420 | /* Write 0xa28 0xa29 */ |
35997ff0 | 1421 | TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + |
04d695d7 | 1422 | (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8); |
8fc8598e JC |
1423 | |
1424 | rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); | |
1425 | RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", | |
1426 | rCCK0_DebugPort, TempVal); | |
04d695d7 | 1427 | } else { |
e1da1d57 LS |
1428 | /*priv->CCKTxPowerAdjustCntNotCh14++; cosa add for debug.*/ |
1429 | /* Write 0xa22 0xa23 */ | |
35997ff0 | 1430 | TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + |
04d695d7 | 1431 | (CCKSwingTable_Ch14[priv->CCK_index][1]<<8); |
8fc8598e JC |
1432 | |
1433 | rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); | |
1434 | RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", | |
f981a79e | 1435 | rCCK0_TxFilter1, TempVal); |
e1da1d57 | 1436 | /* Write 0xa24 ~ 0xa27 */ |
35997ff0 | 1437 | TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] + |
8fc8598e | 1438 | (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) + |
0009631b | 1439 | (CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+ |
8fc8598e JC |
1440 | (CCKSwingTable_Ch14[priv->CCK_index][5]<<24); |
1441 | rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); | |
1442 | RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", | |
f981a79e | 1443 | rCCK0_TxFilter2, TempVal); |
e1da1d57 | 1444 | /* Write 0xa28 0xa29 */ |
35997ff0 | 1445 | TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + |
04d695d7 | 1446 | (CCKSwingTable_Ch14[priv->CCK_index][7]<<8); |
8fc8598e JC |
1447 | |
1448 | rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); | |
0b4ef0a6 | 1449 | RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", |
f981a79e | 1450 | rCCK0_DebugPort, TempVal); |
8fc8598e JC |
1451 | } |
1452 | } | |
1453 | ||
bf316434 | 1454 | void dm_cck_txpower_adjust(struct net_device *dev, bool binch14) |
e1da1d57 | 1455 | { /* dm_CCKTxPowerAdjust */ |
8fc8598e | 1456 | struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d7 | 1457 | |
c40753b5 | 1458 | if (priv->bDcut) |
8fc8598e JC |
1459 | dm_CCKTxPowerAdjust_TSSI(dev, binch14); |
1460 | else | |
1461 | dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14); | |
8fc8598e JC |
1462 | } |
1463 | ||
04d695d7 | 1464 | #ifndef RTL8192U |
8fc8598e JC |
1465 | static void dm_txpower_reset_recovery( |
1466 | struct net_device *dev | |
1467 | ) | |
1468 | { | |
1469 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1470 | ||
1471 | RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n"); | |
1472 | rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); | |
04d695d7 LS |
1473 | RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); |
1474 | RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n", priv->rfa_txpowertrackingindex); | |
1475 | RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain); | |
f78d7669 | 1476 | RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n", priv->cck_present_attenuation); |
0b4ef0a6 | 1477 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
8fc8598e JC |
1478 | |
1479 | rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); | |
04d695d7 LS |
1480 | RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); |
1481 | RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n", priv->rfc_txpowertrackingindex); | |
1482 | RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain); | |
8fc8598e | 1483 | |
e1da1d57 | 1484 | } /* dm_TXPowerResetRecovery */ |
8fc8598e | 1485 | |
bf316434 | 1486 | void dm_restore_dynamic_mechanism_state(struct net_device *dev) |
8fc8598e JC |
1487 | { |
1488 | struct r8192_priv *priv = ieee80211_priv(dev); | |
35997ff0 | 1489 | u32 reg_ratr = priv->rate_adaptive.last_ratr; |
8fc8598e | 1490 | |
04d695d7 | 1491 | if (!priv->up) { |
8fc8598e JC |
1492 | RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n"); |
1493 | return; | |
1494 | } | |
1495 | ||
e1da1d57 | 1496 | /* Restore previous state for rate adaptive */ |
04d695d7 | 1497 | if (priv->rate_adaptive.rate_adaptive_disabled) |
8fc8598e | 1498 | return; |
e1da1d57 | 1499 | /* TODO: Only 11n mode is implemented currently, */ |
04d695d7 | 1500 | if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G || |
f981a79e | 1501 | priv->ieee80211->mode == WIRELESS_MODE_N_5G)) |
04d695d7 LS |
1502 | return; |
1503 | ||
8fc8598e JC |
1504 | { |
1505 | /* 2007/11/15 MH Copy from 8190PCI. */ | |
1506 | u32 ratr_value; | |
04d695d7 | 1507 | |
8fc8598e | 1508 | ratr_value = reg_ratr; |
04d695d7 | 1509 | if (priv->rf_type == RF_1T2R) { /* 1T2R, Spatial Stream 2 should be disabled */ |
33c2aa14 | 1510 | ratr_value &= ~(RATE_ALL_OFDM_2SS); |
e1da1d57 | 1511 | /*DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);*/ |
8fc8598e | 1512 | } |
e1da1d57 LS |
1513 | /*DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);*/ |
1514 | /*cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);*/ | |
8fc8598e JC |
1515 | write_nic_dword(dev, RATR0, ratr_value); |
1516 | write_nic_byte(dev, UFWP, 1); | |
8fc8598e | 1517 | } |
e1da1d57 | 1518 | /* Restore TX Power Tracking Index */ |
2930d0b9 | 1519 | if (priv->btxpower_trackingInit && priv->btxpower_tracking) |
8fc8598e | 1520 | dm_txpower_reset_recovery(dev); |
8fc8598e | 1521 | |
e1da1d57 | 1522 | /* Restore BB Initial Gain */ |
8fc8598e JC |
1523 | dm_bb_initialgain_restore(dev); |
1524 | ||
e1da1d57 | 1525 | } /* DM_RestoreDynamicMechanismState */ |
8fc8598e JC |
1526 | |
1527 | static void dm_bb_initialgain_restore(struct net_device *dev) | |
1528 | { | |
1529 | struct r8192_priv *priv = ieee80211_priv(dev); | |
e1da1d57 | 1530 | u32 bit_mask = 0x7f; /* Bit0~ Bit6 */ |
8fc8598e | 1531 | |
04d695d7 | 1532 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) |
8fc8598e JC |
1533 | return; |
1534 | ||
e1da1d57 LS |
1535 | /* Disable Initial Gain */ |
1536 | /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/ | |
1537 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ | |
8fc8598e JC |
1538 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); |
1539 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1); | |
1540 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1); | |
1541 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1); | |
1542 | bit_mask = bMaskByte2; | |
1543 | rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca); | |
1544 | ||
04d695d7 LS |
1545 | RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n", priv->initgain_backup.xaagccore1); |
1546 | RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n", priv->initgain_backup.xbagccore1); | |
1547 | RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n", priv->initgain_backup.xcagccore1); | |
1548 | RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1); | |
1549 | RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca); | |
e1da1d57 LS |
1550 | /* Enable Initial Gain */ |
1551 | /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);*/ | |
1552 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ | |
8fc8598e | 1553 | |
e1da1d57 | 1554 | } /* dm_BBInitialGainRestore */ |
8fc8598e | 1555 | |
8fc8598e JC |
1556 | static void dm_bb_initialgain_backup(struct net_device *dev) |
1557 | { | |
1558 | struct r8192_priv *priv = ieee80211_priv(dev); | |
e1da1d57 | 1559 | u32 bit_mask = bMaskByte0; /* Bit0~ Bit6 */ |
8fc8598e | 1560 | |
04d695d7 | 1561 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) |
8fc8598e JC |
1562 | return; |
1563 | ||
e1da1d57 LS |
1564 | /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/ |
1565 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ | |
8fc8598e JC |
1566 | priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); |
1567 | priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask); | |
1568 | priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask); | |
1569 | priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask); | |
1570 | bit_mask = bMaskByte2; | |
1571 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask); | |
1572 | ||
04d695d7 LS |
1573 | RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n", priv->initgain_backup.xaagccore1); |
1574 | RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n", priv->initgain_backup.xbagccore1); | |
1575 | RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n", priv->initgain_backup.xcagccore1); | |
1576 | RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n", priv->initgain_backup.xdagccore1); | |
1577 | RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n", priv->initgain_backup.cca); | |
8fc8598e | 1578 | |
e1da1d57 | 1579 | } /* dm_BBInitialGainBakcup */ |
8fc8598e JC |
1580 | |
1581 | #endif | |
8fc8598e JC |
1582 | /*----------------------------------------------------------------------------- |
1583 | * Function: dm_dig_init() | |
1584 | * | |
1585 | * Overview: Set DIG scheme init value. | |
1586 | * | |
1587 | * Input: NONE | |
1588 | * | |
1589 | * Output: NONE | |
1590 | * | |
1591 | * Return: NONE | |
1592 | * | |
1593 | * Revised History: | |
1594 | * When Who Remark | |
1595 | * 05/15/2008 amy Create Version 0 porting from windows code. | |
1596 | * | |
1597 | *---------------------------------------------------------------------------*/ | |
1598 | static void dm_dig_init(struct net_device *dev) | |
1599 | { | |
1600 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1601 | /* 2007/10/05 MH Disable DIG scheme now. Not tested. */ | |
1602 | dm_digtable.dig_enable_flag = true; | |
1603 | dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI; | |
8fc8598e JC |
1604 | dm_digtable.dig_algorithm_switch = 0; |
1605 | ||
589b3d06 | 1606 | /* 2007/10/04 MH Define init gain threshold. */ |
8fc8598e JC |
1607 | dm_digtable.dig_state = DM_STA_DIG_MAX; |
1608 | dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; | |
8fc8598e | 1609 | |
35997ff0 SH |
1610 | dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW; |
1611 | dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH; | |
8fc8598e JC |
1612 | |
1613 | dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW; | |
1614 | dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH; | |
1615 | ||
e1da1d57 | 1616 | dm_digtable.rssi_val = 50; /* for new dig debug rssi value */ |
8fc8598e | 1617 | dm_digtable.backoff_val = DM_DIG_BACKOFF; |
04d695d7 | 1618 | if (priv->CustomerID == RT_CID_819x_Netcore) |
a7a01496 | 1619 | dm_digtable.rx_gain_range_min = DM_DIG_MIN_NETCORE; |
8fc8598e JC |
1620 | else |
1621 | dm_digtable.rx_gain_range_min = DM_DIG_MIN; | |
1622 | ||
1623 | } /* dm_dig_init */ | |
1624 | ||
8fc8598e JC |
1625 | /*----------------------------------------------------------------------------- |
1626 | * Function: dm_ctrl_initgain_byrssi() | |
1627 | * | |
1628 | * Overview: Driver must monitor RSSI and notify firmware to change initial | |
1629 | * gain according to different threshold. BB team provide the | |
1630 | * suggested solution. | |
1631 | * | |
1632 | * Input: struct net_device *dev | |
1633 | * | |
1634 | * Output: NONE | |
1635 | * | |
1636 | * Return: NONE | |
1637 | * | |
1638 | * Revised History: | |
1639 | * When Who Remark | |
1640 | * 05/27/2008 amy Create Version 0 porting from windows code. | |
1641 | *---------------------------------------------------------------------------*/ | |
1642 | static void dm_ctrl_initgain_byrssi(struct net_device *dev) | |
1643 | { | |
f9bd549a | 1644 | if (!dm_digtable.dig_enable_flag) |
8fc8598e JC |
1645 | return; |
1646 | ||
04d695d7 | 1647 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
8fc8598e | 1648 | dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev); |
04d695d7 | 1649 | else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) |
8fc8598e | 1650 | dm_ctrl_initgain_byrssi_by_driverrssi(dev); |
e1da1d57 | 1651 | /* ; */ |
8fc8598e JC |
1652 | else |
1653 | return; | |
1654 | } | |
1655 | ||
8fc8598e JC |
1656 | static void dm_ctrl_initgain_byrssi_by_driverrssi( |
1657 | struct net_device *dev) | |
1658 | { | |
1659 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1660 | u8 i; | |
de13a3da | 1661 | static u8 fw_dig; |
8fc8598e | 1662 | |
f9bd549a | 1663 | if (!dm_digtable.dig_enable_flag) |
8fc8598e JC |
1664 | return; |
1665 | ||
04d695d7 LS |
1666 | /*DbgPrint("Dig by Sw Rssi\n");*/ |
1667 | if (dm_digtable.dig_algorithm_switch) /* if switched algorithm, we have to disable FW Dig. */ | |
8fc8598e | 1668 | fw_dig = 0; |
04d695d7 LS |
1669 | |
1670 | if (fw_dig <= 3) { /* execute several times to make sure the FW Dig is disabled */ | |
e1da1d57 | 1671 | /* FW DIG Off */ |
04d695d7 | 1672 | for (i = 0; i < 3; i++) |
e1da1d57 | 1673 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ |
8fc8598e | 1674 | fw_dig++; |
e1da1d57 | 1675 | dm_digtable.dig_state = DM_STA_DIG_OFF; /* fw dig off. */ |
8fc8598e JC |
1676 | } |
1677 | ||
04d695d7 | 1678 | if (priv->ieee80211->state == IEEE80211_LINKED) |
8fc8598e JC |
1679 | dm_digtable.cur_connect_state = DIG_CONNECT; |
1680 | else | |
1681 | dm_digtable.cur_connect_state = DIG_DISCONNECT; | |
1682 | ||
04d695d7 | 1683 | /*DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d\n", |
e1da1d57 | 1684 | DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);*/ |
8fc8598e | 1685 | |
8add1eb5 | 1686 | dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb; |
04d695d7 | 1687 | /*DbgPrint("DM_DigTable.Rssi_val = %d\n", DM_DigTable.Rssi_val);*/ |
8fc8598e JC |
1688 | dm_initial_gain(dev); |
1689 | dm_pd_th(dev); | |
1690 | dm_cs_ratio(dev); | |
04d695d7 | 1691 | if (dm_digtable.dig_algorithm_switch) |
8fc8598e JC |
1692 | dm_digtable.dig_algorithm_switch = 0; |
1693 | dm_digtable.pre_connect_state = dm_digtable.cur_connect_state; | |
1694 | ||
1695 | } /* dm_CtrlInitGainByRssi */ | |
1696 | ||
1697 | static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm( | |
1698 | struct net_device *dev) | |
1699 | { | |
1700 | struct r8192_priv *priv = ieee80211_priv(dev); | |
de13a3da | 1701 | static u32 reset_cnt; |
8fc8598e JC |
1702 | u8 i; |
1703 | ||
f9bd549a | 1704 | if (!dm_digtable.dig_enable_flag) |
8fc8598e JC |
1705 | return; |
1706 | ||
04d695d7 | 1707 | if (dm_digtable.dig_algorithm_switch) { |
8fc8598e | 1708 | dm_digtable.dig_state = DM_STA_DIG_MAX; |
e1da1d57 | 1709 | /* Fw DIG On. */ |
04d695d7 | 1710 | for (i = 0; i < 3; i++) |
e1da1d57 | 1711 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite.*/ |
8fc8598e JC |
1712 | dm_digtable.dig_algorithm_switch = 0; |
1713 | } | |
1714 | ||
1715 | if (priv->ieee80211->state != IEEE80211_LINKED) | |
1716 | return; | |
1717 | ||
e1da1d57 | 1718 | /* For smooth, we can not change DIG state. */ |
8fc8598e | 1719 | if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) && |
f981a79e | 1720 | (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh)) |
8fc8598e | 1721 | return; |
04d695d7 | 1722 | |
e1da1d57 LS |
1723 | /*DbgPrint("Dig by Fw False Alarm\n");*/ |
1724 | /*if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)*/ | |
8fc8598e JC |
1725 | /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d", |
1726 | pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh, | |
1727 | DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/ | |
589b3d06 | 1728 | /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold |
0dbc8368 CM |
1729 | * and then execute the step below. |
1730 | */ | |
16da7808 | 1731 | if (priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh) { |
8fc8598e | 1732 | /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters |
0dbc8368 CM |
1733 | * will be reset to init value. We must prevent the condition. |
1734 | */ | |
8fc8598e | 1735 | if (dm_digtable.dig_state == DM_STA_DIG_OFF && |
04d695d7 | 1736 | (priv->reset_count == reset_cnt)) { |
8fc8598e | 1737 | return; |
8fc8598e | 1738 | } |
16da7808 | 1739 | reset_cnt = priv->reset_count; |
8fc8598e | 1740 | |
e1da1d57 | 1741 | /* If DIG is off, DIG high power state must reset. */ |
8fc8598e JC |
1742 | dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; |
1743 | dm_digtable.dig_state = DM_STA_DIG_OFF; | |
1744 | ||
e1da1d57 LS |
1745 | /* 1.1 DIG Off. */ |
1746 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ | |
8fc8598e | 1747 | |
e1da1d57 | 1748 | /* 1.2 Set initial gain. */ |
8fc8598e JC |
1749 | write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); |
1750 | write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17); | |
1751 | write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17); | |
1752 | write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17); | |
1753 | ||
e1da1d57 | 1754 | /* 1.3 Lower PD_TH for OFDM. */ |
04d695d7 | 1755 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
d8718e45 | 1756 | /* 2008/01/11 MH 40MHZ 90/92 register are not the same. |
e1da1d57 LS |
1757 | * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. |
1758 | */ | |
91e39f09 | 1759 | write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); |
8fc8598e JC |
1760 | /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) |
1761 | write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40); | |
e1da1d57 LS |
1762 | else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) |
1763 | else | |
1764 | PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40); | |
8fc8598e | 1765 | */ |
04d695d7 | 1766 | } else |
8fc8598e JC |
1767 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); |
1768 | ||
e1da1d57 | 1769 | /* 1.4 Lower CS ratio for CCK. */ |
8fc8598e JC |
1770 | write_nic_byte(dev, 0xa0a, 0x08); |
1771 | ||
e1da1d57 LS |
1772 | /* 1.5 Higher EDCCA. */ |
1773 | /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);*/ | |
8fc8598e | 1774 | return; |
8fc8598e JC |
1775 | } |
1776 | ||
589b3d06 | 1777 | /* 2. When RSSI increase, We have to judge if it is larger than a threshold |
0dbc8368 CM |
1778 | * and then execute the step below. |
1779 | */ | |
16da7808 | 1780 | if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) { |
8fc8598e JC |
1781 | u8 reset_flag = 0; |
1782 | ||
1783 | if (dm_digtable.dig_state == DM_STA_DIG_ON && | |
f981a79e | 1784 | (priv->reset_count == reset_cnt)) { |
8fc8598e JC |
1785 | dm_ctrl_initgain_byrssi_highpwr(dev); |
1786 | return; | |
8fc8598e | 1787 | } |
16da7808 LS |
1788 | if (priv->reset_count != reset_cnt) |
1789 | reset_flag = 1; | |
1790 | ||
1791 | reset_cnt = priv->reset_count; | |
8fc8598e JC |
1792 | |
1793 | dm_digtable.dig_state = DM_STA_DIG_ON; | |
e1da1d57 | 1794 | /*DbgPrint("DIG ON\n\r");*/ |
8fc8598e | 1795 | |
d8718e45 | 1796 | /* 2.1 Set initial gain. |
e1da1d57 LS |
1797 | * 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment. |
1798 | */ | |
04d695d7 | 1799 | if (reset_flag == 1) { |
8fc8598e JC |
1800 | write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); |
1801 | write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c); | |
1802 | write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c); | |
1803 | write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c); | |
04d695d7 | 1804 | } else { |
8fc8598e JC |
1805 | write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); |
1806 | write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20); | |
1807 | write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20); | |
1808 | write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20); | |
1809 | } | |
1810 | ||
e1da1d57 | 1811 | /* 2.2 Higher PD_TH for OFDM. */ |
04d695d7 | 1812 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
d8718e45 | 1813 | /* 2008/01/11 MH 40MHZ 90/92 register are not the same. |
e1da1d57 LS |
1814 | * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. |
1815 | */ | |
91e39f09 | 1816 | write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); |
8fc8598e JC |
1817 | /* |
1818 | else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) | |
1819 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); | |
e1da1d57 LS |
1820 | else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) |
1821 | else | |
1822 | PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42); | |
8fc8598e | 1823 | */ |
04d695d7 | 1824 | } else |
8fc8598e JC |
1825 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); |
1826 | ||
e1da1d57 | 1827 | /* 2.3 Higher CS ratio for CCK. */ |
8fc8598e JC |
1828 | write_nic_byte(dev, 0xa0a, 0xcd); |
1829 | ||
d8718e45 | 1830 | /* 2.4 Lower EDCCA. |
e1da1d57 LS |
1831 | * 2008/01/11 MH 90/92 series are the same. |
1832 | */ | |
1833 | /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);*/ | |
8fc8598e | 1834 | |
e1da1d57 LS |
1835 | /* 2.5 DIG On. */ |
1836 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ | |
8fc8598e JC |
1837 | } |
1838 | ||
1839 | dm_ctrl_initgain_byrssi_highpwr(dev); | |
1840 | ||
1841 | } /* dm_CtrlInitGainByRssi */ | |
1842 | ||
8fc8598e JC |
1843 | /*----------------------------------------------------------------------------- |
1844 | * Function: dm_ctrl_initgain_byrssi_highpwr() | |
1845 | * | |
1846 | * Overview: | |
1847 | * | |
1848 | * Input: NONE | |
1849 | * | |
1850 | * Output: NONE | |
1851 | * | |
1852 | * Return: NONE | |
1853 | * | |
1854 | * Revised History: | |
1855 | * When Who Remark | |
1856 | * 05/28/2008 amy Create Version 0 porting from windows code. | |
1857 | * | |
1858 | *---------------------------------------------------------------------------*/ | |
1859 | static void dm_ctrl_initgain_byrssi_highpwr( | |
999d594b | 1860 | struct net_device *dev) |
8fc8598e JC |
1861 | { |
1862 | struct r8192_priv *priv = ieee80211_priv(dev); | |
de13a3da | 1863 | static u32 reset_cnt_highpwr; |
8fc8598e | 1864 | |
e1da1d57 | 1865 | /* For smooth, we can not change high power DIG state in the range. */ |
8fc8598e JC |
1866 | if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) && |
1867 | (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh)) | |
8fc8598e | 1868 | return; |
8fc8598e | 1869 | |
d8718e45 | 1870 | /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if |
e1da1d57 LS |
1871 | * it is larger than a threshold and then execute the step below. |
1872 | * | |
1873 | * 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue. | |
1874 | */ | |
04d695d7 | 1875 | if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) { |
8fc8598e | 1876 | if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON && |
f981a79e | 1877 | (priv->reset_count == reset_cnt_highpwr)) |
8fc8598e | 1878 | return; |
16da7808 | 1879 | dm_digtable.dig_highpwr_state = DM_STA_DIG_ON; |
8fc8598e | 1880 | |
e1da1d57 | 1881 | /* 3.1 Higher PD_TH for OFDM for high power state. */ |
04d695d7 | 1882 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
91e39f09 | 1883 | write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); |
8fc8598e JC |
1884 | |
1885 | /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) | |
1886 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); | |
1887 | */ | |
1888 | ||
04d695d7 | 1889 | } else |
8fc8598e | 1890 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); |
04d695d7 LS |
1891 | } else { |
1892 | if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF && | |
f981a79e | 1893 | (priv->reset_count == reset_cnt_highpwr)) |
8fc8598e | 1894 | return; |
16da7808 | 1895 | dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF; |
8fc8598e JC |
1896 | |
1897 | if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh && | |
04d695d7 | 1898 | priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) { |
e1da1d57 | 1899 | /* 3.2 Recover PD_TH for OFDM for normal power region. */ |
04d695d7 | 1900 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
91e39f09 | 1901 | write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); |
8fc8598e JC |
1902 | /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) |
1903 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); | |
1904 | */ | |
1905 | ||
04d695d7 | 1906 | } else |
8fc8598e JC |
1907 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); |
1908 | } | |
1909 | } | |
1910 | ||
1911 | reset_cnt_highpwr = priv->reset_count; | |
1912 | ||
1913 | } /* dm_CtrlInitGainByRssiHighPwr */ | |
1914 | ||
8fc8598e | 1915 | static void dm_initial_gain( |
999d594b | 1916 | struct net_device *dev) |
8fc8598e JC |
1917 | { |
1918 | struct r8192_priv *priv = ieee80211_priv(dev); | |
04d695d7 | 1919 | u8 initial_gain = 0; |
de13a3da SH |
1920 | static u8 initialized, force_write; |
1921 | static u32 reset_cnt; | |
b3d42bf1 | 1922 | u8 tmp; |
8fc8598e | 1923 | |
04d695d7 | 1924 | if (dm_digtable.dig_algorithm_switch) { |
8fc8598e JC |
1925 | initialized = 0; |
1926 | reset_cnt = 0; | |
1927 | } | |
1928 | ||
04d695d7 LS |
1929 | if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) { |
1930 | if (dm_digtable.cur_connect_state == DIG_CONNECT) { | |
a2351af9 JW |
1931 | if ((dm_digtable.rssi_val + 10 - dm_digtable.backoff_val) > DM_DIG_MAX) |
1932 | dm_digtable.cur_ig_value = DM_DIG_MAX; | |
04d695d7 | 1933 | else if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min) |
8fc8598e JC |
1934 | dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min; |
1935 | else | |
1936 | dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val; | |
04d695d7 LS |
1937 | } else { /* current state is disconnected */ |
1938 | if (dm_digtable.cur_ig_value == 0) | |
8fc8598e JC |
1939 | dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; |
1940 | else | |
1941 | dm_digtable.cur_ig_value = dm_digtable.pre_ig_value; | |
1942 | } | |
04d695d7 | 1943 | } else { /* disconnected -> connected or connected -> disconnected */ |
8fc8598e JC |
1944 | dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; |
1945 | dm_digtable.pre_ig_value = 0; | |
1946 | } | |
e1da1d57 | 1947 | /*DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);*/ |
8fc8598e | 1948 | |
e1da1d57 | 1949 | /* if silent reset happened, we should rewrite the values back */ |
04d695d7 | 1950 | if (priv->reset_count != reset_cnt) { |
8fc8598e JC |
1951 | force_write = 1; |
1952 | reset_cnt = priv->reset_count; | |
1953 | } | |
1954 | ||
b3d42bf1 XR |
1955 | read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp); |
1956 | if (dm_digtable.pre_ig_value != tmp) | |
8fc8598e JC |
1957 | force_write = 1; |
1958 | ||
1959 | { | |
04d695d7 LS |
1960 | if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value) |
1961 | || !initialized || force_write) { | |
8fc8598e | 1962 | initial_gain = (u8)dm_digtable.cur_ig_value; |
e1da1d57 LS |
1963 | /*DbgPrint("Write initial gain = 0x%x\n", initial_gain);*/ |
1964 | /* Set initial gain. */ | |
8fc8598e JC |
1965 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); |
1966 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); | |
1967 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); | |
1968 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); | |
1969 | dm_digtable.pre_ig_value = dm_digtable.cur_ig_value; | |
1970 | initialized = 1; | |
1971 | force_write = 0; | |
1972 | } | |
1973 | } | |
1974 | } | |
1975 | ||
1976 | static void dm_pd_th( | |
999d594b | 1977 | struct net_device *dev) |
8fc8598e JC |
1978 | { |
1979 | struct r8192_priv *priv = ieee80211_priv(dev); | |
de13a3da SH |
1980 | static u8 initialized, force_write; |
1981 | static u32 reset_cnt; | |
8fc8598e | 1982 | |
04d695d7 | 1983 | if (dm_digtable.dig_algorithm_switch) { |
8fc8598e JC |
1984 | initialized = 0; |
1985 | reset_cnt = 0; | |
1986 | } | |
1987 | ||
04d695d7 LS |
1988 | if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) { |
1989 | if (dm_digtable.cur_connect_state == DIG_CONNECT) { | |
8fc8598e JC |
1990 | if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh) |
1991 | dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER; | |
16da7808 | 1992 | else if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh) |
8fc8598e JC |
1993 | dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; |
1994 | else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) && | |
1995 | (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh)) | |
1996 | dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER; | |
1997 | else | |
1998 | dm_digtable.curpd_thstate = dm_digtable.prepd_thstate; | |
04d695d7 | 1999 | } else { |
8fc8598e JC |
2000 | dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; |
2001 | } | |
04d695d7 | 2002 | } else { /* disconnected -> connected or connected -> disconnected */ |
8fc8598e JC |
2003 | dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; |
2004 | } | |
2005 | ||
e1da1d57 | 2006 | /* if silent reset happened, we should rewrite the values back */ |
04d695d7 | 2007 | if (priv->reset_count != reset_cnt) { |
8fc8598e JC |
2008 | force_write = 1; |
2009 | reset_cnt = priv->reset_count; | |
2010 | } | |
2011 | ||
2012 | { | |
04d695d7 LS |
2013 | if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) || |
2014 | (initialized <= 3) || force_write) { | |
e1da1d57 | 2015 | /*DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);*/ |
04d695d7 | 2016 | if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) { |
e1da1d57 | 2017 | /* Lower PD_TH for OFDM. */ |
04d695d7 | 2018 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
d8718e45 | 2019 | /* 2008/01/11 MH 40MHZ 90/92 register are not the same. |
e1da1d57 LS |
2020 | * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. |
2021 | */ | |
91e39f09 | 2022 | write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); |
8fc8598e JC |
2023 | /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) |
2024 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); | |
2025 | */ | |
04d695d7 | 2026 | } else |
8fc8598e | 2027 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); |
04d695d7 | 2028 | } else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) { |
e1da1d57 | 2029 | /* Higher PD_TH for OFDM. */ |
04d695d7 | 2030 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
d8718e45 | 2031 | /* 2008/01/11 MH 40MHZ 90/92 register are not the same. |
e1da1d57 LS |
2032 | * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. |
2033 | */ | |
91e39f09 | 2034 | write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); |
8fc8598e JC |
2035 | /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) |
2036 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); | |
2037 | */ | |
04d695d7 | 2038 | } else |
8fc8598e | 2039 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); |
04d695d7 | 2040 | } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) { |
e1da1d57 | 2041 | /* Higher PD_TH for OFDM for high power state. */ |
04d695d7 | 2042 | if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
91e39f09 | 2043 | write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); |
8fc8598e JC |
2044 | /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) |
2045 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); | |
2046 | */ | |
04d695d7 | 2047 | } else |
8fc8598e JC |
2048 | write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); |
2049 | } | |
2050 | dm_digtable.prepd_thstate = dm_digtable.curpd_thstate; | |
04d695d7 | 2051 | if (initialized <= 3) |
8fc8598e JC |
2052 | initialized++; |
2053 | force_write = 0; | |
2054 | } | |
2055 | } | |
2056 | } | |
2057 | ||
2058 | static void dm_cs_ratio( | |
999d594b | 2059 | struct net_device *dev) |
8fc8598e JC |
2060 | { |
2061 | struct r8192_priv *priv = ieee80211_priv(dev); | |
0b4ef0a6 | 2062 | static u8 initialized, force_write; |
de13a3da | 2063 | static u32 reset_cnt; |
8fc8598e | 2064 | |
04d695d7 | 2065 | if (dm_digtable.dig_algorithm_switch) { |
8fc8598e JC |
2066 | initialized = 0; |
2067 | reset_cnt = 0; | |
2068 | } | |
2069 | ||
04d695d7 LS |
2070 | if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) { |
2071 | if (dm_digtable.cur_connect_state == DIG_CONNECT) { | |
16da7808 | 2072 | if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh) |
8fc8598e | 2073 | dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; |
16da7808 | 2074 | else if (dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) |
8fc8598e JC |
2075 | dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER; |
2076 | else | |
2077 | dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state; | |
04d695d7 | 2078 | } else { |
8fc8598e JC |
2079 | dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; |
2080 | } | |
04d695d7 | 2081 | } else /* disconnected -> connected or connected -> disconnected */ |
8fc8598e | 2082 | dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; |
8fc8598e | 2083 | |
e1da1d57 | 2084 | /* if silent reset happened, we should rewrite the values back */ |
04d695d7 | 2085 | if (priv->reset_count != reset_cnt) { |
8fc8598e JC |
2086 | force_write = 1; |
2087 | reset_cnt = priv->reset_count; | |
2088 | } | |
2089 | ||
8fc8598e | 2090 | { |
04d695d7 | 2091 | if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) || |
f981a79e | 2092 | !initialized || force_write) { |
e1da1d57 | 2093 | /*DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);*/ |
04d695d7 | 2094 | if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) { |
e1da1d57 | 2095 | /* Lower CS ratio for CCK. */ |
8fc8598e | 2096 | write_nic_byte(dev, 0xa0a, 0x08); |
04d695d7 | 2097 | } else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) { |
e1da1d57 | 2098 | /* Higher CS ratio for CCK. */ |
8fc8598e JC |
2099 | write_nic_byte(dev, 0xa0a, 0xcd); |
2100 | } | |
2101 | dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state; | |
2102 | initialized = 1; | |
2103 | force_write = 0; | |
2104 | } | |
2105 | } | |
2106 | } | |
2107 | ||
c541fa87 | 2108 | void dm_init_edca_turbo(struct net_device *dev) |
8fc8598e JC |
2109 | { |
2110 | struct r8192_priv *priv = ieee80211_priv(dev); | |
2111 | ||
2112 | priv->bcurrent_turbo_EDCA = false; | |
2113 | priv->ieee80211->bis_any_nonbepkts = false; | |
2114 | priv->bis_cur_rdlstate = false; | |
e1da1d57 | 2115 | } /* dm_init_edca_turbo */ |
8fc8598e | 2116 | |
8fc8598e | 2117 | static void dm_check_edca_turbo( |
999d594b | 2118 | struct net_device *dev) |
8fc8598e JC |
2119 | { |
2120 | struct r8192_priv *priv = ieee80211_priv(dev); | |
2121 | PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; | |
e1da1d57 | 2122 | /*PSTA_QOS pStaQos = pMgntInfo->pStaQos;*/ |
8fc8598e | 2123 | |
e1da1d57 | 2124 | /* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */ |
de13a3da SH |
2125 | static unsigned long lastTxOkCnt; |
2126 | static unsigned long lastRxOkCnt; | |
8fc8598e JC |
2127 | unsigned long curTxOkCnt = 0; |
2128 | unsigned long curRxOkCnt = 0; | |
2129 | ||
d8718e45 | 2130 | /* Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters |
e1da1d57 LS |
2131 | * should follow the settings from QAP. By Bruce, 2007-12-07. |
2132 | */ | |
04d695d7 | 2133 | if (priv->ieee80211->state != IEEE80211_LINKED) |
8fc8598e | 2134 | goto dm_CheckEdcaTurbo_EXIT; |
e1da1d57 | 2135 | /* We do not turn on EDCA turbo mode for some AP that has IOT issue */ |
04d695d7 | 2136 | if (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) |
8fc8598e JC |
2137 | goto dm_CheckEdcaTurbo_EXIT; |
2138 | ||
04d695d7 | 2139 | /*printk("========>%s():bis_any_nonbepkts is %d\n", __func__, priv->bis_any_nonbepkts);*/ |
e1da1d57 | 2140 | /* Check the status for current condition. */ |
04d695d7 | 2141 | if (!priv->ieee80211->bis_any_nonbepkts) { |
8fc8598e JC |
2142 | curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; |
2143 | curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; | |
e1da1d57 | 2144 | /* For RT-AP, we needs to turn it on when Rx>Tx */ |
04d695d7 | 2145 | if (curRxOkCnt > 4*curTxOkCnt) { |
e1da1d57 | 2146 | /*printk("%s():curRxOkCnt > 4*curTxOkCnt\n");*/ |
04d695d7 | 2147 | if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) { |
8fc8598e JC |
2148 | write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]); |
2149 | priv->bis_cur_rdlstate = true; | |
2150 | } | |
04d695d7 | 2151 | } else { |
e1da1d57 | 2152 | /*printk("%s():curRxOkCnt < 4*curTxOkCnt\n");*/ |
04d695d7 | 2153 | if (priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) { |
8fc8598e JC |
2154 | write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); |
2155 | priv->bis_cur_rdlstate = false; | |
2156 | } | |
8fc8598e JC |
2157 | } |
2158 | ||
2159 | priv->bcurrent_turbo_EDCA = true; | |
04d695d7 | 2160 | } else { |
d8718e45 | 2161 | /* Turn Off EDCA turbo here. |
e1da1d57 LS |
2162 | * Restore original EDCA according to the declaration of AP. |
2163 | */ | |
04d695d7 | 2164 | if (priv->bcurrent_turbo_EDCA) { |
2b7f2a43 TR |
2165 | u8 u1bAIFS; |
2166 | u32 u4bAcParam, op_limit, cw_max, cw_min; | |
2167 | ||
83dc299e TR |
2168 | struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; |
2169 | u8 mode = priv->ieee80211->mode; | |
2170 | ||
2171 | /* For Each time updating EDCA parameter, reset EDCA turbo mode status. */ | |
2172 | dm_init_edca_turbo(dev); | |
2b7f2a43 TR |
2173 | |
2174 | u1bAIFS = qos_parameters->aifs[0] * ((mode & (IEEE_G | IEEE_N_24G)) ? 9 : 20) + aSifsTime; | |
2175 | ||
2176 | op_limit = (u32)le16_to_cpu(qos_parameters->tx_op_limit[0]); | |
2177 | cw_max = (u32)le16_to_cpu(qos_parameters->cw_max[0]); | |
2178 | cw_min = (u32)le16_to_cpu(qos_parameters->cw_min[0]); | |
2179 | ||
2180 | op_limit <<= AC_PARAM_TXOP_LIMIT_OFFSET; | |
2181 | cw_max <<= AC_PARAM_ECW_MAX_OFFSET; | |
2182 | cw_min <<= AC_PARAM_ECW_MIN_OFFSET; | |
2183 | u1bAIFS <<= AC_PARAM_AIFS_OFFSET; | |
2184 | ||
2185 | u4bAcParam = op_limit | cw_max | cw_min | u1bAIFS; | |
fb8cf3bf | 2186 | cpu_to_le32s(&u4bAcParam); |
2b7f2a43 TR |
2187 | |
2188 | write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); | |
2189 | ||
d8718e45 | 2190 | /* Check ACM bit. |
83dc299e TR |
2191 | * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. |
2192 | */ | |
8fc8598e | 2193 | { |
83dc299e | 2194 | /* TODO: Modified this part and try to set acm control in only 1 IO processing!! */ |
8fc8598e | 2195 | |
ab9a0665 | 2196 | struct aci_aifsn *pAciAifsn = (struct aci_aifsn *)&(qos_parameters->aifs[0]); |
83dc299e TR |
2197 | u8 AcmCtrl; |
2198 | ||
2199 | read_nic_byte(dev, AcmHwCtrl, &AcmCtrl); | |
2200 | ||
ab9a0665 | 2201 | if (pAciAifsn->acm) { /* acm bit is 1. */ |
83dc299e TR |
2202 | AcmCtrl |= AcmHw_BeqEn; |
2203 | } else { /* ACM bit is 0. */ | |
2204 | AcmCtrl &= (~AcmHw_BeqEn); | |
8fc8598e | 2205 | } |
83dc299e TR |
2206 | |
2207 | RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl); | |
2208 | write_nic_byte(dev, AcmHwCtrl, AcmCtrl); | |
8fc8598e JC |
2209 | } |
2210 | priv->bcurrent_turbo_EDCA = false; | |
2211 | } | |
2212 | } | |
2213 | ||
8fc8598e | 2214 | dm_CheckEdcaTurbo_EXIT: |
e1da1d57 | 2215 | /* Set variables for next time. */ |
8fc8598e JC |
2216 | priv->ieee80211->bis_any_nonbepkts = false; |
2217 | lastTxOkCnt = priv->stats.txbytesunicast; | |
2218 | lastRxOkCnt = priv->stats.rxbytesunicast; | |
e1da1d57 | 2219 | } /* dm_CheckEdcaTurbo */ |
8fc8598e | 2220 | |
999d594b | 2221 | static void dm_init_ctstoself(struct net_device *dev) |
8fc8598e | 2222 | { |
efdcb35a | 2223 | struct r8192_priv *priv = ieee80211_priv(dev); |
8fc8598e | 2224 | |
4b2faf80 | 2225 | priv->ieee80211->bCTSToSelfEnable = true; |
070c1ce9 | 2226 | priv->ieee80211->CTSToSelfTH = CTS_TO_SELF_TH_VAL; |
8fc8598e JC |
2227 | } |
2228 | ||
2229 | static void dm_ctstoself(struct net_device *dev) | |
2230 | { | |
efdcb35a | 2231 | struct r8192_priv *priv = ieee80211_priv(dev); |
8fc8598e | 2232 | PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; |
de13a3da SH |
2233 | static unsigned long lastTxOkCnt; |
2234 | static unsigned long lastRxOkCnt; | |
8fc8598e JC |
2235 | unsigned long curTxOkCnt = 0; |
2236 | unsigned long curRxOkCnt = 0; | |
2237 | ||
eab439be | 2238 | if (!priv->ieee80211->bCTSToSelfEnable) { |
8fc8598e JC |
2239 | pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; |
2240 | return; | |
2241 | } | |
0dbc8368 CM |
2242 | /* 1. Uplink |
2243 | * 2. Linksys350/Linksys300N | |
2244 | * 3. <50 disable, >55 enable | |
2245 | */ | |
8fc8598e | 2246 | |
04d695d7 | 2247 | if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) { |
8fc8598e JC |
2248 | curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; |
2249 | curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; | |
04d695d7 | 2250 | if (curRxOkCnt > 4*curTxOkCnt) { /* downlink, disable CTS to self */ |
8fc8598e | 2251 | pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; |
e1da1d57 | 2252 | /*DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");*/ |
04d695d7 | 2253 | } else { /* uplink */ |
8fc8598e | 2254 | pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; |
8fc8598e JC |
2255 | } |
2256 | ||
2257 | lastTxOkCnt = priv->stats.txbytesunicast; | |
2258 | lastRxOkCnt = priv->stats.rxbytesunicast; | |
2259 | } | |
2260 | } | |
2261 | ||
8fc8598e JC |
2262 | /*----------------------------------------------------------------------------- |
2263 | * Function: dm_check_pbc_gpio() | |
2264 | * | |
2265 | * Overview: Check if PBC button is pressed. | |
2266 | * | |
2267 | * Input: NONE | |
2268 | * | |
2269 | * Output: NONE | |
2270 | * | |
2271 | * Return: NONE | |
2272 | * | |
2273 | * Revised History: | |
2274 | * When Who Remark | |
35997ff0 | 2275 | * 05/28/2008 amy Create Version 0 porting from windows code. |
8fc8598e JC |
2276 | * |
2277 | *---------------------------------------------------------------------------*/ | |
2278 | static void dm_check_pbc_gpio(struct net_device *dev) | |
2279 | { | |
8fc8598e JC |
2280 | struct r8192_priv *priv = ieee80211_priv(dev); |
2281 | u8 tmp1byte; | |
2282 | ||
b3d42bf1 | 2283 | read_nic_byte(dev, GPI, &tmp1byte); |
04d695d7 | 2284 | if (tmp1byte == 0xff) |
8fc8598e JC |
2285 | return; |
2286 | ||
56b3152e | 2287 | if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) { |
d8718e45 | 2288 | /* Here we only set bPbcPressed to TRUE |
e1da1d57 LS |
2289 | * After trigger PBC, the variable will be set to FALSE |
2290 | */ | |
8fc8598e JC |
2291 | RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n"); |
2292 | priv->bpbc_pressed = true; | |
2293 | } | |
8fc8598e JC |
2294 | } |
2295 | ||
8fc8598e JC |
2296 | /*----------------------------------------------------------------------------- |
2297 | * Function: DM_RFPathCheckWorkItemCallBack() | |
2298 | * | |
2299 | * Overview: Check if Current RF RX path is enabled | |
2300 | * | |
2301 | * Input: NONE | |
2302 | * | |
2303 | * Output: NONE | |
2304 | * | |
2305 | * Return: NONE | |
2306 | * | |
2307 | * Revised History: | |
2308 | * When Who Remark | |
2309 | * 01/30/2008 MHC Create Version 0. | |
2310 | * | |
2311 | *---------------------------------------------------------------------------*/ | |
bf316434 | 2312 | void dm_rf_pathcheck_workitemcallback(struct work_struct *work) |
8fc8598e | 2313 | { |
a5959f3f | 2314 | struct delayed_work *dwork = to_delayed_work(work); |
04d695d7 LS |
2315 | struct r8192_priv *priv = container_of(dwork, struct r8192_priv, rfpath_check_wq); |
2316 | struct net_device *dev = priv->ieee80211->dev; | |
2317 | /*bool bactually_set = false;*/ | |
8fc8598e JC |
2318 | u8 rfpath = 0, i; |
2319 | ||
8fc8598e | 2320 | /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will |
0dbc8368 CM |
2321 | * always be the same. We only read 0xc04 now. |
2322 | */ | |
b3d42bf1 | 2323 | read_nic_byte(dev, 0xc04, &rfpath); |
8fc8598e | 2324 | |
e1da1d57 | 2325 | /* Check Bit 0-3, it means if RF A-D is enabled. */ |
04d695d7 | 2326 | for (i = 0; i < RF90_PATH_MAX; i++) { |
8fc8598e | 2327 | if (rfpath & (0x01<<i)) |
19cd2297 | 2328 | priv->brfpath_rxenable[i] = true; |
8fc8598e | 2329 | else |
19cd2297 | 2330 | priv->brfpath_rxenable[i] = false; |
8fc8598e | 2331 | } |
8fc8598e JC |
2332 | |
2333 | dm_rxpath_sel_byrssi(dev); | |
2334 | } /* DM_RFPathCheckWorkItemCallBack */ | |
2335 | ||
999d594b | 2336 | static void dm_init_rxpath_selection(struct net_device *dev) |
8fc8598e JC |
2337 | { |
2338 | u8 i; | |
2339 | struct r8192_priv *priv = ieee80211_priv(dev); | |
04d695d7 | 2340 | |
04d695d7 | 2341 | if (priv->CustomerID == RT_CID_819x_Netcore) |
f835f4b3 | 2342 | DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2; |
8fc8598e | 2343 | else |
f835f4b3 | 2344 | DM_RxPathSelTable.cck_method = CCK_RX_VERSION_1; |
68d84843 | 2345 | DM_RxPathSelTable.disabled_rf = 0; |
04d695d7 | 2346 | for (i = 0; i < 4; i++) { |
8fc8598e JC |
2347 | DM_RxPathSelTable.rf_rssi[i] = 50; |
2348 | DM_RxPathSelTable.cck_pwdb_sta[i] = -64; | |
2349 | DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; | |
2350 | } | |
2351 | } | |
2352 | ||
999d594b | 2353 | static void dm_rxpath_sel_byrssi(struct net_device *dev) |
8fc8598e JC |
2354 | { |
2355 | struct r8192_priv *priv = ieee80211_priv(dev); | |
04d695d7 LS |
2356 | u8 i, max_rssi_index = 0, min_rssi_index = 0, sec_rssi_index = 0, rf_num = 0; |
2357 | u8 tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0; | |
2358 | u8 cck_default_Rx = 0x2; /* RF-C */ | |
2359 | u8 cck_optional_Rx = 0x3; /* RF-D */ | |
2360 | long tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0; | |
2361 | u8 cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0, cck_rx_ver2_sec_index = 0; | |
8fc8598e JC |
2362 | u8 cur_rf_rssi; |
2363 | long cur_cck_pwdb; | |
de13a3da | 2364 | static u8 disabled_rf_cnt, cck_Rx_Path_initialized; |
8fc8598e JC |
2365 | u8 update_cck_rx_path; |
2366 | ||
04d695d7 | 2367 | if (priv->rf_type != RF_2T4R) |
8fc8598e JC |
2368 | return; |
2369 | ||
04d695d7 | 2370 | if (!cck_Rx_Path_initialized) { |
f19a08e7 JW |
2371 | read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_rx_path); |
2372 | DM_RxPathSelTable.cck_rx_path &= 0xf; | |
8fc8598e JC |
2373 | cck_Rx_Path_initialized = 1; |
2374 | } | |
2375 | ||
68d84843 JW |
2376 | read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabled_rf); |
2377 | DM_RxPathSelTable.disabled_rf = ~DM_RxPathSelTable.disabled_rf & 0xf; | |
8fc8598e | 2378 | |
04d695d7 | 2379 | if (priv->ieee80211->mode == WIRELESS_MODE_B) { |
f835f4b3 | 2380 | DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2; /* pure B mode, fixed cck version2 */ |
04d695d7 | 2381 | /*DbgPrint("Pure B mode, use cck rx version2\n");*/ |
8fc8598e JC |
2382 | } |
2383 | ||
e1da1d57 | 2384 | /* decide max/sec/min rssi index */ |
04d695d7 | 2385 | for (i = 0; i < RF90_PATH_MAX; i++) { |
8add1eb5 | 2386 | DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i]; |
8fc8598e | 2387 | |
04d695d7 | 2388 | if (priv->brfpath_rxenable[i]) { |
8fc8598e JC |
2389 | rf_num++; |
2390 | cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i]; | |
2391 | ||
04d695d7 | 2392 | if (rf_num == 1) { /* find first enabled rf path and the rssi values */ |
e1da1d57 | 2393 | /* initialize, set all rssi index to the same one */ |
8fc8598e JC |
2394 | max_rssi_index = min_rssi_index = sec_rssi_index = i; |
2395 | tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi; | |
04d695d7 LS |
2396 | } else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */ |
2397 | if (cur_rf_rssi >= tmp_max_rssi) { | |
8fc8598e JC |
2398 | tmp_max_rssi = cur_rf_rssi; |
2399 | max_rssi_index = i; | |
04d695d7 | 2400 | } else { |
8fc8598e JC |
2401 | tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi; |
2402 | sec_rssi_index = min_rssi_index = i; | |
2403 | } | |
04d695d7 LS |
2404 | } else { |
2405 | if (cur_rf_rssi > tmp_max_rssi) { | |
8fc8598e JC |
2406 | tmp_sec_rssi = tmp_max_rssi; |
2407 | sec_rssi_index = max_rssi_index; | |
2408 | tmp_max_rssi = cur_rf_rssi; | |
2409 | max_rssi_index = i; | |
04d695d7 | 2410 | } else if (cur_rf_rssi == tmp_max_rssi) { /* let sec and min point to the different index */ |
8fc8598e JC |
2411 | tmp_sec_rssi = cur_rf_rssi; |
2412 | sec_rssi_index = i; | |
04d695d7 | 2413 | } else if ((cur_rf_rssi < tmp_max_rssi) && (cur_rf_rssi > tmp_sec_rssi)) { |
8fc8598e JC |
2414 | tmp_sec_rssi = cur_rf_rssi; |
2415 | sec_rssi_index = i; | |
04d695d7 LS |
2416 | } else if (cur_rf_rssi == tmp_sec_rssi) { |
2417 | if (tmp_sec_rssi == tmp_min_rssi) { | |
2418 | /* let sec and min point to the different index */ | |
8fc8598e JC |
2419 | tmp_sec_rssi = cur_rf_rssi; |
2420 | sec_rssi_index = i; | |
04d695d7 | 2421 | } else { |
e1da1d57 | 2422 | /* This case we don't need to set any index */ |
8fc8598e | 2423 | } |
04d695d7 | 2424 | } else if ((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) { |
e1da1d57 | 2425 | /* This case we don't need to set any index */ |
04d695d7 LS |
2426 | } else if (cur_rf_rssi == tmp_min_rssi) { |
2427 | if (tmp_sec_rssi == tmp_min_rssi) { | |
2428 | /* let sec and min point to the different index */ | |
8fc8598e JC |
2429 | tmp_min_rssi = cur_rf_rssi; |
2430 | min_rssi_index = i; | |
04d695d7 | 2431 | } else { |
e1da1d57 | 2432 | /* This case we don't need to set any index */ |
8fc8598e | 2433 | } |
04d695d7 | 2434 | } else if (cur_rf_rssi < tmp_min_rssi) { |
8fc8598e JC |
2435 | tmp_min_rssi = cur_rf_rssi; |
2436 | min_rssi_index = i; | |
2437 | } | |
2438 | } | |
2439 | } | |
2440 | } | |
2441 | ||
2442 | rf_num = 0; | |
e1da1d57 | 2443 | /* decide max/sec/min cck pwdb index */ |
f835f4b3 | 2444 | if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) { |
04d695d7 LS |
2445 | for (i = 0; i < RF90_PATH_MAX; i++) { |
2446 | if (priv->brfpath_rxenable[i]) { | |
8fc8598e JC |
2447 | rf_num++; |
2448 | cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i]; | |
2449 | ||
04d695d7 LS |
2450 | if (rf_num == 1) { /* find first enabled rf path and the rssi values */ |
2451 | /* initialize, set all rssi index to the same one */ | |
8fc8598e JC |
2452 | cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i; |
2453 | tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb; | |
04d695d7 LS |
2454 | } else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */ |
2455 | if (cur_cck_pwdb >= tmp_cck_max_pwdb) { | |
8fc8598e JC |
2456 | tmp_cck_max_pwdb = cur_cck_pwdb; |
2457 | cck_rx_ver2_max_index = i; | |
04d695d7 | 2458 | } else { |
8fc8598e JC |
2459 | tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb; |
2460 | cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i; | |
2461 | } | |
04d695d7 LS |
2462 | } else { |
2463 | if (cur_cck_pwdb > tmp_cck_max_pwdb) { | |
8fc8598e JC |
2464 | tmp_cck_sec_pwdb = tmp_cck_max_pwdb; |
2465 | cck_rx_ver2_sec_index = cck_rx_ver2_max_index; | |
2466 | tmp_cck_max_pwdb = cur_cck_pwdb; | |
2467 | cck_rx_ver2_max_index = i; | |
f0e0f8cf LS |
2468 | } else if (cur_cck_pwdb == tmp_cck_max_pwdb) { |
2469 | /* let sec and min point to the different index */ | |
8fc8598e JC |
2470 | tmp_cck_sec_pwdb = cur_cck_pwdb; |
2471 | cck_rx_ver2_sec_index = i; | |
04d695d7 | 2472 | } else if ((cur_cck_pwdb < tmp_cck_max_pwdb) && (cur_cck_pwdb > tmp_cck_sec_pwdb)) { |
8fc8598e JC |
2473 | tmp_cck_sec_pwdb = cur_cck_pwdb; |
2474 | cck_rx_ver2_sec_index = i; | |
f0e0f8cf LS |
2475 | } else if (cur_cck_pwdb == tmp_cck_sec_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { |
2476 | /* let sec and min point to the different index */ | |
2477 | tmp_cck_sec_pwdb = cur_cck_pwdb; | |
2478 | cck_rx_ver2_sec_index = i; | |
2479 | /* otherwise we don't need to set any index */ | |
04d695d7 | 2480 | } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) { |
e1da1d57 | 2481 | /* This case we don't need to set any index */ |
f0e0f8cf LS |
2482 | } else if (cur_cck_pwdb == tmp_cck_min_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { |
2483 | /* let sec and min point to the different index */ | |
2484 | tmp_cck_min_pwdb = cur_cck_pwdb; | |
2485 | cck_rx_ver2_min_index = i; | |
2486 | /* otherwise we don't need to set any index */ | |
04d695d7 | 2487 | } else if (cur_cck_pwdb < tmp_cck_min_pwdb) { |
8fc8598e JC |
2488 | tmp_cck_min_pwdb = cur_cck_pwdb; |
2489 | cck_rx_ver2_min_index = i; | |
2490 | } | |
2491 | } | |
8fc8598e JC |
2492 | } |
2493 | } | |
2494 | } | |
2495 | ||
d8718e45 | 2496 | /* Set CCK Rx path |
e1da1d57 LS |
2497 | * reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path. |
2498 | */ | |
8fc8598e | 2499 | update_cck_rx_path = 0; |
f835f4b3 | 2500 | if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) { |
8fc8598e JC |
2501 | cck_default_Rx = cck_rx_ver2_max_index; |
2502 | cck_optional_Rx = cck_rx_ver2_sec_index; | |
04d695d7 | 2503 | if (tmp_cck_max_pwdb != -64) |
8fc8598e JC |
2504 | update_cck_rx_path = 1; |
2505 | } | |
2506 | ||
f793836c | 2507 | if (tmp_min_rssi < RX_PATH_SELECTION_SS_TH_LOW && disabled_rf_cnt < 2) { |
2a2271e4 | 2508 | if ((tmp_max_rssi - tmp_min_rssi) >= RX_PATH_SELECTION_DIFF_TH) { |
e1da1d57 | 2509 | /* record the enabled rssi threshold */ |
8fc8598e | 2510 | DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5; |
e1da1d57 LS |
2511 | /* disable the BB Rx path, OFDM */ |
2512 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xc04[3:0] */ | |
2513 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xd04[3:0] */ | |
8fc8598e JC |
2514 | disabled_rf_cnt++; |
2515 | } | |
f835f4b3 | 2516 | if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_1) { |
8fc8598e JC |
2517 | cck_default_Rx = max_rssi_index; |
2518 | cck_optional_Rx = sec_rssi_index; | |
04d695d7 | 2519 | if (tmp_max_rssi) |
8fc8598e JC |
2520 | update_cck_rx_path = 1; |
2521 | } | |
2522 | } | |
2523 | ||
04d695d7 | 2524 | if (update_cck_rx_path) { |
f19a08e7 JW |
2525 | DM_RxPathSelTable.cck_rx_path = (cck_default_Rx<<2)|(cck_optional_Rx); |
2526 | rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_rx_path); | |
8fc8598e JC |
2527 | } |
2528 | ||
68d84843 | 2529 | if (DM_RxPathSelTable.disabled_rf) { |
04d695d7 | 2530 | for (i = 0; i < 4; i++) { |
68d84843 | 2531 | if ((DM_RxPathSelTable.disabled_rf >> i) & 0x1) { /* disabled rf */ |
04d695d7 | 2532 | if (tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) { |
e1da1d57 | 2533 | /* enable the BB Rx path */ |
04d695d7 | 2534 | /*DbgPrint("RF-%d is enabled.\n", 0x1<<i);*/ |
e1da1d57 LS |
2535 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); /* 0xc04[3:0] */ |
2536 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); /* 0xd04[3:0] */ | |
8fc8598e JC |
2537 | DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; |
2538 | disabled_rf_cnt--; | |
2539 | } | |
2540 | } | |
2541 | } | |
2542 | } | |
2543 | } | |
2544 | ||
2545 | /*----------------------------------------------------------------------------- | |
2546 | * Function: dm_check_rx_path_selection() | |
2547 | * | |
2548 | * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI. | |
2549 | * | |
2550 | * Input: NONE | |
2551 | * | |
2552 | * Output: NONE | |
2553 | * | |
2554 | * Return: NONE | |
2555 | * | |
2556 | * Revised History: | |
2557 | * When Who Remark | |
2558 | * 05/28/2008 amy Create Version 0 porting from windows code. | |
2559 | * | |
2560 | *---------------------------------------------------------------------------*/ | |
04d695d7 | 2561 | static void dm_check_rx_path_selection(struct net_device *dev) |
8fc8598e JC |
2562 | { |
2563 | struct r8192_priv *priv = ieee80211_priv(dev); | |
8fc8598e | 2564 | |
04d695d7 LS |
2565 | queue_delayed_work(priv->priv_wq, &priv->rfpath_check_wq, 0); |
2566 | } /* dm_CheckRxRFPath */ | |
8fc8598e | 2567 | |
04d695d7 | 2568 | static void dm_init_fsync(struct net_device *dev) |
8fc8598e JC |
2569 | { |
2570 | struct r8192_priv *priv = ieee80211_priv(dev); | |
2571 | ||
2572 | priv->ieee80211->fsync_time_interval = 500; | |
2573 | priv->ieee80211->fsync_rate_bitmap = 0x0f000800; | |
2574 | priv->ieee80211->fsync_rssi_threshold = 30; | |
8fc8598e | 2575 | priv->ieee80211->bfsync_enable = false; |
8fc8598e | 2576 | priv->ieee80211->fsync_multiple_timeinterval = 3; |
04d695d7 LS |
2577 | priv->ieee80211->fsync_firstdiff_ratethreshold = 100; |
2578 | priv->ieee80211->fsync_seconddiff_ratethreshold = 200; | |
8fc8598e | 2579 | priv->ieee80211->fsync_state = Default_Fsync; |
e1da1d57 | 2580 | priv->framesyncMonitor = 1; /* current default 0xc38 monitor on */ |
d2e5af14 | 2581 | timer_setup(&priv->fsync_timer, dm_fsync_timer_callback, 0); |
8fc8598e JC |
2582 | } |
2583 | ||
8fc8598e JC |
2584 | static void dm_deInit_fsync(struct net_device *dev) |
2585 | { | |
2586 | struct r8192_priv *priv = ieee80211_priv(dev); | |
04d695d7 | 2587 | |
8fc8598e JC |
2588 | del_timer_sync(&priv->fsync_timer); |
2589 | } | |
2590 | ||
d2e5af14 | 2591 | void dm_fsync_timer_callback(struct timer_list *t) |
8fc8598e | 2592 | { |
d2e5af14 KC |
2593 | struct r8192_priv *priv = from_timer(priv, t, fsync_timer); |
2594 | struct net_device *dev = priv->ieee80211->dev; | |
04d695d7 | 2595 | u32 rate_index, rate_count = 0, rate_count_diff = 0; |
8fc8598e JC |
2596 | bool bSwitchFromCountDiff = false; |
2597 | bool bDoubleTimeInterval = false; | |
2598 | ||
04d695d7 | 2599 | if (priv->ieee80211->state == IEEE80211_LINKED && |
f981a79e | 2600 | priv->ieee80211->bfsync_enable && |
04d695d7 | 2601 | (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) { |
e1da1d57 | 2602 | /* Count rate 54, MCS [7], [12, 13, 14, 15] */ |
8fc8598e | 2603 | u32 rate_bitmap; |
04d695d7 LS |
2604 | |
2605 | for (rate_index = 0; rate_index <= 27; rate_index++) { | |
8fc8598e | 2606 | rate_bitmap = 1 << rate_index; |
04d695d7 LS |
2607 | if (priv->ieee80211->fsync_rate_bitmap & rate_bitmap) |
2608 | rate_count += priv->stats.received_rate_histogram[1][rate_index]; | |
8fc8598e JC |
2609 | } |
2610 | ||
04d695d7 | 2611 | if (rate_count < priv->rate_record) |
8fc8598e JC |
2612 | rate_count_diff = 0xffffffff - rate_count + priv->rate_record; |
2613 | else | |
2614 | rate_count_diff = rate_count - priv->rate_record; | |
04d695d7 | 2615 | if (rate_count_diff < priv->rateCountDiffRecord) { |
8fc8598e | 2616 | u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff; |
e1da1d57 | 2617 | /* Continue count */ |
04d695d7 | 2618 | if (DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold) |
4c234ebc | 2619 | priv->ContinueDiffCount++; |
8fc8598e | 2620 | else |
4c234ebc | 2621 | priv->ContinueDiffCount = 0; |
8fc8598e | 2622 | |
e1da1d57 | 2623 | /* Continue count over */ |
04d695d7 | 2624 | if (priv->ContinueDiffCount >= 2) { |
8fc8598e | 2625 | bSwitchFromCountDiff = true; |
4c234ebc | 2626 | priv->ContinueDiffCount = 0; |
8fc8598e | 2627 | } |
04d695d7 | 2628 | } else { |
e1da1d57 | 2629 | /* Stop the continued count */ |
4c234ebc | 2630 | priv->ContinueDiffCount = 0; |
8fc8598e JC |
2631 | } |
2632 | ||
e1da1d57 | 2633 | /* If Count diff <= FsyncRateCountThreshold */ |
04d695d7 | 2634 | if (rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) { |
8fc8598e | 2635 | bSwitchFromCountDiff = true; |
4c234ebc | 2636 | priv->ContinueDiffCount = 0; |
8fc8598e JC |
2637 | } |
2638 | priv->rate_record = rate_count; | |
2639 | priv->rateCountDiffRecord = rate_count_diff; | |
04d695d7 | 2640 | RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync); |
e1da1d57 | 2641 | /* if we never receive those mcs rate and rssi > 30 % then switch fsyn */ |
04d695d7 | 2642 | if (priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) { |
8fc8598e JC |
2643 | bDoubleTimeInterval = true; |
2644 | priv->bswitch_fsync = !priv->bswitch_fsync; | |
04d695d7 | 2645 | if (priv->bswitch_fsync) { |
0b4ef0a6 | 2646 | write_nic_byte(dev, 0xC36, 0x1c); |
8fc8598e | 2647 | write_nic_byte(dev, 0xC3e, 0x90); |
04d695d7 | 2648 | } else { |
8fc8598e | 2649 | write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e JC |
2650 | write_nic_byte(dev, 0xC3e, 0x96); |
2651 | } | |
04d695d7 LS |
2652 | } else if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) { |
2653 | if (priv->bswitch_fsync) { | |
8fc8598e | 2654 | priv->bswitch_fsync = false; |
8fc8598e | 2655 | write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e JC |
2656 | write_nic_byte(dev, 0xC3e, 0x96); |
2657 | } | |
2658 | } | |
04d695d7 LS |
2659 | if (bDoubleTimeInterval) { |
2660 | if (timer_pending(&priv->fsync_timer)) | |
8fc8598e | 2661 | del_timer_sync(&priv->fsync_timer); |
e6be66ff AKC |
2662 | priv->fsync_timer.expires = jiffies + |
2663 | msecs_to_jiffies(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval); | |
8fc8598e | 2664 | add_timer(&priv->fsync_timer); |
04d695d7 LS |
2665 | } else { |
2666 | if (timer_pending(&priv->fsync_timer)) | |
8fc8598e | 2667 | del_timer_sync(&priv->fsync_timer); |
e6be66ff AKC |
2668 | priv->fsync_timer.expires = jiffies + |
2669 | msecs_to_jiffies(priv->ieee80211->fsync_time_interval); | |
8fc8598e JC |
2670 | add_timer(&priv->fsync_timer); |
2671 | } | |
04d695d7 | 2672 | } else { |
e1da1d57 | 2673 | /* Let Register return to default value; */ |
04d695d7 | 2674 | if (priv->bswitch_fsync) { |
8fc8598e | 2675 | priv->bswitch_fsync = false; |
8fc8598e | 2676 | write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e JC |
2677 | write_nic_byte(dev, 0xC3e, 0x96); |
2678 | } | |
4c234ebc | 2679 | priv->ContinueDiffCount = 0; |
8fc8598e | 2680 | write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); |
8fc8598e | 2681 | } |
4c234ebc | 2682 | RT_TRACE(COMP_HALDM, "ContinueDiffCount %d\n", priv->ContinueDiffCount); |
04d695d7 | 2683 | RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync); |
8fc8598e JC |
2684 | } |
2685 | ||
2686 | static void dm_StartHWFsync(struct net_device *dev) | |
2687 | { | |
f8628a47 | 2688 | RT_TRACE(COMP_HALDM, "%s\n", __func__); |
8fc8598e JC |
2689 | write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf); |
2690 | write_nic_byte(dev, 0xc3b, 0x41); | |
2691 | } | |
2692 | ||
2693 | static void dm_EndSWFsync(struct net_device *dev) | |
2694 | { | |
2695 | struct r8192_priv *priv = ieee80211_priv(dev); | |
2696 | ||
f8628a47 | 2697 | RT_TRACE(COMP_HALDM, "%s\n", __func__); |
8fc8598e JC |
2698 | del_timer_sync(&(priv->fsync_timer)); |
2699 | ||
e1da1d57 | 2700 | /* Let Register return to default value; */ |
04d695d7 | 2701 | if (priv->bswitch_fsync) { |
8fc8598e JC |
2702 | priv->bswitch_fsync = false; |
2703 | ||
91e39f09 | 2704 | write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e JC |
2705 | |
2706 | write_nic_byte(dev, 0xC3e, 0x96); | |
2707 | } | |
2708 | ||
4c234ebc | 2709 | priv->ContinueDiffCount = 0; |
8fc8598e | 2710 | write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); |
8fc8598e JC |
2711 | } |
2712 | ||
2713 | static void dm_StartSWFsync(struct net_device *dev) | |
2714 | { | |
2715 | struct r8192_priv *priv = ieee80211_priv(dev); | |
35997ff0 SH |
2716 | u32 rateIndex; |
2717 | u32 rateBitmap; | |
8fc8598e | 2718 | |
0b4ef0a6 | 2719 | RT_TRACE(COMP_HALDM, "%s\n", __func__); |
e1da1d57 | 2720 | /* Initial rate record to zero, start to record. */ |
8fc8598e | 2721 | priv->rate_record = 0; |
e1da1d57 | 2722 | /* Initialize continue diff count to zero, start to record. */ |
4c234ebc | 2723 | priv->ContinueDiffCount = 0; |
8fc8598e JC |
2724 | priv->rateCountDiffRecord = 0; |
2725 | priv->bswitch_fsync = false; | |
2726 | ||
04d695d7 LS |
2727 | if (priv->ieee80211->mode == WIRELESS_MODE_N_24G) { |
2728 | priv->ieee80211->fsync_firstdiff_ratethreshold = 600; | |
8fc8598e | 2729 | priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff; |
04d695d7 LS |
2730 | } else { |
2731 | priv->ieee80211->fsync_firstdiff_ratethreshold = 200; | |
8fc8598e JC |
2732 | priv->ieee80211->fsync_seconddiff_ratethreshold = 200; |
2733 | } | |
04d695d7 LS |
2734 | for (rateIndex = 0; rateIndex <= 27; rateIndex++) { |
2735 | rateBitmap = 1 << rateIndex; | |
2736 | if (priv->ieee80211->fsync_rate_bitmap & rateBitmap) | |
8fc8598e JC |
2737 | priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex]; |
2738 | } | |
04d695d7 | 2739 | if (timer_pending(&priv->fsync_timer)) |
8fc8598e | 2740 | del_timer_sync(&priv->fsync_timer); |
e6be66ff AKC |
2741 | priv->fsync_timer.expires = jiffies + |
2742 | msecs_to_jiffies(priv->ieee80211->fsync_time_interval); | |
8fc8598e JC |
2743 | add_timer(&priv->fsync_timer); |
2744 | ||
8fc8598e | 2745 | write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd); |
8fc8598e JC |
2746 | } |
2747 | ||
2748 | static void dm_EndHWFsync(struct net_device *dev) | |
2749 | { | |
0b4ef0a6 | 2750 | RT_TRACE(COMP_HALDM, "%s\n", __func__); |
8fc8598e JC |
2751 | write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); |
2752 | write_nic_byte(dev, 0xc3b, 0x49); | |
8fc8598e JC |
2753 | } |
2754 | ||
2755 | void dm_check_fsync(struct net_device *dev) | |
2756 | { | |
2757 | #define RegC38_Default 0 | |
04d695d7 LS |
2758 | #define RegC38_NonFsync_Other_AP 1 |
2759 | #define RegC38_Fsync_AP_BCM 2 | |
8fc8598e | 2760 | struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d57 | 2761 | /*u32 framesyncC34;*/ |
04d695d7 | 2762 | static u8 reg_c38_State = RegC38_Default; |
de13a3da | 2763 | static u32 reset_cnt; |
8fc8598e JC |
2764 | |
2765 | RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval); | |
2766 | RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold); | |
2767 | ||
04d695d7 LS |
2768 | if (priv->ieee80211->state == IEEE80211_LINKED && |
2769 | (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) { | |
2770 | if (priv->ieee80211->bfsync_enable == 0) { | |
2771 | switch (priv->ieee80211->fsync_state) { | |
2772 | case Default_Fsync: | |
2773 | dm_StartHWFsync(dev); | |
2774 | priv->ieee80211->fsync_state = HW_Fsync; | |
2775 | break; | |
2776 | case SW_Fsync: | |
2777 | dm_EndSWFsync(dev); | |
2778 | dm_StartHWFsync(dev); | |
2779 | priv->ieee80211->fsync_state = HW_Fsync; | |
2780 | break; | |
2781 | case HW_Fsync: | |
2782 | default: | |
2783 | break; | |
8fc8598e | 2784 | } |
04d695d7 LS |
2785 | } else { |
2786 | switch (priv->ieee80211->fsync_state) { | |
2787 | case Default_Fsync: | |
2788 | dm_StartSWFsync(dev); | |
2789 | priv->ieee80211->fsync_state = SW_Fsync; | |
2790 | break; | |
2791 | case HW_Fsync: | |
2792 | dm_EndHWFsync(dev); | |
2793 | dm_StartSWFsync(dev); | |
2794 | priv->ieee80211->fsync_state = SW_Fsync; | |
2795 | break; | |
2796 | case SW_Fsync: | |
2797 | default: | |
2798 | break; | |
8fc8598e JC |
2799 | } |
2800 | } | |
04d695d7 LS |
2801 | if (priv->framesyncMonitor) { |
2802 | if (reg_c38_State != RegC38_Fsync_AP_BCM) { | |
2803 | /* For broadcom AP we write different default value */ | |
91e39f09 | 2804 | write_nic_byte(dev, rOFDM0_RxDetector3, 0x95); |
8fc8598e JC |
2805 | |
2806 | reg_c38_State = RegC38_Fsync_AP_BCM; | |
2807 | } | |
2808 | } | |
04d695d7 LS |
2809 | } else { |
2810 | switch (priv->ieee80211->fsync_state) { | |
2811 | case HW_Fsync: | |
2812 | dm_EndHWFsync(dev); | |
2813 | priv->ieee80211->fsync_state = Default_Fsync; | |
2814 | break; | |
2815 | case SW_Fsync: | |
2816 | dm_EndSWFsync(dev); | |
2817 | priv->ieee80211->fsync_state = Default_Fsync; | |
2818 | break; | |
2819 | case Default_Fsync: | |
2820 | default: | |
2821 | break; | |
8fc8598e JC |
2822 | } |
2823 | ||
04d695d7 LS |
2824 | if (priv->framesyncMonitor) { |
2825 | if (priv->ieee80211->state == IEEE80211_LINKED) { | |
1bb6d9b9 | 2826 | if (priv->undecorated_smoothed_pwdb <= REG_C38_TH) { |
04d695d7 | 2827 | if (reg_c38_State != RegC38_NonFsync_Other_AP) { |
91e39f09 | 2828 | write_nic_byte(dev, rOFDM0_RxDetector3, 0x90); |
8fc8598e JC |
2829 | |
2830 | reg_c38_State = RegC38_NonFsync_Other_AP; | |
8fc8598e | 2831 | } |
1bb6d9b9 | 2832 | } else if (priv->undecorated_smoothed_pwdb >= (REG_C38_TH + 5)) { |
04d695d7 | 2833 | if (reg_c38_State) { |
8fc8598e JC |
2834 | write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); |
2835 | reg_c38_State = RegC38_Default; | |
04d695d7 | 2836 | /*DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x\n", pHalData->framesync);*/ |
8fc8598e JC |
2837 | } |
2838 | } | |
04d695d7 LS |
2839 | } else { |
2840 | if (reg_c38_State) { | |
8fc8598e JC |
2841 | write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); |
2842 | reg_c38_State = RegC38_Default; | |
04d695d7 | 2843 | /*DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x\n", pHalData->framesync);*/ |
8fc8598e JC |
2844 | } |
2845 | } | |
2846 | } | |
2847 | } | |
04d695d7 LS |
2848 | if (priv->framesyncMonitor) { |
2849 | if (priv->reset_count != reset_cnt) { /* After silent reset, the reg_c38_State will be returned to default value */ | |
8fc8598e JC |
2850 | write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); |
2851 | reg_c38_State = RegC38_Default; | |
2852 | reset_cnt = priv->reset_count; | |
04d695d7 | 2853 | /*DbgPrint("reg_c38_State = 0 for silent reset.\n");*/ |
8fc8598e | 2854 | } |
04d695d7 LS |
2855 | } else { |
2856 | if (reg_c38_State) { | |
8fc8598e JC |
2857 | write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); |
2858 | reg_c38_State = RegC38_Default; | |
04d695d7 | 2859 | /*DbgPrint("framesync no monitor, write 0xc38 = 0x%x\n", pHalData->framesync);*/ |
8fc8598e JC |
2860 | } |
2861 | } | |
2862 | } | |
2863 | ||
8fc8598e JC |
2864 | /*----------------------------------------------------------------------------- |
2865 | * Function: dm_shadow_init() | |
2866 | * | |
2867 | * Overview: Store all NIC MAC/BB register content. | |
2868 | * | |
2869 | * Input: NONE | |
2870 | * | |
2871 | * Output: NONE | |
2872 | * | |
2873 | * Return: NONE | |
2874 | * | |
2875 | * Revised History: | |
2876 | * When Who Remark | |
2877 | * 05/29/2008 amy Create Version 0 porting from windows code. | |
2878 | * | |
2879 | *---------------------------------------------------------------------------*/ | |
c541fa87 | 2880 | void dm_shadow_init(struct net_device *dev) |
8fc8598e JC |
2881 | { |
2882 | u8 page; | |
2883 | u16 offset; | |
2884 | ||
2885 | for (page = 0; page < 5; page++) | |
04d695d7 | 2886 | for (offset = 0; offset < 256; offset++) { |
b6ed32ab | 2887 | read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]); |
e1da1d57 | 2888 | /*DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);*/ |
8fc8598e JC |
2889 | } |
2890 | ||
2891 | for (page = 8; page < 11; page++) | |
2892 | for (offset = 0; offset < 256; offset++) | |
b6ed32ab | 2893 | read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]); |
8fc8598e JC |
2894 | |
2895 | for (page = 12; page < 15; page++) | |
2896 | for (offset = 0; offset < 256; offset++) | |
b6ed32ab | 2897 | read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]); |
8fc8598e JC |
2898 | |
2899 | } /* dm_shadow_init */ | |
2900 | ||
2901 | /*---------------------------Define function prototype------------------------*/ | |
2902 | /*----------------------------------------------------------------------------- | |
2903 | * Function: DM_DynamicTxPower() | |
2904 | * | |
2905 | * Overview: Detect Signal strength to control TX Registry | |
e406322b | 2906 | Tx Power Control For Near/Far Range |
8fc8598e JC |
2907 | * |
2908 | * Input: NONE | |
2909 | * | |
2910 | * Output: NONE | |
2911 | * | |
2912 | * Return: NONE | |
2913 | * | |
2914 | * Revised History: | |
2915 | * When Who Remark | |
2916 | * 03/06/2008 Jacken Create Version 0. | |
2917 | * | |
2918 | *---------------------------------------------------------------------------*/ | |
2919 | static void dm_init_dynamic_txpower(struct net_device *dev) | |
2920 | { | |
2921 | struct r8192_priv *priv = ieee80211_priv(dev); | |
2922 | ||
e1da1d57 LS |
2923 | /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */ |
2924 | priv->ieee80211->bdynamic_txpower_enable = true; /* Default to enable Tx Power Control */ | |
8fc8598e JC |
2925 | priv->bLastDTPFlag_High = false; |
2926 | priv->bLastDTPFlag_Low = false; | |
2927 | priv->bDynamicTxHighPower = false; | |
2928 | priv->bDynamicTxLowPower = false; | |
2929 | } | |
2930 | ||
2931 | static void dm_dynamic_txpower(struct net_device *dev) | |
2932 | { | |
2933 | struct r8192_priv *priv = ieee80211_priv(dev); | |
37f86834 | 2934 | unsigned int txhipower_threshold = 0; |
04d695d7 LS |
2935 | unsigned int txlowpower_threshold = 0; |
2936 | ||
eab439be | 2937 | if (!priv->ieee80211->bdynamic_txpower_enable) { |
8fc8598e JC |
2938 | priv->bDynamicTxHighPower = false; |
2939 | priv->bDynamicTxLowPower = false; | |
2940 | return; | |
2941 | } | |
04d695d7 LS |
2942 | /*printk("priv->ieee80211->current_network.unknown_cap_exist is %d , priv->ieee80211->current_network.broadcom_cap_exist is %d\n", priv->ieee80211->current_network.unknown_cap_exist, priv->ieee80211->current_network.broadcom_cap_exist);*/ |
2943 | if ((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)) { | |
37f86834 | 2944 | txhipower_threshold = TX_POWER_ATHEROAP_THRESH_HIGH; |
8fc8598e | 2945 | txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW; |
04d695d7 | 2946 | } else { |
37f86834 | 2947 | txhipower_threshold = TX_POWER_NEAR_FIELD_THRESH_HIGH; |
8fc8598e JC |
2948 | txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW; |
2949 | } | |
2950 | ||
37f86834 | 2951 | /*printk("=======>%s(): txhipower_threshold is %d, txlowpower_threshold is %d\n", __func__, txhipower_threshold, txlowpower_threshold);*/ |
04d695d7 | 2952 | RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n", priv->undecorated_smoothed_pwdb); |
8fc8598e | 2953 | |
04d695d7 | 2954 | if (priv->ieee80211->state == IEEE80211_LINKED) { |
37f86834 | 2955 | if (priv->undecorated_smoothed_pwdb >= txhipower_threshold) { |
8fc8598e JC |
2956 | priv->bDynamicTxHighPower = true; |
2957 | priv->bDynamicTxLowPower = false; | |
04d695d7 | 2958 | } else { |
e1da1d57 | 2959 | /* high power state check */ |
c40753b5 | 2960 | if (priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower) |
8fc8598e | 2961 | priv->bDynamicTxHighPower = false; |
04d695d7 | 2962 | |
e1da1d57 | 2963 | /* low power state check */ |
16da7808 | 2964 | if (priv->undecorated_smoothed_pwdb < 35) |
8fc8598e | 2965 | priv->bDynamicTxLowPower = true; |
16da7808 | 2966 | else if (priv->undecorated_smoothed_pwdb >= 40) |
8fc8598e | 2967 | priv->bDynamicTxLowPower = false; |
8fc8598e | 2968 | } |
04d695d7 | 2969 | } else { |
e1da1d57 | 2970 | /*pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;*/ |
8fc8598e JC |
2971 | priv->bDynamicTxHighPower = false; |
2972 | priv->bDynamicTxLowPower = false; | |
2973 | } | |
2974 | ||
04d695d7 LS |
2975 | if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) || |
2976 | (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) { | |
2977 | RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190() channel = %d\n", priv->ieee80211->current_network.channel); | |
8fc8598e JC |
2978 | |
2979 | #if defined(RTL8190P) || defined(RTL8192E) | |
04d695d7 | 2980 | SetTxPowerLevel8190(Adapter, pHalData->CurrentChannel); |
8fc8598e JC |
2981 | #endif |
2982 | ||
04d695d7 | 2983 | rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel); |
e1da1d57 | 2984 | /*pHalData->bStartTxCtrlByTPCNFR = FALSE; Clear th flag of Set TX Power from Sitesurvey*/ |
8fc8598e JC |
2985 | } |
2986 | priv->bLastDTPFlag_High = priv->bDynamicTxHighPower; | |
2987 | priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower; | |
2988 | ||
2989 | } /* dm_dynamic_txpower */ | |
2990 | ||
e1da1d57 | 2991 | /* added by vivi, for read tx rate and retrycount */ |
999d594b | 2992 | static void dm_check_txrateandretrycount(struct net_device *dev) |
8fc8598e JC |
2993 | { |
2994 | struct r8192_priv *priv = ieee80211_priv(dev); | |
999d594b | 2995 | struct ieee80211_device *ieee = priv->ieee80211; |
e1da1d57 | 2996 | /* for 11n tx rate */ |
1bb6d9b9 JW |
2997 | /*priv->stats.CurrentShowTxate = read_nic_byte(dev, CURRENT_TX_RATE_REG);*/ |
2998 | read_nic_byte(dev, CURRENT_TX_RATE_REG, &ieee->softmac_stats.CurrentShowTxate); | |
e1da1d57 LS |
2999 | /*printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);*/ |
3000 | /* for initial tx rate */ | |
1bb6d9b9 JW |
3001 | /*priv->stats.last_packet_rate = read_nic_byte(dev, INITIAL_TX_RATE_REG);*/ |
3002 | read_nic_byte(dev, INITIAL_TX_RATE_REG, &ieee->softmac_stats.last_packet_rate); | |
e1da1d57 | 3003 | /* for tx tx retry count */ |
1bb6d9b9 JW |
3004 | /*priv->stats.txretrycount = read_nic_dword(dev, TX_RETRY_COUNT_REG);*/ |
3005 | read_nic_dword(dev, TX_RETRY_COUNT_REG, &ieee->softmac_stats.txretrycount); | |
8fc8598e JC |
3006 | } |
3007 | ||
3008 | static void dm_send_rssi_tofw(struct net_device *dev) | |
3009 | { | |
8fc8598e JC |
3010 | struct r8192_priv *priv = ieee80211_priv(dev); |
3011 | ||
d8718e45 | 3012 | /* If we test chariot, we should stop the TX command ? |
e1da1d57 LS |
3013 | * Because 92E will always silent reset when we send tx command. We use register |
3014 | * 0x1e0(byte) to notify driver. | |
3015 | */ | |
8fc8598e | 3016 | write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb); |
8fc8598e JC |
3017 | } |
3018 | ||
3019 | /*---------------------------Define function prototype------------------------*/ |