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staging: rtl8192e: Cleanup checkpatch -f warnings and errors - Part VIII
[linux-2.6-block.git] / drivers / staging / rtl8192e / rtl_core.h
CommitLineData
94a79942
LF		 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * Based on the r8180 driver, which is:
5 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *
19 * The full GNU General Public License is included in this distribution in the
20 * file called LICENSE.
21 *
22 * Contact Information:
23 * wlanfae <wlanfae@realtek.com>
24******************************************************************************/
25
26#ifndef _RTL_CORE_H
27#define _RTL_CORE_H
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/ioport.h>
33#include <linux/sched.h>
34#include <linux/types.h>
35#include <linux/interrupt.h>
36#include <linux/slab.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/etherdevice.h>
40#include <linux/delay.h>
41#include <linux/rtnetlink.h>
42#include <linux/wireless.h>
43#include <linux/timer.h>
44#include <linux/proc_fs.h>
45#include <linux/if_arp.h>
46#include <linux/random.h>
47#include <linux/version.h>
1344ee25 48#include <linux/io.h>
94a79942
LF		 49#include "rtllib.h"
50
94a79942 51#include "dot11d.h"
94a79942
LF		 52
53#include "r8192E_firmware.h"
54#include "r8192E_hw.h"
55
56#include "r8190P_def.h"
57#include "r8192E_dev.h"
58
94a79942
LF		 59#include "rtl_debug.h"
60#include "rtl_eeprom.h"
61#include "rtl_ps.h"
62#include "rtl_pci.h"
63#include "rtl_cam.h"
64
1344ee25
LF		 65#define DRV_COPYRIGHT \
66 "Copyright(c) 2008 - 2010 Realsil Semiconductor Corporation"
94a79942
LF		 67#define DRV_AUTHOR "<wlanfae@realtek.com>"
68#define DRV_VERSION "0014.0401.2010"
69
70#define DRV_NAME "rtl819xE"
71
1344ee25
LF		 72#define IS_HARDWARE_TYPE_819xP(_priv) \
73 ((((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8190P) || \
74 (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192E))
75#define IS_HARDWARE_TYPE_8192SE(_priv) \
76 (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192SE)
77#define IS_HARDWARE_TYPE_8192CE(_priv) \
78 (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192CE)
79#define IS_HARDWARE_TYPE_8192CU(_priv) \
80 (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192CU)
81#define IS_HARDWARE_TYPE_8192DE(_priv) \
82 (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192DE)
83#define IS_HARDWARE_TYPE_8192DU(_priv) \
84 (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192DU)
94a79942
LF		 85
86#define RTL_PCI_DEVICE(vend, dev, cfg) \
87 .vendor = (vend), .device = (dev), \
1344ee25 88 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID , \
94a79942 89 .driver_data = (kernel_ulong_t)&(cfg)
94a79942 90
9de9f962 91#define irqreturn_type irqreturn_t
94a79942 92
1344ee25 93#define rtl8192_interrupt(x, y, z) rtl8192_interrupt_rsl(x, y)
94a79942
LF		 94
95#define RTL_MAX_SCAN_SIZE 128
96
97#define RTL_RATE_MAX 30
98
99#define TOTAL_CAM_ENTRY 32
100#define CAM_CONTENT_COUNT 8
101
102#ifndef BIT
103#define BIT(_i) (1<<(_i))
104#endif
105
106#define IS_NIC_DOWN(priv) (!(priv)->up)
107
108#define IS_ADAPTER_SENDS_BEACON(dev) 0
109
1344ee25
LF		 110#define IS_UNDER_11N_AES_MODE(_rtllib) \
111 ((_rtllib->pHTInfo->bCurrentHTSupport == true) && \
112 (_rtllib->pairwise_key_type == KEY_TYPE_CCMP))
94a79942
LF		 113
114#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000
115#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
116#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000
117#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
118#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000
119#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
120#define HAL_HW_PCI_REVISION_ID_8192CE 0x1
121#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000
122#define HAL_HW_PCI_REVISION_ID_8192DE 0x0
123#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000
124
125#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
126#define HAL_HW_PCI_8185_DEVICE_ID 0x8185
127#define HAL_HW_PCI_8188_DEVICE_ID 0x8188
128#define HAL_HW_PCI_8198_DEVICE_ID 0x8198
129#define HAL_HW_PCI_8190_DEVICE_ID 0x8190
130#define HAL_HW_PCI_8192_DEVICE_ID 0x8192
1344ee25 131#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192
94a79942
LF		 132#define HAL_HW_PCI_8174_DEVICE_ID 0x8174
133#define HAL_HW_PCI_8173_DEVICE_ID 0x8173
134#define HAL_HW_PCI_8172_DEVICE_ID 0x8172
135#define HAL_HW_PCI_8171_DEVICE_ID 0x8171
1344ee25
LF		 136#define HAL_HW_PCI_0045_DEVICE_ID 0x0045
137#define HAL_HW_PCI_0046_DEVICE_ID 0x0046
138#define HAL_HW_PCI_0044_DEVICE_ID 0x0044
139#define HAL_HW_PCI_0047_DEVICE_ID 0x0047
140#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
141#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
142#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
94a79942 143#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191
1344ee25
LF		 144#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178
145#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177
146#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176
147#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191
148#define HAL_HW_PCI_8192DE_DEVICE_ID 0x092D
149#define HAL_HW_PCI_8192DU_DEVICE_ID 0x092D
94a79942
LF		 150
151#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
152
153#define RTLLIB_WATCH_DOG_TIME 2000
154
1344ee25 155#define MAX_DEV_ADDR_SIZE 8 /*support till 64 bit bus width OS*/
94a79942
LF		 156#define MAX_FIRMWARE_INFORMATION_SIZE 32
157#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
158#define ENCRYPTION_MAX_OVERHEAD 128
159#define MAX_FRAGMENT_COUNT 8
1344ee25
LF		 160#define MAX_TRANSMIT_BUFFER_SIZE \
161 (1600 + (MAX_802_11_HEADER_LENGTH + ENCRYPTION_MAX_OVERHEAD) * \
162 MAX_FRAGMENT_COUNT)
94a79942
LF		 163
164#define scrclng 4
165
166#define DEFAULT_FRAG_THRESHOLD 2342U
167#define MIN_FRAG_THRESHOLD 256U
168#define DEFAULT_BEACONINTERVAL 0x64U
169
170#define DEFAULT_SSID ""
171#define DEFAULT_RETRY_RTS 7
172#define DEFAULT_RETRY_DATA 7
173#define PRISM_HDR_SIZE 64
174
175#define PHY_RSSI_SLID_WIN_MAX 100
176
1344ee25 177#define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV + 30)
94a79942 178
1344ee25
LF		 179#define TxBBGainTableLength 37
180#define CCKTxBBGainTableLength 23
94a79942
LF		 181
182#define CHANNEL_PLAN_LEN 10
1344ee25 183#define sCrcLng 4
94a79942
LF		 184
185#define NIC_SEND_HANG_THRESHOLD_NORMAL 4
186#define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8
187
188#define MAX_TX_QUEUE 9
189
190#define MAX_RX_QUEUE 1
191
1344ee25
LF		 192#define MAX_RX_COUNT 64
193#define MAX_TX_QUEUE_COUNT 9
94a79942
LF		 194
195enum RTL819x_PHY_PARAM {
1344ee25
LF		 196 RTL819X_PHY_MACPHY_REG = 0,
197 RTL819X_PHY_MACPHY_REG_PG = 1,
198 RTL8188C_PHY_MACREG = 2,
199 RTL8192C_PHY_MACREG = 3,
94a79942
LF		 200 RTL819X_PHY_REG = 4,
201 RTL819X_PHY_REG_1T2R = 5,
1344ee25
LF		 202 RTL819X_PHY_REG_to1T1R = 6,
203 RTL819X_PHY_REG_to1T2R = 7,
204 RTL819X_PHY_REG_to2T2R = 8,
94a79942
LF		 205 RTL819X_PHY_REG_PG = 9,
206 RTL819X_AGC_TAB = 10,
1344ee25
LF		 207 RTL819X_PHY_RADIO_A = 11,
208 RTL819X_PHY_RADIO_A_1T = 12,
209 RTL819X_PHY_RADIO_A_2T = 13,
210 RTL819X_PHY_RADIO_B = 14,
211 RTL819X_PHY_RADIO_B_GM = 15,
212 RTL819X_PHY_RADIO_C = 16,
213 RTL819X_PHY_RADIO_D = 17,
214 RTL819X_EEPROM_MAP = 18,
215 RTL819X_EFUSE_MAP = 19,
94a79942
LF		 216};
217
218enum RTL_DEBUG {
219 COMP_TRACE = BIT0,
220 COMP_DBG = BIT1,
221 COMP_INIT = BIT2,
222 COMP_RECV = BIT3,
223 COMP_SEND = BIT4,
224 COMP_CMD = BIT5,
1344ee25
LF		 225 COMP_POWER = BIT6,
226 COMP_EPROM = BIT7,
94a79942
LF		 227 COMP_SWBW = BIT8,
228 COMP_SEC = BIT9,
229 COMP_LPS = BIT10,
230 COMP_QOS = BIT11,
231 COMP_RATE = BIT12,
1344ee25 232 COMP_RXDESC = BIT13,
94a79942
LF		 233 COMP_PHY = BIT14,
234 COMP_DIG = BIT15,
235 COMP_TXAGC = BIT16,
1344ee25 236 COMP_HALDM = BIT17,
94a79942 237 COMP_POWER_TRACKING = BIT18,
1344ee25
LF		 238 COMP_CH = BIT19,
239 COMP_RF = BIT20,
240 COMP_FIRMWARE = BIT21,
241 COMP_HT = BIT22,
94a79942 242 COMP_RESET = BIT23,
1344ee25 243 COMP_CMDPKT = BIT24,
94a79942 244 COMP_SCAN = BIT25,
1344ee25 245 COMP_PS = BIT26,
94a79942
LF		 246 COMP_DOWN = BIT27,
247 COMP_INTR = BIT28,
248 COMP_LED = BIT29,
249 COMP_MLME = BIT30,
250 COMP_ERR = BIT31
251};
252
b55941af 253enum nic_t {
94a79942
LF		 254 NIC_UNKNOWN = 0,
255 NIC_8192E = 1,
256 NIC_8190P = 2,
257 NIC_8192SE = 4,
1344ee25
LF		 258 NIC_8192CE = 5,
259 NIC_8192CU = 6,
260 NIC_8192DE = 7,
261 NIC_8192DU = 8,
262};
94a79942 263
e9463775 264enum rt_eeprom_type {
94a79942
LF		 265 EEPROM_93C46,
266 EEPROM_93C56,
267 EEPROM_BOOT_EFUSE,
e9463775 268};
94a79942 269
aec1148c 270enum dcmg_txcmd_op {
1344ee25 271 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
94a79942
LF		 272 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
273 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
274 TXCMD_SET_TX_DURATION = 0xFF900003,
275 TXCMD_SET_RX_RSSI = 0xFF900004,
276 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
277 TXCMD_XXXX_CTRL,
aec1148c 278};
94a79942 279
fc6094f6 280enum rt_rf_type_819xu {
1344ee25
LF		 281 RF_TYPE_MIN = 0,
282 RF_8225,
283 RF_8256,
284 RF_8258,
285 RF_6052 = 4,
286 RF_PSEUDO_11N = 5,
fc6094f6 287};
94a79942 288
6f44d2bd 289enum rf_step {
1344ee25
LF		 290 RF_STEP_INIT = 0,
291 RF_STEP_NORMAL,
292 RF_STEP_MAX
6f44d2bd 293};
94a79942 294
0fd44425 295enum rt_status {
94a79942
LF		 296 RT_STATUS_SUCCESS,
297 RT_STATUS_FAILURE,
298 RT_STATUS_PENDING,
299 RT_STATUS_RESOURCE
0fd44425 300};
94a79942 301
ed8eac2f 302enum rt_customer_id {
1344ee25 303 RT_CID_DEFAULT = 0,
94a79942
LF		 304 RT_CID_8187_ALPHA0 = 1,
305 RT_CID_8187_SERCOMM_PS = 2,
306 RT_CID_8187_HW_LED = 3,
307 RT_CID_8187_NETGEAR = 4,
1344ee25 308 RT_CID_WHQL = 5,
94a79942
LF		 309 RT_CID_819x_CAMEO = 6,
310 RT_CID_819x_RUNTOP = 7,
311 RT_CID_819x_Senao = 8,
1344ee25 312 RT_CID_TOSHIBA = 9,
94a79942 313 RT_CID_819x_Netcore = 10,
1344ee25
LF		 314 RT_CID_Nettronix = 11,
315 RT_CID_DLINK = 12,
316 RT_CID_PRONET = 13,
317 RT_CID_COREGA = 14,
94a79942
LF		 318 RT_CID_819x_ALPHA = 15,
319 RT_CID_819x_Sitecom = 16,
1344ee25 320 RT_CID_CCX = 17,
94a79942 321 RT_CID_819x_Lenovo = 18,
1344ee25 322 RT_CID_819x_QMI = 19,
94a79942
LF		 323 RT_CID_819x_Edimax_Belkin = 20,
324 RT_CID_819x_Sercomm_Belkin = 21,
325 RT_CID_819x_CAMEO1 = 22,
326 RT_CID_819x_MSI = 23,
327 RT_CID_819x_Acer = 24,
1344ee25 328 RT_CID_819x_HP = 27,
94a79942
LF		 329 RT_CID_819x_CLEVO = 28,
330 RT_CID_819x_Arcadyan_Belkin = 29,
331 RT_CID_819x_SAMSUNG = 30,
332 RT_CID_819x_WNC_COREGA = 31,
ed8eac2f 333};
94a79942 334
ab0d7cca 335enum reset_type {
94a79942
LF		 336 RESET_TYPE_NORESET = 0x00,
337 RESET_TYPE_NORMAL = 0x01,
338 RESET_TYPE_SILENT = 0x02
ab0d7cca 339};
94a79942 340
456419db 341enum ic_inferiority_8192s {
1344ee25
LF		 342 IC_INFERIORITY_A = 0,
343 IC_INFERIORITY_B = 1,
456419db 344};
94a79942 345
2f417815 346enum pci_bridge_vendor {
94a79942
LF		 347 PCI_BRIDGE_VENDOR_INTEL = 0x0,
348 PCI_BRIDGE_VENDOR_ATI,
349 PCI_BRIDGE_VENDOR_AMD,
350 PCI_BRIDGE_VENDOR_SIS ,
351 PCI_BRIDGE_VENDOR_UNKNOWN,
352 PCI_BRIDGE_VENDOR_MAX ,
2f417815 353};
94a79942 354
fc22c052 355struct buffer {
94a79942
LF		 356 struct buffer *next;
357 u32 *buf;
358 dma_addr_t dma;
359
fc22c052 360};
94a79942 361
ebbef649 362struct rtl_reg_debug {
1344ee25
LF		 363 unsigned int cmd;
364 struct {
365 unsigned char type;
366 unsigned char addr;
367 unsigned char page;
368 unsigned char length;
369 } head;
370 unsigned char buf[0xff];
d3b2c172 371};
94a79942 372
9c109856 373struct rt_tx_rahis {
1344ee25
LF		 374 u32 cck[4];
375 u32 ofdm[8];
376 u32 ht_mcs[4][16];
d3b2c172 377};
94a79942 378
9d94bbb8 379struct rt_smooth_data_4rf {
94a79942
LF		 380 char elements[4][100];
381 u32 index;
382 u32 TotalNum;
383 u32 TotalVal[4];
d3b2c172 384};
94a79942 385
2fac6fc4 386struct rt_stats {
94a79942
LF		 387 unsigned long txrdu;
388 unsigned long rxrdu;
389 unsigned long rxok;
390 unsigned long rxframgment;
391 unsigned long rxcmdpkt[4];
392 unsigned long rxurberr;
393 unsigned long rxstaterr;
394 unsigned long rxdatacrcerr;
395 unsigned long rxmgmtcrcerr;
396 unsigned long rxcrcerrmin;
397 unsigned long rxcrcerrmid;
398 unsigned long rxcrcerrmax;
399 unsigned long received_rate_histogram[4][32];
400 unsigned long received_preamble_GI[2][32];
401 unsigned long rx_AMPDUsize_histogram[5];
402 unsigned long rx_AMPDUnum_histogram[5];
403 unsigned long numpacket_matchbssid;
404 unsigned long numpacket_toself;
405 unsigned long num_process_phyinfo;
406 unsigned long numqry_phystatus;
407 unsigned long numqry_phystatusCCK;
408 unsigned long numqry_phystatusHT;
409 unsigned long received_bwtype[5];
410 unsigned long txnperr;
411 unsigned long txnpdrop;
412 unsigned long txresumed;
413 unsigned long rxoverflow;
414 unsigned long rxint;
415 unsigned long txnpokint;
416 unsigned long ints;
417 unsigned long shints;
418 unsigned long txoverflow;
419 unsigned long txlpokint;
420 unsigned long txlpdrop;
421 unsigned long txlperr;
422 unsigned long txbeokint;
423 unsigned long txbedrop;
424 unsigned long txbeerr;
425 unsigned long txbkokint;
426 unsigned long txbkdrop;
427 unsigned long txbkerr;
428 unsigned long txviokint;
429 unsigned long txvidrop;
430 unsigned long txvierr;
431 unsigned long txvookint;
432 unsigned long txvodrop;
433 unsigned long txvoerr;
434 unsigned long txbeaconokint;
435 unsigned long txbeacondrop;
436 unsigned long txbeaconerr;
437 unsigned long txmanageokint;
438 unsigned long txmanagedrop;
439 unsigned long txmanageerr;
440 unsigned long txcmdpktokint;
441 unsigned long txdatapkt;
442 unsigned long txfeedback;
443 unsigned long txfeedbackok;
444 unsigned long txoktotal;
445 unsigned long txokbytestotal;
446 unsigned long txokinperiod;
447 unsigned long txmulticast;
448 unsigned long txbytesmulticast;
449 unsigned long txbroadcast;
450 unsigned long txbytesbroadcast;
451 unsigned long txunicast;
452 unsigned long txbytesunicast;
453 unsigned long rxbytesunicast;
454 unsigned long txfeedbackfail;
455 unsigned long txerrtotal;
456 unsigned long txerrbytestotal;
457 unsigned long txerrmulticast;
458 unsigned long txerrbroadcast;
459 unsigned long txerrunicast;
460 unsigned long txretrycount;
461 unsigned long txfeedbackretry;
1344ee25 462 u8 last_packet_rate;
94a79942
LF		 463 unsigned long slide_signal_strength[100];
464 unsigned long slide_evm[100];
465 unsigned long slide_rssi_total;
466 unsigned long slide_evm_total;
467 long signal_strength;
468 long signal_quality;
469 long last_signal_strength_inpercent;
470 long recv_signal_power;
471 u8 rx_rssi_percentage[4];
472 u8 rx_evm_percentage[2];
473 long rxSNRdB[4];
9c109856 474 struct rt_tx_rahis txrate;
94a79942
LF		 475 u32 Slide_Beacon_pwdb[100];
476 u32 Slide_Beacon_Total;
9d94bbb8 477 struct rt_smooth_data_4rf cck_adc_pwdb;
94a79942 478 u32 CurrentShowTxate;
2fac6fc4 479};
94a79942 480
e91dbf03 481struct channel_access_setting {
94a79942
LF		 482 u16 SIFS_Timer;
483 u16 DIFS_Timer;
484 u16 SlotTimeTimer;
485 u16 EIFS_Timer;
486 u16 CWminIndex;
487 u16 CWmaxIndex;
e91dbf03 488};
94a79942 489
ebc95dd0 490enum two_port_status {
94a79942
LF		 491 TWO_PORT_STATUS__DEFAULT_ONLY,
492 TWO_PORT_STATUS__EXTENSION_ONLY,
493 TWO_PORT_STATUS__EXTENSION_FOLLOW_DEFAULT,
494 TWO_PORT_STATUS__DEFAULT_G_EXTENSION_N20,
495 TWO_PORT_STATUS__ADHOC,
496 TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE
ebc95dd0 497};
94a79942 498
031189ec 499struct txbbgain_struct {
94a79942
LF		 500 long txbb_iq_amplifygain;
501 u32 txbbgain_value;
031189ec 502};
94a79942 503
d514e345 504struct ccktxbbgain {
94a79942 505 u8 ccktxbb_valuearray[8];
d514e345 506};
94a79942 507
43267fef 508struct init_gain {
1344ee25
LF		 509 u8 xaagccore1;
510 u8 xbagccore1;
511 u8 xcagccore1;
512 u8 xdagccore1;
513 u8 cca;
94a79942 514
43267fef 515};
94a79942 516
b7a14040 517struct tx_ring {
1344ee25 518 u32 *desc;
94a79942 519 u8 nStuckCount;
1344ee25 520 struct tx_ring *next;
b7a14040 521} __packed;
94a79942
LF		 522
523struct rtl8192_tx_ring {
1344ee25
LF		 524 struct tx_desc *desc;
525 dma_addr_t dma;
526 unsigned int idx;
527 unsigned int entries;
528 struct sk_buff_head queue;
94a79942
LF		 529};
530
531
532
1344ee25 533struct rtl819x_ops {
b55941af 534 enum nic_t nic_type;
1344ee25
LF		 535 void (*get_eeprom_size)(struct net_device *dev);
536 void (*init_adapter_variable)(struct net_device *dev);
537 void (*init_before_adapter_start)(struct net_device *dev);
538 bool (*initialize_adapter)(struct net_device *dev);
539 void (*link_change)(struct net_device *dev);
540 void (*tx_fill_descriptor)(struct net_device *dev,
541 struct tx_desc *tx_desc,
542 struct cb_desc *cb_desc,
543 struct sk_buff *skb);
544 void (*tx_fill_cmd_descriptor)(struct net_device *dev,
545 struct tx_desc_cmd *entry,
546 struct cb_desc *cb_desc,
547 struct sk_buff *skb);
548 bool (*rx_query_status_descriptor)(struct net_device *dev,
549 struct rtllib_rx_stats *stats,
550 struct rx_desc *pdesc,
551 struct sk_buff *skb);
552 bool (*rx_command_packet_handler)(struct net_device *dev,
553 struct sk_buff *skb,
554 struct rx_desc *pdesc);
555 void (*stop_adapter)(struct net_device *dev, bool reset);
556 void (*update_ratr_table)(struct net_device *dev);
557 void (*irq_enable)(struct net_device *dev);
558 void (*irq_disable)(struct net_device *dev);
559 void (*irq_clear)(struct net_device *dev);
560 void (*rx_enable)(struct net_device *dev);
561 void (*tx_enable)(struct net_device *dev);
562 void (*interrupt_recognized)(struct net_device *dev,
563 u32 *p_inta, u32 *p_intb);
564 bool (*TxCheckStuckHandler)(struct net_device *dev);
565 bool (*RxCheckStuckHandler)(struct net_device *dev);
94a79942
LF		 566};
567
e3e37629 568struct r8192_priv {
94a79942
LF		 569 struct pci_dev *pdev;
570 struct pci_dev *bridge_pdev;
571
94a79942
LF		 572 bool bfirst_init;
573 bool bfirst_after_down;
574 bool initialized_at_probe;
575 bool being_init_adapter;
576 bool bDriverIsGoingToUnload;
577
578 int irq;
579 short irq_enabled;
580
581 short up;
582 short up_first_time;
edc4b2c5
LF		 583 struct delayed_work update_beacon_wq;
584 struct delayed_work watch_dog_wq;
585 struct delayed_work txpower_tracking_wq;
586 struct delayed_work rfpath_check_wq;
587 struct delayed_work gpio_change_rf_wq;
588 struct delayed_work initialgain_operate_wq;
589 struct delayed_work check_hw_scan_wq;
590 struct delayed_work hw_scan_simu_wq;
591 struct delayed_work start_hw_scan_wq;
94a79942
LF		 592
593 struct workqueue_struct *priv_wq;
594
e91dbf03 595 struct channel_access_setting ChannelAccessSetting;
94a79942 596
1897a50c 597 struct mp_adapter NdisAdapter;
94a79942
LF		 598
599 struct rtl819x_ops *ops;
600 struct rtllib_device *rtllib;
601
edc4b2c5 602 struct work_struct reset_wq;
94a79942 603
c13ac63b 604 struct log_int_8190 InterruptLog;
94a79942 605
ed8eac2f 606 enum rt_customer_id CustomerID;
94a79942
LF		 607
608
fc6094f6 609 enum rt_rf_type_819xu rf_chip;
456419db 610 enum ic_inferiority_8192s IC_Class;
6e579119 611 enum ht_channel_width CurrentChannelBW;
9bf6e4c1 612 struct bb_reg_definition PHYRegDef[4];
9be6f10e 613 struct rate_adaptive rate_adaptive;
94a79942 614
d514e345
LF		 615 struct ccktxbbgain cck_txbbgain_table[CCKTxBBGainTableLength];
616 struct ccktxbbgain cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
94a79942 617
031189ec 618 struct txbbgain_struct txbbgain_table[TxBBGainTableLength];
94a79942 619
379a20fb 620 enum acm_method AcmMethod;
94a79942 621
5aca114d 622 struct rt_firmware *pFirmware;
70f9f79c 623 enum rtl819x_loopback LoopbackMode;
9659e7f5 624 enum firmware_source firmware_source;
94a79942
LF		 625
626 struct timer_list watch_dog_timer;
627 struct timer_list fsync_timer;
628 struct timer_list gpio_polling_timer;
629
630 spinlock_t fw_scan_lock;
631 spinlock_t irq_lock;
632 spinlock_t irq_th_lock;
633 spinlock_t tx_lock;
634 spinlock_t rf_ps_lock;
635 spinlock_t rw_lock;
636 spinlock_t rt_h2c_lock;
94a79942
LF		 637 spinlock_t rf_lock;
638 spinlock_t ps_lock;
639
640 struct sk_buff_head rx_queue;
641 struct sk_buff_head skb_queue;
642
643 struct tasklet_struct irq_rx_tasklet;
644 struct tasklet_struct irq_tx_tasklet;
645 struct tasklet_struct irq_prepare_beacon_tasklet;
646
647 struct semaphore wx_sem;
648 struct semaphore rf_sem;
94a79942 649 struct mutex mutex;
94a79942 650
2fac6fc4 651 struct rt_stats stats;
94a79942
LF		 652 struct iw_statistics wstats;
653 struct proc_dir_entry *dir_dev;
654
1344ee25
LF		 655 short (*rf_set_sens)(struct net_device *dev, short sens);
656 u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
94a79942
LF		 657 void (*rf_close)(struct net_device *dev);
658 void (*rf_init)(struct net_device *dev);
659
4f534b36 660 struct rx_desc *rx_ring[MAX_RX_QUEUE];
94a79942
LF		 661 struct sk_buff *rx_buf[MAX_RX_QUEUE][MAX_RX_COUNT];
662 dma_addr_t rx_ring_dma[MAX_RX_QUEUE];
663 unsigned int rx_idx[MAX_RX_QUEUE];
664 int rxringcount;
665 u16 rxbuffersize;
666
0dd56506 667 u64 LastRxDescTSF;
94a79942
LF		 668
669 u16 EarlyRxThreshold;
670 u32 ReceiveConfig;
671 u8 AcmControl;
672 u8 RFProgType;
673 u8 retry_data;
674 u8 retry_rts;
675 u16 rts;
676
677 struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
678 int txringcount;
679 int txbuffsize;
680 int txfwbuffersize;
681 atomic_t tx_pending[0x10];
682
683 u16 ShortRetryLimit;
684 u16 LongRetryLimit;
685 u32 TransmitConfig;
686 u8 RegCWinMin;
687 u8 keepAliveLevel;
688
94a79942
LF		 689 bool sw_radio_on;
690 bool bHwRadioOff;
691 bool pwrdown;
692 bool blinked_ingpio;
693 u8 polling_timer_on;
694
695 /**********************************************************/
696
1344ee25
LF		 697 enum card_type {
698 PCI, MINIPCI,
699 CARDBUS, USB
700 } card_type;
94a79942 701
edc4b2c5 702 struct work_struct qos_activate;
94a79942 703
1344ee25 704 u8 bIbssCoordinator;
94a79942
LF		 705
706 short promisc;
707 short crcmon;
708
1344ee25 709 int txbeaconcount;
94a79942
LF		 710
711 short chan;
712 short sens;
713 short max_sens;
1344ee25 714 u32 rx_prevlen;
94a79942 715
1344ee25
LF		 716 u8 ScanDelay;
717 bool ps_force;
94a79942 718
1344ee25 719 u32 irq_mask[2];
94a79942 720
1344ee25 721 u8 Rf_Mode;
b55941af 722 enum nic_t card_8192;
1344ee25 723 u8 card_8192_version;
94a79942
LF		 724
725 short enable_gpio0;
726
1344ee25
LF		 727 u8 rf_type;
728 u8 IC_Cut;
729 char nick[IW_ESSID_MAX_SIZE + 1];
94a79942 730
1344ee25
LF		 731 u8 RegBcnCtrlVal;
732 bool bHwAntDiv;
94a79942 733
1344ee25
LF		 734 bool bTKIPinNmodeFromReg;
735 bool bWEPinNmodeFromReg;
94a79942 736
1344ee25 737 bool bLedOpenDrain;
94a79942 738
1344ee25 739 u8 check_roaming_cnt;
94a79942 740
1344ee25
LF		 741 bool bIgnoreSilentReset;
742 u32 SilentResetRxSoltNum;
743 u32 SilentResetRxSlotIndex;
744 u32 SilentResetRxStuckEvent[MAX_SILENT_RESET_RX_SLOT_NUM];
94a79942 745
1344ee25
LF		 746 void *scan_cmd;
747 u8 hwscan_bw_40;
94a79942 748
1344ee25
LF		 749 u16 nrxAMPDU_size;
750 u8 nrxAMPDU_aggr_num;
94a79942 751
1344ee25
LF		 752 u32 last_rxdesc_tsf_high;
753 u32 last_rxdesc_tsf_low;
94a79942 754
1344ee25
LF		 755 u16 basic_rate;
756 u8 short_preamble;
757 u8 dot11CurrentPreambleMode;
758 u8 slot_time;
759 u16 SifsTime;
94a79942 760
1344ee25 761 u8 RegWirelessMode;
94a79942 762
1344ee25
LF		 763 u8 firmware_version;
764 u16 FirmwareSubVersion;
765 u16 rf_pathmap;
766 bool AutoloadFailFlag;
94a79942 767
1344ee25
LF		 768 u8 RegPciASPM;
769 u8 RegAMDPciASPM;
770 u8 RegHwSwRfOffD3;
771 u8 RegSupportPciASPM;
772 bool bSupportASPM;
94a79942 773
1344ee25 774 u32 RfRegChnlVal[2];
94a79942 775
1344ee25
LF		 776 u8 ShowRateMode;
777 u8 RATRTableBitmap;
94a79942 778
1344ee25
LF		 779 u8 EfuseMap[2][HWSET_MAX_SIZE_92S];
780 u16 EfuseUsedBytes;
781 u8 EfuseUsedPercentage;
94a79942 782
94a79942 783 short epromtype;
1344ee25
LF		 784 u16 eeprom_vid;
785 u16 eeprom_did;
786 u16 eeprom_svid;
787 u16 eeprom_smid;
788 u8 eeprom_CustomerID;
789 u16 eeprom_ChannelPlan;
790 u8 eeprom_version;
791
792 u8 EEPROMRegulatory;
793 u8 EEPROMPwrGroup[2][3];
794 u8 EEPROMOptional;
795
796 u8 EEPROMTxPowerLevelCCK[14];
797 u8 EEPROMTxPowerLevelOFDM24G[14];
798 u8 EEPROMTxPowerLevelOFDM5G[24];
799 u8 EEPROMRfACCKChnl1TxPwLevel[3];
800 u8 EEPROMRfAOfdmChnlTxPwLevel[3];
801 u8 EEPROMRfCCCKChnl1TxPwLevel[3];
802 u8 EEPROMRfCOfdmChnlTxPwLevel[3];
803 u16 EEPROMTxPowerDiff;
804 u16 EEPROMAntPwDiff;
805 u8 EEPROMThermalMeter;
806 u8 EEPROMPwDiff;
807 u8 EEPROMCrystalCap;
808
809 u8 EEPROMBluetoothCoexist;
810 u8 EEPROMBluetoothType;
811 u8 EEPROMBluetoothAntNum;
812 u8 EEPROMBluetoothAntIsolation;
813 u8 EEPROMBluetoothRadioShared;
814
815
816 u8 EEPROMSupportWoWLAN;
817 u8 EEPROMBoardType;
818 u8 EEPROM_Def_Ver;
819 u8 EEPROMHT2T_TxPwr[6];
820 u8 EEPROMTSSI_A;
821 u8 EEPROMTSSI_B;
822 u8 EEPROMTxPowerLevelCCK_V1[3];
823 u8 EEPROMLegacyHTTxPowerDiff;
824
825 u8 BluetoothCoexist;
826
827 u8 CrystalCap;
828 u8 ThermalMeter[2];
829
830 u16 FwCmdIOMap;
831 u32 FwCmdIOParam;
832
833 u8 SwChnlInProgress;
834 u8 SwChnlStage;
835 u8 SwChnlStep;
836 u8 SetBWModeInProgress;
837
838 u8 nCur40MhzPrimeSC;
839
840 u32 RfReg0Value[4];
841 u8 NumTotalRFPath;
842 bool brfpath_rxenable[4];
843
844 bool bTXPowerDataReadFromEEPORM;
845
846 u16 RegChannelPlan;
847 u16 ChannelPlan;
848 bool bChnlPlanFromHW;
849
850 bool RegRfOff;
851 bool isRFOff;
852 bool bInPowerSaveMode;
853 u8 bHwRfOffAction;
854
855 bool aspm_clkreq_enable;
856 u32 pci_bridge_vendor;
857 u8 RegHostPciASPMSetting;
858 u8 RegDevicePciASPMSetting;
859
860 bool RFChangeInProgress;
861 bool SetRFPowerStateInProgress;
862 bool bdisable_nic;
863
864 u8 pwrGroupCnt;
865
866 u8 ThermalValue_LCK;
867 u8 ThermalValue_IQK;
868 bool bRfPiEnable;
869
870 u32 APKoutput[2][2];
871 bool bAPKdone;
872
873 long RegE94;
874 long RegE9C;
875 long RegEB4;
876 long RegEBC;
877
878 u32 RegC04;
879 u32 Reg874;
880 u32 RegC08;
881 u32 ADDA_backup[16];
882 u32 IQK_MAC_backup[3];
883
884 bool SetFwCmdInProgress;
885 u8 CurrentFwCmdIO;
886
887 u8 rssi_level;
888
889 bool bInformFWDriverControlDM;
890 u8 PwrGroupHT20[2][14];
891 u8 PwrGroupHT40[2][14];
892
893 u8 ThermalValue;
894 long EntryMinUndecoratedSmoothedPWDB;
895 long EntryMaxUndecoratedSmoothedPWDB;
896 u8 DynamicTxHighPowerLvl;
897 u8 LastDTPLvl;
898 u32 CurrentRATR0;
38b1f67d 899 struct false_alarm_stats FalseAlmCnt;
94a79942 900
1344ee25
LF		 901 u8 DMFlag;
902 u8 DM_Type;
903
904 u8 CckPwEnl;
905 u16 TSSI_13dBm;
906 u32 Pwr_Track;
907 u8 CCKPresentAttentuation_20Mdefault;
908 u8 CCKPresentAttentuation_40Mdefault;
909 char CCKPresentAttentuation_difference;
910 char CCKPresentAttentuation;
911 u8 bCckHighPower;
912 long undecorated_smoothed_pwdb;
913 long undecorated_smoothed_cck_adc_pwdb[4];
914
915 u32 MCSTxPowerLevelOriginalOffset[6];
916 u32 CCKTxPowerLevelOriginalOffset;
917 u8 TxPowerLevelCCK[14];
918 u8 TxPowerLevelCCK_A[14];
919 u8 TxPowerLevelCCK_C[14];
94a79942
LF		 920 u8 TxPowerLevelOFDM24G[14];
921 u8 TxPowerLevelOFDM5G[14];
922 u8 TxPowerLevelOFDM24G_A[14];
923 u8 TxPowerLevelOFDM24G_C[14];
924 u8 LegacyHTTxPowerDiff;
925 u8 TxPowerDiff;
926 s8 RF_C_TxPwDiff;
927 s8 RF_B_TxPwDiff;
928 u8 RfTxPwrLevelCck[2][14];
929 u8 RfTxPwrLevelOfdm1T[2][14];
930 u8 RfTxPwrLevelOfdm2T[2][14];
931 u8 AntennaTxPwDiff[3];
932 u8 TxPwrHt20Diff[2][14];
933 u8 TxPwrLegacyHtDiff[2][14];
934 u8 TxPwrSafetyFlag;
935 u8 HT2T_TxPwr_A[14];
936 u8 HT2T_TxPwr_B[14];
937 u8 CurrentCckTxPwrIdx;
938 u8 CurrentOfdm24GTxPwrIdx;
939
940 bool bdynamic_txpower;
941 bool bDynamicTxHighPower;
942 bool bDynamicTxLowPower;
943 bool bLastDTPFlag_High;
944 bool bLastDTPFlag_Low;
945
946 bool bstore_last_dtpflag;
947 bool bstart_txctrl_bydtp;
948
949 u8 rfa_txpowertrackingindex;
950 u8 rfa_txpowertrackingindex_real;
951 u8 rfa_txpowertracking_default;
952 u8 rfc_txpowertrackingindex;
953 u8 rfc_txpowertrackingindex_real;
954 u8 rfc_txpowertracking_default;
955 bool btxpower_tracking;
956 bool bcck_in_ch14;
957
958 u8 TxPowerTrackControl;
959 u8 txpower_count;
960 bool btxpower_trackingInit;
961
962 u8 OFDM_index[2];
963 u8 CCK_index;
964
965 u8 Record_CCK_20Mindex;
966 u8 Record_CCK_40Mindex;
967
43267fef 968 struct init_gain initgain_backup;
94a79942
LF		 969 u8 DefaultInitialGain[4];
970 bool bis_any_nonbepkts;
971 bool bcurrent_turbo_EDCA;
972 bool bis_cur_rdlstate;
973
974 bool bCCKinCH14;
975
976 u8 MidHighPwrTHR_L1;
977 u8 MidHighPwrTHR_L2;
978
979 bool bfsync_processing;
980 u32 rate_record;
981 u32 rateCountDiffRecord;
982 u32 ContiuneDiffCount;
983 bool bswitch_fsync;
984 u8 framesync;
985 u32 framesyncC34;
986 u8 framesyncMonitor;
987
988 bool bDMInitialGainEnable;
1344ee25 989 bool MutualAuthenticationFail;
94a79942
LF		 990
991 bool bDisableFrameBursting;
992
993 u32 reset_count;
994 bool bpbc_pressed;
995
996 u32 txpower_checkcnt;
997 u32 txpower_tracking_callback_cnt;
998 u8 thermal_read_val[40];
999 u8 thermal_readback_index;
1000 u32 ccktxpower_adjustcnt_not_ch14;
1001 u32 ccktxpower_adjustcnt_ch14;
1002
ab0d7cca 1003 enum reset_type ResetProgress;
94a79942
LF		 1004 bool bForcedSilentReset;
1005 bool bDisableNormalResetCheck;
1006 u16 TxCounter;
1007 u16 RxCounter;
1008 int IrpPendingCount;
1009 bool bResetInProgress;
1010 bool force_reset;
1011 bool force_lps;
1012 u8 InitialGainOperateType;
1013
1014 bool chan_forced;
1015 bool bSingleCarrier;
1016 bool RegBoard;
1017 bool bCckContTx;
1018 bool bOfdmContTx;
1019 bool bStartContTx;
1020 u8 RegPaModel;
1021 u8 btMpCckTxPower;
1022 u8 btMpOfdmTxPower;
1023
1024 u32 MptActType;
1025 u32 MptIoOffset;
1026 u32 MptIoValue;
1027 u32 MptRfPath;
1028
1029 u32 MptBandWidth;
1030 u32 MptRateIndex;
1031 u8 MptChannelToSw;
1032 u32 MptRCR;
1033
1034 u8 PwrDomainProtect;
1035 u8 H2CTxCmdSeq;
1036
1037
d3b2c172 1038};
94a79942
LF		 1039
1040extern const struct ethtool_ops rtl819x_ethtool_ops;
1041
1042void rtl8192_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1344ee25 1043short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
94a79942
LF		 1044
1045u8 read_nic_io_byte(struct net_device *dev, int x);
1046u32 read_nic_io_dword(struct net_device *dev, int x);
1047u16 read_nic_io_word(struct net_device *dev, int x) ;
1344ee25
LF		 1048void write_nic_io_byte(struct net_device *dev, int x, u8 y);
1049void write_nic_io_word(struct net_device *dev, int x, u16 y);
1050void write_nic_io_dword(struct net_device *dev, int x, u32 y);
94a79942
LF		 1051
1052u8 read_nic_byte(struct net_device *dev, int x);
1053u32 read_nic_dword(struct net_device *dev, int x);
1054u16 read_nic_word(struct net_device *dev, int x) ;
1344ee25
LF		 1055void write_nic_byte(struct net_device *dev, int x, u8 y);
1056void write_nic_word(struct net_device *dev, int x, u16 y);
1057void write_nic_dword(struct net_device *dev, int x, u32 y);
94a79942
LF		 1058
1059void force_pci_posting(struct net_device *dev);
1060
1061void rtl8192_rx_enable(struct net_device *);
1062void rtl8192_tx_enable(struct net_device *);
1063
1344ee25
LF		 1064int rtl8192_hard_start_xmit(struct sk_buff *skb, struct net_device *dev);
1065void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev,
1066 int rate);
94a79942
LF		 1067void rtl8192_data_hard_stop(struct net_device *dev);
1068void rtl8192_data_hard_resume(struct net_device *dev);
1069void rtl8192_restart(void *data);
1070void rtl819x_watchdog_wqcallback(void *data);
1344ee25 1071void rtl8192_hw_sleep_wq(void *data);
94a79942
LF		 1072void watch_dog_timer_callback(unsigned long data);
1073void rtl8192_irq_rx_tasklet(struct r8192_priv *priv);
1074void rtl8192_irq_tx_tasklet(struct r8192_priv *priv);
1344ee25 1075int rtl8192_down(struct net_device *dev, bool shutdownrf);
94a79942
LF		 1076int rtl8192_up(struct net_device *dev);
1077void rtl8192_commit(struct net_device *dev);
1344ee25 1078void rtl8192_set_chan(struct net_device *dev, short ch);
94a79942
LF		 1079
1080void check_rfctrl_gpio_timer(unsigned long data);
1081
1082void rtl8192_hw_wakeup_wq(void *data);
1083irqreturn_type rtl8192_interrupt(int irq, void *netdev, struct pt_regs *regs);
1084
1085short rtl8192_pci_initdescring(struct net_device *dev);
1086
1344ee25 1087void rtl8192_cancel_deferred_work(struct r8192_priv *priv);
94a79942 1088
1344ee25 1089int _rtl8192_up(struct net_device *dev, bool is_silent_reset);
94a79942
LF		 1090
1091short rtl8192_is_tx_queue_empty(struct net_device *dev);
1092void rtl8192_irq_disable(struct net_device *dev);
1093
1094void rtl8192_tx_timeout(struct net_device *dev);
1095void rtl8192_pci_resetdescring(struct net_device *dev);
1344ee25 1096void rtl8192_SetWirelessMode(struct net_device *dev, u8 wireless_mode);
94a79942 1097void rtl8192_irq_enable(struct net_device *dev);
1344ee25
LF		 1098void rtl8192_config_rate(struct net_device *dev, u16 *rate_config);
1099void rtl8192_update_cap(struct net_device *dev, u16 cap);
94a79942
LF		 1100void rtl8192_irq_disable(struct net_device *dev);
1101
1344ee25
LF		 1102void rtl819x_UpdateRxPktTimeStamp(struct net_device *dev,
1103 struct rtllib_rx_stats *stats);
1104long rtl819x_translate_todbm(struct r8192_priv *priv, u8 signal_strength_index);
1105void rtl819x_update_rxsignalstatistics8190pci(struct r8192_priv *priv,
1106 struct rtllib_rx_stats *pprevious_stats);
94a79942 1107u8 rtl819x_evm_dbtopercentage(char value);
1344ee25
LF		 1108void rtl819x_process_cck_rxpathsel(struct r8192_priv *priv,
1109 struct rtllib_rx_stats *pprevious_stats);
1110u8 rtl819x_query_rxpwrpercentage(char antpower);
1111void rtl8192_record_rxdesc_forlateruse(struct rtllib_rx_stats *psrc_stats,
1112 struct rtllib_rx_stats *ptarget_stats);
1113
1114bool NicIFEnableNIC(struct net_device *dev);
1115bool NicIFDisableNIC(struct net_device *dev);
1116
1117bool MgntActSet_RF_State(struct net_device *dev,
1118 enum rt_rf_power_state StateToSet,
1119 RT_RF_CHANGE_SOURCE ChangeSource,
1120 bool ProtectOrNot);
1121void ActUpdateChannelAccessSetting(struct net_device *dev,
1122 enum wireless_mode WirelessMode,
1123 struct channel_access_setting *ChnlAccessSetting);
94a79942 1124
94a79942 1125#endif
Linux 6.x block layer and io_uring tree(s)