[linux-block.git] / drivers / staging / rtl8192e / rtl819x_HT.h

/******************************************************************************
 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef _RTL819XU_HTTYPE_H_
#define _RTL819XU_HTTYPE_H_


#define HT_OPMODE_NO_PROTECT		0
#define HT_OPMODE_OPTIONAL		1
#define HT_OPMODE_40MHZ_PROTECT	2
#define HT_OPMODE_MIXED			3

#define MIMO_PS_STATIC				0
#define MIMO_PS_DYNAMIC			1
#define MIMO_PS_NOLIMIT			3


#define sHTCLng	4


#define HT_SUPPORTED_MCS_1SS_BITMAP					0x000000ff
#define HT_SUPPORTED_MCS_2SS_BITMAP					0x0000ff00
#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP			HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP


enum ht_mcs_rate {
	HT_MCS0   = 0x00000001,
	HT_MCS1   = 0x00000002,
	HT_MCS2   = 0x00000004,
	HT_MCS3   = 0x00000008,
	HT_MCS4   = 0x00000010,
	HT_MCS5   = 0x00000020,
	HT_MCS6   = 0x00000040,
	HT_MCS7   = 0x00000080,
	HT_MCS8   = 0x00000100,
	HT_MCS9   = 0x00000200,
	HT_MCS10 = 0x00000400,
	HT_MCS11 = 0x00000800,
	HT_MCS12 = 0x00001000,
	HT_MCS13 = 0x00002000,
	HT_MCS14 = 0x00004000,
	HT_MCS15 = 0x00008000,
};

enum ht_channel_width {
	HT_CHANNEL_WIDTH_20 = 0,
	HT_CHANNEL_WIDTH_20_40 = 1,
};

enum ht_extchnl_offset {
	HT_EXTCHNL_OFFSET_NO_EXT = 0,
	HT_EXTCHNL_OFFSET_UPPER = 1,
	HT_EXTCHNL_OFFSET_NO_DEF = 2,
	HT_EXTCHNL_OFFSET_LOWER = 3,
};

enum chnl_op {
	CHNLOP_NONE = 0,
	CHNLOP_SCAN = 1,
	CHNLOP_SWBW = 2,
	CHNLOP_SWCHNL = 3,
};

#define CHHLOP_IN_PROGRESS(_pHTInfo)	\
		((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? true : false

/*
union ht_capability {
	u16	ShortData;
	u8	CharData[2];
	struct
	{
		u16	AdvCoding:1;
		u16	ChlWidth:1;
		u16	MimoPwrSave:2;
		u16	GreenField:1;
		u16	ShortGI20Mhz:1;
		u16	ShortGI40Mhz:1;
		u16	STBC:1;
		u16	BeamForm:1;
		u16	DelayBA:1;
		u16	MaxAMSDUSize:1;
		u16	DssCCk:1;
		u16	PSMP:1;
		u16	Rsvd:3;
	}Field;
};

union ht_capability_macpara {
	u8	ShortData;
	u8	CharData[1];
	struct
	{
		u8	MaxRxAMPDU:2;
		u8	MPDUDensity:2;
		u8	Rsvd:4;
	}Field;
};
*/

enum ht_action {
	ACT_RECOMMAND_WIDTH		= 0,
	ACT_MIMO_PWR_SAVE		= 1,
	ACT_PSMP					= 2,
	ACT_SET_PCO_PHASE		= 3,
	ACT_MIMO_CHL_MEASURE	= 4,
	ACT_RECIPROCITY_CORRECT	= 5,
	ACT_MIMO_CSI_MATRICS		= 6,
	ACT_MIMO_NOCOMPR_STEER	= 7,
	ACT_MIMO_COMPR_STEER		= 8,
	ACT_ANTENNA_SELECT		= 9,
};


enum ht_bw40_sc {
	SC_MODE_DUPLICATE = 0,
	SC_MODE_LOWER = 1,
	SC_MODE_UPPER = 2,
	SC_MODE_FULL40MHZ = 3,
};

struct ht_capab_ele {

	u8	AdvCoding:1;
	u8	ChlWidth:1;
	u8	MimoPwrSave:2;
	u8	GreenField:1;
	u8	ShortGI20Mhz:1;
	u8	ShortGI40Mhz:1;
	u8	TxSTBC:1;
	u8	RxSTBC:2;
	u8	DelayBA:1;
	u8	MaxAMSDUSize:1;
	u8	DssCCk:1;
	u8	PSMP:1;
	u8	Rsvd1:1;
	u8	LSigTxopProtect:1;

	u8	MaxRxAMPDUFactor:2;
	u8	MPDUDensity:3;
	u8	Rsvd2:3;

	u8	MCS[16];


	u16	ExtHTCapInfo;

	u8	TxBFCap[4];

	u8	ASCap;

} __packed;


struct ht_info_ele {
	u8	ControlChl;

	u8	ExtChlOffset:2;
	u8	RecommemdedTxWidth:1;
	u8	RIFS:1;
	u8	PSMPAccessOnly:1;
	u8	SrvIntGranularity:3;

	u8	OptMode:2;
	u8	NonGFDevPresent:1;
	u8	Revd1:5;
	u8	Revd2:8;

	u8	Rsvd3:6;
	u8	DualBeacon:1;
	u8	DualCTSProtect:1;

	u8	SecondaryBeacon:1;
	u8	LSigTxopProtectFull:1;
	u8	PcoActive:1;
	u8	PcoPhase:1;
	u8	Rsvd4:4;

	u8	BasicMSC[16];
} __packed;

struct mimops_ctrl {
	u8	MimoPsEnable:1;
	u8	MimoPsMode:1;
	u8	Reserved:6;
};

typedef enum _HT_SPEC_VER{
	HT_SPEC_VER_IEEE = 0,
	HT_SPEC_VER_EWC = 1,
} HT_SPEC_VER, *PHT_SPEC_VER;

typedef enum _HT_AGGRE_MODE_E{
	HT_AGG_AUTO = 0,
	HT_AGG_FORCE_ENABLE = 1,
	HT_AGG_FORCE_DISABLE = 2,
} HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;


struct rt_hi_throughput {
	u8				bEnableHT;
	u8				bCurrentHTSupport;

	u8				bRegBW40MHz;
	u8				bCurBW40MHz;

	u8				bRegShortGI40MHz;
	u8				bCurShortGI40MHz;

	u8				bRegShortGI20MHz;
	u8				bCurShortGI20MHz;

	u8				bRegSuppCCK;
	u8				bCurSuppCCK;

	HT_SPEC_VER			ePeerHTSpecVer;


	struct ht_capab_ele SelfHTCap;
	struct ht_info_ele SelfHTInfo;

	u8				PeerHTCapBuf[32];
	u8				PeerHTInfoBuf[32];


	u8				bAMSDU_Support;
	u16				nAMSDU_MaxSize;
	u8				bCurrent_AMSDU_Support;
	u16				nCurrent_AMSDU_MaxSize;

	u8				bAMPDUEnable;
	u8				bCurrentAMPDUEnable;
	u8				AMPDU_Factor;
	u8				CurrentAMPDUFactor;
	u8				MPDU_Density;
	u8				CurrentMPDUDensity;

	HT_AGGRE_MODE_E	ForcedAMPDUMode;
	u8				ForcedAMPDUFactor;
	u8				ForcedMPDUDensity;

	HT_AGGRE_MODE_E	ForcedAMSDUMode;
	u16				ForcedAMSDUMaxSize;

	u8				bForcedShortGI;

	u8				CurrentOpMode;

	u8				SelfMimoPs;
	u8				PeerMimoPs;

	enum ht_extchnl_offset CurSTAExtChnlOffset;
	u8				bCurTxBW40MHz;
	u8				PeerBandwidth;

	u8				bSwBwInProgress;
	enum chnl_op ChnlOp;
	u8				SwBwStep;

	u8				bRegRT2RTAggregation;
	u8				RT2RT_HT_Mode;
	u8				bCurrentRT2RTAggregation;
	u8				bCurrentRT2RTLongSlotTime;
	u8				szRT2RTAggBuffer[10];

	u8				bRegRxReorderEnable;
	u8				bCurRxReorderEnable;
	u8				RxReorderWinSize;
	u8				RxReorderPendingTime;
	u16				RxReorderDropCounter;

	u8				bIsPeerBcm;

	u8				IOTPeer;
	u32				IOTAction;
	u8				IOTRaFunc;

	u8	bWAIotBroadcom;
	u8	WAIotTH;

	u8				bAcceptAddbaReq;
} __packed;


struct rt_htinfo_sta_entry {
	u8			bEnableHT;

	u8			bSupportCck;

	u16			AMSDU_MaxSize;

	u8			AMPDU_Factor;
	u8			MPDU_Density;

	u8			HTHighestOperaRate;

	u8			bBw40MHz;

	u8			bCurTxBW40MHz;

	u8			bCurShortGI20MHz;

	u8			bCurShortGI40MHz;

	u8			MimoPs;

	u8			McsRateSet[16];

	u8                      bCurRxReorderEnable;

	u16                     nAMSDU_MaxSize;

};


struct bss_ht {

	u8				bdSupportHT;

	u8					bdHTCapBuf[32];
	u16					bdHTCapLen;
	u8					bdHTInfoBuf[32];
	u16					bdHTInfoLen;

	HT_SPEC_VER				bdHTSpecVer;
	enum ht_channel_width bdBandWidth;

	u8					bdRT2RTAggregation;
	u8					bdRT2RTLongSlotTime;
	u8					RT2RT_HT_Mode;
	u8					bdHT1R;
};

struct mimo_rssi {
	u32	EnableAntenna;
	u32	AntennaA;
	u32	AntennaB;
	u32	AntennaC;
	u32	AntennaD;
	u32	Average;
};

struct mimo_evm {
	u32	EVM1;
	u32    EVM2;
};

struct false_alarm_stats {
	u32	Cnt_Parity_Fail;
	u32	Cnt_Rate_Illegal;
	u32	Cnt_Crc8_fail;
	u32	Cnt_Mcs_fail;
	u32	Cnt_Ofdm_fail;
	u32	Cnt_Cck_fail;
	u32	Cnt_all;
};


extern u8 MCS_FILTER_ALL[16];
extern u8 MCS_FILTER_1SS[16];

#define PICK_RATE(_nLegacyRate, _nMcsRate)	\
		(_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
#define	LEGACY_WIRELESS_MODE	IEEE_MODE_MASK

#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate)	\
					((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
						(LegacyRate):\
						(PICK_RATE(LegacyRate, HTRate))


#define	RATE_ADPT_1SS_MASK		0xFF
#define	RATE_ADPT_2SS_MASK		0xF0
#define	RATE_ADPT_MCS32_MASK		0x01

#define		IS_11N_MCS_RATE(rate)		(rate&0x80)

typedef enum _HT_AGGRE_SIZE_E{
	HT_AGG_SIZE_8K = 0,
	HT_AGG_SIZE_16K = 1,
	HT_AGG_SIZE_32K = 2,
	HT_AGG_SIZE_64K = 3,
} HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;

typedef enum _HT_IOT_PEER_E
{
	HT_IOT_PEER_UNKNOWN = 0,
	HT_IOT_PEER_REALTEK = 1,
	HT_IOT_PEER_REALTEK_92SE = 2,
	HT_IOT_PEER_BROADCOM = 3,
	HT_IOT_PEER_RALINK = 4,
	HT_IOT_PEER_ATHEROS = 5,
	HT_IOT_PEER_CISCO= 6,
	HT_IOT_PEER_MARVELL=7,
	HT_IOT_PEER_92U_SOFTAP = 8,
	HT_IOT_PEER_SELF_SOFTAP = 9,
	HT_IOT_PEER_AIRGO = 10,
	HT_IOT_PEER_MAX = 11,
} HT_IOT_PEER_E, *PHTIOT_PEER_E;

typedef enum _HT_IOT_PEER_SUBTYPE_E
{
	HT_IOT_PEER_ATHEROS_DIR635 = 0,
} HT_IOT_PEER_SUBTYPE_E, *PHTIOT_PEER_SUBTYPE_E;

typedef enum _HT_IOT_ACTION_E{
	HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
	HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
	HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
	HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
	HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
	HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
	HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
	HT_IOT_ACT_CDD_FSYNC = 0x00000080,
	HT_IOT_ACT_PURE_N_MODE = 0x00000100,
	HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
	HT_IOT_ACT_FORCED_RTS = 0x00000400,
	HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
	HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
	HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
	HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,

	HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
	HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
	HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
	HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
	HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
	HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,

        HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
        HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,

        HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
	HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
	HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,

	HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,

} HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;

typedef enum _HT_IOT_RAFUNC{
	HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
	HT_IOT_RAFUNC_PEER_1R = 0x01,
	HT_IOT_RAFUNC_TX_AMSDU = 0x02,
} HT_IOT_RAFUNC, *PHT_IOT_RAFUNC;

typedef enum _RT_HT_CAPBILITY{
	RT_HT_CAP_USE_TURBO_AGGR = 0x01,
	RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
	RT_HT_CAP_USE_AMPDU = 0x04,
	RT_HT_CAP_USE_WOW = 0x8,
	RT_HT_CAP_USE_SOFTAP = 0x10,
	RT_HT_CAP_USE_92SE = 0x20,
} RT_HT_CAPBILITY, *PRT_HT_CAPBILITY;

#endif
Commit	Line	Data
94a79942 LF	1	/******************************************************************************
	2	* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
	3	*
	4	* This program is distributed in the hope that it will be useful, but WITHOUT
	5	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	6	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	7	* more details.
	8	*
	9	* You should have received a copy of the GNU General Public License along with
	10	* this program; if not, write to the Free Software Foundation, Inc.,
	11	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	12	*
	13	* The full GNU General Public License is included in this distribution in the
	14	* file called LICENSE.
	15	*
	16	* Contact Information:
	17	* wlanfae <wlanfae@realtek.com>
	18	******************************************************************************/
ecdfa446 GKH	19	#ifndef _RTL819XU_HTTYPE_H_
	20	#define _RTL819XU_HTTYPE_H_
	21
ecdfa446	22
ecdfa446 GKH	23	#define HT_OPMODE_NO_PROTECT 0
	24	#define HT_OPMODE_OPTIONAL 1
	25	#define HT_OPMODE_40MHZ_PROTECT 2
	26	#define HT_OPMODE_MIXED 3
	27
ecdfa446 GKH	28	#define MIMO_PS_STATIC 0
	29	#define MIMO_PS_DYNAMIC 1
	30	#define MIMO_PS_NOLIMIT 3
	31
	32
ecdfa446 GKH	33
	34	#define sHTCLng 4
	35
	36
	37	#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
	38	#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
	39	#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP\|HT_MCS_1SS_2SS_BITMAP
	40
	41
cc8abb26	42	enum ht_mcs_rate {
ecdfa446 GKH	43	HT_MCS0 = 0x00000001,
	44	HT_MCS1 = 0x00000002,
	45	HT_MCS2 = 0x00000004,
	46	HT_MCS3 = 0x00000008,
	47	HT_MCS4 = 0x00000010,
	48	HT_MCS5 = 0x00000020,
	49	HT_MCS6 = 0x00000040,
	50	HT_MCS7 = 0x00000080,
	51	HT_MCS8 = 0x00000100,
	52	HT_MCS9 = 0x00000200,
	53	HT_MCS10 = 0x00000400,
	54	HT_MCS11 = 0x00000800,
	55	HT_MCS12 = 0x00001000,
	56	HT_MCS13 = 0x00002000,
	57	HT_MCS14 = 0x00004000,
	58	HT_MCS15 = 0x00008000,
cc8abb26	59	};
ecdfa446	60
6e579119	61	enum ht_channel_width {
ecdfa446 GKH	62	HT_CHANNEL_WIDTH_20 = 0,
ecdfa446 GKH	63	HT_CHANNEL_WIDTH_20_40 = 1,
6e579119	64	};
ecdfa446	65
b678bd1f	66	enum ht_extchnl_offset {
ecdfa446 GKH	67	HT_EXTCHNL_OFFSET_NO_EXT = 0,
	68	HT_EXTCHNL_OFFSET_UPPER = 1,
	69	HT_EXTCHNL_OFFSET_NO_DEF = 2,
	70	HT_EXTCHNL_OFFSET_LOWER = 3,
b678bd1f	71	};
ecdfa446	72
c1c5d074	73	enum chnl_op {
94a79942 LF	74	CHNLOP_NONE = 0,
	75	CHNLOP_SCAN = 1,
	76	CHNLOP_SWBW = 2,
	77	CHNLOP_SWCHNL = 3,
c1c5d074	78	};
ecdfa446	79
ecdfa446	80	#define CHHLOP_IN_PROGRESS(_pHTInfo) \
94a79942	81	((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? true : false
ecdfa446 GKH	82
ecdfa446 GKH	83	/*
7d5693b2	84	union ht_capability {
ecdfa446 GKH	85	u16 ShortData;
	86	u8 CharData[2];
	87	struct
	88	{
	89	u16 AdvCoding:1;
	90	u16 ChlWidth:1;
	91	u16 MimoPwrSave:2;
	92	u16 GreenField:1;
	93	u16 ShortGI20Mhz:1;
	94	u16 ShortGI40Mhz:1;
	95	u16 STBC:1;
	96	u16 BeamForm:1;
	97	u16 DelayBA:1;
	98	u16 MaxAMSDUSize:1;
	99	u16 DssCCk:1;
	100	u16 PSMP:1;
	101	u16 Rsvd:3;
	102	}Field;
7d5693b2	103	};
ecdfa446	104
a3e99099	105	union ht_capability_macpara {
ecdfa446 GKH	106	u8 ShortData;
	107	u8 CharData[1];
	108	struct
	109	{
	110	u8 MaxRxAMPDU:2;
	111	u8 MPDUDensity:2;
	112	u8 Rsvd:4;
	113	}Field;
a3e99099	114	};
ecdfa446 GKH	115	*/
ecdfa446 GKH	116
c4e6d760	117	enum ht_action {
ecdfa446	118	ACT_RECOMMAND_WIDTH = 0,
94a79942	119	ACT_MIMO_PWR_SAVE = 1,
ecdfa446 GKH	120	ACT_PSMP = 2,
	121	ACT_SET_PCO_PHASE = 3,
	122	ACT_MIMO_CHL_MEASURE = 4,
	123	ACT_RECIPROCITY_CORRECT = 5,
	124	ACT_MIMO_CSI_MATRICS = 6,
	125	ACT_MIMO_NOCOMPR_STEER = 7,
	126	ACT_MIMO_COMPR_STEER = 8,
	127	ACT_ANTENNA_SELECT = 9,
c4e6d760	128	};
ecdfa446 GKH	129
ecdfa446 GKH	130
11b639c3	131	enum ht_bw40_sc {
ecdfa446 GKH	132	SC_MODE_DUPLICATE = 0,
	133	SC_MODE_LOWER = 1,
	134	SC_MODE_UPPER = 2,
	135	SC_MODE_FULL40MHZ = 3,
11b639c3	136	};
ecdfa446	137
e92b71d5	138	struct ht_capab_ele {
ecdfa446	139
ecdfa446 GKH	140	u8 AdvCoding:1;
	141	u8 ChlWidth:1;
	142	u8 MimoPwrSave:2;
	143	u8 GreenField:1;
	144	u8 ShortGI20Mhz:1;
	145	u8 ShortGI40Mhz:1;
	146	u8 TxSTBC:1;
	147	u8 RxSTBC:2;
	148	u8 DelayBA:1;
	149	u8 MaxAMSDUSize:1;
	150	u8 DssCCk:1;
	151	u8 PSMP:1;
	152	u8 Rsvd1:1;
	153	u8 LSigTxopProtect:1;
	154
ecdfa446 GKH	155	u8 MaxRxAMPDUFactor:2;
	156	u8 MPDUDensity:3;
	157	u8 Rsvd2:3;
	158
ecdfa446 GKH	159	u8 MCS[16];
	160
	161
ecdfa446 GKH	162	u16 ExtHTCapInfo;
ecdfa446 GKH	163
ecdfa446 GKH	164	u8 TxBFCap[4];
ecdfa446 GKH	165
ecdfa446 GKH	166	u8 ASCap;
ecdfa446 GKH	167
e92b71d5	168	} __packed;
ecdfa446	169
ecdfa446	170
407e998e	171	struct ht_info_ele {
ecdfa446 GKH	172	u8 ControlChl;
	173
	174	u8 ExtChlOffset:2;
	175	u8 RecommemdedTxWidth:1;
	176	u8 RIFS:1;
	177	u8 PSMPAccessOnly:1;
	178	u8 SrvIntGranularity:3;
	179
	180	u8 OptMode:2;
	181	u8 NonGFDevPresent:1;
	182	u8 Revd1:5;
	183	u8 Revd2:8;
	184
	185	u8 Rsvd3:6;
	186	u8 DualBeacon:1;
	187	u8 DualCTSProtect:1;
	188
	189	u8 SecondaryBeacon:1;
	190	u8 LSigTxopProtectFull:1;
	191	u8 PcoActive:1;
	192	u8 PcoPhase:1;
	193	u8 Rsvd4:4;
	194
	195	u8 BasicMSC[16];
407e998e	196	} __packed;
ecdfa446	197
7f5e8a0a	198	struct mimops_ctrl {
ecdfa446 GKH	199	u8 MimoPsEnable:1;
	200	u8 MimoPsMode:1;
	201	u8 Reserved:6;
7f5e8a0a	202	};
ecdfa446 GKH	203
	204	typedef enum _HT_SPEC_VER{
	205	HT_SPEC_VER_IEEE = 0,
	206	HT_SPEC_VER_EWC = 1,
d3b2c172	207	} HT_SPEC_VER, *PHT_SPEC_VER;
ecdfa446 GKH	208
	209	typedef enum _HT_AGGRE_MODE_E{
	210	HT_AGG_AUTO = 0,
	211	HT_AGG_FORCE_ENABLE = 1,
	212	HT_AGG_FORCE_DISABLE = 2,
d3b2c172	213	} HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
ecdfa446	214
ecdfa446	215
7796d93e	216	struct rt_hi_throughput {
ecdfa446 GKH	217	u8 bEnableHT;
	218	u8 bCurrentHTSupport;
	219
94a79942 LF	220	u8 bRegBW40MHz;
94a79942 LF	221	u8 bCurBW40MHz;
ecdfa446	222
94a79942 LF	223	u8 bRegShortGI40MHz;
94a79942 LF	224	u8 bCurShortGI40MHz;
ecdfa446	225
94a79942 LF	226	u8 bRegShortGI20MHz;
94a79942 LF	227	u8 bCurShortGI20MHz;
ecdfa446	228
94a79942 LF	229	u8 bRegSuppCCK;
94a79942 LF	230	u8 bCurSuppCCK;
ecdfa446	231
ecdfa446 GKH	232	HT_SPEC_VER ePeerHTSpecVer;
	233
	234
e92b71d5	235	struct ht_capab_ele SelfHTCap;
407e998e	236	struct ht_info_ele SelfHTInfo;
ecdfa446	237
ecdfa446 GKH	238	u8 PeerHTCapBuf[32];
	239	u8 PeerHTInfoBuf[32];
	240
	241
94a79942 LF	242	u8 bAMSDU_Support;
	243	u16 nAMSDU_MaxSize;
	244	u8 bCurrent_AMSDU_Support;
	245	u16 nCurrent_AMSDU_MaxSize;
ecdfa446	246
94a79942 LF	247	u8 bAMPDUEnable;
	248	u8 bCurrentAMPDUEnable;
	249	u8 AMPDU_Factor;
	250	u8 CurrentAMPDUFactor;
	251	u8 MPDU_Density;
	252	u8 CurrentMPDUDensity;
ecdfa446	253
ecdfa446 GKH	254	HT_AGGRE_MODE_E ForcedAMPDUMode;
	255	u8 ForcedAMPDUFactor;
	256	u8 ForcedMPDUDensity;
	257
ecdfa446 GKH	258	HT_AGGRE_MODE_E ForcedAMSDUMode;
	259	u16 ForcedAMSDUMaxSize;
	260
	261	u8 bForcedShortGI;
	262
	263	u8 CurrentOpMode;
	264
ecdfa446 GKH	265	u8 SelfMimoPs;
	266	u8 PeerMimoPs;
	267
b678bd1f	268	enum ht_extchnl_offset CurSTAExtChnlOffset;
94a79942	269	u8 bCurTxBW40MHz;
ecdfa446 GKH	270	u8 PeerBandwidth;
ecdfa446 GKH	271
ecdfa446	272	u8 bSwBwInProgress;
c1c5d074	273	enum chnl_op ChnlOp;
ecdfa446	274	u8 SwBwStep;
ecdfa446	275
ecdfa446	276	u8 bRegRT2RTAggregation;
94a79942	277	u8 RT2RT_HT_Mode;
ecdfa446 GKH	278	u8 bCurrentRT2RTAggregation;
	279	u8 bCurrentRT2RTLongSlotTime;
	280	u8 szRT2RTAggBuffer[10];
	281
ecdfa446 GKH	282	u8 bRegRxReorderEnable;
	283	u8 bCurRxReorderEnable;
	284	u8 RxReorderWinSize;
	285	u8 RxReorderPendingTime;
	286	u16 RxReorderDropCounter;
	287
ecdfa446 GKH	288	u8 bIsPeerBcm;
ecdfa446 GKH	289
ecdfa446 GKH	290	u8 IOTPeer;
ecdfa446 GKH	291	u32 IOTAction;
94a79942 LF	292	u8 IOTRaFunc;
	293
	294	u8 bWAIotBroadcom;
	295	u8 WAIotTH;
	296
94a79942	297	u8 bAcceptAddbaReq;
7796d93e	298	} __packed;
ecdfa446 GKH	299
ecdfa446 GKH	300
ecdfa446	301
9801b9f5	302	struct rt_htinfo_sta_entry {
ecdfa446 GKH	303	u8 bEnableHT;
	304
	305	u8 bSupportCck;
	306
	307	u16 AMSDU_MaxSize;
	308
	309	u8 AMPDU_Factor;
	310	u8 MPDU_Density;
	311
	312	u8 HTHighestOperaRate;
	313
	314	u8 bBw40MHz;
	315
94a79942 LF	316	u8 bCurTxBW40MHz;
	317
	318	u8 bCurShortGI20MHz;
	319
	320	u8 bCurShortGI40MHz;
	321
ecdfa446 GKH	322	u8 MimoPs;
	323
	324	u8 McsRateSet[16];
	325
94a79942 LF	326	u8 bCurRxReorderEnable;
	327
	328	u16 nAMSDU_MaxSize;
ecdfa446	329
d3b2c172	330	};
ecdfa446 GKH	331
	332
	333
	334
	335
ecdfa446	336
a15e76ad	337	struct bss_ht {
ecdfa446 GKH	338
	339	u8 bdSupportHT;
	340
ecdfa446 GKH	341	u8 bdHTCapBuf[32];
	342	u16 bdHTCapLen;
	343	u8 bdHTInfoBuf[32];
	344	u16 bdHTInfoLen;
	345
	346	HT_SPEC_VER bdHTSpecVer;
6e579119	347	enum ht_channel_width bdBandWidth;
ecdfa446 GKH	348
	349	u8 bdRT2RTAggregation;
	350	u8 bdRT2RTLongSlotTime;
94a79942 LF	351	u8 RT2RT_HT_Mode;
94a79942 LF	352	u8 bdHT1R;
a15e76ad	353	};
ecdfa446	354
039a3412	355	struct mimo_rssi {
ecdfa446 GKH	356	u32 EnableAntenna;
ecdfa446 GKH	357	u32 AntennaA;
94a79942 LF	358	u32 AntennaB;
	359	u32 AntennaC;
	360	u32 AntennaD;
ecdfa446	361	u32 Average;
d3b2c172	362	};
ecdfa446	363
d6a15cb8	364	struct mimo_evm {
ecdfa446 GKH	365	u32 EVM1;
ecdfa446 GKH	366	u32 EVM2;
d3b2c172	367	};
ecdfa446	368
38b1f67d	369	struct false_alarm_stats {
ecdfa446	370	u32 Cnt_Parity_Fail;
94a79942	371	u32 Cnt_Rate_Illegal;
ecdfa446	372	u32 Cnt_Crc8_fail;
94a79942 LF	373	u32 Cnt_Mcs_fail;
	374	u32 Cnt_Ofdm_fail;
	375	u32 Cnt_Cck_fail;
ecdfa446	376	u32 Cnt_all;
d3b2c172	377	};
ecdfa446 GKH	378
	379
	380	extern u8 MCS_FILTER_ALL[16];
	381	extern u8 MCS_FILTER_1SS[16];
	382
ecdfa446 GKH	383	#define PICK_RATE(_nLegacyRate, _nMcsRate) \
ecdfa446 GKH	384	(_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
ecdfa446 GKH	385	#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK
	386
	387	#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \
	388	((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
	389	(LegacyRate):\
	390	(PICK_RATE(LegacyRate, HTRate))
	391
	392
	393
94a79942 LF	394	#define RATE_ADPT_1SS_MASK 0xFF
94a79942 LF	395	#define RATE_ADPT_2SS_MASK 0xF0
ecdfa446 GKH	396	#define RATE_ADPT_MCS32_MASK 0x01
ecdfa446 GKH	397
94a79942	398	#define IS_11N_MCS_RATE(rate) (rate&0x80)
ecdfa446	399
d3b2c172	400	typedef enum _HT_AGGRE_SIZE_E{
ecdfa446 GKH	401	HT_AGG_SIZE_8K = 0,
	402	HT_AGG_SIZE_16K = 1,
	403	HT_AGG_SIZE_32K = 2,
	404	HT_AGG_SIZE_64K = 3,
d3b2c172	405	} HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
ecdfa446	406
d3b2c172	407	typedef enum _HT_IOT_PEER_E
ecdfa446 GKH	408	{
	409	HT_IOT_PEER_UNKNOWN = 0,
	410	HT_IOT_PEER_REALTEK = 1,
94a79942 LF	411	HT_IOT_PEER_REALTEK_92SE = 2,
	412	HT_IOT_PEER_BROADCOM = 3,
	413	HT_IOT_PEER_RALINK = 4,
	414	HT_IOT_PEER_ATHEROS = 5,
	415	HT_IOT_PEER_CISCO= 6,
	416	HT_IOT_PEER_MARVELL=7,
	417	HT_IOT_PEER_92U_SOFTAP = 8,
	418	HT_IOT_PEER_SELF_SOFTAP = 9,
	419	HT_IOT_PEER_AIRGO = 10,
	420	HT_IOT_PEER_MAX = 11,
d3b2c172	421	} HT_IOT_PEER_E, *PHTIOT_PEER_E;
ecdfa446	422
d3b2c172	423	typedef enum _HT_IOT_PEER_SUBTYPE_E
94a79942 LF	424	{
94a79942 LF	425	HT_IOT_PEER_ATHEROS_DIR635 = 0,
d3b2c172	426	} HT_IOT_PEER_SUBTYPE_E, *PHTIOT_PEER_SUBTYPE_E;
94a79942	427
d3b2c172	428	typedef enum _HT_IOT_ACTION_E{
ecdfa446 GKH	429	HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
	430	HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
	431	HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
	432	HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
	433	HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
	434	HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
	435	HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
	436	HT_IOT_ACT_CDD_FSYNC = 0x00000080,
	437	HT_IOT_ACT_PURE_N_MODE = 0x00000100,
	438	HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
94a79942 LF	439	HT_IOT_ACT_FORCED_RTS = 0x00000400,
	440	HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
	441	HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
	442	HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
	443	HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
	444
	445	HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
	446	HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
	447	HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
	448	HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
	449	HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
	450	HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
	451
	452	HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
	453	HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
	454
	455	HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
	456	HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
	457	HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
	458
	459	HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
	460
d3b2c172	461	} HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
ecdfa446	462
94a79942 LF	463	typedef enum _HT_IOT_RAFUNC{
	464	HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
	465	HT_IOT_RAFUNC_PEER_1R = 0x01,
	466	HT_IOT_RAFUNC_TX_AMSDU = 0x02,
d3b2c172	467	} HT_IOT_RAFUNC, *PHT_IOT_RAFUNC;
94a79942	468
d3b2c172	469	typedef enum _RT_HT_CAPBILITY{
94a79942 LF	470	RT_HT_CAP_USE_TURBO_AGGR = 0x01,
	471	RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
	472	RT_HT_CAP_USE_AMPDU = 0x04,
	473	RT_HT_CAP_USE_WOW = 0x8,
	474	RT_HT_CAP_USE_SOFTAP = 0x10,
	475	RT_HT_CAP_USE_92SE = 0x20,
d3b2c172	476	} RT_HT_CAPBILITY, *PRT_HT_CAPBILITY;
ecdfa446	477
94a79942	478	#endif