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Merge tag 'v4.12-rc3' into for-linus
[linux-2.6-block.git] / drivers / staging / rtl8188eu / hal / rtl8188e_hal_init.c
CommitLineData
615a4d12
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
615a4d12
LF		 14 ******************************************************************************/
15#define _HAL_INIT_C_
16
691dd0b7 17#include <linux/firmware.h>
f42f52aa 18#include <linux/vmalloc.h>
615a4d12
LF		 19#include <drv_types.h>
20#include <rtw_efuse.h>
41b77d26 21#include <phy.h>
615a4d12
LF		 22#include <rtl8188e_hal.h>
23
24#include <rtw_iol.h>
25
ee5f8a43 26void iol_mode_enable(struct adapter *padapter, u8 enable)
615a4d12
LF		 27{
28 u8 reg_0xf0 = 0;
29
30 if (enable) {
31 /* Enable initial offload */
c7b2e995 32 reg_0xf0 = usb_read8(padapter, REG_SYS_CFG);
e76484d0 33 usb_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN);
615a4d12
LF		 34
35 if (!padapter->bFWReady) {
36 DBG_88E("bFWReady == false call reset 8051...\n");
37 _8051Reset88E(padapter);
38 }
39
40 } else {
41 /* disable initial offload */
c7b2e995 42 reg_0xf0 = usb_read8(padapter, REG_SYS_CFG);
e76484d0 43 usb_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
615a4d12
LF		 44 }
45}
46
ee5f8a43 47s32 iol_execute(struct adapter *padapter, u8 control)
615a4d12
LF		 48{
49 s32 status = _FAIL;
50 u8 reg_0x88 = 0;
ed737494 51 unsigned long start = 0;
615a4d12
LF		 52
53 control = control&0x0f;
c7b2e995 54 reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0);
e76484d0 55 usb_write8(padapter, REG_HMEBOX_E0, reg_0x88|control);
615a4d12 56
c01fb496 57 start = jiffies;
c7b2e995 58 while ((reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0)) & control &&
ed737494 59 jiffies_to_msecs(jiffies - start) < 1000) {
3913c19a 60 udelay(5);
615a4d12
LF		 61 }
62
c7b2e995 63 reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0);
615a4d12
LF		 64 status = (reg_0x88 & control) ? _FAIL : _SUCCESS;
65 if (reg_0x88 & control<<4)
66 status = _FAIL;
67 return status;
68}
69
70static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
71{
72 s32 rst = _SUCCESS;
fc988e14 73
615a4d12 74 iol_mode_enable(padapter, 1);
e76484d0 75 usb_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
615a4d12
LF		 76 rst = iol_execute(padapter, CMD_INIT_LLT);
77 iol_mode_enable(padapter, 0);
78 return rst;
79}
80
615a4d12
LF		 81
82s32 rtl8188e_iol_efuse_patch(struct adapter *padapter)
83{
84 s32 result = _SUCCESS;
85
86 DBG_88E("==> %s\n", __func__);
87 if (rtw_IOL_applied(padapter)) {
88 iol_mode_enable(padapter, 1);
89 result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
90 if (result == _SUCCESS)
91 result = iol_execute(padapter, CMD_EFUSE_PATCH);
92
93 iol_mode_enable(padapter, 0);
94 }
95 return result;
96}
97
615a4d12
LF		 98#define MAX_REG_BOLCK_SIZE 196
99
615a4d12
LF		 100void _8051Reset88E(struct adapter *padapter)
101{
102 u8 u1bTmp;
103
c7b2e995 104 u1bTmp = usb_read8(padapter, REG_SYS_FUNC_EN+1);
9c68ed09
AB		 105 usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT(2)));
106 usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT(2)));
615a4d12
LF		 107 DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n");
108}
109
615a4d12
LF		 110void rtl8188e_InitializeFirmwareVars(struct adapter *padapter)
111{
615a4d12
LF		 112 /* Init Fw LPS related. */
113 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
114
115 /* Init H2C counter. by tynli. 2009.12.09. */
177aa53a 116 padapter->HalData->LastHMEBoxNum = 0;
615a4d12
LF		 117}
118
2490fbf7 119void rtw_hal_free_data(struct adapter *padapter)
615a4d12 120{
615a4d12
LF		 121 kfree(padapter->HalData);
122 padapter->HalData = NULL;
615a4d12
LF		 123}
124
f86fc9b0 125void rtw_hal_read_chip_version(struct adapter *padapter)
615a4d12
LF		 126{
127 u32 value32;
128 struct HAL_VERSION ChipVersion;
177aa53a 129 struct hal_data_8188e *pHalData = padapter->HalData;
615a4d12 130
99ecfb06 131 value32 = usb_read32(padapter, REG_SYS_CFG);
615a4d12 132 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
615a4d12
LF		 133 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
134 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
135
615a4d12
LF		 136 dump_chip_info(ChipVersion);
137
138 pHalData->VersionID = ChipVersion;
615a4d12
LF		 139}
140
685adf8a 141void rtw_hal_set_odm_var(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
615a4d12 142{
177aa53a
IS		 143 struct odm_dm_struct *podmpriv = &Adapter->HalData->odmpriv;
144
615a4d12
LF		 145 switch (eVariable) {
146 case HAL_ODM_STA_INFO:
147 {
08a3d85a 148 struct sta_info *psta = pValue1;
8b21696c 149
615a4d12
LF		 150 if (bSet) {
151 DBG_88E("### Set STA_(%d) info\n", psta->mac_id);
152 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
153 ODM_RAInfo_Init(podmpriv, psta->mac_id);
154 } else {
155 DBG_88E("### Clean STA_(%d) info\n", psta->mac_id);
156 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
157 }
158 }
159 break;
160 case HAL_ODM_P2P_STATE:
7399c2c3 161 podmpriv->bWIFI_Direct = bSet;
615a4d12
LF		 162 break;
163 case HAL_ODM_WIFI_DISPLAY_STATE:
7399c2c3 164 podmpriv->bWIFI_Display = bSet;
615a4d12
LF		 165 break;
166 default:
167 break;
168 }
169}
170
91d06962 171void rtw_hal_notch_filter(struct adapter *adapter, bool enable)
615a4d12
LF		 172{
173 if (enable) {
174 DBG_88E("Enable notch filter\n");
9c68ed09 175 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT(1));
615a4d12
LF		 176 } else {
177 DBG_88E("Disable notch filter\n");
9c68ed09 178 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT(1));
615a4d12
LF		 179 }
180}
615a4d12 181
615a4d12
LF		 182/* */
183/* */
184/* LLT R/W/Init function */
185/* */
186/* */
187static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data)
188{
189 s32 status = _SUCCESS;
190 s32 count = 0;
191 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
192 u16 LLTReg = REG_LLT_INIT;
193
fc158079 194 usb_write32(padapter, LLTReg, value);
615a4d12
LF		 195
196 /* polling */
197 do {
99ecfb06 198 value = usb_read32(padapter, LLTReg);
615a4d12
LF		 199 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
200 break;
201
202 if (count > POLLING_LLT_THRESHOLD) {
203 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling write LLT done at address %d!\n", address));
204 status = _FAIL;
205 break;
206 }
3913c19a 207 udelay(5);
615a4d12
LF		 208 } while (count++);
209
210 return status;
211}
212
213s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
214{
215 s32 status = _FAIL;
216 u32 i;
217 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */
218
219 if (rtw_IOL_applied(padapter)) {
220 status = iol_InitLLTTable(padapter, txpktbuf_bndy);
221 } else {
222 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
223 status = _LLTWrite(padapter, i, i + 1);
224 if (_SUCCESS != status)
225 return status;
226 }
227
228 /* end of list */
229 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
230 if (_SUCCESS != status)
231 return status;
232
233 /* Make the other pages as ring buffer */
234 /* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */
235 /* Otherwise used as local loopback buffer. */
236 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
237 status = _LLTWrite(padapter, i, (i + 1));
238 if (_SUCCESS != status)
239 return status;
240 }
241
242 /* Let last entry point to the start entry of ring buffer */
243 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
244 if (_SUCCESS != status) {
245 return status;
246 }
247 }
248
249 return status;
250}
251
252void
253Hal_InitPGData88E(struct adapter *padapter)
254{
255 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
256
257 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
258 if (!is_boot_from_eeprom(padapter)) {
259 /* Read EFUSE real map to shadow. */
b0d255c7 260 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI);
615a4d12
LF		 261 }
262 } else {/* autoload fail */
263 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
264 /* update to default value 0xFF */
265 if (!is_boot_from_eeprom(padapter))
b0d255c7 266 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI);
615a4d12
LF		 267 }
268}
269
270void
271Hal_EfuseParseIDCode88E(
272 struct adapter *padapter,
273 u8 *hwinfo
274 )
275{
276 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
277 u16 EEPROMId;
278
279 /* Checl 0x8129 again for making sure autoload status!! */
280 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
281 if (EEPROMId != RTL_EEPROM_ID) {
282 DBG_88E("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
283 pEEPROM->bautoload_fail_flag = true;
284 } else {
285 pEEPROM->bautoload_fail_flag = false;
286 }
287
288 DBG_88E("EEPROM ID = 0x%04x\n", EEPROMId);
289}
290
291static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, u8 *PROMContent, bool AutoLoadFail)
292{
293 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_88E, group, TxCount = 0;
294
1ce39848 295 memset(pwrInfo24G, 0, sizeof(struct txpowerinfo24g));
615a4d12
LF		 296
297 if (AutoLoadFail) {
298 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
299 /* 2.4G default value */
300 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
301 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
302 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
303 }
304 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
305 if (TxCount == 0) {
306 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
307 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
308 } else {
309 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
310 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
311 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
312 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
313 }
314 }
315 }
316 return;
317 }
318
319 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
320 /* 2.4G default value */
321 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
322 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
323 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
324 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
325 }
326 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
327 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
328 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
329 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
330 }
331 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
332 if (TxCount == 0) {
333 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
334 if (PROMContent[eeAddr] == 0xFF) {
335 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
336 } else {
337 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
9c68ed09 338 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
615a4d12
LF		 339 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
340 }
341
342 if (PROMContent[eeAddr] == 0xFF) {
343 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
344 } else {
345 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
9c68ed09 346 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
615a4d12
LF		 347 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
348 }
349 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
350 eeAddr++;
351 } else {
352 if (PROMContent[eeAddr] == 0xFF) {
353 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
354 } else {
355 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
9c68ed09 356 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
615a4d12
LF		 357 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
358 }
359
360 if (PROMContent[eeAddr] == 0xFF) {
361 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
362 } else {
363 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
9c68ed09 364 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
615a4d12
LF		 365 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
366 }
367 eeAddr++;
368
369 if (PROMContent[eeAddr] == 0xFF) {
370 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
371 } else {
372 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
9c68ed09 373 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
615a4d12
LF		 374 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
375 }
376
377 if (PROMContent[eeAddr] == 0xFF) {
378 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
379 } else {
380 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
9c68ed09 381 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
615a4d12
LF		 382 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
383 }
384 eeAddr++;
385 }
386 }
387 }
388}
389
390static u8 Hal_GetChnlGroup88E(u8 chnl, u8 *pGroup)
391{
392 u8 bIn24G = true;
393
394 if (chnl <= 14) {
395 bIn24G = true;
396
5e809e50 397 if (chnl < 3) /* Channel 1-2 */
615a4d12
LF		 398 *pGroup = 0;
399 else if (chnl < 6) /* Channel 3-5 */
400 *pGroup = 1;
401 else if (chnl < 9) /* Channel 6-8 */
402 *pGroup = 2;
403 else if (chnl < 12) /* Channel 9-11 */
404 *pGroup = 3;
405 else if (chnl < 14) /* Channel 12-13 */
406 *pGroup = 4;
407 else if (chnl == 14) /* Channel 14 */
408 *pGroup = 5;
409 } else {
32b5844e
IS		 410
411 /* probably, this branch is suitable only for 5 GHz */
412
615a4d12
LF		 413 bIn24G = false;
414
415 if (chnl <= 40)
416 *pGroup = 0;
417 else if (chnl <= 48)
418 *pGroup = 1;
419 else if (chnl <= 56)
420 *pGroup = 2;
421 else if (chnl <= 64)
422 *pGroup = 3;
423 else if (chnl <= 104)
424 *pGroup = 4;
425 else if (chnl <= 112)
426 *pGroup = 5;
427 else if (chnl <= 120)
428 *pGroup = 5;
429 else if (chnl <= 128)
430 *pGroup = 6;
431 else if (chnl <= 136)
432 *pGroup = 7;
433 else if (chnl <= 144)
434 *pGroup = 8;
435 else if (chnl <= 153)
436 *pGroup = 9;
437 else if (chnl <= 161)
438 *pGroup = 10;
439 else if (chnl <= 177)
440 *pGroup = 11;
441 }
442 return bIn24G;
443}
444
445void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
446{
447 if (AutoLoadFail) {
448 padapter->pwrctrlpriv.bHWPowerdown = false;
449 padapter->pwrctrlpriv.bSupportRemoteWakeup = false;
450 } else {
451 /* hw power down mode selection , 0:rf-off / 1:power down */
452
453 if (padapter->registrypriv.hwpdn_mode == 2)
9c68ed09 454 padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT(4));
615a4d12
LF		 455 else
456 padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode;
457
458 /* decide hw if support remote wakeup function */
459 /* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */
9c68ed09 460 padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false;
615a4d12
LF		 461
462 DBG_88E("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) , bSupportRemoteWakeup(%x)\n", __func__,
62f98689 463 padapter->pwrctrlpriv.bHWPwrPindetect, padapter->pwrctrlpriv.bHWPowerdown, padapter->pwrctrlpriv.bSupportRemoteWakeup);
615a4d12
LF		 464
465 DBG_88E("### PS params => power_mgnt(%x), usbss_enable(%x) ###\n", padapter->registrypriv.power_mgnt, padapter->registrypriv.usbss_enable);
466 }
467}
468
469void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail)
470{
177aa53a 471 struct hal_data_8188e *pHalData = padapter->HalData;
615a4d12 472 struct txpowerinfo24g pwrInfo24G;
b39db0b1 473 u8 ch, group;
615a4d12
LF		 474 u8 bIn24G, TxCount;
475
476 Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
477
478 if (!AutoLoadFail)
479 pHalData->bTXPowerDataReadFromEEPORM = true;
480
b39db0b1
IS		 481 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
482 bIn24G = Hal_GetChnlGroup88E(ch, &group);
483 if (bIn24G) {
484 pHalData->Index24G_CCK_Base[0][ch] = pwrInfo24G.IndexCCK_Base[0][group];
485 if (ch == 14)
486 pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][4];
487 else
488 pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][group];
615a4d12 489 }
b39db0b1
IS		 490 if (bIn24G) {
491 DBG_88E("======= Path %d, Channel %d =======\n", 0, ch);
57935a3f
AB		 492 DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", 0, ch, pHalData->Index24G_CCK_Base[0][ch]);
493 DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", 0, ch, pHalData->Index24G_BW40_Base[0][ch]);
615a4d12
LF		 494 }
495 }
b39db0b1
IS		 496 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
497 pHalData->CCK_24G_Diff[0][TxCount] = pwrInfo24G.CCK_Diff[0][TxCount];
498 pHalData->OFDM_24G_Diff[0][TxCount] = pwrInfo24G.OFDM_Diff[0][TxCount];
499 pHalData->BW20_24G_Diff[0][TxCount] = pwrInfo24G.BW20_Diff[0][TxCount];
500 pHalData->BW40_24G_Diff[0][TxCount] = pwrInfo24G.BW40_Diff[0][TxCount];
501 DBG_88E("======= TxCount %d =======\n", TxCount);
502 DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->CCK_24G_Diff[0][TxCount]);
503 DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->OFDM_24G_Diff[0][TxCount]);
504 DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW20_24G_Diff[0][TxCount]);
505 DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW40_24G_Diff[0][TxCount]);
506 }
615a4d12
LF		 507
508 /* 2010/10/19 MH Add Regulator recognize for CU. */
509 if (!AutoLoadFail) {
510 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); /* bit0~2 */
511 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
512 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
513 } else {
514 pHalData->EEPROMRegulatory = 0;
515 }
516 DBG_88E("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
517}
518
519void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
520{
177aa53a 521 struct hal_data_8188e *pHalData = pAdapter->HalData;
615a4d12
LF		 522
523 if (!AutoLoadFail) {
524 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
525 if (pHalData->CrystalCap == 0xFF)
526 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
527 } else {
528 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
529 }
530 DBG_88E("CrystalCap: 0x%2x\n", pHalData->CrystalCap);
531}
532
533void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
534{
177aa53a 535 struct hal_data_8188e *pHalData = pAdapter->HalData;
615a4d12
LF		 536
537 if (!AutoLoadFail)
07add2d3
AM		 538 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_88E]
539 & 0xE0) >> 5;
615a4d12
LF		 540 else
541 pHalData->BoardType = 0;
542 DBG_88E("Board Type: 0x%2x\n", pHalData->BoardType);
543}
544
545void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
546{
177aa53a 547 struct hal_data_8188e *pHalData = padapter->HalData;
615a4d12
LF		 548
549 if (!AutoLoadFail) {
550 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
551 if (pHalData->EEPROMVersion == 0xFF)
552 pHalData->EEPROMVersion = EEPROM_Default_Version;
553 } else {
554 pHalData->EEPROMVersion = 1;
555 }
556 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
557 ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
558 pHalData->EEPROMVersion));
559}
560
561void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
562{
563 padapter->mlmepriv.ChannelPlan =
564 hal_com_get_channel_plan(padapter,
565 hwinfo ? hwinfo[EEPROM_ChannelPlan_88E] : 0xFF,
566 padapter->registrypriv.channel_plan,
567 RT_CHANNEL_DOMAIN_WORLD_WIDE_13, AutoLoadFail);
568
569 DBG_88E("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
570}
571
572void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
573{
177aa53a 574 struct hal_data_8188e *pHalData = padapter->HalData;
615a4d12
LF		 575
576 if (!AutoLoadFail) {
577 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E];
578 } else {
579 pHalData->EEPROMCustomerID = 0;
580 pHalData->EEPROMSubCustomerID = 0;
581 }
582 DBG_88E("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
583}
584
585void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, bool AutoLoadFail)
586{
177aa53a 587 struct hal_data_8188e *pHalData = pAdapter->HalData;
615a4d12
LF		 588 struct registry_priv *registry_par = &pAdapter->registrypriv;
589
590 if (!AutoLoadFail) {
591 /* Antenna Diversity setting. */
592 if (registry_par->antdiv_cfg == 2) { /* 2:By EFUSE */
593 pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3;
594 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
74772fcf 595 pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;
615a4d12
LF		 596 } else {
597 pHalData->AntDivCfg = registry_par->antdiv_cfg; /* 0:OFF , 1:ON, 2:By EFUSE */
598 }
599
600 if (registry_par->antdiv_type == 0) {
601 /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
602 pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
603 if (pHalData->TRxAntDivType == 0xFF)
604 pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
605 } else {
606 pHalData->TRxAntDivType = registry_par->antdiv_type;
607 }
608
609 if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
610 pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */
611 } else {
612 pHalData->AntDivCfg = 0;
613 pHalData->TRxAntDivType = pHalData->TRxAntDivType; /* The value in the driver setting of device manager. */
614 }
615 DBG_88E("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n", pHalData->AntDivCfg, pHalData->TRxAntDivType);
616}
617
618void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
619{
177aa53a 620 struct hal_data_8188e *pHalData = Adapter->HalData;
615a4d12
LF		 621
622 /* ThermalMeter from EEPROM */
623 if (!AutoloadFail)
624 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
625 else
626 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
627
628 if (pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) {
629 pHalData->bAPKThermalMeterIgnore = true;
630 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
631 }
632 DBG_88E("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter);
633}
Linux 6.x block layer and io_uring tree(s)