Commit | Line | Data |
---|---|---|
c8d86be3 GKH |
1 | /* |
2 | This is part of rtl818x pci OpenSource driver - v 0.1 | |
3 | Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> | |
4 | Released under the terms of GPL (General Public License) | |
5 | ||
6 | Parts of this driver are based on the GPL part of the official | |
7 | Realtek driver. | |
8 | ||
9 | Parts of this driver are based on the rtl8180 driver skeleton | |
10 | from Patric Schenke & Andres Salomon. | |
11 | ||
12 | Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. | |
13 | ||
14 | Parts of BB/RF code are derived from David Young rtl8180 netbsd driver. | |
15 | ||
16 | RSSI calc function from 'The Deuce' | |
17 | ||
18 | Some ideas borrowed from the 8139too.c driver included in linux kernel. | |
19 | ||
20 | We (I?) want to thanks the Authors of those projecs and also the | |
21 | Ndiswrapper's project Authors. | |
22 | ||
23 | A big big thanks goes also to Realtek corp. for their help in my attempt to | |
24 | add RTL8185 and RTL8225 support, and to David Young also. | |
b6d11c07 BZ |
25 | |
26 | Power management interface routines. | |
27 | Written by Mariusz Matuszek. | |
c8d86be3 GKH |
28 | */ |
29 | ||
c8d86be3 | 30 | #undef RX_DONT_PASS_UL |
c8d86be3 | 31 | #undef DUMMY_RX |
c8d86be3 | 32 | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
c8d86be3 | 34 | #include <linux/syscalls.h> |
742821ce | 35 | #include <linux/eeprom_93cx6.h> |
219eb47e | 36 | #include <linux/interrupt.h> |
fd882783 | 37 | |
c8d86be3 GKH |
38 | #include "r8180_hw.h" |
39 | #include "r8180.h" | |
c8d86be3 | 40 | #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */ |
c8d86be3 GKH |
41 | #include "r8180_93cx6.h" /* Card EEPROM */ |
42 | #include "r8180_wx.h" | |
43 | #include "r8180_dm.h" | |
44 | ||
fd9b8d6e | 45 | #include "ieee80211/dot11d.h" |
c8d86be3 | 46 | |
c8d86be3 | 47 | static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = { |
cb73da25 JC |
48 | { |
49 | .vendor = PCI_VENDOR_ID_REALTEK, | |
50 | .device = 0x8199, | |
51 | .subvendor = PCI_ANY_ID, | |
52 | .subdevice = PCI_ANY_ID, | |
53 | .driver_data = 0, | |
54 | }, | |
55 | { | |
56 | .vendor = 0, | |
57 | .device = 0, | |
58 | .subvendor = 0, | |
59 | .subdevice = 0, | |
60 | .driver_data = 0, | |
61 | } | |
c8d86be3 GKH |
62 | }; |
63 | ||
64 | ||
dca41306 | 65 | static char ifname[IFNAMSIZ] = "wlan%d"; |
c8d86be3 | 66 | static int hwseqnum = 0; |
c8d86be3 GKH |
67 | static int hwwep = 0; |
68 | static int channels = 0x3fff; | |
69 | ||
c8d86be3 GKH |
70 | MODULE_LICENSE("GPL"); |
71 | MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl); | |
72 | MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); | |
73 | MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards"); | |
74 | ||
75 | ||
dca41306 | 76 | module_param_string(ifname, ifname, sizeof(ifname), S_IRUGO|S_IWUSR); |
bbfb5652 PS |
77 | module_param(hwseqnum, int, S_IRUGO|S_IWUSR); |
78 | module_param(hwwep, int, S_IRUGO|S_IWUSR); | |
79 | module_param(channels, int, S_IRUGO|S_IWUSR); | |
c8d86be3 | 80 | |
bbfb5652 PS |
81 | MODULE_PARM_DESC(devname, " Net interface name, wlan%d=default"); |
82 | MODULE_PARM_DESC(hwseqnum, " Try to use hardware 802.11 header sequence numbers. Zero=default"); | |
83 | MODULE_PARM_DESC(hwwep, " Try to use hardware WEP support. Still broken and not available on all cards"); | |
84 | MODULE_PARM_DESC(channels, " Channel bitmask for specific locales. NYI"); | |
c8d86be3 GKH |
85 | |
86 | ||
87 | static int __devinit rtl8180_pci_probe(struct pci_dev *pdev, | |
88 | const struct pci_device_id *id); | |
89 | ||
90 | static void __devexit rtl8180_pci_remove(struct pci_dev *pdev); | |
91 | ||
bbfb5652 | 92 | static void rtl8180_shutdown(struct pci_dev *pdev) |
c8d86be3 GKH |
93 | { |
94 | struct net_device *dev = pci_get_drvdata(pdev); | |
727ae303 AB |
95 | if (dev->netdev_ops->ndo_stop) |
96 | dev->netdev_ops->ndo_stop(dev); | |
c8d86be3 GKH |
97 | pci_disable_device(pdev); |
98 | } | |
99 | ||
b6d11c07 BZ |
100 | static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state) |
101 | { | |
102 | struct net_device *dev = pci_get_drvdata(pdev); | |
103 | ||
104 | if (!netif_running(dev)) | |
105 | goto out_pci_suspend; | |
106 | ||
107 | if (dev->netdev_ops->ndo_stop) | |
108 | dev->netdev_ops->ndo_stop(dev); | |
109 | ||
110 | netif_device_detach(dev); | |
111 | ||
112 | out_pci_suspend: | |
113 | pci_save_state(pdev); | |
114 | pci_disable_device(pdev); | |
115 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
116 | return 0; | |
117 | } | |
118 | ||
119 | static int rtl8180_resume(struct pci_dev *pdev) | |
120 | { | |
121 | struct net_device *dev = pci_get_drvdata(pdev); | |
122 | int err; | |
123 | u32 val; | |
124 | ||
125 | pci_set_power_state(pdev, PCI_D0); | |
126 | ||
127 | err = pci_enable_device(pdev); | |
128 | if (err) { | |
129 | printk(KERN_ERR "%s: pci_enable_device failed on resume\n", | |
130 | dev->name); | |
131 | ||
132 | return err; | |
133 | } | |
134 | ||
135 | pci_restore_state(pdev); | |
136 | ||
137 | /* | |
138 | * Suspend/Resume resets the PCI configuration space, so we have to | |
139 | * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries | |
140 | * from interfering with C3 CPU state. pci_restore_state won't help | |
141 | * here since it only restores the first 64 bytes pci config header. | |
142 | */ | |
143 | pci_read_config_dword(pdev, 0x40, &val); | |
144 | if ((val & 0x0000ff00) != 0) | |
145 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
146 | ||
147 | if (!netif_running(dev)) | |
148 | goto out; | |
149 | ||
150 | if (dev->netdev_ops->ndo_open) | |
151 | dev->netdev_ops->ndo_open(dev); | |
152 | ||
153 | netif_device_attach(dev); | |
154 | out: | |
155 | return 0; | |
156 | } | |
157 | ||
c8d86be3 | 158 | static struct pci_driver rtl8180_pci_driver = { |
fd882783 BZ |
159 | .name = RTL8180_MODULE_NAME, |
160 | .id_table = rtl8180_pci_id_tbl, | |
161 | .probe = rtl8180_pci_probe, | |
162 | .remove = __devexit_p(rtl8180_pci_remove), | |
163 | .suspend = rtl8180_suspend, | |
164 | .resume = rtl8180_resume, | |
c8d86be3 GKH |
165 | .shutdown = rtl8180_shutdown, |
166 | }; | |
167 | ||
c8d86be3 GKH |
168 | u8 read_nic_byte(struct net_device *dev, int x) |
169 | { | |
cb73da25 | 170 | return 0xff&readb((u8 *)dev->mem_start + x); |
c8d86be3 GKH |
171 | } |
172 | ||
173 | u32 read_nic_dword(struct net_device *dev, int x) | |
174 | { | |
cb73da25 | 175 | return readl((u8 *)dev->mem_start + x); |
c8d86be3 GKH |
176 | } |
177 | ||
178 | u16 read_nic_word(struct net_device *dev, int x) | |
179 | { | |
cb73da25 | 180 | return readw((u8 *)dev->mem_start + x); |
c8d86be3 GKH |
181 | } |
182 | ||
bbfb5652 | 183 | void write_nic_byte(struct net_device *dev, int x, u8 y) |
c8d86be3 | 184 | { |
cb73da25 | 185 | writeb(y, (u8 *)dev->mem_start + x); |
c8d86be3 GKH |
186 | udelay(20); |
187 | } | |
188 | ||
bbfb5652 | 189 | void write_nic_dword(struct net_device *dev, int x, u32 y) |
c8d86be3 | 190 | { |
cb73da25 | 191 | writel(y, (u8 *)dev->mem_start + x); |
c8d86be3 GKH |
192 | udelay(20); |
193 | } | |
194 | ||
bbfb5652 | 195 | void write_nic_word(struct net_device *dev, int x, u16 y) |
c8d86be3 | 196 | { |
cb73da25 | 197 | writew(y, (u8 *)dev->mem_start + x); |
c8d86be3 GKH |
198 | udelay(20); |
199 | } | |
200 | ||
c8d86be3 GKH |
201 | inline void force_pci_posting(struct net_device *dev) |
202 | { | |
bbfb5652 | 203 | read_nic_byte(dev, EPROM_CMD); |
c8d86be3 | 204 | mb(); |
c8d86be3 GKH |
205 | } |
206 | ||
c8d86be3 GKH |
207 | irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs); |
208 | void set_nic_rxring(struct net_device *dev); | |
209 | void set_nic_txring(struct net_device *dev); | |
210 | static struct net_device_stats *rtl8180_stats(struct net_device *dev); | |
211 | void rtl8180_commit(struct net_device *dev); | |
212 | void rtl8180_start_tx_beacon(struct net_device *dev); | |
213 | ||
c8d86be3 GKH |
214 | static struct proc_dir_entry *rtl8180_proc = NULL; |
215 | ||
216 | static int proc_get_registers(char *page, char **start, | |
217 | off_t offset, int count, | |
218 | int *eof, void *data) | |
219 | { | |
220 | struct net_device *dev = data; | |
c8d86be3 | 221 | int len = 0; |
bbfb5652 | 222 | int i, n; |
fd882783 | 223 | int max = 0xff; |
c8d86be3 GKH |
224 | |
225 | /* This dump the current register page */ | |
fd882783 BZ |
226 | for (n = 0; n <= max;) { |
227 | len += snprintf(page + len, count - len, "\nD: %2x > ", n); | |
c8d86be3 | 228 | |
fd882783 BZ |
229 | for (i = 0; i < 16 && n <= max; i++, n++) |
230 | len += snprintf(page + len, count - len, "%2x ", | |
231 | read_nic_byte(dev, n)); | |
c8d86be3 | 232 | } |
bbfb5652 | 233 | len += snprintf(page + len, count - len, "\n"); |
c8d86be3 | 234 | |
c8d86be3 GKH |
235 | *eof = 1; |
236 | return len; | |
c8d86be3 GKH |
237 | } |
238 | ||
239 | int get_curr_tx_free_desc(struct net_device *dev, int priority); | |
240 | ||
241 | static int proc_get_stats_hw(char *page, char **start, | |
242 | off_t offset, int count, | |
243 | int *eof, void *data) | |
244 | { | |
c8d86be3 | 245 | int len = 0; |
c8d86be3 | 246 | |
c8d86be3 GKH |
247 | *eof = 1; |
248 | return len; | |
249 | } | |
250 | ||
c8d86be3 GKH |
251 | static int proc_get_stats_rx(char *page, char **start, |
252 | off_t offset, int count, | |
253 | int *eof, void *data) | |
254 | { | |
255 | struct net_device *dev = data; | |
256 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
257 | ||
258 | int len = 0; | |
259 | ||
260 | len += snprintf(page + len, count - len, | |
c8d86be3 GKH |
261 | "RX OK: %lu\n" |
262 | "RX Retry: %lu\n" | |
263 | "RX CRC Error(0-500): %lu\n" | |
264 | "RX CRC Error(500-1000): %lu\n" | |
265 | "RX CRC Error(>1000): %lu\n" | |
266 | "RX ICV Error: %lu\n", | |
267 | priv->stats.rxint, | |
268 | priv->stats.rxerr, | |
269 | priv->stats.rxcrcerrmin, | |
270 | priv->stats.rxcrcerrmid, | |
271 | priv->stats.rxcrcerrmax, | |
272 | priv->stats.rxicverr | |
273 | ); | |
274 | ||
275 | *eof = 1; | |
276 | return len; | |
277 | } | |
278 | ||
c8d86be3 GKH |
279 | static int proc_get_stats_tx(char *page, char **start, |
280 | off_t offset, int count, | |
281 | int *eof, void *data) | |
282 | { | |
283 | struct net_device *dev = data; | |
284 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
285 | ||
286 | int len = 0; | |
287 | unsigned long totalOK; | |
288 | ||
bbfb5652 | 289 | totalOK = priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint; |
c8d86be3 | 290 | len += snprintf(page + len, count - len, |
c8d86be3 GKH |
291 | "TX OK: %lu\n" |
292 | "TX Error: %lu\n" | |
293 | "TX Retry: %lu\n" | |
294 | "TX beacon OK: %lu\n" | |
295 | "TX beacon error: %lu\n", | |
296 | totalOK, | |
297 | priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr, | |
298 | priv->stats.txretry, | |
299 | priv->stats.txbeacon, | |
300 | priv->stats.txbeaconerr | |
301 | ); | |
302 | ||
303 | *eof = 1; | |
304 | return len; | |
305 | } | |
306 | ||
c8d86be3 GKH |
307 | void rtl8180_proc_module_init(void) |
308 | { | |
309 | DMESG("Initializing proc filesystem"); | |
e55d92b9 | 310 | rtl8180_proc = proc_mkdir(RTL8180_MODULE_NAME, init_net.proc_net); |
c8d86be3 GKH |
311 | } |
312 | ||
c8d86be3 GKH |
313 | void rtl8180_proc_module_remove(void) |
314 | { | |
cb73da25 | 315 | remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net); |
c8d86be3 GKH |
316 | } |
317 | ||
c8d86be3 GKH |
318 | void rtl8180_proc_remove_one(struct net_device *dev) |
319 | { | |
320 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
321 | if (priv->dir_dev) { | |
322 | remove_proc_entry("stats-hw", priv->dir_dev); | |
323 | remove_proc_entry("stats-tx", priv->dir_dev); | |
324 | remove_proc_entry("stats-rx", priv->dir_dev); | |
c8d86be3 GKH |
325 | remove_proc_entry("registers", priv->dir_dev); |
326 | remove_proc_entry(dev->name, rtl8180_proc); | |
327 | priv->dir_dev = NULL; | |
328 | } | |
329 | } | |
330 | ||
c8d86be3 GKH |
331 | void rtl8180_proc_init_one(struct net_device *dev) |
332 | { | |
333 | struct proc_dir_entry *e; | |
334 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
fd882783 | 335 | |
be286fd2 | 336 | priv->dir_dev = rtl8180_proc; |
c8d86be3 | 337 | if (!priv->dir_dev) { |
be286fd2 | 338 | DMESGE("Unable to initialize /proc/net/r8180/%s\n", |
c8d86be3 GKH |
339 | dev->name); |
340 | return; | |
341 | } | |
342 | ||
343 | e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO, | |
344 | priv->dir_dev, proc_get_stats_hw, dev); | |
c8d86be3 GKH |
345 | if (!e) { |
346 | DMESGE("Unable to initialize " | |
be286fd2 | 347 | "/proc/net/r8180/%s/stats-hw\n", |
c8d86be3 GKH |
348 | dev->name); |
349 | } | |
350 | ||
351 | e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO, | |
352 | priv->dir_dev, proc_get_stats_rx, dev); | |
c8d86be3 GKH |
353 | if (!e) { |
354 | DMESGE("Unable to initialize " | |
be286fd2 | 355 | "/proc/net/r8180/%s/stats-rx\n", |
c8d86be3 GKH |
356 | dev->name); |
357 | } | |
358 | ||
359 | ||
360 | e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO, | |
361 | priv->dir_dev, proc_get_stats_tx, dev); | |
c8d86be3 GKH |
362 | if (!e) { |
363 | DMESGE("Unable to initialize " | |
be286fd2 | 364 | "/proc/net/r8180/%s/stats-tx\n", |
c8d86be3 GKH |
365 | dev->name); |
366 | } | |
c8d86be3 GKH |
367 | |
368 | e = create_proc_read_entry("registers", S_IFREG | S_IRUGO, | |
369 | priv->dir_dev, proc_get_registers, dev); | |
c8d86be3 GKH |
370 | if (!e) { |
371 | DMESGE("Unable to initialize " | |
be286fd2 | 372 | "/proc/net/r8180/%s/registers\n", |
c8d86be3 GKH |
373 | dev->name); |
374 | } | |
375 | } | |
fd882783 | 376 | |
c8d86be3 GKH |
377 | /* |
378 | FIXME: check if we can use some standard already-existent | |
379 | data type+functions in kernel | |
380 | */ | |
381 | ||
382 | short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma, | |
383 | struct buffer **bufferhead) | |
384 | { | |
cb73da25 | 385 | struct buffer *tmp; |
c8d86be3 | 386 | |
bbfb5652 | 387 | if (!*buffer) { |
c8d86be3 | 388 | |
bbfb5652 | 389 | *buffer = kmalloc(sizeof(struct buffer), GFP_KERNEL); |
c8d86be3 GKH |
390 | |
391 | if (*buffer == NULL) { | |
392 | DMESGE("Failed to kmalloc head of TX/RX struct"); | |
393 | return -1; | |
394 | } | |
bbfb5652 PS |
395 | (*buffer)->next = *buffer; |
396 | (*buffer)->buf = buf; | |
397 | (*buffer)->dma = dma; | |
398 | if (bufferhead != NULL) | |
c8d86be3 GKH |
399 | (*bufferhead) = (*buffer); |
400 | return 0; | |
401 | } | |
bbfb5652 | 402 | tmp = *buffer; |
c8d86be3 | 403 | |
bbfb5652 PS |
404 | while (tmp->next != (*buffer)) |
405 | tmp = tmp->next; | |
406 | tmp->next = kmalloc(sizeof(struct buffer), GFP_KERNEL); | |
53756de3 | 407 | if (tmp->next == NULL) { |
c8d86be3 GKH |
408 | DMESGE("Failed to kmalloc TX/RX struct"); |
409 | return -1; | |
410 | } | |
bbfb5652 PS |
411 | tmp->next->buf = buf; |
412 | tmp->next->dma = dma; | |
413 | tmp->next->next = *buffer; | |
c8d86be3 GKH |
414 | |
415 | return 0; | |
416 | } | |
417 | ||
bbfb5652 | 418 | void buffer_free(struct net_device *dev, struct buffer **buffer, int len, short consistent) |
c8d86be3 GKH |
419 | { |
420 | ||
bbfb5652 | 421 | struct buffer *tmp, *next; |
c8d86be3 | 422 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
bbfb5652 | 423 | struct pci_dev *pdev = priv->pdev; |
c8d86be3 | 424 | |
fd882783 BZ |
425 | if (!*buffer) |
426 | return; | |
c8d86be3 | 427 | |
fd882783 | 428 | tmp = *buffer; |
c8d86be3 | 429 | |
bbfb5652 PS |
430 | do { |
431 | next = tmp->next; | |
432 | if (consistent) { | |
433 | pci_free_consistent(pdev, len, | |
434 | tmp->buf, tmp->dma); | |
435 | } else { | |
c8d86be3 | 436 | pci_unmap_single(pdev, tmp->dma, |
bbfb5652 | 437 | len, PCI_DMA_FROMDEVICE); |
c8d86be3 GKH |
438 | kfree(tmp->buf); |
439 | } | |
440 | kfree(tmp); | |
441 | tmp = next; | |
442 | } | |
bbfb5652 | 443 | while (next != *buffer); |
c8d86be3 | 444 | |
bbfb5652 | 445 | *buffer = NULL; |
c8d86be3 GKH |
446 | } |
447 | ||
c8d86be3 GKH |
448 | void print_buffer(u32 *buffer, int len) |
449 | { | |
450 | int i; | |
bbfb5652 | 451 | u8 *buf = (u8 *)buffer; |
c8d86be3 | 452 | |
bbfb5652 | 453 | printk("ASCII BUFFER DUMP (len: %x):\n", len); |
c8d86be3 | 454 | |
bbfb5652 PS |
455 | for (i = 0; i < len; i++) |
456 | printk("%c", buf[i]); | |
c8d86be3 | 457 | |
bbfb5652 | 458 | printk("\nBINARY BUFFER DUMP (len: %x):\n", len); |
c8d86be3 | 459 | |
bbfb5652 PS |
460 | for (i = 0; i < len; i++) |
461 | printk("%02x", buf[i]); | |
c8d86be3 GKH |
462 | |
463 | printk("\n"); | |
464 | } | |
465 | ||
c8d86be3 GKH |
466 | int get_curr_tx_free_desc(struct net_device *dev, int priority) |
467 | { | |
468 | struct r8180_priv *priv = ieee80211_priv(dev); | |
bbfb5652 PS |
469 | u32 *tail; |
470 | u32 *head; | |
c8d86be3 GKH |
471 | int ret; |
472 | ||
bbfb5652 PS |
473 | switch (priority) { |
474 | case MANAGE_PRIORITY: | |
475 | head = priv->txmapringhead; | |
476 | tail = priv->txmapringtail; | |
477 | break; | |
478 | case BK_PRIORITY: | |
479 | head = priv->txbkpringhead; | |
480 | tail = priv->txbkpringtail; | |
481 | break; | |
482 | case BE_PRIORITY: | |
483 | head = priv->txbepringhead; | |
484 | tail = priv->txbepringtail; | |
485 | break; | |
486 | case VI_PRIORITY: | |
487 | head = priv->txvipringhead; | |
488 | tail = priv->txvipringtail; | |
489 | break; | |
490 | case VO_PRIORITY: | |
491 | head = priv->txvopringhead; | |
492 | tail = priv->txvopringtail; | |
493 | break; | |
494 | case HI_PRIORITY: | |
495 | head = priv->txhpringhead; | |
496 | tail = priv->txhpringtail; | |
497 | break; | |
498 | default: | |
499 | return -1; | |
c8d86be3 GKH |
500 | } |
501 | ||
fd882783 | 502 | if (head <= tail) |
c8d86be3 GKH |
503 | ret = priv->txringcount - (tail - head)/8; |
504 | else | |
505 | ret = (head - tail)/8; | |
506 | ||
fd882783 BZ |
507 | if (ret > priv->txringcount) |
508 | DMESG("BUG"); | |
509 | ||
c8d86be3 | 510 | return ret; |
c8d86be3 GKH |
511 | } |
512 | ||
c8d86be3 GKH |
513 | short check_nic_enought_desc(struct net_device *dev, int priority) |
514 | { | |
515 | struct r8180_priv *priv = ieee80211_priv(dev); | |
516 | struct ieee80211_device *ieee = netdev_priv(dev); | |
c8d86be3 | 517 | int requiredbyte, required; |
fd882783 | 518 | |
c8d86be3 GKH |
519 | requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data); |
520 | ||
fd882783 | 521 | if (ieee->current_network.QoS_Enable) |
c8d86be3 | 522 | requiredbyte += 2; |
c8d86be3 GKH |
523 | |
524 | required = requiredbyte / (priv->txbuffsize-4); | |
fd882783 BZ |
525 | |
526 | if (requiredbyte % priv->txbuffsize) | |
527 | required++; | |
528 | ||
c8d86be3 GKH |
529 | /* for now we keep two free descriptor as a safety boundary |
530 | * between the tail and the head | |
531 | */ | |
532 | ||
bbfb5652 | 533 | return (required+2 < get_curr_tx_free_desc(dev, priority)); |
c8d86be3 GKH |
534 | } |
535 | ||
c8d86be3 GKH |
536 | void fix_tx_fifo(struct net_device *dev) |
537 | { | |
538 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
539 | u32 *tmp; | |
540 | int i; | |
ff954853 | 541 | |
bbfb5652 | 542 | for (tmp = priv->txmapring, i = 0; |
c8d86be3 | 543 | i < priv->txringcount; |
bbfb5652 PS |
544 | tmp += 8, i++) { |
545 | *tmp = *tmp & ~(1<<31); | |
c8d86be3 GKH |
546 | } |
547 | ||
bbfb5652 | 548 | for (tmp = priv->txbkpring, i = 0; |
c8d86be3 | 549 | i < priv->txringcount; |
bbfb5652 PS |
550 | tmp += 8, i++) { |
551 | *tmp = *tmp & ~(1<<31); | |
c8d86be3 GKH |
552 | } |
553 | ||
bbfb5652 | 554 | for (tmp = priv->txbepring, i = 0; |
c8d86be3 | 555 | i < priv->txringcount; |
bbfb5652 PS |
556 | tmp += 8, i++) { |
557 | *tmp = *tmp & ~(1<<31); | |
c8d86be3 | 558 | } |
bbfb5652 | 559 | for (tmp = priv->txvipring, i = 0; |
c8d86be3 | 560 | i < priv->txringcount; |
bbfb5652 PS |
561 | tmp += 8, i++) { |
562 | *tmp = *tmp & ~(1<<31); | |
c8d86be3 GKH |
563 | } |
564 | ||
bbfb5652 | 565 | for (tmp = priv->txvopring, i = 0; |
c8d86be3 | 566 | i < priv->txringcount; |
bbfb5652 PS |
567 | tmp += 8, i++) { |
568 | *tmp = *tmp & ~(1<<31); | |
c8d86be3 GKH |
569 | } |
570 | ||
bbfb5652 | 571 | for (tmp = priv->txhpring, i = 0; |
c8d86be3 | 572 | i < priv->txringcount; |
bbfb5652 PS |
573 | tmp += 8, i++) { |
574 | *tmp = *tmp & ~(1<<31); | |
c8d86be3 GKH |
575 | } |
576 | ||
bbfb5652 | 577 | for (tmp = priv->txbeaconring, i = 0; |
c8d86be3 | 578 | i < priv->txbeaconcount; |
bbfb5652 PS |
579 | tmp += 8, i++) { |
580 | *tmp = *tmp & ~(1<<31); | |
c8d86be3 | 581 | } |
ff954853 | 582 | |
c8d86be3 GKH |
583 | priv->txmapringtail = priv->txmapring; |
584 | priv->txmapringhead = priv->txmapring; | |
585 | priv->txmapbufstail = priv->txmapbufs; | |
586 | ||
587 | priv->txbkpringtail = priv->txbkpring; | |
588 | priv->txbkpringhead = priv->txbkpring; | |
589 | priv->txbkpbufstail = priv->txbkpbufs; | |
590 | ||
591 | priv->txbepringtail = priv->txbepring; | |
592 | priv->txbepringhead = priv->txbepring; | |
593 | priv->txbepbufstail = priv->txbepbufs; | |
594 | ||
595 | priv->txvipringtail = priv->txvipring; | |
596 | priv->txvipringhead = priv->txvipring; | |
597 | priv->txvipbufstail = priv->txvipbufs; | |
598 | ||
599 | priv->txvopringtail = priv->txvopring; | |
600 | priv->txvopringhead = priv->txvopring; | |
601 | priv->txvopbufstail = priv->txvopbufs; | |
602 | ||
603 | priv->txhpringtail = priv->txhpring; | |
604 | priv->txhpringhead = priv->txhpring; | |
605 | priv->txhpbufstail = priv->txhpbufs; | |
606 | ||
607 | priv->txbeaconringtail = priv->txbeaconring; | |
608 | priv->txbeaconbufstail = priv->txbeaconbufs; | |
609 | set_nic_txring(dev); | |
610 | ||
611 | ieee80211_reset_queue(priv->ieee80211); | |
612 | priv->ack_tx_to_ieee = 0; | |
613 | } | |
614 | ||
c8d86be3 GKH |
615 | void fix_rx_fifo(struct net_device *dev) |
616 | { | |
617 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
618 | u32 *tmp; | |
619 | struct buffer *rxbuf; | |
620 | u8 rx_desc_size; | |
621 | ||
3f56c109 | 622 | rx_desc_size = 8; /* 4*8 = 32 bytes */ |
c8d86be3 | 623 | |
bbfb5652 | 624 | for (tmp = priv->rxring, rxbuf = priv->rxbufferhead; |
c8d86be3 | 625 | (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size); |
bbfb5652 | 626 | tmp += rx_desc_size, rxbuf = rxbuf->next) { |
c8d86be3 | 627 | *(tmp+2) = rxbuf->dma; |
bbfb5652 PS |
628 | *tmp = *tmp & ~0xfff; |
629 | *tmp = *tmp | priv->rxbuffersize; | |
c8d86be3 GKH |
630 | *tmp |= (1<<31); |
631 | } | |
632 | ||
bbfb5652 PS |
633 | priv->rxringtail = priv->rxring; |
634 | priv->rxbuffer = priv->rxbufferhead; | |
635 | priv->rx_skb_complete = 1; | |
c8d86be3 GKH |
636 | set_nic_rxring(dev); |
637 | } | |
638 | ||
c8d86be3 | 639 | unsigned char QUALITY_MAP[] = { |
fd882783 BZ |
640 | 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61, |
641 | 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c, | |
642 | 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f, | |
643 | 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29, | |
644 | 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, | |
645 | 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20, | |
646 | 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e, | |
647 | 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19, | |
648 | 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f, | |
649 | 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00 | |
c8d86be3 GKH |
650 | }; |
651 | ||
652 | unsigned char STRENGTH_MAP[] = { | |
fd882783 BZ |
653 | 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e, |
654 | 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50, | |
655 | 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f, | |
656 | 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b, | |
657 | 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17, | |
658 | 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13, | |
659 | 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f, | |
660 | 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b, | |
661 | 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07, | |
662 | 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00 | |
c8d86be3 GKH |
663 | }; |
664 | ||
fd882783 BZ |
665 | void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual) |
666 | { | |
c8d86be3 GKH |
667 | u32 temp; |
668 | u32 temp2; | |
c8d86be3 GKH |
669 | u32 q; |
670 | u32 orig_qual; | |
671 | u8 _rssi; | |
672 | ||
673 | q = *qual; | |
674 | orig_qual = *qual; | |
3f56c109 | 675 | _rssi = 0; /* avoid gcc complains.. */ |
c8d86be3 GKH |
676 | |
677 | if (q <= 0x4e) { | |
678 | temp = QUALITY_MAP[q]; | |
679 | } else { | |
bbfb5652 | 680 | if (q & 0x80) |
c8d86be3 | 681 | temp = 0x32; |
bbfb5652 | 682 | else |
c8d86be3 | 683 | temp = 1; |
c8d86be3 GKH |
684 | } |
685 | ||
686 | *qual = temp; | |
687 | temp2 = *rssi; | |
688 | ||
bbfb5652 PS |
689 | if (_rssi < 0x64) { |
690 | if (_rssi == 0) | |
c8d86be3 | 691 | *rssi = 1; |
c8d86be3 GKH |
692 | } else { |
693 | *rssi = 0x64; | |
694 | } | |
695 | ||
696 | return; | |
697 | } | |
698 | ||
c8d86be3 GKH |
699 | void rtl8180_irq_enable(struct net_device *dev) |
700 | { | |
701 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
fd882783 | 702 | |
c8d86be3 | 703 | priv->irq_enabled = 1; |
bbfb5652 | 704 | write_nic_word(dev, INTA_MASK, priv->irq_mask); |
c8d86be3 GKH |
705 | } |
706 | ||
c8d86be3 GKH |
707 | void rtl8180_irq_disable(struct net_device *dev) |
708 | { | |
709 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
710 | ||
bbfb5652 | 711 | write_nic_dword(dev, IMR, 0); |
c8d86be3 GKH |
712 | force_pci_posting(dev); |
713 | priv->irq_enabled = 0; | |
714 | } | |
715 | ||
bbfb5652 | 716 | void rtl8180_set_mode(struct net_device *dev, int mode) |
c8d86be3 GKH |
717 | { |
718 | u8 ecmd; | |
fd882783 | 719 | |
bbfb5652 PS |
720 | ecmd = read_nic_byte(dev, EPROM_CMD); |
721 | ecmd = ecmd & ~EPROM_CMD_OPERATING_MODE_MASK; | |
722 | ecmd = ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT); | |
723 | ecmd = ecmd & ~(1<<EPROM_CS_SHIFT); | |
724 | ecmd = ecmd & ~(1<<EPROM_CK_SHIFT); | |
c8d86be3 GKH |
725 | write_nic_byte(dev, EPROM_CMD, ecmd); |
726 | } | |
727 | ||
728 | void rtl8180_adapter_start(struct net_device *dev); | |
729 | void rtl8180_beacon_tx_enable(struct net_device *dev); | |
730 | ||
731 | void rtl8180_update_msr(struct net_device *dev) | |
732 | { | |
733 | struct r8180_priv *priv = ieee80211_priv(dev); | |
734 | u8 msr; | |
735 | u32 rxconf; | |
736 | ||
737 | msr = read_nic_byte(dev, MSR); | |
bbfb5652 | 738 | msr &= ~MSR_LINK_MASK; |
c8d86be3 | 739 | |
bbfb5652 | 740 | rxconf = read_nic_dword(dev, RX_CONF); |
c8d86be3 | 741 | |
bbfb5652 PS |
742 | if (priv->ieee80211->state == IEEE80211_LINKED) { |
743 | if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) | |
c8d86be3 GKH |
744 | msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT); |
745 | else if (priv->ieee80211->iw_mode == IW_MODE_MASTER) | |
746 | msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT); | |
747 | else if (priv->ieee80211->iw_mode == IW_MODE_INFRA) | |
748 | msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT); | |
749 | else | |
750 | msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); | |
751 | rxconf |= (1<<RX_CHECK_BSSID_SHIFT); | |
752 | ||
bbfb5652 | 753 | } else { |
c8d86be3 GKH |
754 | msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); |
755 | rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT); | |
756 | } | |
757 | ||
758 | write_nic_byte(dev, MSR, msr); | |
759 | write_nic_dword(dev, RX_CONF, rxconf); | |
c8d86be3 GKH |
760 | } |
761 | ||
bbfb5652 | 762 | void rtl8180_set_chan(struct net_device *dev, short ch) |
c8d86be3 GKH |
763 | { |
764 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
765 | ||
fd882783 | 766 | if ((ch > 14) || (ch < 1)) { |
d599edca | 767 | printk("In %s: Invalid chnanel %d\n", __func__, ch); |
c8d86be3 GKH |
768 | return; |
769 | } | |
770 | ||
bbfb5652 PS |
771 | priv->chan = ch; |
772 | priv->rf_set_chan(dev, priv->chan); | |
c8d86be3 GKH |
773 | } |
774 | ||
c8d86be3 GKH |
775 | void rtl8180_rx_enable(struct net_device *dev) |
776 | { | |
777 | u8 cmd; | |
778 | u32 rxconf; | |
779 | /* for now we accept data, management & ctl frame*/ | |
780 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
781 | ||
bbfb5652 PS |
782 | rxconf = read_nic_dword(dev, RX_CONF); |
783 | rxconf = rxconf & ~MAC_FILTER_MASK; | |
c8d86be3 GKH |
784 | rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT); |
785 | rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT); | |
786 | rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT); | |
787 | rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT); | |
fd882783 BZ |
788 | if (dev->flags & IFF_PROMISC) |
789 | DMESG("NIC in promisc mode"); | |
c8d86be3 | 790 | |
bbfb5652 PS |
791 | if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || \ |
792 | dev->flags & IFF_PROMISC) { | |
c8d86be3 | 793 | rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT); |
bbfb5652 | 794 | } else { |
c8d86be3 | 795 | rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT); |
c8d86be3 GKH |
796 | } |
797 | ||
bbfb5652 | 798 | if (priv->ieee80211->iw_mode == IW_MODE_MONITOR) { |
c8d86be3 GKH |
799 | rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT); |
800 | rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT); | |
801 | rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT); | |
802 | } | |
803 | ||
bbfb5652 | 804 | if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR) |
c8d86be3 GKH |
805 | rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT); |
806 | ||
fd882783 BZ |
807 | rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK; |
808 | rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT); | |
c8d86be3 GKH |
809 | |
810 | rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT); | |
bbfb5652 | 811 | rxconf = rxconf & ~MAX_RX_DMA_MASK; |
c8d86be3 GKH |
812 | rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT); |
813 | ||
fd882783 | 814 | rxconf = rxconf | RCR_ONLYERLPKT; |
c8d86be3 | 815 | |
bbfb5652 | 816 | rxconf = rxconf & ~RCR_CS_MASK; |
fd882783 | 817 | |
c8d86be3 GKH |
818 | write_nic_dword(dev, RX_CONF, rxconf); |
819 | ||
820 | fix_rx_fifo(dev); | |
821 | ||
bbfb5652 PS |
822 | cmd = read_nic_byte(dev, CMD); |
823 | write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT)); | |
c8d86be3 GKH |
824 | } |
825 | ||
c8d86be3 GKH |
826 | void set_nic_txring(struct net_device *dev) |
827 | { | |
828 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 GKH |
829 | |
830 | write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma); | |
c8d86be3 | 831 | write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma); |
c8d86be3 | 832 | write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma); |
c8d86be3 | 833 | write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma); |
c8d86be3 | 834 | write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma); |
c8d86be3 | 835 | write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma); |
c8d86be3 GKH |
836 | write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma); |
837 | } | |
838 | ||
c8d86be3 GKH |
839 | void rtl8180_conttx_enable(struct net_device *dev) |
840 | { | |
841 | u32 txconf; | |
fd882783 | 842 | |
bbfb5652 PS |
843 | txconf = read_nic_dword(dev, TX_CONF); |
844 | txconf = txconf & ~TX_LOOPBACK_MASK; | |
845 | txconf = txconf | (TX_LOOPBACK_CONTINUE<<TX_LOOPBACK_SHIFT); | |
846 | write_nic_dword(dev, TX_CONF, txconf); | |
c8d86be3 GKH |
847 | } |
848 | ||
c8d86be3 GKH |
849 | void rtl8180_conttx_disable(struct net_device *dev) |
850 | { | |
851 | u32 txconf; | |
fd882783 | 852 | |
bbfb5652 PS |
853 | txconf = read_nic_dword(dev, TX_CONF); |
854 | txconf = txconf & ~TX_LOOPBACK_MASK; | |
855 | txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT); | |
856 | write_nic_dword(dev, TX_CONF, txconf); | |
c8d86be3 GKH |
857 | } |
858 | ||
c8d86be3 GKH |
859 | void rtl8180_tx_enable(struct net_device *dev) |
860 | { | |
861 | u8 cmd; | |
862 | u8 tx_agc_ctl; | |
863 | u8 byte; | |
864 | u32 txconf; | |
865 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 | 866 | |
fd882783 | 867 | txconf = read_nic_dword(dev, TX_CONF); |
c8d86be3 | 868 | |
d44eb889 LF |
869 | byte = read_nic_byte(dev, CW_CONF); |
870 | byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT); | |
871 | byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT); | |
872 | write_nic_byte(dev, CW_CONF, byte); | |
c8d86be3 | 873 | |
d44eb889 LF |
874 | tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL); |
875 | tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT); | |
876 | tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT); | |
877 | tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT); | |
878 | write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl); | |
879 | write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */ | |
880 | ||
881 | txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT); | |
c8d86be3 | 882 | |
bbfb5652 PS |
883 | txconf = txconf & ~TX_LOOPBACK_MASK; |
884 | txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT); | |
885 | txconf = txconf & ~TCR_DPRETRY_MASK; | |
886 | txconf = txconf & ~TCR_RTSRETRY_MASK; | |
c8d86be3 GKH |
887 | txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT); |
888 | txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT); | |
bbfb5652 | 889 | txconf = txconf & ~(1<<TX_NOCRC_SHIFT); |
c8d86be3 | 890 | |
d44eb889 LF |
891 | if (priv->hw_plcp_len) |
892 | txconf = txconf & ~TCR_PLCP_LEN; | |
893 | else | |
894 | txconf = txconf | TCR_PLCP_LEN; | |
fd882783 | 895 | |
bbfb5652 | 896 | txconf = txconf & ~TCR_MXDMA_MASK; |
c8d86be3 GKH |
897 | txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT); |
898 | txconf = txconf | TCR_CWMIN; | |
899 | txconf = txconf | TCR_DISCW; | |
900 | ||
fd882783 | 901 | txconf = txconf | (1 << TX_NOICV_SHIFT); |
c8d86be3 | 902 | |
bbfb5652 | 903 | write_nic_dword(dev, TX_CONF, txconf); |
c8d86be3 | 904 | |
c8d86be3 GKH |
905 | fix_tx_fifo(dev); |
906 | ||
bbfb5652 PS |
907 | cmd = read_nic_byte(dev, CMD); |
908 | write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT)); | |
c8d86be3 | 909 | |
bbfb5652 | 910 | write_nic_dword(dev, TX_CONF, txconf); |
c8d86be3 GKH |
911 | } |
912 | ||
c8d86be3 GKH |
913 | void rtl8180_beacon_tx_enable(struct net_device *dev) |
914 | { | |
915 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
916 | ||
bbfb5652 | 917 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
c8d86be3 | 918 | priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ); |
bbfb5652 PS |
919 | write_nic_byte(dev, TPPollStop, priv->dma_poll_mask); |
920 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
c8d86be3 GKH |
921 | } |
922 | ||
c8d86be3 GKH |
923 | void rtl8180_beacon_tx_disable(struct net_device *dev) |
924 | { | |
925 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
926 | ||
bbfb5652 | 927 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
c8d86be3 | 928 | priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ; |
bbfb5652 PS |
929 | write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask); |
930 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
c8d86be3 GKH |
931 | |
932 | } | |
933 | ||
c8d86be3 GKH |
934 | void rtl8180_rtx_disable(struct net_device *dev) |
935 | { | |
936 | u8 cmd; | |
937 | struct r8180_priv *priv = ieee80211_priv(dev); | |
938 | ||
bbfb5652 PS |
939 | cmd = read_nic_byte(dev, CMD); |
940 | write_nic_byte(dev, CMD, cmd & ~\ | |
c8d86be3 GKH |
941 | ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT))); |
942 | force_pci_posting(dev); | |
943 | mdelay(10); | |
c8d86be3 | 944 | |
bbfb5652 | 945 | if (!priv->rx_skb_complete) |
c8d86be3 GKH |
946 | dev_kfree_skb_any(priv->rx_skb); |
947 | } | |
948 | ||
c8d86be3 GKH |
949 | short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count, |
950 | int addr) | |
951 | { | |
952 | int i; | |
953 | u32 *desc; | |
954 | u32 *tmp; | |
955 | dma_addr_t dma_desc, dma_tmp; | |
956 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
957 | struct pci_dev *pdev = priv->pdev; | |
958 | void *buf; | |
959 | ||
bbfb5652 PS |
960 | if ((bufsize & 0xfff) != bufsize) { |
961 | DMESGE("TX buffer allocation too large"); | |
c8d86be3 GKH |
962 | return 0; |
963 | } | |
bbfb5652 | 964 | desc = (u32 *)pci_alloc_consistent(pdev, |
c8d86be3 | 965 | sizeof(u32)*8*count+256, &dma_desc); |
fd882783 BZ |
966 | if (desc == NULL) |
967 | return -1; | |
c8d86be3 | 968 | |
fd882783 | 969 | if (dma_desc & 0xff) |
c8d86be3 GKH |
970 | /* |
971 | * descriptor's buffer must be 256 byte aligned | |
972 | * we shouldn't be here, since we set DMA mask ! | |
973 | */ | |
be286fd2 | 974 | WARN(1, "DMA buffer is not aligned\n"); |
fd882783 BZ |
975 | |
976 | tmp = desc; | |
977 | ||
978 | for (i = 0; i < count; i++) { | |
979 | buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp); | |
980 | if (buf == NULL) | |
981 | return -ENOMEM; | |
c8d86be3 | 982 | |
bbfb5652 | 983 | switch (addr) { |
c8d86be3 | 984 | case TX_MANAGEPRIORITY_RING_ADDR: |
bbfb5652 | 985 | if (-1 == buffer_add(&(priv->txmapbufs), buf, dma_tmp, NULL)) { |
c8d86be3 GKH |
986 | DMESGE("Unable to allocate mem for buffer NP"); |
987 | return -ENOMEM; | |
988 | } | |
989 | break; | |
c8d86be3 | 990 | case TX_BKPRIORITY_RING_ADDR: |
bbfb5652 | 991 | if (-1 == buffer_add(&(priv->txbkpbufs), buf, dma_tmp, NULL)) { |
c8d86be3 GKH |
992 | DMESGE("Unable to allocate mem for buffer LP"); |
993 | return -ENOMEM; | |
994 | } | |
995 | break; | |
996 | case TX_BEPRIORITY_RING_ADDR: | |
bbfb5652 | 997 | if (-1 == buffer_add(&(priv->txbepbufs), buf, dma_tmp, NULL)) { |
c8d86be3 GKH |
998 | DMESGE("Unable to allocate mem for buffer NP"); |
999 | return -ENOMEM; | |
1000 | } | |
1001 | break; | |
c8d86be3 | 1002 | case TX_VIPRIORITY_RING_ADDR: |
bbfb5652 | 1003 | if (-1 == buffer_add(&(priv->txvipbufs), buf, dma_tmp, NULL)) { |
c8d86be3 GKH |
1004 | DMESGE("Unable to allocate mem for buffer LP"); |
1005 | return -ENOMEM; | |
1006 | } | |
1007 | break; | |
1008 | case TX_VOPRIORITY_RING_ADDR: | |
bbfb5652 | 1009 | if (-1 == buffer_add(&(priv->txvopbufs), buf, dma_tmp, NULL)) { |
c8d86be3 GKH |
1010 | DMESGE("Unable to allocate mem for buffer NP"); |
1011 | return -ENOMEM; | |
1012 | } | |
1013 | break; | |
c8d86be3 | 1014 | case TX_HIGHPRIORITY_RING_ADDR: |
bbfb5652 | 1015 | if (-1 == buffer_add(&(priv->txhpbufs), buf, dma_tmp, NULL)) { |
c8d86be3 GKH |
1016 | DMESGE("Unable to allocate mem for buffer HP"); |
1017 | return -ENOMEM; | |
1018 | } | |
1019 | break; | |
1020 | case TX_BEACON_RING_ADDR: | |
bbfb5652 PS |
1021 | if (-1 == buffer_add(&(priv->txbeaconbufs), buf, dma_tmp, NULL)) { |
1022 | DMESGE("Unable to allocate mem for buffer BP"); | |
c8d86be3 GKH |
1023 | return -ENOMEM; |
1024 | } | |
1025 | break; | |
1026 | } | |
3f56c109 | 1027 | *tmp = *tmp & ~(1<<31); /* descriptor empty, owned by the drv */ |
c8d86be3 GKH |
1028 | *(tmp+2) = (u32)dma_tmp; |
1029 | *(tmp+3) = bufsize; | |
1030 | ||
bbfb5652 | 1031 | if (i+1 < count) |
c8d86be3 GKH |
1032 | *(tmp+4) = (u32)dma_desc+((i+1)*8*4); |
1033 | else | |
1034 | *(tmp+4) = (u32)dma_desc; | |
1035 | ||
bbfb5652 | 1036 | tmp = tmp+8; |
c8d86be3 GKH |
1037 | } |
1038 | ||
bbfb5652 | 1039 | switch (addr) { |
c8d86be3 | 1040 | case TX_MANAGEPRIORITY_RING_ADDR: |
bbfb5652 PS |
1041 | priv->txmapringdma = dma_desc; |
1042 | priv->txmapring = desc; | |
c8d86be3 | 1043 | break; |
c8d86be3 | 1044 | case TX_BKPRIORITY_RING_ADDR: |
bbfb5652 PS |
1045 | priv->txbkpringdma = dma_desc; |
1046 | priv->txbkpring = desc; | |
c8d86be3 | 1047 | break; |
c8d86be3 | 1048 | case TX_BEPRIORITY_RING_ADDR: |
bbfb5652 PS |
1049 | priv->txbepringdma = dma_desc; |
1050 | priv->txbepring = desc; | |
c8d86be3 | 1051 | break; |
c8d86be3 | 1052 | case TX_VIPRIORITY_RING_ADDR: |
bbfb5652 PS |
1053 | priv->txvipringdma = dma_desc; |
1054 | priv->txvipring = desc; | |
c8d86be3 | 1055 | break; |
c8d86be3 | 1056 | case TX_VOPRIORITY_RING_ADDR: |
bbfb5652 PS |
1057 | priv->txvopringdma = dma_desc; |
1058 | priv->txvopring = desc; | |
c8d86be3 | 1059 | break; |
c8d86be3 | 1060 | case TX_HIGHPRIORITY_RING_ADDR: |
bbfb5652 PS |
1061 | priv->txhpringdma = dma_desc; |
1062 | priv->txhpring = desc; | |
c8d86be3 | 1063 | break; |
c8d86be3 | 1064 | case TX_BEACON_RING_ADDR: |
bbfb5652 PS |
1065 | priv->txbeaconringdma = dma_desc; |
1066 | priv->txbeaconring = desc; | |
c8d86be3 GKH |
1067 | break; |
1068 | ||
1069 | } | |
1070 | ||
c8d86be3 GKH |
1071 | return 0; |
1072 | } | |
1073 | ||
c8d86be3 GKH |
1074 | void free_tx_desc_rings(struct net_device *dev) |
1075 | { | |
c8d86be3 | 1076 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
bbfb5652 | 1077 | struct pci_dev *pdev = priv->pdev; |
c8d86be3 GKH |
1078 | int count = priv->txringcount; |
1079 | ||
1080 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1081 | priv->txmapring, priv->txmapringdma); | |
bbfb5652 | 1082 | buffer_free(dev, &(priv->txmapbufs), priv->txbuffsize, 1); |
c8d86be3 GKH |
1083 | |
1084 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1085 | priv->txbkpring, priv->txbkpringdma); | |
bbfb5652 | 1086 | buffer_free(dev, &(priv->txbkpbufs), priv->txbuffsize, 1); |
c8d86be3 GKH |
1087 | |
1088 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1089 | priv->txbepring, priv->txbepringdma); | |
bbfb5652 | 1090 | buffer_free(dev, &(priv->txbepbufs), priv->txbuffsize, 1); |
c8d86be3 GKH |
1091 | |
1092 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1093 | priv->txvipring, priv->txvipringdma); | |
bbfb5652 | 1094 | buffer_free(dev, &(priv->txvipbufs), priv->txbuffsize, 1); |
c8d86be3 GKH |
1095 | |
1096 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1097 | priv->txvopring, priv->txvopringdma); | |
bbfb5652 | 1098 | buffer_free(dev, &(priv->txvopbufs), priv->txbuffsize, 1); |
c8d86be3 GKH |
1099 | |
1100 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1101 | priv->txhpring, priv->txhpringdma); | |
bbfb5652 | 1102 | buffer_free(dev, &(priv->txhpbufs), priv->txbuffsize, 1); |
c8d86be3 GKH |
1103 | |
1104 | count = priv->txbeaconcount; | |
1105 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, | |
1106 | priv->txbeaconring, priv->txbeaconringdma); | |
bbfb5652 | 1107 | buffer_free(dev, &(priv->txbeaconbufs), priv->txbuffsize, 1); |
c8d86be3 GKH |
1108 | } |
1109 | ||
c8d86be3 GKH |
1110 | void free_rx_desc_ring(struct net_device *dev) |
1111 | { | |
1112 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1113 | struct pci_dev *pdev = priv->pdev; | |
c8d86be3 GKH |
1114 | int count = priv->rxringcount; |
1115 | ||
c8d86be3 GKH |
1116 | pci_free_consistent(pdev, sizeof(u32)*8*count+256, |
1117 | priv->rxring, priv->rxringdma); | |
c8d86be3 | 1118 | |
bbfb5652 | 1119 | buffer_free(dev, &(priv->rxbuffer), priv->rxbuffersize, 0); |
c8d86be3 GKH |
1120 | } |
1121 | ||
c8d86be3 GKH |
1122 | short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count) |
1123 | { | |
1124 | int i; | |
1125 | u32 *desc; | |
1126 | u32 *tmp; | |
bbfb5652 | 1127 | dma_addr_t dma_desc, dma_tmp; |
c8d86be3 | 1128 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
bbfb5652 | 1129 | struct pci_dev *pdev = priv->pdev; |
c8d86be3 GKH |
1130 | void *buf; |
1131 | u8 rx_desc_size; | |
1132 | ||
3f56c109 | 1133 | rx_desc_size = 8; /* 4*8 = 32 bytes */ |
c8d86be3 | 1134 | |
bbfb5652 PS |
1135 | if ((bufsize & 0xfff) != bufsize) { |
1136 | DMESGE("RX buffer allocation too large"); | |
c8d86be3 GKH |
1137 | return -1; |
1138 | } | |
1139 | ||
bbfb5652 | 1140 | desc = (u32 *)pci_alloc_consistent(pdev, sizeof(u32)*rx_desc_size*count+256, |
c8d86be3 GKH |
1141 | &dma_desc); |
1142 | ||
fd882783 | 1143 | if (dma_desc & 0xff) |
c8d86be3 GKH |
1144 | /* |
1145 | * descriptor's buffer must be 256 byte aligned | |
1146 | * should never happen since we specify the DMA mask | |
1147 | */ | |
be286fd2 | 1148 | WARN(1, "DMA buffer is not aligned\n"); |
c8d86be3 | 1149 | |
bbfb5652 PS |
1150 | priv->rxring = desc; |
1151 | priv->rxringdma = dma_desc; | |
1152 | tmp = desc; | |
c8d86be3 | 1153 | |
fd882783 | 1154 | for (i = 0; i < count; i++) { |
bbfb5652 | 1155 | buf = kmalloc(bufsize * sizeof(u8), GFP_ATOMIC); |
53756de3 | 1156 | if (buf == NULL) { |
c8d86be3 GKH |
1157 | DMESGE("Failed to kmalloc RX buffer"); |
1158 | return -1; | |
1159 | } | |
1160 | ||
bbfb5652 | 1161 | dma_tmp = pci_map_single(pdev, buf, bufsize * sizeof(u8), |
c8d86be3 GKH |
1162 | PCI_DMA_FROMDEVICE); |
1163 | ||
bbfb5652 PS |
1164 | if (-1 == buffer_add(&(priv->rxbuffer), buf, dma_tmp, |
1165 | &(priv->rxbufferhead))) { | |
1166 | DMESGE("Unable to allocate mem RX buf"); | |
1167 | return -1; | |
c8d86be3 | 1168 | } |
3f56c109 | 1169 | *tmp = 0; /* zero pads the header of the descriptor */ |
bbfb5652 | 1170 | *tmp = *tmp | (bufsize&0xfff); |
c8d86be3 | 1171 | *(tmp+2) = (u32)dma_tmp; |
3f56c109 | 1172 | *tmp = *tmp | (1<<31); /* descriptor void, owned by the NIC */ |
c8d86be3 | 1173 | |
bbfb5652 | 1174 | tmp = tmp+rx_desc_size; |
c8d86be3 GKH |
1175 | } |
1176 | ||
3f56c109 | 1177 | *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); /* this is the last descriptor */ |
c8d86be3 | 1178 | |
c8d86be3 GKH |
1179 | return 0; |
1180 | } | |
1181 | ||
1182 | ||
1183 | void set_nic_rxring(struct net_device *dev) | |
1184 | { | |
1185 | u8 pgreg; | |
1186 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1187 | ||
bbfb5652 PS |
1188 | pgreg = read_nic_byte(dev, PGSELECT); |
1189 | write_nic_byte(dev, PGSELECT, pgreg & ~(1<<PGSELECT_PG_SHIFT)); | |
c8d86be3 | 1190 | |
bbfb5652 | 1191 | write_nic_dword(dev, RXRING_ADDR, priv->rxringdma); |
c8d86be3 GKH |
1192 | } |
1193 | ||
c8d86be3 GKH |
1194 | void rtl8180_reset(struct net_device *dev) |
1195 | { | |
c8d86be3 GKH |
1196 | u8 cr; |
1197 | ||
c8d86be3 GKH |
1198 | rtl8180_irq_disable(dev); |
1199 | ||
bbfb5652 | 1200 | cr = read_nic_byte(dev, CMD); |
c8d86be3 GKH |
1201 | cr = cr & 2; |
1202 | cr = cr | (1<<CMD_RST_SHIFT); | |
bbfb5652 | 1203 | write_nic_byte(dev, CMD, cr); |
c8d86be3 GKH |
1204 | |
1205 | force_pci_posting(dev); | |
1206 | ||
1207 | mdelay(200); | |
1208 | ||
bbfb5652 | 1209 | if (read_nic_byte(dev, CMD) & (1<<CMD_RST_SHIFT)) |
c8d86be3 GKH |
1210 | DMESGW("Card reset timeout!"); |
1211 | else | |
1212 | DMESG("Card successfully reset"); | |
1213 | ||
bbfb5652 | 1214 | rtl8180_set_mode(dev, EPROM_CMD_LOAD); |
c8d86be3 GKH |
1215 | force_pci_posting(dev); |
1216 | mdelay(200); | |
c8d86be3 GKH |
1217 | } |
1218 | ||
1219 | inline u16 ieeerate2rtlrate(int rate) | |
1220 | { | |
bbfb5652 | 1221 | switch (rate) { |
c8d86be3 | 1222 | case 10: |
fd882783 | 1223 | return 0; |
c8d86be3 | 1224 | case 20: |
fd882783 | 1225 | return 1; |
c8d86be3 | 1226 | case 55: |
fd882783 | 1227 | return 2; |
c8d86be3 | 1228 | case 110: |
fd882783 | 1229 | return 3; |
c8d86be3 | 1230 | case 60: |
fd882783 | 1231 | return 4; |
c8d86be3 | 1232 | case 90: |
fd882783 | 1233 | return 5; |
c8d86be3 | 1234 | case 120: |
fd882783 | 1235 | return 6; |
c8d86be3 | 1236 | case 180: |
fd882783 | 1237 | return 7; |
c8d86be3 | 1238 | case 240: |
fd882783 | 1239 | return 8; |
c8d86be3 | 1240 | case 360: |
fd882783 | 1241 | return 9; |
c8d86be3 | 1242 | case 480: |
fd882783 | 1243 | return 10; |
c8d86be3 | 1244 | case 540: |
fd882783 | 1245 | return 11; |
c8d86be3 | 1246 | default: |
fd882783 | 1247 | return 3; |
c8d86be3 GKH |
1248 | } |
1249 | } | |
1250 | ||
bbfb5652 | 1251 | static u16 rtl_rate[] = {10, 20, 55, 110, 60, 90, 120, 180, 240, 360, 480, 540, 720}; |
fd882783 | 1252 | |
c8d86be3 GKH |
1253 | inline u16 rtl8180_rate2rate(short rate) |
1254 | { | |
fd882783 BZ |
1255 | if (rate > 12) |
1256 | return 10; | |
c8d86be3 GKH |
1257 | return rtl_rate[rate]; |
1258 | } | |
fd882783 | 1259 | |
c8d86be3 GKH |
1260 | inline u8 rtl8180_IsWirelessBMode(u16 rate) |
1261 | { | |
bbfb5652 | 1262 | if (((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220)) |
c8d86be3 | 1263 | return 1; |
fd882783 BZ |
1264 | else |
1265 | return 0; | |
c8d86be3 | 1266 | } |
fd882783 | 1267 | |
c8d86be3 | 1268 | u16 N_DBPSOfRate(u16 DataRate); |
fd882783 BZ |
1269 | |
1270 | u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame, | |
1271 | u8 bShortPreamble) | |
c8d86be3 GKH |
1272 | { |
1273 | u16 FrameTime; | |
1274 | u16 N_DBPS; | |
1275 | u16 Ceiling; | |
1276 | ||
fd882783 BZ |
1277 | if (rtl8180_IsWirelessBMode(DataRate)) { |
1278 | if (bManagementFrame || !bShortPreamble || DataRate == 10) | |
1279 | /* long preamble */ | |
c8d86be3 | 1280 | FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10))); |
c8d86be3 | 1281 | else |
fd882783 | 1282 | /* short preamble */ |
c8d86be3 | 1283 | FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10))); |
fd882783 BZ |
1284 | |
1285 | if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */ | |
1286 | FrameTime++; | |
1287 | } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */ | |
c8d86be3 GKH |
1288 | N_DBPS = N_DBPSOfRate(DataRate); |
1289 | Ceiling = (16 + 8*FrameLength + 6) / N_DBPS | |
1290 | + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0); | |
1291 | FrameTime = (u16)(16 + 4 + 4*Ceiling + 6); | |
1292 | } | |
1293 | return FrameTime; | |
1294 | } | |
fd882783 | 1295 | |
c8d86be3 GKH |
1296 | u16 N_DBPSOfRate(u16 DataRate) |
1297 | { | |
1298 | u16 N_DBPS = 24; | |
1299 | ||
fd882783 BZ |
1300 | switch (DataRate) { |
1301 | case 60: | |
1302 | N_DBPS = 24; | |
1303 | break; | |
1304 | case 90: | |
1305 | N_DBPS = 36; | |
1306 | break; | |
1307 | case 120: | |
1308 | N_DBPS = 48; | |
1309 | break; | |
1310 | case 180: | |
1311 | N_DBPS = 72; | |
1312 | break; | |
1313 | case 240: | |
1314 | N_DBPS = 96; | |
1315 | break; | |
1316 | case 360: | |
1317 | N_DBPS = 144; | |
1318 | break; | |
1319 | case 480: | |
1320 | N_DBPS = 192; | |
1321 | break; | |
1322 | case 540: | |
1323 | N_DBPS = 216; | |
1324 | break; | |
1325 | default: | |
1326 | break; | |
1327 | } | |
c8d86be3 | 1328 | |
fd882783 | 1329 | return N_DBPS; |
c8d86be3 GKH |
1330 | } |
1331 | ||
3f56c109 PS |
1332 | /* |
1333 | * For Netgear case, they want good-looking singal strength. | |
1334 | */ | |
fd882783 | 1335 | long NetgearSignalStrengthTranslate(long LastSS, long CurrSS) |
c8d86be3 GKH |
1336 | { |
1337 | long RetSS; | |
1338 | ||
3f56c109 | 1339 | /* Step 1. Scale mapping. */ |
fd882783 | 1340 | if (CurrSS >= 71 && CurrSS <= 100) |
c8d86be3 | 1341 | RetSS = 90 + ((CurrSS - 70) / 3); |
fd882783 | 1342 | else if (CurrSS >= 41 && CurrSS <= 70) |
c8d86be3 | 1343 | RetSS = 78 + ((CurrSS - 40) / 3); |
fd882783 | 1344 | else if (CurrSS >= 31 && CurrSS <= 40) |
c8d86be3 | 1345 | RetSS = 66 + (CurrSS - 30); |
fd882783 | 1346 | else if (CurrSS >= 21 && CurrSS <= 30) |
c8d86be3 | 1347 | RetSS = 54 + (CurrSS - 20); |
fd882783 | 1348 | else if (CurrSS >= 5 && CurrSS <= 20) |
c8d86be3 | 1349 | RetSS = 42 + (((CurrSS - 5) * 2) / 3); |
fd882783 | 1350 | else if (CurrSS == 4) |
c8d86be3 | 1351 | RetSS = 36; |
fd882783 | 1352 | else if (CurrSS == 3) |
c8d86be3 | 1353 | RetSS = 27; |
fd882783 | 1354 | else if (CurrSS == 2) |
c8d86be3 | 1355 | RetSS = 18; |
fd882783 | 1356 | else if (CurrSS == 1) |
c8d86be3 | 1357 | RetSS = 9; |
c8d86be3 | 1358 | else |
c8d86be3 | 1359 | RetSS = CurrSS; |
c8d86be3 | 1360 | |
3f56c109 | 1361 | /* Step 2. Smoothing. */ |
bbfb5652 PS |
1362 | if (LastSS > 0) |
1363 | RetSS = ((LastSS * 5) + (RetSS) + 5) / 6; | |
c8d86be3 GKH |
1364 | |
1365 | return RetSS; | |
1366 | } | |
fd882783 | 1367 | |
3f56c109 PS |
1368 | /* |
1369 | * Translate 0-100 signal strength index into dBm. | |
1370 | */ | |
fd882783 | 1371 | long TranslateToDbm8185(u8 SignalStrengthIndex) |
c8d86be3 | 1372 | { |
fd882783 | 1373 | long SignalPower; |
c8d86be3 | 1374 | |
3f56c109 | 1375 | /* Translate to dBm (x=0.5y-95). */ |
c8d86be3 GKH |
1376 | SignalPower = (long)((SignalStrengthIndex + 1) >> 1); |
1377 | SignalPower -= 95; | |
1378 | ||
1379 | return SignalPower; | |
1380 | } | |
fd882783 | 1381 | |
3f56c109 PS |
1382 | /* |
1383 | * Perform signal smoothing for dynamic mechanism. | |
1384 | * This is different with PerformSignalSmoothing8185 in smoothing fomula. | |
1385 | * No dramatic adjustion is apply because dynamic mechanism need some degree | |
1386 | * of correctness. Ported from 8187B. | |
1387 | */ | |
fd882783 BZ |
1388 | void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv, |
1389 | bool bCckRate) | |
c8d86be3 | 1390 | { |
3f56c109 | 1391 | /* Determin the current packet is CCK rate. */ |
c8d86be3 GKH |
1392 | priv->bCurCCKPkt = bCckRate; |
1393 | ||
fd882783 | 1394 | if (priv->UndecoratedSmoothedSS >= 0) |
bbfb5652 | 1395 | priv->UndecoratedSmoothedSS = ((priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10)) / 6; |
c8d86be3 | 1396 | else |
c8d86be3 | 1397 | priv->UndecoratedSmoothedSS = priv->SignalStrength * 10; |
c8d86be3 | 1398 | |
bbfb5652 | 1399 | priv->UndercorateSmoothedRxPower = ((priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower * 11)) / 60; |
c8d86be3 | 1400 | |
fd882783 | 1401 | if (bCckRate) |
c8d86be3 | 1402 | priv->CurCCKRSSI = priv->RSSI; |
c8d86be3 | 1403 | else |
c8d86be3 | 1404 | priv->CurCCKRSSI = 0; |
c8d86be3 GKH |
1405 | } |
1406 | ||
c8d86be3 | 1407 | |
3f56c109 PS |
1408 | /* |
1409 | * This is rough RX isr handling routine | |
1410 | */ | |
c8d86be3 GKH |
1411 | void rtl8180_rx(struct net_device *dev) |
1412 | { | |
1413 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1414 | struct sk_buff *tmp_skb; | |
bbfb5652 | 1415 | short first, last; |
c8d86be3 GKH |
1416 | u32 len; |
1417 | int lastlen; | |
1418 | unsigned char quality, signal; | |
1419 | u8 rate; | |
bbfb5652 | 1420 | u32 *tmp, *tmp2; |
c8d86be3 GKH |
1421 | u8 rx_desc_size; |
1422 | u8 padding; | |
c8d86be3 GKH |
1423 | char rxpower = 0; |
1424 | u32 RXAGC = 0; | |
1425 | long RxAGC_dBm = 0; | |
bbfb5652 | 1426 | u8 LNA = 0, BB = 0; |
cb73da25 | 1427 | u8 LNA_gain[4] = {02, 17, 29, 39}; |
c8d86be3 | 1428 | u8 Antenna = 0; |
0604384d | 1429 | struct ieee80211_hdr_4addr *hdr; |
bbfb5652 PS |
1430 | u16 fc, type; |
1431 | u8 bHwError = 0, bCRC = 0, bICV = 0; | |
c8d86be3 GKH |
1432 | bool bCckRate = false; |
1433 | u8 RSSI = 0; | |
fd882783 | 1434 | long SignalStrengthIndex = 0; |
c8d86be3 GKH |
1435 | struct ieee80211_rx_stats stats = { |
1436 | .signal = 0, | |
1437 | .noise = -98, | |
1438 | .rate = 0, | |
c8d86be3 GKH |
1439 | .freq = IEEE80211_24GHZ_BAND, |
1440 | }; | |
1441 | ||
c8d86be3 GKH |
1442 | stats.nic_type = NIC_8185B; |
1443 | rx_desc_size = 8; | |
1444 | ||
c8d86be3 | 1445 | if ((*(priv->rxringtail)) & (1<<31)) { |
c8d86be3 | 1446 | /* we have got an RX int, but the descriptor |
3f56c109 | 1447 | * we are pointing is empty */ |
c8d86be3 GKH |
1448 | |
1449 | priv->stats.rxnodata++; | |
1450 | priv->ieee80211->stats.rx_errors++; | |
1451 | ||
c8d86be3 GKH |
1452 | tmp2 = NULL; |
1453 | tmp = priv->rxringtail; | |
bbfb5652 PS |
1454 | do { |
1455 | if (tmp == priv->rxring) | |
c8d86be3 GKH |
1456 | tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size; |
1457 | else | |
1458 | tmp -= rx_desc_size; | |
1459 | ||
bbfb5652 | 1460 | if (!(*tmp & (1<<31))) |
c8d86be3 | 1461 | tmp2 = tmp; |
bbfb5652 | 1462 | } while (tmp != priv->rxring); |
c8d86be3 | 1463 | |
bbfb5652 PS |
1464 | if (tmp2) |
1465 | priv->rxringtail = tmp2; | |
c8d86be3 GKH |
1466 | } |
1467 | ||
1468 | /* while there are filled descriptors */ | |
bbfb5652 PS |
1469 | while (!(*(priv->rxringtail) & (1<<31))) { |
1470 | if (*(priv->rxringtail) & (1<<26)) | |
c8d86be3 | 1471 | DMESGW("RX buffer overflow"); |
bbfb5652 | 1472 | if (*(priv->rxringtail) & (1<<12)) |
c8d86be3 GKH |
1473 | priv->stats.rxicverr++; |
1474 | ||
bbfb5652 | 1475 | if (*(priv->rxringtail) & (1<<27)) { |
c8d86be3 | 1476 | priv->stats.rxdmafail++; |
3f56c109 | 1477 | /* DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail); */ |
c8d86be3 GKH |
1478 | goto drop; |
1479 | } | |
1480 | ||
1481 | pci_dma_sync_single_for_cpu(priv->pdev, | |
1482 | priv->rxbuffer->dma, | |
1483 | priv->rxbuffersize * \ | |
1484 | sizeof(u8), | |
1485 | PCI_DMA_FROMDEVICE); | |
1486 | ||
bbfb5652 PS |
1487 | first = *(priv->rxringtail) & (1<<29) ? 1 : 0; |
1488 | if (first) | |
1489 | priv->rx_prevlen = 0; | |
c8d86be3 | 1490 | |
bbfb5652 PS |
1491 | last = *(priv->rxringtail) & (1<<28) ? 1 : 0; |
1492 | if (last) { | |
1493 | lastlen = ((*priv->rxringtail) & 0xfff); | |
c8d86be3 GKH |
1494 | |
1495 | /* if the last descriptor (that should | |
1496 | * tell us the total packet len) tell | |
1497 | * us something less than the descriptors | |
1498 | * len we had until now, then there is some | |
1499 | * problem.. | |
1500 | * workaround to prevent kernel panic | |
1501 | */ | |
bbfb5652 PS |
1502 | if (lastlen < priv->rx_prevlen) |
1503 | len = 0; | |
c8d86be3 | 1504 | else |
bbfb5652 | 1505 | len = lastlen-priv->rx_prevlen; |
c8d86be3 | 1506 | |
bbfb5652 PS |
1507 | if (*(priv->rxringtail) & (1<<13)) { |
1508 | if ((*(priv->rxringtail) & 0xfff) < 500) | |
c8d86be3 | 1509 | priv->stats.rxcrcerrmin++; |
bbfb5652 | 1510 | else if ((*(priv->rxringtail) & 0x0fff) > 1000) |
c8d86be3 GKH |
1511 | priv->stats.rxcrcerrmax++; |
1512 | else | |
1513 | priv->stats.rxcrcerrmid++; | |
1514 | ||
1515 | } | |
1516 | ||
bbfb5652 | 1517 | } else { |
c8d86be3 GKH |
1518 | len = priv->rxbuffersize; |
1519 | } | |
1520 | ||
bbfb5652 | 1521 | if (first && last) { |
c8d86be3 | 1522 | padding = ((*(priv->rxringtail+3))&(0x04000000))>>26; |
bbfb5652 | 1523 | } else if (first) { |
c8d86be3 | 1524 | padding = ((*(priv->rxringtail+3))&(0x04000000))>>26; |
bbfb5652 | 1525 | if (padding) |
c8d86be3 | 1526 | len -= 2; |
bbfb5652 | 1527 | } else { |
c8d86be3 GKH |
1528 | padding = 0; |
1529 | } | |
cb73da25 | 1530 | padding = 0; |
bbfb5652 | 1531 | priv->rx_prevlen += len; |
c8d86be3 | 1532 | |
bbfb5652 | 1533 | if (priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100) { |
c8d86be3 GKH |
1534 | /* HW is probably passing several buggy frames |
1535 | * without FD or LD flag set. | |
1536 | * Throw this garbage away to prevent skb | |
1537 | * memory exausting | |
1538 | */ | |
bbfb5652 | 1539 | if (!priv->rx_skb_complete) |
c8d86be3 GKH |
1540 | dev_kfree_skb_any(priv->rx_skb); |
1541 | priv->rx_skb_complete = 1; | |
1542 | } | |
1543 | ||
bbfb5652 | 1544 | signal = (unsigned char)(((*(priv->rxringtail+3)) & (0x00ff0000))>>16); |
1994130e | 1545 | signal = (signal & 0xfe) >> 1; |
c8d86be3 | 1546 | |
bbfb5652 | 1547 | quality = (unsigned char)((*(priv->rxringtail+3)) & (0xff)); |
c8d86be3 GKH |
1548 | |
1549 | stats.mac_time[0] = *(priv->rxringtail+1); | |
1550 | stats.mac_time[1] = *(priv->rxringtail+2); | |
bbfb5652 PS |
1551 | rxpower = ((char)(((*(priv->rxringtail+4)) & (0x00ff0000))>>16))/2 - 42; |
1552 | RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>>8)) & (0x7f); | |
c8d86be3 | 1553 | |
bbfb5652 | 1554 | rate = ((*(priv->rxringtail)) & |
c8d86be3 GKH |
1555 | ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20; |
1556 | ||
1557 | stats.rate = rtl8180_rate2rate(rate); | |
bbfb5652 | 1558 | Antenna = (((*(priv->rxringtail+3)) & (0x00008000)) == 0) ? 0 : 1; |
3f56c109 PS |
1559 | if (!rtl8180_IsWirelessBMode(stats.rate)) { /* OFDM rate. */ |
1560 | RxAGC_dBm = rxpower+1; /* bias */ | |
1561 | } else { /* CCK rate. */ | |
1562 | RxAGC_dBm = signal; /* bit 0 discard */ | |
c8d86be3 | 1563 | |
3f56c109 PS |
1564 | LNA = (u8) (RxAGC_dBm & 0x60) >> 5; /* bit 6~ bit 5 */ |
1565 | BB = (u8) (RxAGC_dBm & 0x1F); /* bit 4 ~ bit 0 */ | |
c8d86be3 | 1566 | |
3f56c109 | 1567 | RxAGC_dBm = -(LNA_gain[LNA] + (BB*2)); /* Pin_11b=-(LNA_gain+BB_gain) (dBm) */ |
c8d86be3 | 1568 | |
3f56c109 | 1569 | RxAGC_dBm += 4; /* bias */ |
c8d86be3 GKH |
1570 | } |
1571 | ||
3f56c109 | 1572 | if (RxAGC_dBm & 0x80) /* absolute value */ |
bbfb5652 | 1573 | RXAGC = ~(RxAGC_dBm)+1; |
c8d86be3 | 1574 | bCckRate = rtl8180_IsWirelessBMode(stats.rate); |
3f56c109 PS |
1575 | /* Translate RXAGC into 1-100. */ |
1576 | if (!rtl8180_IsWirelessBMode(stats.rate)) { /* OFDM rate. */ | |
bbfb5652 PS |
1577 | if (RXAGC > 90) |
1578 | RXAGC = 90; | |
1579 | else if (RXAGC < 25) | |
1580 | RXAGC = 25; | |
1581 | RXAGC = (90-RXAGC)*100/65; | |
3f56c109 | 1582 | } else { /* CCK rate. */ |
bbfb5652 PS |
1583 | if (RXAGC > 95) |
1584 | RXAGC = 95; | |
1585 | else if (RXAGC < 30) | |
1586 | RXAGC = 30; | |
1587 | RXAGC = (95-RXAGC)*100/65; | |
c8d86be3 GKH |
1588 | } |
1589 | priv->SignalStrength = (u8)RXAGC; | |
1994130e | 1590 | priv->RecvSignalPower = RxAGC_dBm; |
c8d86be3 GKH |
1591 | priv->RxPower = rxpower; |
1592 | priv->RSSI = RSSI; | |
1994130e | 1593 | /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */ |
bbfb5652 | 1594 | if (quality >= 127) |
25985edc | 1595 | quality = 1; /*0; */ /* 0 will cause epc to show signal zero , walk around now; */ |
bbfb5652 | 1596 | else if (quality < 27) |
c8d86be3 GKH |
1597 | quality = 100; |
1598 | else | |
1599 | quality = 127 - quality; | |
1600 | priv->SignalQuality = quality; | |
c8d86be3 | 1601 | |
3f56c109 | 1602 | stats.signal = (u8)quality; /*priv->wstats.qual.level = priv->SignalStrength; */ |
c8d86be3 | 1603 | stats.signalstrength = RXAGC; |
bbfb5652 | 1604 | if (stats.signalstrength > 100) |
c8d86be3 GKH |
1605 | stats.signalstrength = 100; |
1606 | stats.signalstrength = (stats.signalstrength * 70)/100 + 30; | |
3f56c109 | 1607 | /* printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength); */ |
c8d86be3 | 1608 | stats.rssi = priv->wstats.qual.qual = priv->SignalQuality; |
bbfb5652 PS |
1609 | stats.noise = priv->wstats.qual.noise = 100 - priv->wstats.qual.qual; |
1610 | bHwError = (((*(priv->rxringtail)) & (0x00000fff)) == 4080) | (((*(priv->rxringtail)) & (0x04000000)) != 0) | |
1611 | | (((*(priv->rxringtail)) & (0x08000000)) != 0) | (((~(*(priv->rxringtail))) & (0x10000000)) != 0) | (((~(*(priv->rxringtail))) & (0x20000000)) != 0); | |
c8d86be3 GKH |
1612 | bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13; |
1613 | bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12; | |
0604384d | 1614 | hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf; |
c8d86be3 | 1615 | fc = le16_to_cpu(hdr->frame_ctl); |
cb73da25 | 1616 | type = WLAN_FC_GET_TYPE(fc); |
c8d86be3 | 1617 | |
bbfb5652 PS |
1618 | if ((IEEE80211_FTYPE_CTL != type) && |
1619 | (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : hdr->addr3)) | |
1620 | && (!bHwError) && (!bCRC) && (!bICV)) { | |
1994130e LF |
1621 | /* Perform signal smoothing for dynamic |
1622 | * mechanism on demand. This is different | |
1623 | * with PerformSignalSmoothing8185 in smoothing | |
1624 | * fomula. No dramatic adjustion is apply | |
1625 | * because dynamic mechanism need some degree | |
1626 | * of correctness. */ | |
bbfb5652 | 1627 | PerformUndecoratedSignalSmoothing8185(priv, bCckRate); |
3f56c109 PS |
1628 | |
1629 | /* For good-looking singal strength. */ | |
c8d86be3 GKH |
1630 | SignalStrengthIndex = NetgearSignalStrengthTranslate( |
1631 | priv->LastSignalStrengthInPercent, | |
1632 | priv->SignalStrength); | |
1633 | ||
1634 | priv->LastSignalStrengthInPercent = SignalStrengthIndex; | |
1635 | priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex); | |
3f56c109 PS |
1636 | /* |
1637 | * We need more correct power of received packets and the "SignalStrength" of RxStats is beautified, | |
1638 | * so we record the correct power here. | |
1639 | */ | |
bbfb5652 PS |
1640 | priv->Stats_SignalQuality = (long)(priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6; |
1641 | priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower - 1) / 6; | |
c8d86be3 | 1642 | |
3f56c109 PS |
1643 | /* Figure out which antenna that received the lasted packet. */ |
1644 | priv->LastRxPktAntenna = Antenna ? 1 : 0; /* 0: aux, 1: main. */ | |
bbfb5652 | 1645 | SwAntennaDiversityRxOk8185(dev, priv->SignalStrength); |
c8d86be3 GKH |
1646 | } |
1647 | ||
bbfb5652 PS |
1648 | if (first) { |
1649 | if (!priv->rx_skb_complete) { | |
c8d86be3 GKH |
1650 | /* seems that HW sometimes fails to reiceve and |
1651 | doesn't provide the last descriptor */ | |
c8d86be3 GKH |
1652 | dev_kfree_skb_any(priv->rx_skb); |
1653 | priv->stats.rxnolast++; | |
c8d86be3 GKH |
1654 | } |
1655 | /* support for prism header has been originally added by Christian */ | |
bbfb5652 PS |
1656 | if (priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR) { |
1657 | ||
1658 | } else { | |
c8d86be3 | 1659 | priv->rx_skb = dev_alloc_skb(len+2); |
bbfb5652 PS |
1660 | if (!priv->rx_skb) |
1661 | goto drop; | |
c8d86be3 GKH |
1662 | } |
1663 | ||
bbfb5652 PS |
1664 | priv->rx_skb_complete = 0; |
1665 | priv->rx_skb->dev = dev; | |
1666 | } else { | |
c8d86be3 GKH |
1667 | /* if we are here we should have already RXed |
1668 | * the first frame. | |
1669 | * If we get here and the skb is not allocated then | |
1670 | * we have just throw out garbage (skb not allocated) | |
1671 | * and we are still rxing garbage.... | |
1672 | */ | |
bbfb5652 | 1673 | if (!priv->rx_skb_complete) { |
c8d86be3 | 1674 | |
bbfb5652 | 1675 | tmp_skb = dev_alloc_skb(priv->rx_skb->len+len+2); |
c8d86be3 | 1676 | |
bbfb5652 PS |
1677 | if (!tmp_skb) |
1678 | goto drop; | |
c8d86be3 | 1679 | |
bbfb5652 | 1680 | tmp_skb->dev = dev; |
c8d86be3 | 1681 | |
bbfb5652 | 1682 | memcpy(skb_put(tmp_skb, priv->rx_skb->len), |
c8d86be3 GKH |
1683 | priv->rx_skb->data, |
1684 | priv->rx_skb->len); | |
c8d86be3 GKH |
1685 | |
1686 | dev_kfree_skb_any(priv->rx_skb); | |
c8d86be3 | 1687 | |
bbfb5652 | 1688 | priv->rx_skb = tmp_skb; |
c8d86be3 GKH |
1689 | } |
1690 | } | |
ff954853 | 1691 | |
bbfb5652 PS |
1692 | if (!priv->rx_skb_complete) { |
1693 | if (padding) { | |
1694 | memcpy(skb_put(priv->rx_skb, len), | |
1695 | (((unsigned char *)priv->rxbuffer->buf) + 2), len); | |
c8d86be3 | 1696 | } else { |
bbfb5652 PS |
1697 | memcpy(skb_put(priv->rx_skb, len), |
1698 | priv->rxbuffer->buf, len); | |
c8d86be3 | 1699 | } |
c8d86be3 | 1700 | } |
c8d86be3 | 1701 | |
bbfb5652 PS |
1702 | if (last && !priv->rx_skb_complete) { |
1703 | if (priv->rx_skb->len > 4) | |
1704 | skb_trim(priv->rx_skb, priv->rx_skb->len-4); | |
1705 | if (!ieee80211_rtl_rx(priv->ieee80211, | |
1994130e | 1706 | priv->rx_skb, &stats)) |
c8d86be3 | 1707 | dev_kfree_skb_any(priv->rx_skb); |
bbfb5652 | 1708 | priv->rx_skb_complete = 1; |
c8d86be3 GKH |
1709 | } |
1710 | ||
c8d86be3 GKH |
1711 | pci_dma_sync_single_for_device(priv->pdev, |
1712 | priv->rxbuffer->dma, | |
1713 | priv->rxbuffersize * \ | |
1714 | sizeof(u8), | |
1715 | PCI_DMA_FROMDEVICE); | |
1716 | ||
3f56c109 | 1717 | drop: /* this is used when we have not enough mem */ |
c8d86be3 | 1718 | /* restore the descriptor */ |
bbfb5652 PS |
1719 | *(priv->rxringtail+2) = priv->rxbuffer->dma; |
1720 | *(priv->rxringtail) = *(priv->rxringtail) & ~0xfff; | |
1721 | *(priv->rxringtail) = | |
c8d86be3 GKH |
1722 | *(priv->rxringtail) | priv->rxbuffersize; |
1723 | ||
bbfb5652 | 1724 | *(priv->rxringtail) = |
c8d86be3 | 1725 | *(priv->rxringtail) | (1<<31); |
c8d86be3 | 1726 | |
bbfb5652 PS |
1727 | priv->rxringtail += rx_desc_size; |
1728 | if (priv->rxringtail >= | |
1729 | (priv->rxring)+(priv->rxringcount)*rx_desc_size) | |
1730 | priv->rxringtail = priv->rxring; | |
c8d86be3 | 1731 | |
bbfb5652 | 1732 | priv->rxbuffer = (priv->rxbuffer->next); |
c8d86be3 | 1733 | } |
c8d86be3 GKH |
1734 | } |
1735 | ||
1736 | ||
1737 | void rtl8180_dma_kick(struct net_device *dev, int priority) | |
1738 | { | |
1739 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1740 | ||
bbfb5652 | 1741 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
c8d86be3 GKH |
1742 | write_nic_byte(dev, TX_DMA_POLLING, |
1743 | (1 << (priority + 1)) | priv->dma_poll_mask); | |
bbfb5652 | 1744 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); |
c8d86be3 GKH |
1745 | |
1746 | force_pci_posting(dev); | |
1747 | } | |
1748 | ||
c8d86be3 GKH |
1749 | void rtl8180_data_hard_stop(struct net_device *dev) |
1750 | { | |
1751 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1752 | ||
bbfb5652 | 1753 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
c8d86be3 | 1754 | priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ; |
bbfb5652 PS |
1755 | write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask); |
1756 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
c8d86be3 GKH |
1757 | } |
1758 | ||
c8d86be3 GKH |
1759 | void rtl8180_data_hard_resume(struct net_device *dev) |
1760 | { | |
1761 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
1762 | ||
bbfb5652 | 1763 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
c8d86be3 | 1764 | priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ); |
bbfb5652 PS |
1765 | write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask); |
1766 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
c8d86be3 GKH |
1767 | } |
1768 | ||
3f56c109 PS |
1769 | /* |
1770 | * This function TX data frames when the ieee80211 stack requires this. | |
c8d86be3 GKH |
1771 | * It checks also if we need to stop the ieee tx queue, eventually do it |
1772 | */ | |
bbfb5652 PS |
1773 | void rtl8180_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int |
1774 | rate) { | |
c8d86be3 GKH |
1775 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
1776 | int mode; | |
bbfb5652 | 1777 | struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data; |
b6b1ac69 | 1778 | short morefrag = (h->frame_control) & IEEE80211_FCTL_MOREFRAGS; |
c8d86be3 GKH |
1779 | unsigned long flags; |
1780 | int priority; | |
c8d86be3 GKH |
1781 | |
1782 | mode = priv->ieee80211->iw_mode; | |
1783 | ||
1784 | rate = ieeerate2rtlrate(rate); | |
1785 | /* | |
3f56c109 PS |
1786 | * This function doesn't require lock because we make |
1787 | * sure it's called with the tx_lock already acquired. | |
1788 | * this come from the kernel's hard_xmit callback (through | |
1789 | * the ieee stack, or from the try_wake_queue (again through | |
1790 | * the ieee stack. | |
1791 | */ | |
c8d86be3 | 1792 | priority = AC2Q(skb->priority); |
bbfb5652 | 1793 | spin_lock_irqsave(&priv->tx_lock, flags); |
c8d86be3 | 1794 | |
bbfb5652 PS |
1795 | if (priv->ieee80211->bHwRadioOff) { |
1796 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
c8d86be3 GKH |
1797 | |
1798 | return; | |
1799 | } | |
1800 | ||
bbfb5652 | 1801 | if (!check_nic_enought_desc(dev, priority)) { |
c8d86be3 GKH |
1802 | DMESGW("Error: no descriptor left by previous TX (avail %d) ", |
1803 | get_curr_tx_free_desc(dev, priority)); | |
df574b8e | 1804 | ieee80211_rtl_stop_queue(priv->ieee80211); |
c8d86be3 | 1805 | } |
bbfb5652 | 1806 | rtl8180_tx(dev, skb->data, skb->len, priority, morefrag, 0, rate); |
c8d86be3 | 1807 | if (!check_nic_enought_desc(dev, priority)) |
df574b8e | 1808 | ieee80211_rtl_stop_queue(priv->ieee80211); |
c8d86be3 | 1809 | |
bbfb5652 | 1810 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
c8d86be3 GKH |
1811 | } |
1812 | ||
3f56c109 PS |
1813 | /* |
1814 | * This is a rough attempt to TX a frame | |
c8d86be3 GKH |
1815 | * This is called by the ieee 80211 stack to TX management frames. |
1816 | * If the ring is full packet are dropped (for data frame the queue | |
1817 | * is stopped before this can happen). For this reason it is better | |
1818 | * if the descriptors are larger than the largest management frame | |
1819 | * we intend to TX: i'm unsure what the HW does if it will not found | |
1820 | * the last fragment of a frame because it has been dropped... | |
1821 | * Since queues for Management and Data frames are different we | |
1822 | * might use a different lock than tx_lock (for example mgmt_tx_lock) | |
1823 | */ | |
3f56c109 | 1824 | /* these function may loops if invoked with 0 descriptors or 0 len buffer */ |
bbfb5652 | 1825 | int rtl8180_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) |
c8d86be3 GKH |
1826 | { |
1827 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 | 1828 | unsigned long flags; |
c8d86be3 GKH |
1829 | int priority; |
1830 | ||
c8d86be3 | 1831 | priority = MANAGE_PRIORITY; |
c8d86be3 | 1832 | |
bbfb5652 | 1833 | spin_lock_irqsave(&priv->tx_lock, flags); |
c8d86be3 | 1834 | |
fd882783 | 1835 | if (priv->ieee80211->bHwRadioOff) { |
bbfb5652 | 1836 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
c8d86be3 | 1837 | dev_kfree_skb_any(skb); |
ec634fe3 | 1838 | return NETDEV_TX_OK; |
c8d86be3 GKH |
1839 | } |
1840 | ||
1841 | rtl8180_tx(dev, skb->data, skb->len, priority, | |
bbfb5652 | 1842 | 0, 0, ieeerate2rtlrate(priv->ieee80211->basic_rate)); |
c8d86be3 | 1843 | |
bbfb5652 | 1844 | priv->ieee80211->stats.tx_bytes += skb->len; |
c8d86be3 | 1845 | priv->ieee80211->stats.tx_packets++; |
bbfb5652 | 1846 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
c8d86be3 GKH |
1847 | |
1848 | dev_kfree_skb_any(skb); | |
ec634fe3 | 1849 | return NETDEV_TX_OK; |
c8d86be3 GKH |
1850 | } |
1851 | ||
3f56c109 | 1852 | /* longpre 144+48 shortpre 72+24 */ |
bbfb5652 | 1853 | u16 rtl8180_len2duration(u32 len, short rate, short *ext) |
c8d86be3 GKH |
1854 | { |
1855 | u16 duration; | |
1856 | u16 drift; | |
bbfb5652 | 1857 | *ext = 0; |
c8d86be3 | 1858 | |
bbfb5652 | 1859 | switch (rate) { |
3f56c109 | 1860 | case 0: /* 1mbps */ |
bbfb5652 PS |
1861 | *ext = 0; |
1862 | duration = ((len+4)<<4) / 0x2; | |
c8d86be3 | 1863 | drift = ((len+4)<<4) % 0x2; |
bbfb5652 PS |
1864 | if (drift == 0) |
1865 | break; | |
c8d86be3 GKH |
1866 | duration++; |
1867 | break; | |
3f56c109 | 1868 | case 1: /* 2mbps */ |
bbfb5652 PS |
1869 | *ext = 0; |
1870 | duration = ((len+4)<<4) / 0x4; | |
c8d86be3 | 1871 | drift = ((len+4)<<4) % 0x4; |
bbfb5652 PS |
1872 | if (drift == 0) |
1873 | break; | |
c8d86be3 GKH |
1874 | duration++; |
1875 | break; | |
3f56c109 | 1876 | case 2: /* 5.5mbps */ |
bbfb5652 PS |
1877 | *ext = 0; |
1878 | duration = ((len+4)<<4) / 0xb; | |
c8d86be3 | 1879 | drift = ((len+4)<<4) % 0xb; |
bbfb5652 | 1880 | if (drift == 0) |
c8d86be3 GKH |
1881 | break; |
1882 | duration++; | |
1883 | break; | |
c8d86be3 | 1884 | default: |
3f56c109 | 1885 | case 3: /* 11mbps */ |
bbfb5652 PS |
1886 | *ext = 0; |
1887 | duration = ((len+4)<<4) / 0x16; | |
c8d86be3 | 1888 | drift = ((len+4)<<4) % 0x16; |
bbfb5652 | 1889 | if (drift == 0) |
c8d86be3 GKH |
1890 | break; |
1891 | duration++; | |
bbfb5652 | 1892 | if (drift > 6) |
c8d86be3 | 1893 | break; |
bbfb5652 | 1894 | *ext = 1; |
c8d86be3 GKH |
1895 | break; |
1896 | } | |
1897 | ||
1898 | return duration; | |
1899 | } | |
1900 | ||
c8d86be3 GKH |
1901 | void rtl8180_prepare_beacon(struct net_device *dev) |
1902 | { | |
c8d86be3 | 1903 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
c8d86be3 GKH |
1904 | struct sk_buff *skb; |
1905 | ||
1906 | u16 word = read_nic_word(dev, BcnItv); | |
3f56c109 PS |
1907 | word &= ~BcnItv_BcnItv; /* clear Bcn_Itv */ |
1908 | word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval); /* 0x64; */ | |
c8d86be3 GKH |
1909 | write_nic_word(dev, BcnItv, word); |
1910 | ||
c8d86be3 | 1911 | skb = ieee80211_get_beacon(priv->ieee80211); |
bbfb5652 PS |
1912 | if (skb) { |
1913 | rtl8180_tx(dev, skb->data, skb->len, BEACON_PRIORITY, | |
1914 | 0, 0, ieeerate2rtlrate(priv->ieee80211->basic_rate)); | |
c8d86be3 GKH |
1915 | dev_kfree_skb_any(skb); |
1916 | } | |
c8d86be3 GKH |
1917 | } |
1918 | ||
3f56c109 PS |
1919 | /* |
1920 | * This function do the real dirty work: it enqueues a TX command | |
c8d86be3 GKH |
1921 | * descriptor in the ring buffer, copyes the frame in a TX buffer |
1922 | * and kicks the NIC to ensure it does the DMA transfer. | |
1923 | */ | |
1924 | short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority, | |
1925 | short morefrag, short descfrag, int rate) | |
1926 | { | |
1927 | struct r8180_priv *priv = ieee80211_priv(dev); | |
bbfb5652 | 1928 | u32 *tail, *temp_tail; |
c8d86be3 GKH |
1929 | u32 *begin; |
1930 | u32 *buf; | |
1931 | int i; | |
1932 | int remain; | |
1933 | int buflen; | |
1934 | int count; | |
c8d86be3 GKH |
1935 | u16 duration; |
1936 | short ext; | |
bbfb5652 | 1937 | struct buffer *buflist; |
c8d86be3 GKH |
1938 | struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf; |
1939 | u8 dest[ETH_ALEN]; | |
1940 | u8 bUseShortPreamble = 0; | |
1941 | u8 bCTSEnable = 0; | |
1942 | u8 bRTSEnable = 0; | |
cb73da25 | 1943 | u16 Duration = 0; |
c8d86be3 GKH |
1944 | u16 RtsDur = 0; |
1945 | u16 ThisFrameTime = 0; | |
1946 | u16 TxDescDuration = 0; | |
cb73da25 | 1947 | u8 ownbit_flag = false; |
c8d86be3 | 1948 | |
bbfb5652 | 1949 | switch (priority) { |
c8d86be3 | 1950 | case MANAGE_PRIORITY: |
bbfb5652 PS |
1951 | tail = priv->txmapringtail; |
1952 | begin = priv->txmapring; | |
c8d86be3 GKH |
1953 | buflist = priv->txmapbufstail; |
1954 | count = priv->txringcount; | |
1955 | break; | |
c8d86be3 | 1956 | case BK_PRIORITY: |
bbfb5652 PS |
1957 | tail = priv->txbkpringtail; |
1958 | begin = priv->txbkpring; | |
c8d86be3 GKH |
1959 | buflist = priv->txbkpbufstail; |
1960 | count = priv->txringcount; | |
1961 | break; | |
c8d86be3 | 1962 | case BE_PRIORITY: |
bbfb5652 PS |
1963 | tail = priv->txbepringtail; |
1964 | begin = priv->txbepring; | |
c8d86be3 GKH |
1965 | buflist = priv->txbepbufstail; |
1966 | count = priv->txringcount; | |
1967 | break; | |
c8d86be3 | 1968 | case VI_PRIORITY: |
bbfb5652 PS |
1969 | tail = priv->txvipringtail; |
1970 | begin = priv->txvipring; | |
c8d86be3 GKH |
1971 | buflist = priv->txvipbufstail; |
1972 | count = priv->txringcount; | |
1973 | break; | |
c8d86be3 | 1974 | case VO_PRIORITY: |
bbfb5652 PS |
1975 | tail = priv->txvopringtail; |
1976 | begin = priv->txvopring; | |
c8d86be3 GKH |
1977 | buflist = priv->txvopbufstail; |
1978 | count = priv->txringcount; | |
1979 | break; | |
c8d86be3 | 1980 | case HI_PRIORITY: |
bbfb5652 PS |
1981 | tail = priv->txhpringtail; |
1982 | begin = priv->txhpring; | |
c8d86be3 GKH |
1983 | buflist = priv->txhpbufstail; |
1984 | count = priv->txringcount; | |
1985 | break; | |
c8d86be3 | 1986 | case BEACON_PRIORITY: |
bbfb5652 PS |
1987 | tail = priv->txbeaconringtail; |
1988 | begin = priv->txbeaconring; | |
c8d86be3 GKH |
1989 | buflist = priv->txbeaconbufstail; |
1990 | count = priv->txbeaconcount; | |
1991 | break; | |
c8d86be3 GKH |
1992 | default: |
1993 | return -1; | |
1994 | break; | |
cb73da25 | 1995 | } |
c8d86be3 | 1996 | |
c8d86be3 GKH |
1997 | memcpy(&dest, frag_hdr->addr1, ETH_ALEN); |
1998 | if (is_multicast_ether_addr(dest) || | |
bbfb5652 | 1999 | is_broadcast_ether_addr(dest)) { |
c8d86be3 GKH |
2000 | Duration = 0; |
2001 | RtsDur = 0; | |
2002 | bRTSEnable = 0; | |
2003 | bCTSEnable = 0; | |
2004 | ||
2005 | ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble); | |
2006 | TxDescDuration = ThisFrameTime; | |
3f56c109 | 2007 | } else { /* Unicast packet */ |
c8d86be3 GKH |
2008 | u16 AckTime; |
2009 | ||
3f56c109 | 2010 | /* YJ,add,080828,for Keep alive */ |
c8d86be3 GKH |
2011 | priv->NumTxUnicast++; |
2012 | ||
1994130e LF |
2013 | /* Figure out ACK rate according to BSS basic rate |
2014 | * and Tx rate. */ | |
3f56c109 | 2015 | AckTime = ComputeTxTime(14, 10, 0, 0); /* AckCTSLng = 14 use 1M bps send */ |
c8d86be3 | 2016 | |
3f56c109 | 2017 | if (((len + sCrcLng) > priv->rts) && priv->rts) { /* RTS/CTS. */ |
c8d86be3 | 2018 | u16 RtsTime, CtsTime; |
3f56c109 | 2019 | /* u16 CtsRate; */ |
c8d86be3 GKH |
2020 | bRTSEnable = 1; |
2021 | bCTSEnable = 0; | |
2022 | ||
3f56c109 | 2023 | /* Rate and time required for RTS. */ |
bbfb5652 | 2024 | RtsTime = ComputeTxTime(sAckCtsLng/8, priv->ieee80211->basic_rate, 0, 0); |
3f56c109 PS |
2025 | /* Rate and time required for CTS. */ |
2026 | CtsTime = ComputeTxTime(14, 10, 0, 0); /* AckCTSLng = 14 use 1M bps send */ | |
c8d86be3 | 2027 | |
3f56c109 | 2028 | /* Figure out time required to transmit this frame. */ |
c8d86be3 GKH |
2029 | ThisFrameTime = ComputeTxTime(len + sCrcLng, |
2030 | rtl8180_rate2rate(rate), | |
2031 | 0, | |
2032 | bUseShortPreamble); | |
2033 | ||
3f56c109 | 2034 | /* RTS-CTS-ThisFrame-ACK. */ |
c8d86be3 GKH |
2035 | RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime; |
2036 | ||
2037 | TxDescDuration = RtsTime + RtsDur; | |
3f56c109 | 2038 | } else { /* Normal case. */ |
c8d86be3 GKH |
2039 | bCTSEnable = 0; |
2040 | bRTSEnable = 0; | |
2041 | RtsDur = 0; | |
2042 | ||
2043 | ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble); | |
2044 | TxDescDuration = ThisFrameTime + aSifsTime + AckTime; | |
2045 | } | |
2046 | ||
b6b1ac69 | 2047 | if (!(frag_hdr->frame_control & IEEE80211_FCTL_MOREFRAGS)) { |
3f56c109 | 2048 | /* ThisFrame-ACK. */ |
c8d86be3 | 2049 | Duration = aSifsTime + AckTime; |
3f56c109 | 2050 | } else { /* One or more fragments remained. */ |
c8d86be3 | 2051 | u16 NextFragTime; |
3f56c109 | 2052 | NextFragTime = ComputeTxTime(len + sCrcLng, /* pretend following packet length equal current packet */ |
c8d86be3 GKH |
2053 | rtl8180_rate2rate(rate), |
2054 | 0, | |
bbfb5652 | 2055 | bUseShortPreamble); |
c8d86be3 | 2056 | |
3f56c109 | 2057 | /* ThisFrag-ACk-NextFrag-ACK. */ |
c8d86be3 GKH |
2058 | Duration = NextFragTime + 3*aSifsTime + 2*AckTime; |
2059 | } | |
2060 | ||
3f56c109 | 2061 | } /* End of Unicast packet */ |
c8d86be3 GKH |
2062 | |
2063 | frag_hdr->duration_id = Duration; | |
c8d86be3 | 2064 | |
bbfb5652 PS |
2065 | buflen = priv->txbuffsize; |
2066 | remain = len; | |
c8d86be3 | 2067 | temp_tail = tail; |
fd882783 | 2068 | |
bbfb5652 | 2069 | while (remain != 0) { |
c8d86be3 | 2070 | mb(); |
bbfb5652 | 2071 | if (!buflist) { |
c8d86be3 | 2072 | DMESGE("TX buffer error, cannot TX frames. pri %d.", priority); |
c8d86be3 GKH |
2073 | return -1; |
2074 | } | |
bbfb5652 | 2075 | buf = buflist->buf; |
c8d86be3 | 2076 | |
fd882783 BZ |
2077 | if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) { |
2078 | DMESGW("No more TX desc, returning %x of %x", | |
2079 | remain, len); | |
2080 | priv->stats.txrdu++; | |
c8d86be3 | 2081 | return remain; |
c8d86be3 GKH |
2082 | } |
2083 | ||
3f56c109 | 2084 | *tail = 0; /* zeroes header */ |
c8d86be3 GKH |
2085 | *(tail+1) = 0; |
2086 | *(tail+3) = 0; | |
2087 | *(tail+5) = 0; | |
2088 | *(tail+6) = 0; | |
2089 | *(tail+7) = 0; | |
2090 | ||
3f56c109 | 2091 | /* FIXME: this should be triggered by HW encryption parameters.*/ |
d44eb889 | 2092 | *tail |= (1<<15); /* no encrypt */ |
fd882783 | 2093 | |
bbfb5652 | 2094 | if (remain == len && !descfrag) { |
1994130e | 2095 | ownbit_flag = false; |
3f56c109 | 2096 | *tail = *tail | (1<<29) ; /* fist segment of the packet */ |
bbfb5652 | 2097 | *tail = *tail | (len); |
c8d86be3 GKH |
2098 | } else { |
2099 | ownbit_flag = true; | |
2100 | } | |
2101 | ||
bbfb5652 | 2102 | for (i = 0; i < buflen && remain > 0; i++, remain--) { |
3f56c109 | 2103 | ((u8 *)buf)[i] = txbuf[i]; /* copy data into descriptor pointed DMAble buffer */ |
bbfb5652 PS |
2104 | if (remain == 4 && i+4 >= buflen) |
2105 | break; | |
c8d86be3 GKH |
2106 | /* ensure the last desc has at least 4 bytes payload */ |
2107 | ||
2108 | } | |
2109 | txbuf = txbuf + i; | |
bbfb5652 | 2110 | *(tail+3) = *(tail+3) & ~0xfff; |
3f56c109 PS |
2111 | *(tail+3) = *(tail+3) | i; /* buffer length */ |
2112 | /* Use short preamble or not */ | |
c8d86be3 | 2113 | if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE) |
3f56c109 PS |
2114 | if (priv->plcp_preamble_mode == 1 && rate != 0) /* short mode now, not long! */ |
2115 | ; /* *tail |= (1<<16); */ /* enable short preamble mode. */ | |
c8d86be3 | 2116 | |
bbfb5652 | 2117 | if (bCTSEnable) |
c8d86be3 | 2118 | *tail |= (1<<18); |
c8d86be3 | 2119 | |
3f56c109 PS |
2120 | if (bRTSEnable) { /* rts enable */ |
2121 | *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19); /* RTS RATE */ | |
2122 | *tail |= (1<<23); /* rts enable */ | |
2123 | *(tail+1) |= (RtsDur&0xffff); /* RTS Duration */ | |
c8d86be3 | 2124 | } |
3f56c109 PS |
2125 | *(tail+3) |= ((TxDescDuration&0xffff)<<16); /* DURATION */ |
2126 | /* *(tail+3) |= (0xe6<<16); */ | |
2127 | *(tail+5) |= (11<<8); /* (priv->retry_data<<8); */ /* retry lim; */ | |
c8d86be3 GKH |
2128 | |
2129 | *tail = *tail | ((rate&0xf) << 24); | |
c8d86be3 GKH |
2130 | |
2131 | /* hw_plcp_len is not used for rtl8180 chip */ | |
2132 | /* FIXME */ | |
d44eb889 | 2133 | if (!priv->hw_plcp_len) { |
fd882783 | 2134 | duration = rtl8180_len2duration(len, rate, &ext); |
c8d86be3 | 2135 | *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16); |
bbfb5652 | 2136 | if (ext) |
3f56c109 | 2137 | *(tail+1) = *(tail+1) | (1<<31); /* plcp length extension */ |
c8d86be3 GKH |
2138 | } |
2139 | ||
bbfb5652 | 2140 | if (morefrag) |
3f56c109 | 2141 | *tail = (*tail) | (1<<17); /* more fragment */ |
bbfb5652 | 2142 | if (!remain) |
3f56c109 | 2143 | *tail = (*tail) | (1<<28); /* last segment of frame */ |
c8d86be3 | 2144 | |
cb73da25 JC |
2145 | *(tail+5) = *(tail+5)|(2<<27); |
2146 | *(tail+7) = *(tail+7)|(1<<4); | |
c8d86be3 GKH |
2147 | |
2148 | wmb(); | |
bbfb5652 | 2149 | if (ownbit_flag) |
3f56c109 | 2150 | *tail = *tail | (1<<31); /* descriptor ready to be txed */ |
c8d86be3 | 2151 | |
bbfb5652 PS |
2152 | if ((tail - begin)/8 == count-1) |
2153 | tail = begin; | |
c8d86be3 | 2154 | else |
bbfb5652 | 2155 | tail = tail+8; |
c8d86be3 | 2156 | |
bbfb5652 | 2157 | buflist = buflist->next; |
c8d86be3 GKH |
2158 | |
2159 | mb(); | |
2160 | ||
bbfb5652 PS |
2161 | switch (priority) { |
2162 | case MANAGE_PRIORITY: | |
2163 | priv->txmapringtail = tail; | |
2164 | priv->txmapbufstail = buflist; | |
2165 | break; | |
2166 | case BK_PRIORITY: | |
2167 | priv->txbkpringtail = tail; | |
2168 | priv->txbkpbufstail = buflist; | |
2169 | break; | |
2170 | case BE_PRIORITY: | |
2171 | priv->txbepringtail = tail; | |
2172 | priv->txbepbufstail = buflist; | |
2173 | break; | |
2174 | case VI_PRIORITY: | |
2175 | priv->txvipringtail = tail; | |
2176 | priv->txvipbufstail = buflist; | |
2177 | break; | |
2178 | case VO_PRIORITY: | |
2179 | priv->txvopringtail = tail; | |
2180 | priv->txvopbufstail = buflist; | |
2181 | break; | |
2182 | case HI_PRIORITY: | |
2183 | priv->txhpringtail = tail; | |
2184 | priv->txhpbufstail = buflist; | |
2185 | break; | |
2186 | case BEACON_PRIORITY: | |
3f56c109 PS |
2187 | /* |
2188 | * The HW seems to be happy with the 1st | |
bbfb5652 PS |
2189 | * descriptor filled and the 2nd empty... |
2190 | * So always update descriptor 1 and never | |
2191 | * touch 2nd | |
2192 | */ | |
2193 | break; | |
c8d86be3 | 2194 | } |
c8d86be3 | 2195 | } |
3f56c109 | 2196 | *temp_tail = *temp_tail | (1<<31); /* descriptor ready to be txed */ |
bbfb5652 | 2197 | rtl8180_dma_kick(dev, priority); |
c8d86be3 GKH |
2198 | |
2199 | return 0; | |
c8d86be3 GKH |
2200 | } |
2201 | ||
bbfb5652 | 2202 | void rtl8180_irq_rx_tasklet(struct r8180_priv *priv); |
c8d86be3 | 2203 | |
c8d86be3 GKH |
2204 | void rtl8180_link_change(struct net_device *dev) |
2205 | { | |
2206 | struct r8180_priv *priv = ieee80211_priv(dev); | |
2207 | u16 beacon_interval; | |
c8d86be3 | 2208 | struct ieee80211_network *net = &priv->ieee80211->current_network; |
c8d86be3 | 2209 | |
fd882783 | 2210 | rtl8180_update_msr(dev); |
c8d86be3 | 2211 | |
bbfb5652 | 2212 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
c8d86be3 | 2213 | |
bbfb5652 PS |
2214 | write_nic_dword(dev, BSSID, ((u32 *)net->bssid)[0]); |
2215 | write_nic_word(dev, BSSID+4, ((u16 *)net->bssid)[2]); | |
c8d86be3 | 2216 | |
bbfb5652 PS |
2217 | beacon_interval = read_nic_dword(dev, BEACON_INTERVAL); |
2218 | beacon_interval &= ~BEACON_INTERVAL_MASK; | |
c8d86be3 GKH |
2219 | beacon_interval |= net->beacon_interval; |
2220 | write_nic_dword(dev, BEACON_INTERVAL, beacon_interval); | |
2221 | ||
2222 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
2223 | ||
d44eb889 | 2224 | rtl8180_set_chan(dev, priv->chan); |
c8d86be3 GKH |
2225 | } |
2226 | ||
bbfb5652 PS |
2227 | void rtl8180_rq_tx_ack(struct net_device *dev) |
2228 | { | |
c8d86be3 GKH |
2229 | |
2230 | struct r8180_priv *priv = ieee80211_priv(dev); | |
fd882783 | 2231 | |
bbfb5652 | 2232 | write_nic_byte(dev, CONFIG4, read_nic_byte(dev, CONFIG4) | CONFIG4_PWRMGT); |
c8d86be3 GKH |
2233 | priv->ack_tx_to_ieee = 1; |
2234 | } | |
2235 | ||
bbfb5652 PS |
2236 | short rtl8180_is_tx_queue_empty(struct net_device *dev) |
2237 | { | |
c8d86be3 GKH |
2238 | |
2239 | struct r8180_priv *priv = ieee80211_priv(dev); | |
bbfb5652 | 2240 | u32 *d; |
c8d86be3 GKH |
2241 | |
2242 | for (d = priv->txmapring; | |
bbfb5652 PS |
2243 | d < priv->txmapring + priv->txringcount; d += 8) |
2244 | if (*d & (1<<31)) | |
2245 | return 0; | |
c8d86be3 GKH |
2246 | |
2247 | for (d = priv->txbkpring; | |
bbfb5652 PS |
2248 | d < priv->txbkpring + priv->txringcount; d += 8) |
2249 | if (*d & (1<<31)) | |
2250 | return 0; | |
c8d86be3 GKH |
2251 | |
2252 | for (d = priv->txbepring; | |
bbfb5652 PS |
2253 | d < priv->txbepring + priv->txringcount; d += 8) |
2254 | if (*d & (1<<31)) | |
2255 | return 0; | |
c8d86be3 GKH |
2256 | |
2257 | for (d = priv->txvipring; | |
bbfb5652 PS |
2258 | d < priv->txvipring + priv->txringcount; d += 8) |
2259 | if (*d & (1<<31)) | |
2260 | return 0; | |
c8d86be3 GKH |
2261 | |
2262 | for (d = priv->txvopring; | |
bbfb5652 PS |
2263 | d < priv->txvopring + priv->txringcount; d += 8) |
2264 | if (*d & (1<<31)) | |
2265 | return 0; | |
c8d86be3 GKH |
2266 | |
2267 | for (d = priv->txhpring; | |
bbfb5652 PS |
2268 | d < priv->txhpring + priv->txringcount; d += 8) |
2269 | if (*d & (1<<31)) | |
2270 | return 0; | |
c8d86be3 GKH |
2271 | return 1; |
2272 | } | |
2273 | /* FIXME FIXME 5msecs is random */ | |
2274 | #define HW_WAKE_DELAY 5 | |
2275 | ||
2276 | void rtl8180_hw_wakeup(struct net_device *dev) | |
2277 | { | |
2278 | unsigned long flags; | |
c8d86be3 GKH |
2279 | struct r8180_priv *priv = ieee80211_priv(dev); |
2280 | ||
bbfb5652 PS |
2281 | spin_lock_irqsave(&priv->ps_lock, flags); |
2282 | write_nic_byte(dev, CONFIG4, read_nic_byte(dev, CONFIG4) & ~CONFIG4_PWRMGT); | |
fd882783 | 2283 | if (priv->rf_wakeup) |
c8d86be3 | 2284 | priv->rf_wakeup(dev); |
bbfb5652 | 2285 | spin_unlock_irqrestore(&priv->ps_lock, flags); |
c8d86be3 GKH |
2286 | } |
2287 | ||
2288 | void rtl8180_hw_sleep_down(struct net_device *dev) | |
2289 | { | |
cb73da25 JC |
2290 | unsigned long flags; |
2291 | struct r8180_priv *priv = ieee80211_priv(dev); | |
c8d86be3 | 2292 | |
cb73da25 JC |
2293 | spin_lock_irqsave(&priv->ps_lock, flags); |
2294 | if (priv->rf_sleep) | |
2295 | priv->rf_sleep(dev); | |
2296 | spin_unlock_irqrestore(&priv->ps_lock, flags); | |
c8d86be3 GKH |
2297 | } |
2298 | ||
c8d86be3 GKH |
2299 | void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl) |
2300 | { | |
c8d86be3 | 2301 | struct r8180_priv *priv = ieee80211_priv(dev); |
c8d86be3 GKH |
2302 | u32 rb = jiffies; |
2303 | unsigned long flags; | |
2304 | ||
bbfb5652 | 2305 | spin_lock_irqsave(&priv->ps_lock, flags); |
c8d86be3 | 2306 | |
3f56c109 PS |
2307 | /* |
2308 | * Writing HW register with 0 equals to disable | |
c8d86be3 GKH |
2309 | * the timer, that is not really what we want |
2310 | */ | |
2311 | tl -= MSECS(4+16+7); | |
2312 | ||
3f56c109 PS |
2313 | /* |
2314 | * If the interval in witch we are requested to sleep is too | |
c8d86be3 GKH |
2315 | * short then give up and remain awake |
2316 | */ | |
bbfb5652 PS |
2317 | if (((tl >= rb) && (tl-rb) <= MSECS(MIN_SLEEP_TIME)) |
2318 | || ((rb > tl) && (rb-tl) < MSECS(MIN_SLEEP_TIME))) { | |
2319 | spin_unlock_irqrestore(&priv->ps_lock, flags); | |
c8d86be3 GKH |
2320 | printk("too short to sleep\n"); |
2321 | return; | |
2322 | } | |
2323 | ||
c8d86be3 | 2324 | { |
bbfb5652 | 2325 | u32 tmp = (tl > rb) ? (tl-rb) : (rb-tl); |
c8d86be3 | 2326 | |
c8d86be3 GKH |
2327 | priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp); |
2328 | ||
3f56c109 | 2329 | queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); /* as tl may be less than rb */ |
c8d86be3 | 2330 | } |
3f56c109 PS |
2331 | /* |
2332 | * If we suspect the TimerInt is gone beyond tl | |
c8d86be3 GKH |
2333 | * while setting it, then give up |
2334 | */ | |
fd882783 | 2335 | |
bbfb5652 | 2336 | if (((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME))) || |
c8d86be3 | 2337 | ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) { |
bbfb5652 | 2338 | spin_unlock_irqrestore(&priv->ps_lock, flags); |
c8d86be3 GKH |
2339 | return; |
2340 | } | |
c8d86be3 GKH |
2341 | |
2342 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq); | |
bbfb5652 | 2343 | spin_unlock_irqrestore(&priv->ps_lock, flags); |
c8d86be3 GKH |
2344 | } |
2345 | ||
bbfb5652 | 2346 | void rtl8180_wmm_param_update(struct work_struct *work) |
c8d86be3 | 2347 | { |
bbfb5652 | 2348 | struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, wmm_param_update_wq); |
c8d86be3 | 2349 | struct net_device *dev = ieee->dev; |
c8d86be3 GKH |
2350 | u8 *ac_param = (u8 *)(ieee->current_network.wmm_param); |
2351 | u8 mode = ieee->current_network.mode; | |
2352 | AC_CODING eACI; | |
2353 | AC_PARAM AcParam; | |
2354 | PAC_PARAM pAcParam; | |
2355 | u8 i; | |
2356 | ||
bbfb5652 | 2357 | if (!ieee->current_network.QoS_Enable) { |
3f56c109 | 2358 | /* legacy ac_xx_param update */ |
c8d86be3 | 2359 | AcParam.longData = 0; |
3f56c109 | 2360 | AcParam.f.AciAifsn.f.AIFSN = 2; /* Follow 802.11 DIFS. */ |
c8d86be3 | 2361 | AcParam.f.AciAifsn.f.ACM = 0; |
3f56c109 PS |
2362 | AcParam.f.Ecw.f.ECWmin = 3; /* Follow 802.11 CWmin. */ |
2363 | AcParam.f.Ecw.f.ECWmax = 7; /* Follow 802.11 CWmax. */ | |
c8d86be3 | 2364 | AcParam.f.TXOPLimit = 0; |
bbfb5652 | 2365 | for (eACI = 0; eACI < AC_MAX; eACI++) { |
c8d86be3 GKH |
2366 | AcParam.f.AciAifsn.f.ACI = (u8)eACI; |
2367 | { | |
2368 | u8 u1bAIFS; | |
2369 | u32 u4bAcParam; | |
2370 | pAcParam = (PAC_PARAM)(&AcParam); | |
3f56c109 | 2371 | /* Retrive paramters to udpate. */ |
bbfb5652 | 2372 | u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G) ? 9 : 20) + aSifsTime; |
c8d86be3 GKH |
2373 | u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)| |
2374 | (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)| | |
2375 | (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)| | |
2376 | (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); | |
bbfb5652 PS |
2377 | switch (eACI) { |
2378 | case AC1_BK: | |
2379 | write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); | |
2380 | break; | |
2381 | case AC0_BE: | |
2382 | write_nic_dword(dev, AC_BE_PARAM, u4bAcParam); | |
2383 | break; | |
2384 | case AC2_VI: | |
2385 | write_nic_dword(dev, AC_VI_PARAM, u4bAcParam); | |
2386 | break; | |
2387 | case AC3_VO: | |
2388 | write_nic_dword(dev, AC_VO_PARAM, u4bAcParam); | |
2389 | break; | |
2390 | default: | |
2391 | printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI); | |
2392 | break; | |
c8d86be3 GKH |
2393 | } |
2394 | } | |
2395 | } | |
2396 | return; | |
2397 | } | |
2398 | ||
bbfb5652 | 2399 | for (i = 0; i < AC_MAX; i++) { |
3f56c109 | 2400 | /* AcParam.longData = 0; */ |
bbfb5652 | 2401 | pAcParam = (AC_PARAM *)ac_param; |
c8d86be3 GKH |
2402 | { |
2403 | AC_CODING eACI; | |
2404 | u8 u1bAIFS; | |
2405 | u32 u4bAcParam; | |
2406 | ||
3f56c109 | 2407 | /* Retrive paramters to udpate. */ |
c8d86be3 | 2408 | eACI = pAcParam->f.AciAifsn.f.ACI; |
3f56c109 | 2409 | /* Mode G/A: slotTimeTimer = 9; Mode B: 20 */ |
bbfb5652 PS |
2410 | u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G) ? 9 : 20) + aSifsTime; |
2411 | u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) | | |
c8d86be3 GKH |
2412 | (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) | |
2413 | (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) | | |
2414 | (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); | |
2415 | ||
bbfb5652 PS |
2416 | switch (eACI) { |
2417 | case AC1_BK: | |
2418 | write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); | |
2419 | break; | |
2420 | case AC0_BE: | |
2421 | write_nic_dword(dev, AC_BE_PARAM, u4bAcParam); | |
2422 | break; | |
2423 | case AC2_VI: | |
2424 | write_nic_dword(dev, AC_VI_PARAM, u4bAcParam); | |
2425 | break; | |
2426 | case AC3_VO: | |
2427 | write_nic_dword(dev, AC_VO_PARAM, u4bAcParam); | |
2428 | break; | |
2429 | default: | |
2430 | printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI); | |
2431 | break; | |
c8d86be3 GKH |
2432 | } |
2433 | } | |
2434 | ac_param += (sizeof(AC_PARAM)); | |
2435 | } | |
c8d86be3 GKH |
2436 | } |
2437 | ||
c8d86be3 | 2438 | void rtl8180_tx_irq_wq(struct work_struct *work); |
c8d86be3 | 2439 | void rtl8180_restart_wq(struct work_struct *work); |
3f56c109 | 2440 | /* void rtl8180_rq_tx_ack(struct work_struct *work); */ |
c8d86be3 | 2441 | void rtl8180_watch_dog_wq(struct work_struct *work); |
c8d86be3 | 2442 | void rtl8180_hw_wakeup_wq(struct work_struct *work); |
c8d86be3 | 2443 | void rtl8180_hw_sleep_wq(struct work_struct *work); |
c8d86be3 | 2444 | void rtl8180_sw_antenna_wq(struct work_struct *work); |
0370453f BZ |
2445 | void rtl8180_watch_dog(struct net_device *dev); |
2446 | ||
c8d86be3 GKH |
2447 | void watch_dog_adaptive(unsigned long data) |
2448 | { | |
fd882783 BZ |
2449 | struct r8180_priv* priv = ieee80211_priv((struct net_device *)data); |
2450 | ||
2451 | if (!priv->up) { | |
c8d86be3 GKH |
2452 | DMESG("<----watch_dog_adaptive():driver is not up!\n"); |
2453 | return; | |
2454 | } | |
2455 | ||
3f56c109 | 2456 | /* Tx High Power Mechanism. */ |
bbfb5652 | 2457 | if (CheckHighPower((struct net_device *)data)) |
c8d86be3 | 2458 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq); |
c8d86be3 | 2459 | |
3f56c109 | 2460 | /* Tx Power Tracking on 87SE. */ |
cffd4e16 | 2461 | if (CheckTxPwrTracking((struct net_device *)data)) |
c8d86be3 | 2462 | TxPwrTracking87SE((struct net_device *)data); |
c8d86be3 | 2463 | |
3f56c109 | 2464 | /* Perform DIG immediately. */ |
bbfb5652 | 2465 | if (CheckDig((struct net_device *)data) == true) |
c8d86be3 | 2466 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq); |
bbfb5652 | 2467 | rtl8180_watch_dog((struct net_device *)data); |
c8d86be3 | 2468 | |
c8d86be3 GKH |
2469 | queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem); |
2470 | ||
bbfb5652 | 2471 | priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME); |
c8d86be3 | 2472 | add_timer(&priv->watch_dog_timer); |
c8d86be3 GKH |
2473 | } |
2474 | ||
c8d86be3 | 2475 | static CHANNEL_LIST ChannelPlan[] = { |
3f56c109 PS |
2476 | {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, /* FCC */ |
2477 | {{1,2,3,4,5,6,7,8,9,10,11},11}, /* IC */ | |
2478 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* ETSI */ | |
2479 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* Spain. Change to ETSI. */ | |
2480 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* France. Change to ETSI. */ | |
2481 | {{14,36,40,44,48,52,56,60,64},9}, /* MKK */ | |
2482 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},/* MKK1 */ | |
2483 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* Israel. */ | |
2484 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, /* For 11a , TELEC */ | |
2485 | {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, /* For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626 */ | |
2486 | {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} /* world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826 */ | |
c8d86be3 GKH |
2487 | }; |
2488 | ||
2489 | static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee) | |
2490 | { | |
2491 | int i; | |
2492 | ||
3f56c109 | 2493 | /* lzm add 080826 */ |
bbfb5652 PS |
2494 | ieee->MinPassiveChnlNum = MAX_CHANNEL_NUMBER+1; |
2495 | ieee->IbssStartChnl = 0; | |
2496 | ||
2497 | switch (channel_plan) { | |
2498 | case COUNTRY_CODE_FCC: | |
2499 | case COUNTRY_CODE_IC: | |
2500 | case COUNTRY_CODE_ETSI: | |
2501 | case COUNTRY_CODE_SPAIN: | |
2502 | case COUNTRY_CODE_FRANCE: | |
2503 | case COUNTRY_CODE_MKK: | |
2504 | case COUNTRY_CODE_MKK1: | |
2505 | case COUNTRY_CODE_ISRAEL: | |
2506 | case COUNTRY_CODE_TELEC: | |
c8d86be3 GKH |
2507 | { |
2508 | Dot11d_Init(ieee); | |
2509 | ieee->bGlobalDomain = false; | |
bbfb5652 | 2510 | if (ChannelPlan[channel_plan].Len != 0) { |
3f56c109 | 2511 | /* Clear old channel map */ |
c8d86be3 | 2512 | memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); |
3f56c109 | 2513 | /* Set new channel map */ |
bbfb5652 PS |
2514 | for (i = 0; i < ChannelPlan[channel_plan].Len; i++) { |
2515 | if (ChannelPlan[channel_plan].Channel[i] <= 14) | |
c8d86be3 GKH |
2516 | GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1; |
2517 | } | |
2518 | } | |
2519 | break; | |
2520 | } | |
bbfb5652 | 2521 | case COUNTRY_CODE_GLOBAL_DOMAIN: |
c8d86be3 GKH |
2522 | { |
2523 | GET_DOT11D_INFO(ieee)->bEnabled = 0; | |
2524 | Dot11d_Reset(ieee); | |
2525 | ieee->bGlobalDomain = true; | |
2526 | break; | |
2527 | } | |
3f56c109 | 2528 | case COUNTRY_CODE_WORLD_WIDE_13_INDEX:/* lzm add 080826 */ |
c8d86be3 | 2529 | { |
bbfb5652 PS |
2530 | ieee->MinPassiveChnlNum = 12; |
2531 | ieee->IbssStartChnl = 10; | |
2532 | break; | |
c8d86be3 | 2533 | } |
bbfb5652 | 2534 | default: |
c8d86be3 GKH |
2535 | { |
2536 | Dot11d_Init(ieee); | |
2537 | ieee->bGlobalDomain = false; | |
2538 | memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); | |
bbfb5652 | 2539 | for (i = 1; i <= 14; i++) |
c8d86be3 | 2540 | GET_DOT11D_INFO(ieee)->channel_map[i] = 1; |
c8d86be3 GKH |
2541 | break; |
2542 | } | |
2543 | } | |
2544 | } | |
c8d86be3 | 2545 | |
c8d86be3 | 2546 | void GPIOChangeRFWorkItemCallBack(struct work_struct *work); |
c8d86be3 | 2547 | |
3f56c109 | 2548 | /* YJ,add,080828 */ |
c8d86be3 GKH |
2549 | static void rtl8180_statistics_init(struct Stats *pstats) |
2550 | { | |
2551 | memset(pstats, 0, sizeof(struct Stats)); | |
2552 | } | |
fd882783 | 2553 | |
c8d86be3 GKH |
2554 | static void rtl8180_link_detect_init(plink_detect_t plink_detect) |
2555 | { | |
2556 | memset(plink_detect, 0, sizeof(link_detect_t)); | |
2557 | plink_detect->SlotNum = DEFAULT_SLOT_NUM; | |
2558 | } | |
c8d86be3 | 2559 | |
3f56c109 | 2560 | /* YJ,add,080828,end */ |
742821ce LF |
2561 | static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom) |
2562 | { | |
2563 | struct net_device *dev = eeprom->data; | |
2564 | u8 reg = read_nic_byte(dev, EPROM_CMD); | |
2565 | ||
2566 | eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; | |
2567 | eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; | |
2568 | eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; | |
2569 | eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; | |
2570 | } | |
2571 | ||
2572 | static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom) | |
2573 | { | |
2574 | struct net_device *dev = eeprom->data; | |
2575 | u8 reg = 2 << 6; | |
2576 | ||
2577 | if (eeprom->reg_data_in) | |
2578 | reg |= RTL818X_EEPROM_CMD_WRITE; | |
2579 | if (eeprom->reg_data_out) | |
2580 | reg |= RTL818X_EEPROM_CMD_READ; | |
2581 | if (eeprom->reg_data_clock) | |
2582 | reg |= RTL818X_EEPROM_CMD_CK; | |
2583 | if (eeprom->reg_chip_select) | |
2584 | reg |= RTL818X_EEPROM_CMD_CS; | |
2585 | ||
2586 | write_nic_byte(dev, EPROM_CMD, reg); | |
2587 | read_nic_byte(dev, EPROM_CMD); | |
2588 | udelay(10); | |
2589 | } | |
2590 | ||
c8d86be3 GKH |
2591 | short rtl8180_init(struct net_device *dev) |
2592 | { | |
2593 | struct r8180_priv *priv = ieee80211_priv(dev); | |
2594 | u16 word; | |
2595 | u16 version; | |
c8d86be3 GKH |
2596 | u32 usValue; |
2597 | u16 tmpu16; | |
2598 | int i, j; | |
742821ce LF |
2599 | struct eeprom_93cx6 eeprom; |
2600 | u16 eeprom_val; | |
2601 | ||
2602 | eeprom.data = dev; | |
2603 | eeprom.register_read = rtl8187se_eeprom_register_read; | |
2604 | eeprom.register_write = rtl8187se_eeprom_register_write; | |
2605 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
c8d86be3 | 2606 | |
742821ce LF |
2607 | eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val); |
2608 | priv->channel_plan = eeprom_val & 0xFF; | |
bbfb5652 | 2609 | if (priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN) { |
c8d86be3 GKH |
2610 | printk("rtl8180_init:Error channel plan! Set to default.\n"); |
2611 | priv->channel_plan = 0; | |
2612 | } | |
c8d86be3 | 2613 | |
bbfb5652 | 2614 | DMESG("Channel plan is %d\n", priv->channel_plan); |
c8d86be3 | 2615 | rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211); |
c8d86be3 | 2616 | |
3f56c109 PS |
2617 | /* FIXME: these constants are placed in a bad pleace. */ |
2618 | priv->txbuffsize = 2048; /* 1024; */ | |
2619 | priv->txringcount = 32; /* 32; */ | |
2620 | priv->rxbuffersize = 2048; /* 1024; */ | |
2621 | priv->rxringcount = 64; /* 32; */ | |
c8d86be3 GKH |
2622 | priv->txbeaconcount = 2; |
2623 | priv->rx_skb_complete = 1; | |
c8d86be3 | 2624 | |
c8d86be3 GKH |
2625 | priv->RFChangeInProgress = false; |
2626 | priv->SetRFPowerStateInProgress = false; | |
2627 | priv->RFProgType = 0; | |
2628 | priv->bInHctTest = false; | |
2629 | ||
bbfb5652 | 2630 | priv->irq_enabled = 0; |
c8d86be3 | 2631 | |
c8d86be3 GKH |
2632 | rtl8180_statistics_init(&priv->stats); |
2633 | rtl8180_link_detect_init(&priv->link_detect); | |
c8d86be3 GKH |
2634 | |
2635 | priv->ack_tx_to_ieee = 0; | |
2636 | priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL; | |
2637 | priv->ieee80211->iw_mode = IW_MODE_INFRA; | |
2638 | priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN | | |
2639 | IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | | |
2640 | IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE; | |
2641 | priv->ieee80211->active_scan = 1; | |
3f56c109 | 2642 | priv->ieee80211->rate = 110; /* 11 mbps */ |
c8d86be3 GKH |
2643 | priv->ieee80211->modulation = IEEE80211_CCK_MODULATION; |
2644 | priv->ieee80211->host_encrypt = 1; | |
2645 | priv->ieee80211->host_decrypt = 1; | |
2646 | priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup; | |
2647 | priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack; | |
2648 | priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep; | |
2649 | priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty; | |
2650 | ||
2651 | priv->hw_wep = hwwep; | |
bbfb5652 PS |
2652 | priv->prism_hdr = 0; |
2653 | priv->dev = dev; | |
c8d86be3 GKH |
2654 | priv->retry_rts = DEFAULT_RETRY_RTS; |
2655 | priv->retry_data = DEFAULT_RETRY_DATA; | |
2656 | priv->RFChangeInProgress = false; | |
2657 | priv->SetRFPowerStateInProgress = false; | |
2658 | priv->RFProgType = 0; | |
2659 | priv->bInHctTest = false; | |
3f56c109 | 2660 | priv->bInactivePs = true; /* false; */ |
c8d86be3 GKH |
2661 | priv->ieee80211->bInactivePs = priv->bInactivePs; |
2662 | priv->bSwRfProcessing = false; | |
2663 | priv->eRFPowerState = eRfOff; | |
2664 | priv->RfOffReason = 0; | |
2665 | priv->LedStrategy = SW_LED_MODE0; | |
3f56c109 | 2666 | priv->TxPollingTimes = 0; /* lzm add 080826 */ |
c8d86be3 GKH |
2667 | priv->bLeisurePs = true; |
2668 | priv->dot11PowerSaveMode = eActive; | |
c8d86be3 GKH |
2669 | priv->AdMinCheckPeriod = 5; |
2670 | priv->AdMaxCheckPeriod = 10; | |
3f56c109 PS |
2671 | priv->AdMaxRxSsThreshold = 30; /* 60->30 */ |
2672 | priv->AdRxSsThreshold = 20; /* 50->20 */ | |
c8d86be3 GKH |
2673 | priv->AdCheckPeriod = priv->AdMinCheckPeriod; |
2674 | priv->AdTickCount = 0; | |
2675 | priv->AdRxSignalStrength = -1; | |
2676 | priv->RegSwAntennaDiversityMechanism = 0; | |
2677 | priv->RegDefaultAntenna = 0; | |
2678 | priv->SignalStrength = 0; | |
2679 | priv->AdRxOkCnt = 0; | |
2680 | priv->CurrAntennaIndex = 0; | |
2681 | priv->AdRxSsBeforeSwitched = 0; | |
2682 | init_timer(&priv->SwAntennaDiversityTimer); | |
2683 | priv->SwAntennaDiversityTimer.data = (unsigned long)dev; | |
2684 | priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback; | |
c8d86be3 GKH |
2685 | priv->bDigMechanism = 1; |
2686 | priv->InitialGain = 6; | |
2687 | priv->bXtalCalibration = false; | |
2688 | priv->XtalCal_Xin = 0; | |
2689 | priv->XtalCal_Xout = 0; | |
2690 | priv->bTxPowerTrack = false; | |
2691 | priv->ThermalMeter = 0; | |
2692 | priv->FalseAlarmRegValue = 0; | |
3f56c109 | 2693 | priv->RegDigOfdmFaUpTh = 0xc; /* Upper threhold of OFDM false alarm, which is used in DIG. */ |
c8d86be3 GKH |
2694 | priv->DIG_NumberFallbackVote = 0; |
2695 | priv->DIG_NumberUpgradeVote = 0; | |
2696 | priv->LastSignalStrengthInPercent = 0; | |
2697 | priv->Stats_SignalStrength = 0; | |
2698 | priv->LastRxPktAntenna = 0; | |
3f56c109 | 2699 | priv->SignalQuality = 0; /* in 0-100 index. */ |
c8d86be3 | 2700 | priv->Stats_SignalQuality = 0; |
3f56c109 | 2701 | priv->RecvSignalPower = 0; /* in dBm. */ |
c8d86be3 GKH |
2702 | priv->Stats_RecvSignalPower = 0; |
2703 | priv->AdMainAntennaRxOkCnt = 0; | |
2704 | priv->AdAuxAntennaRxOkCnt = 0; | |
2705 | priv->bHWAdSwitched = false; | |
2706 | priv->bRegHighPowerMechanism = true; | |
2707 | priv->RegHiPwrUpperTh = 77; | |
2708 | priv->RegHiPwrLowerTh = 75; | |
2709 | priv->RegRSSIHiPwrUpperTh = 70; | |
2710 | priv->RegRSSIHiPwrLowerTh = 20; | |
2711 | priv->bCurCCKPkt = false; | |
2712 | priv->UndecoratedSmoothedSS = -1; | |
2713 | priv->bToUpdateTxPwr = false; | |
2714 | priv->CurCCKRSSI = 0; | |
2715 | priv->RxPower = 0; | |
2716 | priv->RSSI = 0; | |
c8d86be3 GKH |
2717 | priv->NumTxOkTotal = 0; |
2718 | priv->NumTxUnicast = 0; | |
2719 | priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL; | |
2720 | priv->PowerProfile = POWER_PROFILE_AC; | |
1994130e LF |
2721 | priv->CurrRetryCnt = 0; |
2722 | priv->LastRetryCnt = 0; | |
2723 | priv->LastTxokCnt = 0; | |
2724 | priv->LastRxokCnt = 0; | |
2725 | priv->LastRetryRate = 0; | |
2726 | priv->bTryuping = 0; | |
2727 | priv->CurrTxRate = 0; | |
2728 | priv->CurrRetryRate = 0; | |
2729 | priv->TryupingCount = 0; | |
2730 | priv->TryupingCountNoData = 0; | |
2731 | priv->TryDownCountLowData = 0; | |
2732 | priv->LastTxOKBytes = 0; | |
2733 | priv->LastFailTxRate = 0; | |
2734 | priv->LastFailTxRateSS = 0; | |
2735 | priv->FailTxRateCount = 0; | |
2736 | priv->LastTxThroughput = 0; | |
2737 | priv->NumTxOkBytesTotal = 0; | |
c8d86be3 GKH |
2738 | priv->ForcedDataRate = 0; |
2739 | priv->RegBModeGainStage = 1; | |
2740 | ||
1994130e | 2741 | priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; |
c8d86be3 GKH |
2742 | spin_lock_init(&priv->irq_lock); |
2743 | spin_lock_init(&priv->irq_th_lock); | |
2744 | spin_lock_init(&priv->tx_lock); | |
2745 | spin_lock_init(&priv->ps_lock); | |
2746 | spin_lock_init(&priv->rf_ps_lock); | |
1994130e LF |
2747 | sema_init(&priv->wx_sem, 1); |
2748 | sema_init(&priv->rf_state, 1); | |
2749 | INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq); | |
2750 | INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq); | |
2751 | INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq, | |
2752 | (void *)rtl8180_hw_wakeup_wq); | |
2753 | INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq, | |
2754 | (void *)rtl8180_hw_sleep_wq); | |
2755 | INIT_WORK(&priv->ieee80211->wmm_param_update_wq, | |
2756 | (void *)rtl8180_wmm_param_update); | |
2757 | INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq, | |
2758 | (void *)rtl8180_rate_adapter); | |
2759 | INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq, | |
2760 | (void *)rtl8180_hw_dig_wq); | |
2761 | INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq, | |
2762 | (void *)rtl8180_tx_pw_wq); | |
2763 | INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem, | |
2764 | (void *) GPIOChangeRFWorkItemCallBack); | |
c8d86be3 GKH |
2765 | tasklet_init(&priv->irq_rx_tasklet, |
2766 | (void(*)(unsigned long)) rtl8180_irq_rx_tasklet, | |
2767 | (unsigned long)priv); | |
fd882783 | 2768 | |
1994130e | 2769 | init_timer(&priv->watch_dog_timer); |
c8d86be3 GKH |
2770 | priv->watch_dog_timer.data = (unsigned long)dev; |
2771 | priv->watch_dog_timer.function = watch_dog_adaptive; | |
c8d86be3 | 2772 | |
1994130e LF |
2773 | init_timer(&priv->rateadapter_timer); |
2774 | priv->rateadapter_timer.data = (unsigned long)dev; | |
2775 | priv->rateadapter_timer.function = timer_rate_adaptive; | |
2776 | priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD; | |
2777 | priv->bEnhanceTxPwr = false; | |
c8d86be3 GKH |
2778 | |
2779 | priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit; | |
2780 | priv->ieee80211->set_chan = rtl8180_set_chan; | |
2781 | priv->ieee80211->link_change = rtl8180_link_change; | |
2782 | priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit; | |
2783 | priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop; | |
2784 | priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume; | |
2785 | ||
cb73da25 | 2786 | priv->ieee80211->init_wmmparam_flag = 0; |
c8d86be3 GKH |
2787 | |
2788 | priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon; | |
2789 | priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable; | |
2790 | priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; | |
2791 | ||
c8d86be3 GKH |
2792 | priv->MWIEnable = 0; |
2793 | ||
2794 | priv->ShortRetryLimit = 7; | |
2795 | priv->LongRetryLimit = 7; | |
2796 | priv->EarlyRxThreshold = 7; | |
2797 | ||
2798 | priv->CSMethod = (0x01 << 29); | |
2799 | ||
1994130e LF |
2800 | priv->TransmitConfig = TCR_DurProcMode_OFFSET | |
2801 | (7<<TCR_MXDMA_OFFSET) | | |
2802 | (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | | |
2803 | (priv->LongRetryLimit<<TCR_LRL_OFFSET) | | |
2804 | (0 ? TCR_SAT : 0); | |
2805 | ||
2806 | priv->ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF | | |
2807 | RCR_AB | RCR_AM | RCR_APM | | |
2808 | (7<<RCR_MXDMA_OFFSET) | | |
2809 | (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | | |
2810 | (priv->EarlyRxThreshold == 7 ? | |
2811 | RCR_ONLYERLPKT : 0); | |
c8d86be3 GKH |
2812 | |
2813 | priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER | | |
1994130e LF |
2814 | IMR_THPDER | IMR_THPDOK | |
2815 | IMR_TVODER | IMR_TVODOK | | |
2816 | IMR_TVIDER | IMR_TVIDOK | | |
2817 | IMR_TBEDER | IMR_TBEDOK | | |
2818 | IMR_TBKDER | IMR_TBKDOK | | |
2819 | IMR_RDU | | |
2820 | IMR_RER | IMR_ROK | | |
2821 | IMR_RQoSOK; | |
c8d86be3 GKH |
2822 | |
2823 | priv->InitialGain = 6; | |
c8d86be3 | 2824 | |
d44eb889 LF |
2825 | DMESG("MAC controller is a RTL8187SE b/g"); |
2826 | priv->phy_ver = 2; | |
c8d86be3 | 2827 | |
d44eb889 LF |
2828 | priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION; |
2829 | priv->ieee80211->short_slot = 1; | |
c8d86be3 | 2830 | |
3f56c109 | 2831 | /* just for sync 85 */ |
c8d86be3 GKH |
2832 | priv->enable_gpio0 = 0; |
2833 | ||
742821ce LF |
2834 | eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val); |
2835 | usValue = eeprom_val; | |
bbfb5652 | 2836 | DMESG("usValue is 0x%x\n", usValue); |
3f56c109 | 2837 | /* 3Read AntennaDiversity */ |
fd882783 | 2838 | |
3f56c109 | 2839 | /* SW Antenna Diversity. */ |
fd882783 | 2840 | if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE) |
c8d86be3 | 2841 | priv->EEPROMSwAntennaDiversity = false; |
c8d86be3 | 2842 | else |
c8d86be3 | 2843 | priv->EEPROMSwAntennaDiversity = true; |
fd882783 | 2844 | |
3f56c109 | 2845 | /* Default Antenna to use. */ |
fd882783 | 2846 | if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1) |
c8d86be3 | 2847 | priv->EEPROMDefaultAntenna1 = false; |
c8d86be3 | 2848 | else |
c8d86be3 | 2849 | priv->EEPROMDefaultAntenna1 = true; |
c8d86be3 | 2850 | |
3f56c109 | 2851 | if (priv->RegSwAntennaDiversityMechanism == 0) /* Auto */ |
fd882783 | 2852 | /* 0: default from EEPROM. */ |
c8d86be3 | 2853 | priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity; |
c8d86be3 | 2854 | else |
fd882783 | 2855 | /* 1:disable antenna diversity, 2: enable antenna diversity. */ |
bbfb5652 | 2856 | priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1) ? false : true); |
c8d86be3 | 2857 | |
fd882783 BZ |
2858 | if (priv->RegDefaultAntenna == 0) |
2859 | /* 0: default from EEPROM. */ | |
c8d86be3 | 2860 | priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1; |
c8d86be3 | 2861 | else |
fd882783 | 2862 | /* 1: main, 2: aux. */ |
bbfb5652 | 2863 | priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna == 2) ? true : false); |
fd882783 | 2864 | |
3f56c109 | 2865 | /* rtl8185 can calc plcp len in HW. */ |
c8d86be3 GKH |
2866 | priv->hw_plcp_len = 1; |
2867 | ||
2868 | priv->plcp_preamble_mode = 2; | |
3f56c109 | 2869 | /* the eeprom type is stored in RCR register bit #6 */ |
fd882783 | 2870 | if (RCR_9356SEL & read_nic_dword(dev, RCR)) |
bbfb5652 | 2871 | priv->epromtype = EPROM_93c56; |
fd882783 | 2872 | else |
bbfb5652 | 2873 | priv->epromtype = EPROM_93c46; |
c8d86be3 | 2874 | |
742821ce LF |
2875 | eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *) |
2876 | dev->dev_addr, 3); | |
c8d86be3 | 2877 | |
bbfb5652 | 2878 | for (i = 1, j = 0; i < 14; i += 2, j++) { |
742821ce | 2879 | eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word); |
bbfb5652 PS |
2880 | priv->chtxpwr[i] = word & 0xff; |
2881 | priv->chtxpwr[i+1] = (word & 0xff00)>>8; | |
c8d86be3 | 2882 | } |
d44eb889 | 2883 | for (i = 1, j = 0; i < 14; i += 2, j++) { |
742821ce | 2884 | eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word); |
d44eb889 | 2885 | priv->chtxpwr_ofdm[i] = word & 0xff; |
1994130e | 2886 | priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8; |
c8d86be3 | 2887 | } |
fd882783 | 2888 | |
1994130e | 2889 | /* 3Read crystal calibtration and thermal meter indication on 87SE. */ |
742821ce | 2890 | eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16); |
c8d86be3 | 2891 | |
1994130e LF |
2892 | /* Crystal calibration for Xin and Xout resp. */ |
2893 | priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; | |
2894 | priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4; | |
2895 | if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12) | |
2896 | priv->bXtalCalibration = true; | |
c8d86be3 | 2897 | |
1994130e LF |
2898 | /* Thermal meter reference indication. */ |
2899 | priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8); | |
2900 | if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13) | |
2901 | priv->bTxPowerTrack = true; | |
c8d86be3 | 2902 | |
742821ce | 2903 | eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word); |
c8d86be3 GKH |
2904 | priv->cck_txpwr_base = word & 0xf; |
2905 | priv->ofdm_txpwr_base = (word>>4) & 0xf; | |
c8d86be3 | 2906 | |
742821ce | 2907 | eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version); |
bbfb5652 | 2908 | DMESG("EEPROM version %x", version); |
d44eb889 | 2909 | priv->rcr_csense = 3; |
c8d86be3 | 2910 | |
742821ce LF |
2911 | eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val); |
2912 | priv->cs_treshold = (eeprom_val & 0xff00) >> 8; | |
c8d86be3 | 2913 | |
742821ce | 2914 | eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val); |
c8d86be3 GKH |
2915 | priv->rf_sleep = rtl8225z4_rf_sleep; |
2916 | priv->rf_wakeup = rtl8225z4_rf_wakeup; | |
c8d86be3 GKH |
2917 | DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!"); |
2918 | ||
2919 | priv->rf_close = rtl8225z2_rf_close; | |
2920 | priv->rf_init = rtl8225z2_rf_init; | |
2921 | priv->rf_set_chan = rtl8225z2_rf_set_chan; | |
2922 | priv->rf_set_sens = NULL; | |
c8d86be3 | 2923 | |
bbfb5652 | 2924 | if (0 != alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount)) |
c8d86be3 GKH |
2925 | return -ENOMEM; |
2926 | ||
bbfb5652 | 2927 | if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, |
c8d86be3 GKH |
2928 | TX_MANAGEPRIORITY_RING_ADDR)) |
2929 | return -ENOMEM; | |
2930 | ||
bbfb5652 | 2931 | if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, |
c8d86be3 GKH |
2932 | TX_BKPRIORITY_RING_ADDR)) |
2933 | return -ENOMEM; | |
2934 | ||
bbfb5652 | 2935 | if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, |
c8d86be3 GKH |
2936 | TX_BEPRIORITY_RING_ADDR)) |
2937 | return -ENOMEM; | |
2938 | ||
bbfb5652 | 2939 | if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, |
c8d86be3 GKH |
2940 | TX_VIPRIORITY_RING_ADDR)) |
2941 | return -ENOMEM; | |
2942 | ||
bbfb5652 | 2943 | if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, |
c8d86be3 GKH |
2944 | TX_VOPRIORITY_RING_ADDR)) |
2945 | return -ENOMEM; | |
2946 | ||
bbfb5652 | 2947 | if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, |
c8d86be3 GKH |
2948 | TX_HIGHPRIORITY_RING_ADDR)) |
2949 | return -ENOMEM; | |
2950 | ||
bbfb5652 | 2951 | if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount, |
c8d86be3 GKH |
2952 | TX_BEACON_RING_ADDR)) |
2953 | return -ENOMEM; | |
2954 | ||
bbfb5652 | 2955 | if (request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)) { |
cb73da25 JC |
2956 | DMESGE("Error allocating IRQ %d", dev->irq); |
2957 | return -1; | |
bbfb5652 PS |
2958 | } else { |
2959 | priv->irq = dev->irq; | |
2960 | DMESG("IRQ %d", dev->irq); | |
c8d86be3 GKH |
2961 | } |
2962 | ||
c8d86be3 | 2963 | return 0; |
c8d86be3 GKH |
2964 | } |
2965 | ||
c8d86be3 GKH |
2966 | void rtl8180_no_hw_wep(struct net_device *dev) |
2967 | { | |
c8d86be3 GKH |
2968 | } |
2969 | ||
c8d86be3 GKH |
2970 | void rtl8180_set_hw_wep(struct net_device *dev) |
2971 | { | |
2972 | struct r8180_priv *priv = ieee80211_priv(dev); | |
2973 | u8 pgreg; | |
2974 | u8 security; | |
2975 | u32 key0_word4; | |
2976 | ||
bbfb5652 PS |
2977 | pgreg = read_nic_byte(dev, PGSELECT); |
2978 | write_nic_byte(dev, PGSELECT, pgreg & ~(1<<PGSELECT_PG_SHIFT)); | |
c8d86be3 GKH |
2979 | |
2980 | key0_word4 = read_nic_dword(dev, KEY0+4+4+4); | |
bbfb5652 PS |
2981 | key0_word4 &= ~0xff; |
2982 | key0_word4 |= priv->key0[3] & 0xff; | |
2983 | write_nic_dword(dev, KEY0, (priv->key0[0])); | |
2984 | write_nic_dword(dev, KEY0+4, (priv->key0[1])); | |
2985 | write_nic_dword(dev, KEY0+4+4, (priv->key0[2])); | |
2986 | write_nic_dword(dev, KEY0+4+4+4, (key0_word4)); | |
2987 | ||
2988 | security = read_nic_byte(dev, SECURITY); | |
c8d86be3 GKH |
2989 | security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT); |
2990 | security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT); | |
bbfb5652 | 2991 | security &= ~SECURITY_ENCRYP_MASK; |
c8d86be3 GKH |
2992 | security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT); |
2993 | ||
2994 | write_nic_byte(dev, SECURITY, security); | |
2995 | ||
bbfb5652 PS |
2996 | DMESG("key %x %x %x %x", read_nic_dword(dev, KEY0+4+4+4), |
2997 | read_nic_dword(dev, KEY0+4+4), read_nic_dword(dev, KEY0+4), | |
2998 | read_nic_dword(dev, KEY0)); | |
c8d86be3 GKH |
2999 | } |
3000 | ||
3001 | ||
3002 | void rtl8185_rf_pins_enable(struct net_device *dev) | |
3003 | { | |
3f56c109 PS |
3004 | /* u16 tmp; */ |
3005 | /* tmp = read_nic_word(dev, RFPinsEnable); */ | |
3006 | write_nic_word(dev, RFPinsEnable, 0x1fff); /* | tmp); */ | |
c8d86be3 GKH |
3007 | } |
3008 | ||
c8d86be3 GKH |
3009 | void rtl8185_set_anaparam2(struct net_device *dev, u32 a) |
3010 | { | |
3011 | u8 conf3; | |
3012 | ||
3013 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); | |
3014 | ||
3015 | conf3 = read_nic_byte(dev, CONFIG3); | |
3016 | write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT)); | |
3017 | write_nic_dword(dev, ANAPARAM2, a); | |
3018 | ||
3019 | conf3 = read_nic_byte(dev, CONFIG3); | |
bbfb5652 | 3020 | write_nic_byte(dev, CONFIG3, conf3 & ~(1<<CONFIG3_ANAPARAM_W_SHIFT)); |
c8d86be3 | 3021 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); |
c8d86be3 GKH |
3022 | } |
3023 | ||
c8d86be3 GKH |
3024 | void rtl8180_set_anaparam(struct net_device *dev, u32 a) |
3025 | { | |
3026 | u8 conf3; | |
3027 | ||
3028 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); | |
3029 | ||
3030 | conf3 = read_nic_byte(dev, CONFIG3); | |
3031 | write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT)); | |
3032 | write_nic_dword(dev, ANAPARAM, a); | |
3033 | ||
3034 | conf3 = read_nic_byte(dev, CONFIG3); | |
bbfb5652 | 3035 | write_nic_byte(dev, CONFIG3, conf3 & ~(1<<CONFIG3_ANAPARAM_W_SHIFT)); |
c8d86be3 GKH |
3036 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); |
3037 | } | |
3038 | ||
c8d86be3 GKH |
3039 | void rtl8185_tx_antenna(struct net_device *dev, u8 ant) |
3040 | { | |
3041 | write_nic_byte(dev, TX_ANTENNA, ant); | |
3042 | force_pci_posting(dev); | |
3043 | mdelay(1); | |
3044 | } | |
3045 | ||
c8d86be3 GKH |
3046 | void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data) |
3047 | { | |
c8d86be3 | 3048 | u32 phyw; |
c8d86be3 GKH |
3049 | |
3050 | adr |= 0x80; | |
3051 | ||
bbfb5652 | 3052 | phyw = ((data<<8) | adr); |
c8d86be3 | 3053 | |
3f56c109 | 3054 | /* Note that, we must write 0xff7c after 0x7d-0x7f to write BB register. */ |
c8d86be3 GKH |
3055 | write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24)); |
3056 | write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16)); | |
3057 | write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8)); | |
bbfb5652 | 3058 | write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff))); |
5521a513 | 3059 | |
c8d86be3 GKH |
3060 | /* this is ok to fail when we write AGC table. check for AGC table might be |
3061 | * done by masking with 0x7f instead of 0xff | |
3062 | */ | |
3f56c109 | 3063 | /* if (phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data, adr); */ |
c8d86be3 GKH |
3064 | } |
3065 | ||
bbfb5652 | 3066 | inline void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data) |
c8d86be3 GKH |
3067 | { |
3068 | data = data & 0xff; | |
3069 | rtl8185_write_phy(dev, adr, data); | |
3070 | } | |
3071 | ||
bbfb5652 | 3072 | void write_phy_cck(struct net_device *dev, u8 adr, u32 data) |
c8d86be3 GKH |
3073 | { |
3074 | data = data & 0xff; | |
3075 | rtl8185_write_phy(dev, adr, data | 0x10000); | |
3076 | } | |
3077 | ||
c8d86be3 GKH |
3078 | void rtl8185_set_rate(struct net_device *dev) |
3079 | { | |
3080 | int i; | |
3081 | u16 word; | |
bbfb5652 | 3082 | int basic_rate, min_rr_rate, max_rr_rate; |
c8d86be3 | 3083 | |
c8d86be3 GKH |
3084 | basic_rate = ieeerate2rtlrate(240); |
3085 | min_rr_rate = ieeerate2rtlrate(60); | |
3086 | max_rr_rate = ieeerate2rtlrate(240); | |
3087 | ||
c8d86be3 | 3088 | write_nic_byte(dev, RESP_RATE, |
bbfb5652 | 3089 | max_rr_rate<<MAX_RESP_RATE_SHIFT | min_rr_rate<<MIN_RESP_RATE_SHIFT); |
c8d86be3 GKH |
3090 | |
3091 | word = read_nic_word(dev, BRSR); | |
3092 | word &= ~BRSR_MBR_8185; | |
3093 | ||
bbfb5652 | 3094 | for (i = 0; i <= basic_rate; i++) |
c8d86be3 GKH |
3095 | word |= (1<<i); |
3096 | ||
3097 | write_nic_word(dev, BRSR, word); | |
c8d86be3 GKH |
3098 | } |
3099 | ||
c8d86be3 GKH |
3100 | void rtl8180_adapter_start(struct net_device *dev) |
3101 | { | |
cb73da25 | 3102 | struct r8180_priv *priv = ieee80211_priv(dev); |
c8d86be3 GKH |
3103 | |
3104 | rtl8180_rtx_disable(dev); | |
3105 | rtl8180_reset(dev); | |
3106 | ||
c8d86be3 GKH |
3107 | /* enable beacon timeout, beacon TX ok and err |
3108 | * LP tx ok and err, HP TX ok and err, NP TX ok and err, | |
3f56c109 PS |
3109 | * RX ok and ERR, and GP timer |
3110 | */ | |
c8d86be3 GKH |
3111 | priv->irq_mask = 0x6fcf; |
3112 | ||
3113 | priv->dma_poll_mask = 0; | |
3114 | ||
3115 | rtl8180_beacon_tx_disable(dev); | |
3116 | ||
c8d86be3 | 3117 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
bbfb5652 PS |
3118 | write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]); |
3119 | write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff); | |
c8d86be3 GKH |
3120 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); |
3121 | ||
3122 | rtl8180_update_msr(dev); | |
3123 | ||
c8d86be3 GKH |
3124 | /* These might be unnecessary since we do in rx_enable / tx_enable */ |
3125 | fix_rx_fifo(dev); | |
3126 | fix_tx_fifo(dev); | |
c8d86be3 GKH |
3127 | |
3128 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); | |
3129 | ||
3130 | /* | |
3f56c109 PS |
3131 | * The following is very strange. seems to be that 1 means test mode, |
3132 | * but we need to acknolwledges the nic when a packet is ready | |
3133 | * although we set it to 0 | |
3134 | */ | |
c8d86be3 GKH |
3135 | |
3136 | write_nic_byte(dev, | |
bbfb5652 | 3137 | CONFIG2, read_nic_byte(dev, CONFIG2) & ~\ |
c8d86be3 | 3138 | (1<<CONFIG2_DMA_POLLING_MODE_SHIFT)); |
3f56c109 | 3139 | /* ^the nic isn't in test mode */ |
d44eb889 | 3140 | write_nic_byte(dev, |
bbfb5652 | 3141 | CONFIG2, read_nic_byte(dev, CONFIG2)|(1<<4)); |
c8d86be3 | 3142 | |
bbfb5652 | 3143 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); |
c8d86be3 | 3144 | |
bbfb5652 | 3145 | write_nic_dword(dev, INT_TIMEOUT, 0); |
c8d86be3 | 3146 | |
d44eb889 | 3147 | write_nic_byte(dev, WPA_CONFIG, 0); |
c8d86be3 GKH |
3148 | |
3149 | rtl8180_no_hw_wep(dev); | |
3150 | ||
d44eb889 LF |
3151 | rtl8185_set_rate(dev); |
3152 | write_nic_byte(dev, RATE_FALLBACK, 0x81); | |
c8d86be3 | 3153 | |
d44eb889 | 3154 | write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6)); |
c8d86be3 | 3155 | |
3f56c109 | 3156 | /* FIXME cfg 3 ClkRun enable - isn't it ReadOnly ? */ |
d44eb889 LF |
3157 | rtl8180_set_mode(dev, EPROM_CMD_CONFIG); |
3158 | write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | |
3159 | | (1 << CONFIG3_CLKRUN_SHIFT)); | |
3160 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); | |
c8d86be3 GKH |
3161 | |
3162 | priv->rf_init(dev); | |
3163 | ||
bbfb5652 PS |
3164 | if (priv->rf_set_sens != NULL) |
3165 | priv->rf_set_sens(dev, priv->sens); | |
c8d86be3 GKH |
3166 | rtl8180_irq_enable(dev); |
3167 | ||
3168 | netif_start_queue(dev); | |
c8d86be3 GKH |
3169 | } |
3170 | ||
3f56c109 PS |
3171 | /* |
3172 | * This configures registers for beacon tx and enables it via | |
c8d86be3 GKH |
3173 | * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might |
3174 | * be used to stop beacon transmission | |
3175 | */ | |
3176 | void rtl8180_start_tx_beacon(struct net_device *dev) | |
3177 | { | |
c8d86be3 | 3178 | u16 word; |
c8d86be3 GKH |
3179 | |
3180 | DMESG("Enabling beacon TX"); | |
c8d86be3 GKH |
3181 | rtl8180_prepare_beacon(dev); |
3182 | rtl8180_irq_disable(dev); | |
3183 | rtl8180_beacon_tx_enable(dev); | |
c8d86be3 | 3184 | |
bbfb5652 | 3185 | word = read_nic_word(dev, AtimWnd) & ~AtimWnd_AtimWnd; |
3f56c109 | 3186 | write_nic_word(dev, AtimWnd, word); /* word |= */ |
c8d86be3 GKH |
3187 | |
3188 | word = read_nic_word(dev, BintrItv); | |
3189 | word &= ~BintrItv_BintrItv; | |
3f56c109 | 3190 | word |= 1000; /* priv->ieee80211->current_network.beacon_interval * |
c8d86be3 GKH |
3191 | ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1); |
3192 | // FIXME: check if correct ^^ worked with 0x3e8; | |
3193 | */ | |
3194 | write_nic_word(dev, BintrItv, word); | |
3195 | ||
c8d86be3 GKH |
3196 | rtl8180_set_mode(dev, EPROM_CMD_NORMAL); |
3197 | ||
cb73da25 | 3198 | rtl8185b_irq_enable(dev); |
c8d86be3 GKH |
3199 | } |
3200 | ||
c8d86be3 GKH |
3201 | static struct net_device_stats *rtl8180_stats(struct net_device *dev) |
3202 | { | |
3203 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3204 | ||
3205 | return &priv->ieee80211->stats; | |
3206 | } | |
3f56c109 PS |
3207 | |
3208 | /* | |
3209 | * Change current and default preamble mode. | |
3210 | */ | |
c8d86be3 GKH |
3211 | bool |
3212 | MgntActSet_802_11_PowerSaveMode( | |
3213 | struct r8180_priv *priv, | |
3214 | RT_PS_MODE rtPsMode | |
3215 | ) | |
3216 | { | |
3f56c109 | 3217 | /* Currently, we do not change power save mode on IBSS mode. */ |
bbfb5652 | 3218 | if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) |
c8d86be3 | 3219 | return false; |
c8d86be3 | 3220 | |
c8d86be3 | 3221 | priv->ieee80211->ps = rtPsMode; |
5521a513 | 3222 | |
c8d86be3 GKH |
3223 | return true; |
3224 | } | |
3225 | ||
fd882783 | 3226 | void LeisurePSEnter(struct r8180_priv *priv) |
c8d86be3 | 3227 | { |
fd882783 | 3228 | if (priv->bLeisurePs) { |
c8d86be3 | 3229 | if (priv->ieee80211->ps == IEEE80211_PS_DISABLED) |
3f56c109 | 3230 | MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST); /* IEEE80211_PS_ENABLE */ |
c8d86be3 GKH |
3231 | } |
3232 | } | |
3233 | ||
fd882783 | 3234 | void LeisurePSLeave(struct r8180_priv *priv) |
c8d86be3 | 3235 | { |
fd882783 | 3236 | if (priv->bLeisurePs) { |
c8d86be3 | 3237 | if (priv->ieee80211->ps != IEEE80211_PS_DISABLED) |
c8d86be3 | 3238 | MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED); |
c8d86be3 GKH |
3239 | } |
3240 | } | |
0370453f | 3241 | |
bbfb5652 | 3242 | void rtl8180_hw_wakeup_wq(struct work_struct *work) |
c8d86be3 | 3243 | { |
bf6aede7 | 3244 | struct delayed_work *dwork = to_delayed_work(work); |
bbfb5652 | 3245 | struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, hw_wakeup_wq); |
c8d86be3 | 3246 | struct net_device *dev = ieee->dev; |
c8d86be3 | 3247 | |
c8d86be3 | 3248 | rtl8180_hw_wakeup(dev); |
c8d86be3 GKH |
3249 | } |
3250 | ||
bbfb5652 | 3251 | void rtl8180_hw_sleep_wq(struct work_struct *work) |
c8d86be3 | 3252 | { |
bf6aede7 | 3253 | struct delayed_work *dwork = to_delayed_work(work); |
bbfb5652 | 3254 | struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, hw_sleep_wq); |
cb73da25 | 3255 | struct net_device *dev = ieee->dev; |
c8d86be3 | 3256 | |
cb73da25 | 3257 | rtl8180_hw_sleep_down(dev); |
c8d86be3 GKH |
3258 | } |
3259 | ||
bbfb5652 | 3260 | static void MgntLinkKeepAlive(struct r8180_priv *priv) |
c8d86be3 GKH |
3261 | { |
3262 | if (priv->keepAliveLevel == 0) | |
3263 | return; | |
3264 | ||
bbfb5652 | 3265 | if (priv->ieee80211->state == IEEE80211_LINKED) { |
3f56c109 PS |
3266 | /* |
3267 | * Keep-Alive. | |
3268 | */ | |
c8d86be3 | 3269 | |
bbfb5652 | 3270 | if ((priv->keepAliveLevel == 2) || |
c8d86be3 | 3271 | (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast && |
bbfb5652 PS |
3272 | priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast) |
3273 | ) { | |
c8d86be3 GKH |
3274 | priv->link_detect.IdleCount++; |
3275 | ||
3f56c109 PS |
3276 | /* |
3277 | * Send a Keep-Alive packet packet to AP if we had been idle for a while. | |
3278 | */ | |
bbfb5652 | 3279 | if (priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1)) { |
c8d86be3 GKH |
3280 | priv->link_detect.IdleCount = 0; |
3281 | ieee80211_sta_ps_send_null_frame(priv->ieee80211, false); | |
3282 | } | |
bbfb5652 | 3283 | } else { |
c8d86be3 GKH |
3284 | priv->link_detect.IdleCount = 0; |
3285 | } | |
3286 | priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast; | |
3287 | priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast; | |
3288 | } | |
3289 | } | |
c8d86be3 GKH |
3290 | |
3291 | static u8 read_acadapter_file(char *filename); | |
fd882783 | 3292 | |
c8d86be3 GKH |
3293 | void rtl8180_watch_dog(struct net_device *dev) |
3294 | { | |
3295 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3296 | bool bEnterPS = false; | |
3297 | bool bBusyTraffic = false; | |
3298 | u32 TotalRxNum = 0; | |
3299 | u16 SlotIndex = 0; | |
3300 | u16 i = 0; | |
bbfb5652 PS |
3301 | if (priv->ieee80211->actscanning == false) { |
3302 | if ((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)) | |
c8d86be3 | 3303 | IPSEnter(dev); |
c8d86be3 | 3304 | } |
3f56c109 | 3305 | /* YJ,add,080828,for link state check */ |
bbfb5652 | 3306 | if ((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)) { |
c8d86be3 GKH |
3307 | SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum; |
3308 | priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod; | |
bbfb5652 PS |
3309 | for (i = 0; i < priv->link_detect.SlotNum; i++) |
3310 | TotalRxNum += priv->link_detect.RxFrameNum[i]; | |
fd882783 | 3311 | |
bbfb5652 | 3312 | if (TotalRxNum == 0) { |
c8d86be3 GKH |
3313 | priv->ieee80211->state = IEEE80211_ASSOCIATING; |
3314 | queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq); | |
3315 | } | |
3316 | } | |
3317 | ||
3f56c109 | 3318 | /* YJ,add,080828,for KeepAlive */ |
c8d86be3 GKH |
3319 | MgntLinkKeepAlive(priv); |
3320 | ||
3f56c109 | 3321 | /* YJ,add,080828,for LPS */ |
fd882783 | 3322 | if (priv->PowerProfile == POWER_PROFILE_BATTERY) |
c8d86be3 | 3323 | priv->bLeisurePs = true; |
fd882783 | 3324 | else if (priv->PowerProfile == POWER_PROFILE_AC) { |
c8d86be3 | 3325 | LeisurePSLeave(priv); |
bbfb5652 | 3326 | priv->bLeisurePs = false; |
c8d86be3 | 3327 | } |
c8d86be3 | 3328 | |
bbfb5652 | 3329 | if (priv->ieee80211->state == IEEE80211_LINKED) { |
c8d86be3 | 3330 | priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod; |
bbfb5652 PS |
3331 | if (priv->link_detect.NumRxOkInPeriod > 666 || |
3332 | priv->link_detect.NumTxOkInPeriod > 666) { | |
c8d86be3 GKH |
3333 | bBusyTraffic = true; |
3334 | } | |
bbfb5652 | 3335 | if (((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8) |
c8d86be3 | 3336 | || (priv->link_detect.NumRxOkInPeriod > 2)) { |
bbfb5652 | 3337 | bEnterPS = false; |
fd882783 | 3338 | } else |
bbfb5652 | 3339 | bEnterPS = true; |
c8d86be3 | 3340 | |
fd882783 | 3341 | if (bEnterPS) |
c8d86be3 | 3342 | LeisurePSEnter(priv); |
fd882783 | 3343 | else |
c8d86be3 | 3344 | LeisurePSLeave(priv); |
fd882783 | 3345 | } else |
c8d86be3 | 3346 | LeisurePSLeave(priv); |
c8d86be3 GKH |
3347 | priv->link_detect.bBusyTraffic = bBusyTraffic; |
3348 | priv->link_detect.NumRxOkInPeriod = 0; | |
3349 | priv->link_detect.NumTxOkInPeriod = 0; | |
3350 | priv->ieee80211->NumRxDataInPeriod = 0; | |
3351 | priv->ieee80211->NumRxBcnInPeriod = 0; | |
c8d86be3 | 3352 | } |
fd882783 | 3353 | |
c8d86be3 GKH |
3354 | int _rtl8180_up(struct net_device *dev) |
3355 | { | |
3356 | struct r8180_priv *priv = ieee80211_priv(dev); | |
c8d86be3 | 3357 | |
bbfb5652 | 3358 | priv->up = 1; |
c8d86be3 GKH |
3359 | |
3360 | DMESG("Bringing up iface"); | |
c8d86be3 GKH |
3361 | rtl8185b_adapter_start(dev); |
3362 | rtl8185b_rx_enable(dev); | |
3363 | rtl8185b_tx_enable(dev); | |
bbfb5652 PS |
3364 | if (priv->bInactivePs) { |
3365 | if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) | |
c8d86be3 GKH |
3366 | IPSLeave(dev); |
3367 | } | |
bbfb5652 | 3368 | timer_rate_adaptive((unsigned long)dev); |
c8d86be3 | 3369 | watch_dog_adaptive((unsigned long)dev); |
cb73da25 | 3370 | if (priv->bSwAntennaDiverity) |
c8d86be3 | 3371 | SwAntennaDiversityTimerCallback(dev); |
c8d86be3 | 3372 | ieee80211_softmac_start_protocol(priv->ieee80211); |
c8d86be3 GKH |
3373 | return 0; |
3374 | } | |
3375 | ||
c8d86be3 GKH |
3376 | int rtl8180_open(struct net_device *dev) |
3377 | { | |
3378 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3379 | int ret; | |
3380 | ||
3381 | down(&priv->wx_sem); | |
3382 | ret = rtl8180_up(dev); | |
3383 | up(&priv->wx_sem); | |
3384 | return ret; | |
c8d86be3 GKH |
3385 | } |
3386 | ||
c8d86be3 GKH |
3387 | int rtl8180_up(struct net_device *dev) |
3388 | { | |
3389 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3390 | ||
bbfb5652 PS |
3391 | if (priv->up == 1) |
3392 | return -1; | |
c8d86be3 GKH |
3393 | |
3394 | return _rtl8180_up(dev); | |
3395 | } | |
3396 | ||
c8d86be3 GKH |
3397 | int rtl8180_close(struct net_device *dev) |
3398 | { | |
3399 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3400 | int ret; | |
3401 | ||
3402 | down(&priv->wx_sem); | |
3403 | ret = rtl8180_down(dev); | |
3404 | up(&priv->wx_sem); | |
3405 | ||
3406 | return ret; | |
c8d86be3 GKH |
3407 | } |
3408 | ||
3409 | int rtl8180_down(struct net_device *dev) | |
3410 | { | |
3411 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3412 | ||
fd882783 BZ |
3413 | if (priv->up == 0) |
3414 | return -1; | |
c8d86be3 | 3415 | |
bbfb5652 | 3416 | priv->up = 0; |
c8d86be3 GKH |
3417 | |
3418 | ieee80211_softmac_stop_protocol(priv->ieee80211); | |
3419 | /* FIXME */ | |
3420 | if (!netif_queue_stopped(dev)) | |
3421 | netif_stop_queue(dev); | |
3422 | rtl8180_rtx_disable(dev); | |
3423 | rtl8180_irq_disable(dev); | |
3424 | del_timer_sync(&priv->watch_dog_timer); | |
fd882783 BZ |
3425 | del_timer_sync(&priv->rateadapter_timer); |
3426 | cancel_delayed_work(&priv->ieee80211->rate_adapter_wq); | |
c8d86be3 GKH |
3427 | cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); |
3428 | cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); | |
3429 | cancel_delayed_work(&priv->ieee80211->hw_dig_wq); | |
3430 | cancel_delayed_work(&priv->ieee80211->tx_pw_wq); | |
3431 | del_timer_sync(&priv->SwAntennaDiversityTimer); | |
bbfb5652 PS |
3432 | SetZebraRFPowerState8185(dev, eRfOff); |
3433 | memset(&(priv->ieee80211->current_network), 0, sizeof(struct ieee80211_network)); | |
c8d86be3 GKH |
3434 | priv->ieee80211->state = IEEE80211_NOLINK; |
3435 | return 0; | |
3436 | } | |
3437 | ||
c8d86be3 GKH |
3438 | void rtl8180_restart_wq(struct work_struct *work) |
3439 | { | |
3440 | struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq); | |
3441 | struct net_device *dev = priv->dev; | |
0370453f | 3442 | |
c8d86be3 GKH |
3443 | down(&priv->wx_sem); |
3444 | ||
3445 | rtl8180_commit(dev); | |
3446 | ||
3447 | up(&priv->wx_sem); | |
3448 | } | |
3449 | ||
3450 | void rtl8180_restart(struct net_device *dev) | |
3451 | { | |
3452 | struct r8180_priv *priv = ieee80211_priv(dev); | |
fd882783 | 3453 | |
c8d86be3 | 3454 | schedule_work(&priv->reset_wq); |
c8d86be3 GKH |
3455 | } |
3456 | ||
c8d86be3 GKH |
3457 | void rtl8180_commit(struct net_device *dev) |
3458 | { | |
3459 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3460 | ||
fd882783 BZ |
3461 | if (priv->up == 0) |
3462 | return ; | |
3463 | ||
c8d86be3 | 3464 | del_timer_sync(&priv->watch_dog_timer); |
fd882783 BZ |
3465 | del_timer_sync(&priv->rateadapter_timer); |
3466 | cancel_delayed_work(&priv->ieee80211->rate_adapter_wq); | |
c8d86be3 GKH |
3467 | cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); |
3468 | cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); | |
3469 | cancel_delayed_work(&priv->ieee80211->hw_dig_wq); | |
3470 | cancel_delayed_work(&priv->ieee80211->tx_pw_wq); | |
3471 | del_timer_sync(&priv->SwAntennaDiversityTimer); | |
3472 | ieee80211_softmac_stop_protocol(priv->ieee80211); | |
3473 | rtl8180_irq_disable(dev); | |
3474 | rtl8180_rtx_disable(dev); | |
3475 | _rtl8180_up(dev); | |
3476 | } | |
3477 | ||
c8d86be3 GKH |
3478 | static void r8180_set_multicast(struct net_device *dev) |
3479 | { | |
3480 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3481 | short promisc; | |
3482 | ||
bbfb5652 | 3483 | promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; |
c8d86be3 GKH |
3484 | |
3485 | if (promisc != priv->promisc) | |
3486 | rtl8180_restart(dev); | |
3487 | ||
3488 | priv->promisc = promisc; | |
c8d86be3 GKH |
3489 | } |
3490 | ||
c8d86be3 GKH |
3491 | int r8180_set_mac_adr(struct net_device *dev, void *mac) |
3492 | { | |
3493 | struct r8180_priv *priv = ieee80211_priv(dev); | |
3494 | struct sockaddr *addr = mac; | |
3495 | ||
3496 | down(&priv->wx_sem); | |
3497 | ||
3498 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
3499 | ||
bbfb5652 | 3500 | if (priv->ieee80211->iw_mode == IW_MODE_MASTER) |
c8d86be3 GKH |
3501 | memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN); |
3502 | ||
3503 | if (priv->up) { | |
3504 | rtl8180_down(dev); | |
3505 | rtl8180_up(dev); | |
3506 | } | |
3507 | ||
3508 | up(&priv->wx_sem); | |
3509 | ||
3510 | return 0; | |
3511 | } | |
3512 | ||
3513 | /* based on ipw2200 driver */ | |
3514 | int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
3515 | { | |
3516 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
c8d86be3 | 3517 | struct iwreq *wrq = (struct iwreq *) rq; |
bbfb5652 | 3518 | int ret = -1; |
fd882783 | 3519 | |
c8d86be3 | 3520 | switch (cmd) { |
fd882783 | 3521 | case RTL_IOCTL_WPA_SUPPLICANT: |
c8d86be3 GKH |
3522 | ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data); |
3523 | return ret; | |
fd882783 | 3524 | default: |
c8d86be3 GKH |
3525 | return -EOPNOTSUPP; |
3526 | } | |
3527 | ||
3528 | return -EOPNOTSUPP; | |
3529 | } | |
3530 | ||
727ae303 AB |
3531 | static const struct net_device_ops rtl8180_netdev_ops = { |
3532 | .ndo_open = rtl8180_open, | |
3533 | .ndo_stop = rtl8180_close, | |
3534 | .ndo_get_stats = rtl8180_stats, | |
3535 | .ndo_tx_timeout = rtl8180_restart, | |
3536 | .ndo_do_ioctl = rtl8180_ioctl, | |
3537 | .ndo_set_multicast_list = r8180_set_multicast, | |
3538 | .ndo_set_mac_address = r8180_set_mac_adr, | |
3539 | .ndo_validate_addr = eth_validate_addr, | |
3540 | .ndo_change_mtu = eth_change_mtu, | |
df574b8e | 3541 | .ndo_start_xmit = ieee80211_rtl_xmit, |
727ae303 | 3542 | }; |
c8d86be3 GKH |
3543 | |
3544 | static int __devinit rtl8180_pci_probe(struct pci_dev *pdev, | |
3545 | const struct pci_device_id *id) | |
3546 | { | |
3547 | unsigned long ioaddr = 0; | |
3548 | struct net_device *dev = NULL; | |
bbfb5652 | 3549 | struct r8180_priv *priv = NULL; |
c8d86be3 | 3550 | u8 unit = 0; |
beef9697 | 3551 | int ret = -ENODEV; |
c8d86be3 | 3552 | |
c8d86be3 | 3553 | unsigned long pmem_start, pmem_len, pmem_flags; |
c8d86be3 GKH |
3554 | |
3555 | DMESG("Configuring chip resources"); | |
3556 | ||
bbfb5652 | 3557 | if (pci_enable_device(pdev)) { |
c8d86be3 GKH |
3558 | DMESG("Failed to enable PCI device"); |
3559 | return -EIO; | |
3560 | } | |
3561 | ||
3562 | pci_set_master(pdev); | |
c8d86be3 | 3563 | pci_set_dma_mask(pdev, 0xffffff00ULL); |
bbfb5652 | 3564 | pci_set_consistent_dma_mask(pdev, 0xffffff00ULL); |
c8d86be3 | 3565 | dev = alloc_ieee80211(sizeof(struct r8180_priv)); |
beef9697 KV |
3566 | if (!dev) { |
3567 | ret = -ENOMEM; | |
3568 | goto fail_free; | |
3569 | } | |
c8d86be3 GKH |
3570 | priv = ieee80211_priv(dev); |
3571 | priv->ieee80211 = netdev_priv(dev); | |
3572 | ||
c8d86be3 GKH |
3573 | pci_set_drvdata(pdev, dev); |
3574 | SET_NETDEV_DEV(dev, &pdev->dev); | |
3575 | ||
3576 | priv = ieee80211_priv(dev); | |
fd882783 | 3577 | priv->pdev = pdev; |
c8d86be3 GKH |
3578 | |
3579 | pmem_start = pci_resource_start(pdev, 1); | |
3580 | pmem_len = pci_resource_len(pdev, 1); | |
bbfb5652 | 3581 | pmem_flags = pci_resource_flags(pdev, 1); |
c8d86be3 GKH |
3582 | |
3583 | if (!(pmem_flags & IORESOURCE_MEM)) { | |
3584 | DMESG("region #1 not a MMIO resource, aborting"); | |
3585 | goto fail; | |
3586 | } | |
3587 | ||
bbfb5652 | 3588 | if (!request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) { |
c8d86be3 GKH |
3589 | DMESG("request_mem_region failed!"); |
3590 | goto fail; | |
3591 | } | |
3592 | ||
bbfb5652 PS |
3593 | ioaddr = (unsigned long)ioremap_nocache(pmem_start, pmem_len); |
3594 | if (ioaddr == (unsigned long)NULL) { | |
c8d86be3 | 3595 | DMESG("ioremap failed!"); |
c8d86be3 GKH |
3596 | goto fail1; |
3597 | } | |
3598 | ||
3f56c109 PS |
3599 | dev->mem_start = ioaddr; /* shared mem start */ |
3600 | dev->mem_end = ioaddr + pci_resource_len(pdev, 0); /* shared mem end */ | |
c8d86be3 | 3601 | |
c8d86be3 GKH |
3602 | pci_read_config_byte(pdev, 0x05, &unit); |
3603 | pci_write_config_byte(pdev, 0x05, unit & (~0x04)); | |
c8d86be3 GKH |
3604 | |
3605 | dev->irq = pdev->irq; | |
3606 | priv->irq = 0; | |
3607 | ||
727ae303 | 3608 | dev->netdev_ops = &rtl8180_netdev_ops; |
c8d86be3 | 3609 | dev->wireless_handlers = &r8180_wx_handlers_def; |
c8d86be3 | 3610 | |
bbfb5652 | 3611 | dev->type = ARPHRD_ETHER; |
1994130e | 3612 | dev->watchdog_timeo = HZ*3; |
c8d86be3 | 3613 | |
bbfb5652 | 3614 | if (dev_alloc_name(dev, ifname) < 0) { |
cb73da25 | 3615 | DMESG("Oops: devname already taken! Trying wlan%%d...\n"); |
dca41306 | 3616 | strcpy(ifname, "wlan%d"); |
c8d86be3 | 3617 | dev_alloc_name(dev, ifname); |
cb73da25 | 3618 | } |
c8d86be3 | 3619 | |
bbfb5652 | 3620 | if (rtl8180_init(dev) != 0) { |
c8d86be3 GKH |
3621 | DMESG("Initialization failed"); |
3622 | goto fail1; | |
3623 | } | |
3624 | ||
3625 | netif_carrier_off(dev); | |
3626 | ||
3627 | register_netdev(dev); | |
3628 | ||
3629 | rtl8180_proc_init_one(dev); | |
3630 | ||
3631 | DMESG("Driver probe completed\n"); | |
3632 | return 0; | |
c8d86be3 | 3633 | fail1: |
bbfb5652 PS |
3634 | if (dev->mem_start != (unsigned long)NULL) { |
3635 | iounmap((void *)dev->mem_start); | |
3636 | release_mem_region(pci_resource_start(pdev, 1), | |
3637 | pci_resource_len(pdev, 1)); | |
c8d86be3 | 3638 | } |
c8d86be3 | 3639 | fail: |
bbfb5652 | 3640 | if (dev) { |
c8d86be3 GKH |
3641 | if (priv->irq) { |
3642 | free_irq(dev->irq, dev); | |
bbfb5652 | 3643 | dev->irq = 0; |
c8d86be3 GKH |
3644 | } |
3645 | free_ieee80211(dev); | |
3646 | } | |
3647 | ||
beef9697 | 3648 | fail_free: |
c8d86be3 GKH |
3649 | pci_disable_device(pdev); |
3650 | ||
3651 | DMESG("wlan driver load failed\n"); | |
3652 | pci_set_drvdata(pdev, NULL); | |
beef9697 | 3653 | return ret; |
c8d86be3 GKH |
3654 | } |
3655 | ||
c8d86be3 GKH |
3656 | static void __devexit rtl8180_pci_remove(struct pci_dev *pdev) |
3657 | { | |
3658 | struct r8180_priv *priv; | |
3659 | struct net_device *dev = pci_get_drvdata(pdev); | |
c8d86be3 | 3660 | |
fd882783 | 3661 | if (dev) { |
c8d86be3 GKH |
3662 | unregister_netdev(dev); |
3663 | ||
fd882783 | 3664 | priv = ieee80211_priv(dev); |
c8d86be3 GKH |
3665 | |
3666 | rtl8180_proc_remove_one(dev); | |
3667 | rtl8180_down(dev); | |
3668 | priv->rf_close(dev); | |
3669 | rtl8180_reset(dev); | |
c8d86be3 | 3670 | mdelay(10); |
c8d86be3 | 3671 | |
bbfb5652 PS |
3672 | if (priv->irq) { |
3673 | DMESG("Freeing irq %d", dev->irq); | |
c8d86be3 | 3674 | free_irq(dev->irq, dev); |
bbfb5652 | 3675 | priv->irq = 0; |
c8d86be3 GKH |
3676 | } |
3677 | ||
3678 | free_rx_desc_ring(dev); | |
3679 | free_tx_desc_rings(dev); | |
c8d86be3 | 3680 | |
bbfb5652 PS |
3681 | if (dev->mem_start != (unsigned long)NULL) { |
3682 | iounmap((void *)dev->mem_start); | |
3683 | release_mem_region(pci_resource_start(pdev, 1), | |
3684 | pci_resource_len(pdev, 1)); | |
c8d86be3 | 3685 | } |
c8d86be3 GKH |
3686 | |
3687 | free_ieee80211(dev); | |
3688 | } | |
3689 | pci_disable_device(pdev); | |
3690 | ||
3691 | DMESG("wlan driver removed\n"); | |
3692 | } | |
3693 | ||
c8d86be3 GKH |
3694 | /* fun with the built-in ieee80211 stack... */ |
3695 | extern int ieee80211_crypto_init(void); | |
3696 | extern void ieee80211_crypto_deinit(void); | |
3697 | extern int ieee80211_crypto_tkip_init(void); | |
3698 | extern void ieee80211_crypto_tkip_exit(void); | |
3699 | extern int ieee80211_crypto_ccmp_init(void); | |
3700 | extern void ieee80211_crypto_ccmp_exit(void); | |
3701 | extern int ieee80211_crypto_wep_init(void); | |
3702 | extern void ieee80211_crypto_wep_exit(void); | |
3703 | ||
3704 | static int __init rtl8180_pci_module_init(void) | |
3705 | { | |
3706 | int ret; | |
3707 | ||
3708 | ret = ieee80211_crypto_init(); | |
3709 | if (ret) { | |
3710 | printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret); | |
3711 | return ret; | |
3712 | } | |
3713 | ret = ieee80211_crypto_tkip_init(); | |
3714 | if (ret) { | |
3715 | printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret); | |
3716 | return ret; | |
3717 | } | |
3718 | ret = ieee80211_crypto_ccmp_init(); | |
3719 | if (ret) { | |
3720 | printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret); | |
3721 | return ret; | |
3722 | } | |
3723 | ret = ieee80211_crypto_wep_init(); | |
3724 | if (ret) { | |
3725 | printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret); | |
3726 | return ret; | |
3727 | } | |
3728 | ||
bc568942 | 3729 | printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n"); |
c8d86be3 GKH |
3730 | printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n"); |
3731 | DMESG("Initializing module"); | |
3732 | DMESG("Wireless extensions version %d", WIRELESS_EXT); | |
3733 | rtl8180_proc_module_init(); | |
3734 | ||
fd882783 | 3735 | if (pci_register_driver(&rtl8180_pci_driver)) { |
c8d86be3 | 3736 | DMESG("No device found"); |
c8d86be3 GKH |
3737 | return -ENODEV; |
3738 | } | |
3739 | return 0; | |
3740 | } | |
3741 | ||
c8d86be3 GKH |
3742 | static void __exit rtl8180_pci_module_exit(void) |
3743 | { | |
bbfb5652 | 3744 | pci_unregister_driver(&rtl8180_pci_driver); |
c8d86be3 | 3745 | rtl8180_proc_module_remove(); |
c8d86be3 GKH |
3746 | ieee80211_crypto_tkip_exit(); |
3747 | ieee80211_crypto_ccmp_exit(); | |
3748 | ieee80211_crypto_wep_exit(); | |
096c55d1 | 3749 | ieee80211_crypto_deinit(); |
c8d86be3 GKH |
3750 | DMESG("Exiting"); |
3751 | } | |
3752 | ||
c8d86be3 GKH |
3753 | void rtl8180_try_wake_queue(struct net_device *dev, int pri) |
3754 | { | |
3755 | unsigned long flags; | |
3756 | short enough_desc; | |
3757 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
3758 | ||
bbfb5652 PS |
3759 | spin_lock_irqsave(&priv->tx_lock, flags); |
3760 | enough_desc = check_nic_enought_desc(dev, pri); | |
3761 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
c8d86be3 | 3762 | |
bbfb5652 | 3763 | if (enough_desc) |
df574b8e | 3764 | ieee80211_rtl_wake_queue(priv->ieee80211); |
c8d86be3 GKH |
3765 | } |
3766 | ||
bbfb5652 | 3767 | void rtl8180_tx_isr(struct net_device *dev, int pri, short error) |
c8d86be3 GKH |
3768 | { |
3769 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
3f56c109 PS |
3770 | u32 *tail; /* tail virtual addr */ |
3771 | u32 *head; /* head virtual addr */ | |
3772 | u32 *begin; /* start of ring virtual addr */ | |
3773 | u32 *nicv; /* nic pointer virtual addr */ | |
3774 | u32 nic; /* nic pointer physical addr */ | |
3775 | u32 nicbegin; /* start of ring physical addr */ | |
c8d86be3 | 3776 | unsigned long flag; |
3f56c109 | 3777 | /* physical addr are ok on 32 bits since we set DMA mask */ |
c8d86be3 | 3778 | int offs; |
bbfb5652 | 3779 | int j, i; |
c8d86be3 | 3780 | int hd; |
bbfb5652 | 3781 | if (error) |
3f56c109 | 3782 | priv->stats.txretry++; /* tony 20060601 */ |
bbfb5652 PS |
3783 | spin_lock_irqsave(&priv->tx_lock, flag); |
3784 | switch (pri) { | |
c8d86be3 GKH |
3785 | case MANAGE_PRIORITY: |
3786 | tail = priv->txmapringtail; | |
3787 | begin = priv->txmapring; | |
3788 | head = priv->txmapringhead; | |
bbfb5652 | 3789 | nic = read_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR); |
c8d86be3 GKH |
3790 | nicbegin = priv->txmapringdma; |
3791 | break; | |
c8d86be3 GKH |
3792 | case BK_PRIORITY: |
3793 | tail = priv->txbkpringtail; | |
3794 | begin = priv->txbkpring; | |
3795 | head = priv->txbkpringhead; | |
bbfb5652 | 3796 | nic = read_nic_dword(dev, TX_BKPRIORITY_RING_ADDR); |
c8d86be3 GKH |
3797 | nicbegin = priv->txbkpringdma; |
3798 | break; | |
c8d86be3 GKH |
3799 | case BE_PRIORITY: |
3800 | tail = priv->txbepringtail; | |
3801 | begin = priv->txbepring; | |
3802 | head = priv->txbepringhead; | |
bbfb5652 | 3803 | nic = read_nic_dword(dev, TX_BEPRIORITY_RING_ADDR); |
c8d86be3 GKH |
3804 | nicbegin = priv->txbepringdma; |
3805 | break; | |
c8d86be3 GKH |
3806 | case VI_PRIORITY: |
3807 | tail = priv->txvipringtail; | |
3808 | begin = priv->txvipring; | |
3809 | head = priv->txvipringhead; | |
bbfb5652 | 3810 | nic = read_nic_dword(dev, TX_VIPRIORITY_RING_ADDR); |
c8d86be3 GKH |
3811 | nicbegin = priv->txvipringdma; |
3812 | break; | |
c8d86be3 GKH |
3813 | case VO_PRIORITY: |
3814 | tail = priv->txvopringtail; | |
3815 | begin = priv->txvopring; | |
3816 | head = priv->txvopringhead; | |
bbfb5652 | 3817 | nic = read_nic_dword(dev, TX_VOPRIORITY_RING_ADDR); |
c8d86be3 GKH |
3818 | nicbegin = priv->txvopringdma; |
3819 | break; | |
c8d86be3 GKH |
3820 | case HI_PRIORITY: |
3821 | tail = priv->txhpringtail; | |
3822 | begin = priv->txhpring; | |
3823 | head = priv->txhpringhead; | |
bbfb5652 | 3824 | nic = read_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR); |
c8d86be3 GKH |
3825 | nicbegin = priv->txhpringdma; |
3826 | break; | |
3827 | ||
3828 | default: | |
bbfb5652 | 3829 | spin_unlock_irqrestore(&priv->tx_lock, flag); |
c8d86be3 GKH |
3830 | return ; |
3831 | } | |
fd882783 | 3832 | |
bbfb5652 PS |
3833 | nicv = (u32 *)((nic - nicbegin) + (u8*)begin); |
3834 | if ((head <= tail && (nicv > tail || nicv < head)) || | |
3835 | (head > tail && (nicv > tail && nicv < head))) { | |
c8d86be3 | 3836 | DMESGW("nic has lost pointer"); |
bbfb5652 | 3837 | spin_unlock_irqrestore(&priv->tx_lock, flag); |
c8d86be3 GKH |
3838 | rtl8180_restart(dev); |
3839 | return; | |
3840 | } | |
3841 | ||
3f56c109 PS |
3842 | /* |
3843 | * We check all the descriptors between the head and the nic, | |
bbc9a991 | 3844 | * but not the currently pointed by the nic (the next to be txed) |
c8d86be3 | 3845 | * and the previous of the pointed (might be in process ??) |
3f56c109 | 3846 | */ |
c8d86be3 | 3847 | offs = (nic - nicbegin); |
bbfb5652 PS |
3848 | offs = offs / 8 / 4; |
3849 | hd = (head - begin) / 8; | |
c8d86be3 | 3850 | |
bbfb5652 | 3851 | if (offs >= hd) |
c8d86be3 GKH |
3852 | j = offs - hd; |
3853 | else | |
bbfb5652 | 3854 | j = offs + (priv->txringcount-1-hd); |
c8d86be3 | 3855 | |
bbfb5652 PS |
3856 | j -= 2; |
3857 | if (j < 0) | |
3858 | j = 0; | |
c8d86be3 | 3859 | |
bbfb5652 PS |
3860 | for (i = 0; i < j; i++) { |
3861 | if ((*head) & (1<<31)) | |
c8d86be3 | 3862 | break; |
bbfb5652 | 3863 | if (((*head)&(0x10000000)) != 0) { |
c8d86be3 | 3864 | priv->CurrRetryCnt += (u16)((*head) & (0x000000ff)); |
fd882783 | 3865 | if (!error) |
c8d86be3 | 3866 | priv->NumTxOkTotal++; |
c8d86be3 | 3867 | } |
fd882783 BZ |
3868 | |
3869 | if (!error) | |
c8d86be3 | 3870 | priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff); |
fd882783 | 3871 | |
bbfb5652 | 3872 | *head = *head & ~(1<<31); |
c8d86be3 | 3873 | |
bbfb5652 PS |
3874 | if ((head - begin)/8 == priv->txringcount-1) |
3875 | head = begin; | |
c8d86be3 | 3876 | else |
bbfb5652 | 3877 | head += 8; |
c8d86be3 | 3878 | } |
c8d86be3 | 3879 | |
3f56c109 PS |
3880 | /* |
3881 | * The head has been moved to the last certainly TXed | |
c8d86be3 GKH |
3882 | * (or at least processed by the nic) packet. |
3883 | * The driver take forcefully owning of all these packets | |
3884 | * If the packet previous of the nic pointer has been | |
3885 | * processed this doesn't matter: it will be checked | |
3886 | * here at the next round. Anyway if no more packet are | |
25985edc | 3887 | * TXed no memory leak occur at all. |
c8d86be3 GKH |
3888 | */ |
3889 | ||
bbfb5652 | 3890 | switch (pri) { |
c8d86be3 GKH |
3891 | case MANAGE_PRIORITY: |
3892 | priv->txmapringhead = head; | |
fd882783 | 3893 | |
bbfb5652 PS |
3894 | if (priv->ack_tx_to_ieee) { |
3895 | if (rtl8180_is_tx_queue_empty(dev)) { | |
c8d86be3 | 3896 | priv->ack_tx_to_ieee = 0; |
bbfb5652 | 3897 | ieee80211_ps_tx_ack(priv->ieee80211, !error); |
c8d86be3 | 3898 | } |
c8d86be3 GKH |
3899 | } |
3900 | break; | |
c8d86be3 GKH |
3901 | case BK_PRIORITY: |
3902 | priv->txbkpringhead = head; | |
3903 | break; | |
c8d86be3 GKH |
3904 | case BE_PRIORITY: |
3905 | priv->txbepringhead = head; | |
3906 | break; | |
c8d86be3 GKH |
3907 | case VI_PRIORITY: |
3908 | priv->txvipringhead = head; | |
3909 | break; | |
c8d86be3 GKH |
3910 | case VO_PRIORITY: |
3911 | priv->txvopringhead = head; | |
3912 | break; | |
c8d86be3 GKH |
3913 | case HI_PRIORITY: |
3914 | priv->txhpringhead = head; | |
3915 | break; | |
3916 | } | |
3917 | ||
bbfb5652 | 3918 | spin_unlock_irqrestore(&priv->tx_lock, flag); |
c8d86be3 GKH |
3919 | } |
3920 | ||
c8d86be3 GKH |
3921 | void rtl8180_tx_irq_wq(struct work_struct *work) |
3922 | { | |
bf6aede7 | 3923 | struct delayed_work *dwork = to_delayed_work(work); |
bbfb5652 PS |
3924 | struct ieee80211_device * ieee = (struct ieee80211_device *) |
3925 | container_of(dwork, struct ieee80211_device, watch_dog_wq); | |
c8d86be3 | 3926 | struct net_device *dev = ieee->dev; |
0370453f | 3927 | |
bbfb5652 | 3928 | rtl8180_tx_isr(dev, MANAGE_PRIORITY, 0); |
c8d86be3 GKH |
3929 | } |
3930 | irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs) | |
3931 | { | |
3932 | struct net_device *dev = (struct net_device *) netdev; | |
3933 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); | |
3934 | unsigned long flags; | |
3935 | u32 inta; | |
3936 | ||
3937 | /* We should return IRQ_NONE, but for now let me keep this */ | |
bbfb5652 PS |
3938 | if (priv->irq_enabled == 0) |
3939 | return IRQ_HANDLED; | |
c8d86be3 | 3940 | |
bbfb5652 | 3941 | spin_lock_irqsave(&priv->irq_th_lock, flags); |
c8d86be3 | 3942 | |
3f56c109 PS |
3943 | /* ISR: 4bytes */ |
3944 | inta = read_nic_dword(dev, ISR); /* & priv->IntrMask; */ | |
3945 | write_nic_dword(dev, ISR, inta); /* reset int situation */ | |
c8d86be3 GKH |
3946 | |
3947 | priv->stats.shints++; | |
3948 | ||
bbfb5652 PS |
3949 | if (!inta) { |
3950 | spin_unlock_irqrestore(&priv->irq_th_lock, flags); | |
c8d86be3 GKH |
3951 | return IRQ_HANDLED; |
3952 | /* | |
3f56c109 PS |
3953 | * most probably we can safely return IRQ_NONE, |
3954 | * but for now is better to avoid problems | |
3955 | */ | |
c8d86be3 GKH |
3956 | } |
3957 | ||
fd882783 BZ |
3958 | if (inta == 0xffff) { |
3959 | /* HW disappared */ | |
3960 | spin_unlock_irqrestore(&priv->irq_th_lock, flags); | |
3961 | return IRQ_HANDLED; | |
c8d86be3 GKH |
3962 | } |
3963 | ||
3964 | priv->stats.ints++; | |
c8d86be3 | 3965 | |
bbfb5652 PS |
3966 | if (!netif_running(dev)) { |
3967 | spin_unlock_irqrestore(&priv->irq_th_lock, flags); | |
c8d86be3 GKH |
3968 | return IRQ_HANDLED; |
3969 | } | |
3970 | ||
fd882783 | 3971 | if (inta & ISR_TimeOut) |
c8d86be3 | 3972 | write_nic_dword(dev, TimerInt, 0); |
c8d86be3 | 3973 | |
fd882783 | 3974 | if (inta & ISR_TBDOK) |
c8d86be3 | 3975 | priv->stats.txbeacon++; |
c8d86be3 | 3976 | |
fd882783 | 3977 | if (inta & ISR_TBDER) |
c8d86be3 | 3978 | priv->stats.txbeaconerr++; |
c8d86be3 | 3979 | |
fd882783 | 3980 | if (inta & IMR_TMGDOK) |
bbfb5652 | 3981 | rtl8180_tx_isr(dev, MANAGE_PRIORITY, 0); |
c8d86be3 | 3982 | |
bbfb5652 | 3983 | if (inta & ISR_THPDER) { |
c8d86be3 | 3984 | priv->stats.txhperr++; |
bbfb5652 | 3985 | rtl8180_tx_isr(dev, HI_PRIORITY, 1); |
c8d86be3 GKH |
3986 | priv->ieee80211->stats.tx_errors++; |
3987 | } | |
3988 | ||
3f56c109 PS |
3989 | if (inta & ISR_THPDOK) { /* High priority tx ok */ |
3990 | priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ | |
c8d86be3 | 3991 | priv->stats.txhpokint++; |
bbfb5652 | 3992 | rtl8180_tx_isr(dev, HI_PRIORITY, 0); |
c8d86be3 GKH |
3993 | } |
3994 | ||
bbfb5652 | 3995 | if (inta & ISR_RER) |
c8d86be3 | 3996 | priv->stats.rxerr++; |
bbfb5652 | 3997 | |
3f56c109 | 3998 | if (inta & ISR_TBKDER) { /* corresponding to BK_PRIORITY */ |
c8d86be3 GKH |
3999 | priv->stats.txbkperr++; |
4000 | priv->ieee80211->stats.tx_errors++; | |
bbfb5652 | 4001 | rtl8180_tx_isr(dev, BK_PRIORITY, 1); |
c8d86be3 GKH |
4002 | rtl8180_try_wake_queue(dev, BE_PRIORITY); |
4003 | } | |
4004 | ||
3f56c109 | 4005 | if (inta & ISR_TBEDER) { /* corresponding to BE_PRIORITY */ |
c8d86be3 GKH |
4006 | priv->stats.txbeperr++; |
4007 | priv->ieee80211->stats.tx_errors++; | |
bbfb5652 | 4008 | rtl8180_tx_isr(dev, BE_PRIORITY, 1); |
c8d86be3 GKH |
4009 | rtl8180_try_wake_queue(dev, BE_PRIORITY); |
4010 | } | |
3f56c109 | 4011 | if (inta & ISR_TNPDER) { /* corresponding to VO_PRIORITY */ |
c8d86be3 GKH |
4012 | priv->stats.txnperr++; |
4013 | priv->ieee80211->stats.tx_errors++; | |
bbfb5652 | 4014 | rtl8180_tx_isr(dev, NORM_PRIORITY, 1); |
c8d86be3 | 4015 | rtl8180_try_wake_queue(dev, NORM_PRIORITY); |
c8d86be3 GKH |
4016 | } |
4017 | ||
3f56c109 | 4018 | if (inta & ISR_TLPDER) { /* corresponding to VI_PRIORITY */ |
c8d86be3 GKH |
4019 | priv->stats.txlperr++; |
4020 | priv->ieee80211->stats.tx_errors++; | |
bbfb5652 | 4021 | rtl8180_tx_isr(dev, LOW_PRIORITY, 1); |
c8d86be3 GKH |
4022 | rtl8180_try_wake_queue(dev, LOW_PRIORITY); |
4023 | } | |
4024 | ||
bbfb5652 | 4025 | if (inta & ISR_ROK) { |
c8d86be3 GKH |
4026 | priv->stats.rxint++; |
4027 | tasklet_schedule(&priv->irq_rx_tasklet); | |
4028 | } | |
4029 | ||
bbfb5652 | 4030 | if (inta & ISR_RQoSOK) { |
c8d86be3 GKH |
4031 | priv->stats.rxint++; |
4032 | tasklet_schedule(&priv->irq_rx_tasklet); | |
4033 | } | |
bbfb5652 PS |
4034 | |
4035 | if (inta & ISR_BcnInt) | |
c8d86be3 | 4036 | rtl8180_prepare_beacon(dev); |
c8d86be3 | 4037 | |
bbfb5652 | 4038 | if (inta & ISR_RDU) { |
c8d86be3 GKH |
4039 | DMESGW("No RX descriptor available"); |
4040 | priv->stats.rxrdu++; | |
c8d86be3 | 4041 | tasklet_schedule(&priv->irq_rx_tasklet); |
c8d86be3 | 4042 | } |
fd882783 | 4043 | |
bbfb5652 | 4044 | if (inta & ISR_RXFOVW) { |
c8d86be3 GKH |
4045 | priv->stats.rxoverflow++; |
4046 | tasklet_schedule(&priv->irq_rx_tasklet); | |
c8d86be3 GKH |
4047 | } |
4048 | ||
fd882783 BZ |
4049 | if (inta & ISR_TXFOVW) |
4050 | priv->stats.txoverflow++; | |
c8d86be3 | 4051 | |
3f56c109 PS |
4052 | if (inta & ISR_TNPDOK) { /* Normal priority tx ok */ |
4053 | priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ | |
c8d86be3 | 4054 | priv->stats.txnpokint++; |
bbfb5652 | 4055 | rtl8180_tx_isr(dev, NORM_PRIORITY, 0); |
c8d86be3 GKH |
4056 | } |
4057 | ||
3f56c109 PS |
4058 | if (inta & ISR_TLPDOK) { /* Low priority tx ok */ |
4059 | priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ | |
c8d86be3 | 4060 | priv->stats.txlpokint++; |
bbfb5652 | 4061 | rtl8180_tx_isr(dev, LOW_PRIORITY, 0); |
c8d86be3 GKH |
4062 | rtl8180_try_wake_queue(dev, LOW_PRIORITY); |
4063 | } | |
4064 | ||
3f56c109 | 4065 | if (inta & ISR_TBKDOK) { /* corresponding to BK_PRIORITY */ |
c8d86be3 | 4066 | priv->stats.txbkpokint++; |
3f56c109 | 4067 | priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ |
bbfb5652 | 4068 | rtl8180_tx_isr(dev, BK_PRIORITY, 0); |
c8d86be3 GKH |
4069 | rtl8180_try_wake_queue(dev, BE_PRIORITY); |
4070 | } | |
4071 | ||
3f56c109 | 4072 | if (inta & ISR_TBEDOK) { /* corresponding to BE_PRIORITY */ |
c8d86be3 | 4073 | priv->stats.txbeperr++; |
3f56c109 | 4074 | priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ |
bbfb5652 | 4075 | rtl8180_tx_isr(dev, BE_PRIORITY, 0); |
c8d86be3 GKH |
4076 | rtl8180_try_wake_queue(dev, BE_PRIORITY); |
4077 | } | |
c8d86be3 | 4078 | force_pci_posting(dev); |
bbfb5652 | 4079 | spin_unlock_irqrestore(&priv->irq_th_lock, flags); |
c8d86be3 GKH |
4080 | |
4081 | return IRQ_HANDLED; | |
4082 | } | |
4083 | ||
bbfb5652 | 4084 | void rtl8180_irq_rx_tasklet(struct r8180_priv *priv) |
c8d86be3 | 4085 | { |
c8d86be3 | 4086 | rtl8180_rx(priv->dev); |
c8d86be3 GKH |
4087 | } |
4088 | ||
c8d86be3 GKH |
4089 | void GPIOChangeRFWorkItemCallBack(struct work_struct *work) |
4090 | { | |
c8d86be3 GKH |
4091 | struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work); |
4092 | struct net_device *dev = ieee->dev; | |
4093 | struct r8180_priv *priv = ieee80211_priv(dev); | |
c8d86be3 GKH |
4094 | u8 btPSR; |
4095 | u8 btConfig0; | |
4096 | RT_RF_POWER_STATE eRfPowerStateToSet; | |
cb73da25 | 4097 | bool bActuallySet = false; |
c8d86be3 GKH |
4098 | |
4099 | char *argv[3]; | |
cb73da25 | 4100 | static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh"; |
bbfb5652 | 4101 | static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL}; |
c8d86be3 | 4102 | static int readf_count = 0; |
c8d86be3 | 4103 | |
bbfb5652 | 4104 | if (readf_count % 10 == 0) |
c8d86be3 GKH |
4105 | priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state"); |
4106 | ||
4107 | readf_count = (readf_count+1)%0xffff; | |
1994130e | 4108 | /* We should turn off LED before polling FF51[4]. */ |
c8d86be3 | 4109 | |
1994130e LF |
4110 | /* Turn off LED. */ |
4111 | btPSR = read_nic_byte(dev, PSR); | |
4112 | write_nic_byte(dev, PSR, (btPSR & ~BIT3)); | |
c8d86be3 | 4113 | |
1994130e LF |
4114 | /* It need to delay 4us suggested by Jong, 2008-01-16 */ |
4115 | udelay(4); | |
c8d86be3 | 4116 | |
1994130e LF |
4117 | /* HW radio On/Off according to the value of FF51[4](config0) */ |
4118 | btConfig0 = btPSR = read_nic_byte(dev, CONFIG0); | |
c8d86be3 | 4119 | |
1994130e | 4120 | eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff; |
c8d86be3 | 4121 | |
6de92dd6 LF |
4122 | /* Turn LED back on when radio enabled */ |
4123 | if (eRfPowerStateToSet == eRfOn) | |
4124 | write_nic_byte(dev, PSR, btPSR | BIT3); | |
c8d86be3 | 4125 | |
1994130e LF |
4126 | if ((priv->ieee80211->bHwRadioOff == true) && |
4127 | (eRfPowerStateToSet == eRfOn)) { | |
4128 | priv->ieee80211->bHwRadioOff = false; | |
4129 | bActuallySet = true; | |
4130 | } else if ((priv->ieee80211->bHwRadioOff == false) && | |
4131 | (eRfPowerStateToSet == eRfOff)) { | |
4132 | priv->ieee80211->bHwRadioOff = true; | |
4133 | bActuallySet = true; | |
4134 | } | |
c8d86be3 | 4135 | |
1994130e LF |
4136 | if (bActuallySet) { |
4137 | MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); | |
4138 | ||
4139 | /* To update the UI status for Power status changed */ | |
4140 | if (priv->ieee80211->bHwRadioOff == true) | |
4141 | argv[1] = "RFOFF"; | |
4142 | else | |
4143 | argv[1] = "RFON"; | |
4144 | argv[0] = RadioPowerPath; | |
4145 | argv[2] = NULL; | |
4146 | ||
4147 | call_usermodehelper(RadioPowerPath, argv, envp, 1); | |
4148 | } | |
c8d86be3 GKH |
4149 | } |
4150 | ||
4151 | static u8 read_acadapter_file(char *filename) | |
4152 | { | |
c8d86be3 GKH |
4153 | return 0; |
4154 | } | |
4155 | ||
c8d86be3 GKH |
4156 | module_init(rtl8180_pci_module_init); |
4157 | module_exit(rtl8180_pci_module_exit); |