Staging: r8187se: Remove two private variables that have a fixed value
[linux-2.6-block.git] / drivers / staging / rtl8187se / r8180_core.c
CommitLineData
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1/*
2 This is part of rtl818x pci OpenSource driver - v 0.1
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public License)
5
6 Parts of this driver are based on the GPL part of the official
7 Realtek driver.
8
9 Parts of this driver are based on the rtl8180 driver skeleton
10 from Patric Schenke & Andres Salomon.
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
13
14 Parts of BB/RF code are derived from David Young rtl8180 netbsd driver.
15
16 RSSI calc function from 'The Deuce'
17
18 Some ideas borrowed from the 8139too.c driver included in linux kernel.
19
20 We (I?) want to thanks the Authors of those projecs and also the
21 Ndiswrapper's project Authors.
22
23 A big big thanks goes also to Realtek corp. for their help in my attempt to
24 add RTL8185 and RTL8225 support, and to David Young also.
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25
26 Power management interface routines.
27 Written by Mariusz Matuszek.
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28*/
29
c8d86be3 30#undef RX_DONT_PASS_UL
c8d86be3 31#undef DUMMY_RX
c8d86be3 32
c8d86be3 33#include <linux/syscalls.h>
742821ce 34#include <linux/eeprom_93cx6.h>
fd882783 35
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36#include "r8180_hw.h"
37#include "r8180.h"
c8d86be3 38#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
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39#include "r8180_93cx6.h" /* Card EEPROM */
40#include "r8180_wx.h"
41#include "r8180_dm.h"
42
fd9b8d6e 43#include "ieee80211/dot11d.h"
c8d86be3 44
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45static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = {
46 {
47 .vendor = PCI_VENDOR_ID_REALTEK,
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48 .device = 0x8199,
49 .subvendor = PCI_ANY_ID,
50 .subdevice = PCI_ANY_ID,
51 .driver_data = 0,
52 },
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53 {
54 .vendor = 0,
55 .device = 0,
56 .subvendor = 0,
57 .subdevice = 0,
58 .driver_data = 0,
59 }
60};
61
62
63static char* ifname = "wlan%d";
64static int hwseqnum = 0;
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65static int hwwep = 0;
66static int channels = 0x3fff;
67
68#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
69#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
70MODULE_LICENSE("GPL");
71MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl);
72MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
73MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards");
74
75
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76module_param(ifname, charp, S_IRUGO|S_IWUSR );
77module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
78module_param(hwwep,int, S_IRUGO|S_IWUSR);
79module_param(channels,int, S_IRUGO|S_IWUSR);
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80
81MODULE_PARM_DESC(devname," Net interface name, wlan%d=default");
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82MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
83MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards");
84MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
85
86
87static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
88 const struct pci_device_id *id);
89
90static void __devexit rtl8180_pci_remove(struct pci_dev *pdev);
91
92static void rtl8180_shutdown (struct pci_dev *pdev)
93{
94 struct net_device *dev = pci_get_drvdata(pdev);
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95 if (dev->netdev_ops->ndo_stop)
96 dev->netdev_ops->ndo_stop(dev);
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97 pci_disable_device(pdev);
98}
99
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100static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
101{
102 struct net_device *dev = pci_get_drvdata(pdev);
103
104 if (!netif_running(dev))
105 goto out_pci_suspend;
106
107 if (dev->netdev_ops->ndo_stop)
108 dev->netdev_ops->ndo_stop(dev);
109
110 netif_device_detach(dev);
111
112out_pci_suspend:
113 pci_save_state(pdev);
114 pci_disable_device(pdev);
115 pci_set_power_state(pdev, pci_choose_state(pdev, state));
116 return 0;
117}
118
119static int rtl8180_resume(struct pci_dev *pdev)
120{
121 struct net_device *dev = pci_get_drvdata(pdev);
122 int err;
123 u32 val;
124
125 pci_set_power_state(pdev, PCI_D0);
126
127 err = pci_enable_device(pdev);
128 if (err) {
129 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
130 dev->name);
131
132 return err;
133 }
134
135 pci_restore_state(pdev);
136
137 /*
138 * Suspend/Resume resets the PCI configuration space, so we have to
139 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
140 * from interfering with C3 CPU state. pci_restore_state won't help
141 * here since it only restores the first 64 bytes pci config header.
142 */
143 pci_read_config_dword(pdev, 0x40, &val);
144 if ((val & 0x0000ff00) != 0)
145 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
146
147 if (!netif_running(dev))
148 goto out;
149
150 if (dev->netdev_ops->ndo_open)
151 dev->netdev_ops->ndo_open(dev);
152
153 netif_device_attach(dev);
154out:
155 return 0;
156}
157
c8d86be3 158static struct pci_driver rtl8180_pci_driver = {
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159 .name = RTL8180_MODULE_NAME,
160 .id_table = rtl8180_pci_id_tbl,
161 .probe = rtl8180_pci_probe,
162 .remove = __devexit_p(rtl8180_pci_remove),
163 .suspend = rtl8180_suspend,
164 .resume = rtl8180_resume,
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165 .shutdown = rtl8180_shutdown,
166};
167
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168u8 read_nic_byte(struct net_device *dev, int x)
169{
170 return 0xff&readb((u8*)dev->mem_start +x);
171}
172
173u32 read_nic_dword(struct net_device *dev, int x)
174{
175 return readl((u8*)dev->mem_start +x);
176}
177
178u16 read_nic_word(struct net_device *dev, int x)
179{
180 return readw((u8*)dev->mem_start +x);
181}
182
183void write_nic_byte(struct net_device *dev, int x,u8 y)
184{
185 writeb(y,(u8*)dev->mem_start +x);
186 udelay(20);
187}
188
189void write_nic_dword(struct net_device *dev, int x,u32 y)
190{
191 writel(y,(u8*)dev->mem_start +x);
192 udelay(20);
193}
194
195void write_nic_word(struct net_device *dev, int x,u16 y)
196{
197 writew(y,(u8*)dev->mem_start +x);
198 udelay(20);
199}
200
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201inline void force_pci_posting(struct net_device *dev)
202{
203 read_nic_byte(dev,EPROM_CMD);
c8d86be3 204 mb();
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205}
206
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207irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs);
208void set_nic_rxring(struct net_device *dev);
209void set_nic_txring(struct net_device *dev);
210static struct net_device_stats *rtl8180_stats(struct net_device *dev);
211void rtl8180_commit(struct net_device *dev);
212void rtl8180_start_tx_beacon(struct net_device *dev);
213
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214static struct proc_dir_entry *rtl8180_proc = NULL;
215
216static int proc_get_registers(char *page, char **start,
217 off_t offset, int count,
218 int *eof, void *data)
219{
220 struct net_device *dev = data;
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221 int len = 0;
222 int i,n;
fd882783 223 int max = 0xff;
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224
225 /* This dump the current register page */
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226 for (n = 0; n <= max;) {
227 len += snprintf(page + len, count - len, "\nD: %2x > ", n);
c8d86be3 228
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229 for (i = 0; i < 16 && n <= max; i++, n++)
230 len += snprintf(page + len, count - len, "%2x ",
231 read_nic_byte(dev, n));
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232 }
233 len += snprintf(page + len, count - len,"\n");
234
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235 *eof = 1;
236 return len;
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237}
238
239int get_curr_tx_free_desc(struct net_device *dev, int priority);
240
241static int proc_get_stats_hw(char *page, char **start,
242 off_t offset, int count,
243 int *eof, void *data)
244{
c8d86be3 245 int len = 0;
c8d86be3 246
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247 *eof = 1;
248 return len;
249}
250
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251static int proc_get_stats_rx(char *page, char **start,
252 off_t offset, int count,
253 int *eof, void *data)
254{
255 struct net_device *dev = data;
256 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
257
258 int len = 0;
259
260 len += snprintf(page + len, count - len,
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261 "RX OK: %lu\n"
262 "RX Retry: %lu\n"
263 "RX CRC Error(0-500): %lu\n"
264 "RX CRC Error(500-1000): %lu\n"
265 "RX CRC Error(>1000): %lu\n"
266 "RX ICV Error: %lu\n",
267 priv->stats.rxint,
268 priv->stats.rxerr,
269 priv->stats.rxcrcerrmin,
270 priv->stats.rxcrcerrmid,
271 priv->stats.rxcrcerrmax,
272 priv->stats.rxicverr
273 );
274
275 *eof = 1;
276 return len;
277}
278
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279static int proc_get_stats_tx(char *page, char **start,
280 off_t offset, int count,
281 int *eof, void *data)
282{
283 struct net_device *dev = data;
284 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
285
286 int len = 0;
287 unsigned long totalOK;
288
289 totalOK=priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint;
290 len += snprintf(page + len, count - len,
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291 "TX OK: %lu\n"
292 "TX Error: %lu\n"
293 "TX Retry: %lu\n"
294 "TX beacon OK: %lu\n"
295 "TX beacon error: %lu\n",
296 totalOK,
297 priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr,
298 priv->stats.txretry,
299 priv->stats.txbeacon,
300 priv->stats.txbeaconerr
301 );
302
303 *eof = 1;
304 return len;
305}
306
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307void rtl8180_proc_module_init(void)
308{
309 DMESG("Initializing proc filesystem");
c8d86be3 310 rtl8180_proc=create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net);
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311}
312
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313void rtl8180_proc_module_remove(void)
314{
c8d86be3 315 remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net);
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316}
317
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318void rtl8180_proc_remove_one(struct net_device *dev)
319{
320 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
321 if (priv->dir_dev) {
322 remove_proc_entry("stats-hw", priv->dir_dev);
323 remove_proc_entry("stats-tx", priv->dir_dev);
324 remove_proc_entry("stats-rx", priv->dir_dev);
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325 remove_proc_entry("registers", priv->dir_dev);
326 remove_proc_entry(dev->name, rtl8180_proc);
327 priv->dir_dev = NULL;
328 }
329}
330
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331void rtl8180_proc_init_one(struct net_device *dev)
332{
333 struct proc_dir_entry *e;
334 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 335
be286fd2 336 priv->dir_dev = rtl8180_proc;
c8d86be3 337 if (!priv->dir_dev) {
be286fd2 338 DMESGE("Unable to initialize /proc/net/r8180/%s\n",
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339 dev->name);
340 return;
341 }
342
343 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
344 priv->dir_dev, proc_get_stats_hw, dev);
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345 if (!e) {
346 DMESGE("Unable to initialize "
be286fd2 347 "/proc/net/r8180/%s/stats-hw\n",
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348 dev->name);
349 }
350
351 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
352 priv->dir_dev, proc_get_stats_rx, dev);
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353 if (!e) {
354 DMESGE("Unable to initialize "
be286fd2 355 "/proc/net/r8180/%s/stats-rx\n",
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356 dev->name);
357 }
358
359
360 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
361 priv->dir_dev, proc_get_stats_tx, dev);
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362 if (!e) {
363 DMESGE("Unable to initialize "
be286fd2 364 "/proc/net/r8180/%s/stats-tx\n",
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365 dev->name);
366 }
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367
368 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
369 priv->dir_dev, proc_get_registers, dev);
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370 if (!e) {
371 DMESGE("Unable to initialize "
be286fd2 372 "/proc/net/r8180/%s/registers\n",
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373 dev->name);
374 }
375}
fd882783 376
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377/*
378 FIXME: check if we can use some standard already-existent
379 data type+functions in kernel
380*/
381
382short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma,
383 struct buffer **bufferhead)
384{
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385 struct buffer *tmp;
386
387 if(! *buffer){
388
389 *buffer = kmalloc(sizeof(struct buffer),GFP_KERNEL);
390
391 if (*buffer == NULL) {
392 DMESGE("Failed to kmalloc head of TX/RX struct");
393 return -1;
394 }
395 (*buffer)->next=*buffer;
396 (*buffer)->buf=buf;
397 (*buffer)->dma=dma;
398 if(bufferhead !=NULL)
399 (*bufferhead) = (*buffer);
400 return 0;
401 }
402 tmp=*buffer;
403
404 while(tmp->next!=(*buffer)) tmp=tmp->next;
405 if ((tmp->next= kmalloc(sizeof(struct buffer),GFP_KERNEL)) == NULL){
406 DMESGE("Failed to kmalloc TX/RX struct");
407 return -1;
408 }
409 tmp->next->buf=buf;
410 tmp->next->dma=dma;
411 tmp->next->next=*buffer;
412
413 return 0;
414}
415
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416void buffer_free(struct net_device *dev,struct buffer **buffer,int len,short
417consistent)
418{
419
420 struct buffer *tmp,*next;
421 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
422 struct pci_dev *pdev=priv->pdev;
c8d86be3 423
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424 if (!*buffer)
425 return;
c8d86be3 426
fd882783 427 tmp = *buffer;
c8d86be3 428
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429 do{
430 next=tmp->next;
431 if(consistent){
432 pci_free_consistent(pdev,len,
433 tmp->buf,tmp->dma);
434 }else{
435 pci_unmap_single(pdev, tmp->dma,
436 len,PCI_DMA_FROMDEVICE);
437 kfree(tmp->buf);
438 }
439 kfree(tmp);
440 tmp = next;
441 }
442 while(next != *buffer);
443
444 *buffer=NULL;
445}
446
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447void print_buffer(u32 *buffer, int len)
448{
449 int i;
450 u8 *buf =(u8*)buffer;
451
452 printk("ASCII BUFFER DUMP (len: %x):\n",len);
453
454 for(i=0;i<len;i++)
455 printk("%c",buf[i]);
456
457 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
458
459 for(i=0;i<len;i++)
460 printk("%02x",buf[i]);
461
462 printk("\n");
463}
464
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465int get_curr_tx_free_desc(struct net_device *dev, int priority)
466{
467 struct r8180_priv *priv = ieee80211_priv(dev);
468 u32* tail;
469 u32* head;
470 int ret;
471
472 switch (priority){
473 case MANAGE_PRIORITY:
474 head = priv->txmapringhead;
475 tail = priv->txmapringtail;
476 break;
477 case BK_PRIORITY:
478 head = priv->txbkpringhead;
479 tail = priv->txbkpringtail;
480 break;
481 case BE_PRIORITY:
482 head = priv->txbepringhead;
483 tail = priv->txbepringtail;
484 break;
485 case VI_PRIORITY:
486 head = priv->txvipringhead;
487 tail = priv->txvipringtail;
488 break;
489 case VO_PRIORITY:
490 head = priv->txvopringhead;
491 tail = priv->txvopringtail;
492 break;
493 case HI_PRIORITY:
494 head = priv->txhpringhead;
495 tail = priv->txhpringtail;
496 break;
497 default:
498 return -1;
499 }
500
fd882783 501 if (head <= tail)
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502 ret = priv->txringcount - (tail - head)/8;
503 else
504 ret = (head - tail)/8;
505
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506 if (ret > priv->txringcount)
507 DMESG("BUG");
508
c8d86be3 509 return ret;
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510}
511
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512short check_nic_enought_desc(struct net_device *dev, int priority)
513{
514 struct r8180_priv *priv = ieee80211_priv(dev);
515 struct ieee80211_device *ieee = netdev_priv(dev);
c8d86be3 516 int requiredbyte, required;
fd882783 517
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518 requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data);
519
fd882783 520 if (ieee->current_network.QoS_Enable)
c8d86be3 521 requiredbyte += 2;
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522
523 required = requiredbyte / (priv->txbuffsize-4);
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524
525 if (requiredbyte % priv->txbuffsize)
526 required++;
527
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528 /* for now we keep two free descriptor as a safety boundary
529 * between the tail and the head
530 */
531
532 return (required+2 < get_curr_tx_free_desc(dev,priority));
533}
534
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535void fix_tx_fifo(struct net_device *dev)
536{
537 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
538 u32 *tmp;
539 int i;
ff954853 540
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541 for (tmp=priv->txmapring, i=0;
542 i < priv->txringcount;
543 tmp+=8, i++){
544 *tmp = *tmp &~ (1<<31);
545 }
546
547 for (tmp=priv->txbkpring, i=0;
548 i < priv->txringcount;
549 tmp+=8, i++) {
550 *tmp = *tmp &~ (1<<31);
551 }
552
553 for (tmp=priv->txbepring, i=0;
554 i < priv->txringcount;
555 tmp+=8, i++){
556 *tmp = *tmp &~ (1<<31);
557 }
558 for (tmp=priv->txvipring, i=0;
559 i < priv->txringcount;
560 tmp+=8, i++) {
561 *tmp = *tmp &~ (1<<31);
562 }
563
564 for (tmp=priv->txvopring, i=0;
565 i < priv->txringcount;
566 tmp+=8, i++){
567 *tmp = *tmp &~ (1<<31);
568 }
569
570 for (tmp=priv->txhpring, i=0;
571 i < priv->txringcount;
572 tmp+=8,i++){
573 *tmp = *tmp &~ (1<<31);
574 }
575
576 for (tmp=priv->txbeaconring, i=0;
577 i < priv->txbeaconcount;
578 tmp+=8, i++){
579 *tmp = *tmp &~ (1<<31);
580 }
ff954853 581
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582 priv->txmapringtail = priv->txmapring;
583 priv->txmapringhead = priv->txmapring;
584 priv->txmapbufstail = priv->txmapbufs;
585
586 priv->txbkpringtail = priv->txbkpring;
587 priv->txbkpringhead = priv->txbkpring;
588 priv->txbkpbufstail = priv->txbkpbufs;
589
590 priv->txbepringtail = priv->txbepring;
591 priv->txbepringhead = priv->txbepring;
592 priv->txbepbufstail = priv->txbepbufs;
593
594 priv->txvipringtail = priv->txvipring;
595 priv->txvipringhead = priv->txvipring;
596 priv->txvipbufstail = priv->txvipbufs;
597
598 priv->txvopringtail = priv->txvopring;
599 priv->txvopringhead = priv->txvopring;
600 priv->txvopbufstail = priv->txvopbufs;
601
602 priv->txhpringtail = priv->txhpring;
603 priv->txhpringhead = priv->txhpring;
604 priv->txhpbufstail = priv->txhpbufs;
605
606 priv->txbeaconringtail = priv->txbeaconring;
607 priv->txbeaconbufstail = priv->txbeaconbufs;
608 set_nic_txring(dev);
609
610 ieee80211_reset_queue(priv->ieee80211);
611 priv->ack_tx_to_ieee = 0;
612}
613
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614void fix_rx_fifo(struct net_device *dev)
615{
616 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
617 u32 *tmp;
618 struct buffer *rxbuf;
619 u8 rx_desc_size;
620
c8d86be3 621 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3 622
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623 for (tmp=priv->rxring, rxbuf=priv->rxbufferhead;
624 (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size);
625 tmp+=rx_desc_size,rxbuf=rxbuf->next){
626 *(tmp+2) = rxbuf->dma;
627 *tmp=*tmp &~ 0xfff;
628 *tmp=*tmp | priv->rxbuffersize;
629 *tmp |= (1<<31);
630 }
631
c8d86be3
GKH
632 priv->rxringtail=priv->rxring;
633 priv->rxbuffer=priv->rxbufferhead;
634 priv->rx_skb_complete=1;
635 set_nic_rxring(dev);
636}
637
c8d86be3 638unsigned char QUALITY_MAP[] = {
fd882783
BZ
639 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61,
640 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c,
641 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f,
642 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29,
643 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
644 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20,
645 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e,
646 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19,
647 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f,
648 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00
c8d86be3
GKH
649};
650
651unsigned char STRENGTH_MAP[] = {
fd882783
BZ
652 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e,
653 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50,
654 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f,
655 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b,
656 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17,
657 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13,
658 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f,
659 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
660 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07,
661 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00
c8d86be3
GKH
662};
663
fd882783
BZ
664void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual)
665{
c8d86be3
GKH
666 u32 temp;
667 u32 temp2;
c8d86be3
GKH
668 u32 q;
669 u32 orig_qual;
670 u8 _rssi;
671
672 q = *qual;
673 orig_qual = *qual;
674 _rssi = 0; // avoid gcc complains..
675
676 if (q <= 0x4e) {
677 temp = QUALITY_MAP[q];
678 } else {
679 if( q & 0x80 ) {
680 temp = 0x32;
681 } else {
682 temp = 1;
683 }
684 }
685
686 *qual = temp;
687 temp2 = *rssi;
688
c8d86be3
GKH
689 if ( _rssi < 0x64 ){
690 if ( _rssi == 0 ) {
691 *rssi = 1;
692 }
693 } else {
694 *rssi = 0x64;
695 }
696
697 return;
698}
699
c8d86be3
GKH
700void rtl8180_irq_enable(struct net_device *dev)
701{
702 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 703
c8d86be3 704 priv->irq_enabled = 1;
c8d86be3
GKH
705 write_nic_word(dev,INTA_MASK, priv->irq_mask);
706}
707
c8d86be3
GKH
708void rtl8180_irq_disable(struct net_device *dev)
709{
710 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
711
c8d86be3 712 write_nic_dword(dev,IMR,0);
c8d86be3
GKH
713 force_pci_posting(dev);
714 priv->irq_enabled = 0;
715}
716
c8d86be3
GKH
717void rtl8180_set_mode(struct net_device *dev,int mode)
718{
719 u8 ecmd;
fd882783 720
c8d86be3
GKH
721 ecmd=read_nic_byte(dev, EPROM_CMD);
722 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
723 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
724 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
725 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
726 write_nic_byte(dev, EPROM_CMD, ecmd);
727}
728
729void rtl8180_adapter_start(struct net_device *dev);
730void rtl8180_beacon_tx_enable(struct net_device *dev);
731
732void rtl8180_update_msr(struct net_device *dev)
733{
734 struct r8180_priv *priv = ieee80211_priv(dev);
735 u8 msr;
736 u32 rxconf;
737
738 msr = read_nic_byte(dev, MSR);
739 msr &= ~ MSR_LINK_MASK;
740
741 rxconf=read_nic_dword(dev,RX_CONF);
742
743 if(priv->ieee80211->state == IEEE80211_LINKED)
744 {
745 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
746 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
747 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
748 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
749 else if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
750 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
751 else
752 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
753 rxconf |= (1<<RX_CHECK_BSSID_SHIFT);
754
755 }else {
756 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
757 rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT);
758 }
759
760 write_nic_byte(dev, MSR, msr);
761 write_nic_dword(dev, RX_CONF, rxconf);
c8d86be3
GKH
762}
763
c8d86be3
GKH
764void rtl8180_set_chan(struct net_device *dev,short ch)
765{
766 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
767
fd882783 768 if ((ch > 14) || (ch < 1)) {
d599edca 769 printk("In %s: Invalid chnanel %d\n", __func__, ch);
c8d86be3
GKH
770 return;
771 }
772
773 priv->chan=ch;
c8d86be3 774 priv->rf_set_chan(dev,priv->chan);
c8d86be3
GKH
775}
776
c8d86be3
GKH
777void rtl8180_rx_enable(struct net_device *dev)
778{
779 u8 cmd;
780 u32 rxconf;
781 /* for now we accept data, management & ctl frame*/
782 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
783
784 rxconf=read_nic_dword(dev,RX_CONF);
785 rxconf = rxconf &~ MAC_FILTER_MASK;
786 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
787 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
788 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
789 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
fd882783
BZ
790 if (dev->flags & IFF_PROMISC)
791 DMESG("NIC in promisc mode");
c8d86be3
GKH
792
793 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
794 dev->flags & IFF_PROMISC){
795 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
796 }else{
797 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
c8d86be3
GKH
798 }
799
c8d86be3
GKH
800 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
801 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
802 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
803 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
804 }
805
806 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
807 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
808
fd882783
BZ
809 rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK;
810 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT);
c8d86be3
GKH
811
812 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
813 rxconf = rxconf &~ MAX_RX_DMA_MASK;
814 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
815
fd882783 816 rxconf = rxconf | RCR_ONLYERLPKT;
c8d86be3
GKH
817
818 rxconf = rxconf &~ RCR_CS_MASK;
fd882783 819
c8d86be3
GKH
820 write_nic_dword(dev, RX_CONF, rxconf);
821
822 fix_rx_fifo(dev);
823
c8d86be3
GKH
824 cmd=read_nic_byte(dev,CMD);
825 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
c8d86be3
GKH
826}
827
c8d86be3
GKH
828void set_nic_txring(struct net_device *dev)
829{
830 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
831
832 write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma);
c8d86be3 833 write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma);
c8d86be3 834 write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma);
c8d86be3 835 write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma);
c8d86be3 836 write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma);
c8d86be3 837 write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma);
c8d86be3
GKH
838 write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma);
839}
840
c8d86be3
GKH
841void rtl8180_conttx_enable(struct net_device *dev)
842{
843 u32 txconf;
fd882783 844
c8d86be3
GKH
845 txconf = read_nic_dword(dev,TX_CONF);
846 txconf = txconf &~ TX_LOOPBACK_MASK;
847 txconf = txconf | (TX_LOOPBACK_CONTINUE <<TX_LOOPBACK_SHIFT);
848 write_nic_dword(dev,TX_CONF,txconf);
849}
850
c8d86be3
GKH
851void rtl8180_conttx_disable(struct net_device *dev)
852{
853 u32 txconf;
fd882783 854
c8d86be3
GKH
855 txconf = read_nic_dword(dev,TX_CONF);
856 txconf = txconf &~ TX_LOOPBACK_MASK;
857 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
858 write_nic_dword(dev,TX_CONF,txconf);
859}
860
c8d86be3
GKH
861void rtl8180_tx_enable(struct net_device *dev)
862{
863 u8 cmd;
864 u8 tx_agc_ctl;
865 u8 byte;
866 u32 txconf;
867 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 868
fd882783 869 txconf = read_nic_dword(dev, TX_CONF);
c8d86be3 870
d44eb889
LF
871 byte = read_nic_byte(dev, CW_CONF);
872 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
873 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
874 write_nic_byte(dev, CW_CONF, byte);
c8d86be3 875
d44eb889
LF
876 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
877 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
878 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
879 tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT);
880 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
881 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
882
883 txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
c8d86be3
GKH
884
885 txconf = txconf &~ TX_LOOPBACK_MASK;
886 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
887 txconf = txconf &~ TCR_DPRETRY_MASK;
888 txconf = txconf &~ TCR_RTSRETRY_MASK;
889 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
890 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
891 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
892
d44eb889
LF
893 if (priv->hw_plcp_len)
894 txconf = txconf & ~TCR_PLCP_LEN;
895 else
896 txconf = txconf | TCR_PLCP_LEN;
fd882783 897
c8d86be3
GKH
898 txconf = txconf &~ TCR_MXDMA_MASK;
899 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
900 txconf = txconf | TCR_CWMIN;
901 txconf = txconf | TCR_DISCW;
902
fd882783 903 txconf = txconf | (1 << TX_NOICV_SHIFT);
c8d86be3
GKH
904
905 write_nic_dword(dev,TX_CONF,txconf);
906
c8d86be3
GKH
907 fix_tx_fifo(dev);
908
c8d86be3
GKH
909 cmd=read_nic_byte(dev,CMD);
910 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
911
c8d86be3 912 write_nic_dword(dev,TX_CONF,txconf);
c8d86be3
GKH
913}
914
c8d86be3
GKH
915void rtl8180_beacon_tx_enable(struct net_device *dev)
916{
917 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
918
919 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
920 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);
921 write_nic_byte(dev,TPPollStop, priv->dma_poll_mask);
c8d86be3
GKH
922 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
923}
924
c8d86be3
GKH
925void rtl8180_beacon_tx_disable(struct net_device *dev)
926{
927 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
928
929 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
930 priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ;
931 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH
932 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
933
934}
935
c8d86be3
GKH
936void rtl8180_rtx_disable(struct net_device *dev)
937{
938 u8 cmd;
939 struct r8180_priv *priv = ieee80211_priv(dev);
940
941 cmd=read_nic_byte(dev,CMD);
942 write_nic_byte(dev, CMD, cmd &~ \
943 ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT)));
944 force_pci_posting(dev);
945 mdelay(10);
c8d86be3
GKH
946
947 if(!priv->rx_skb_complete)
948 dev_kfree_skb_any(priv->rx_skb);
949}
950
c8d86be3
GKH
951short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count,
952 int addr)
953{
954 int i;
955 u32 *desc;
956 u32 *tmp;
957 dma_addr_t dma_desc, dma_tmp;
958 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
959 struct pci_dev *pdev = priv->pdev;
960 void *buf;
961
962 if((bufsize & 0xfff) != bufsize) {
963 DMESGE ("TX buffer allocation too large");
964 return 0;
965 }
966 desc = (u32*)pci_alloc_consistent(pdev,
967 sizeof(u32)*8*count+256, &dma_desc);
fd882783
BZ
968 if (desc == NULL)
969 return -1;
c8d86be3 970
fd882783 971 if (dma_desc & 0xff)
c8d86be3
GKH
972 /*
973 * descriptor's buffer must be 256 byte aligned
974 * we shouldn't be here, since we set DMA mask !
975 */
be286fd2 976 WARN(1, "DMA buffer is not aligned\n");
fd882783
BZ
977
978 tmp = desc;
979
980 for (i = 0; i < count; i++) {
981 buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp);
982 if (buf == NULL)
983 return -ENOMEM;
c8d86be3
GKH
984
985 switch(addr) {
c8d86be3
GKH
986 case TX_MANAGEPRIORITY_RING_ADDR:
987 if(-1 == buffer_add(&(priv->txmapbufs),buf,dma_tmp,NULL)){
988 DMESGE("Unable to allocate mem for buffer NP");
989 return -ENOMEM;
990 }
991 break;
c8d86be3
GKH
992 case TX_BKPRIORITY_RING_ADDR:
993 if(-1 == buffer_add(&(priv->txbkpbufs),buf,dma_tmp,NULL)){
994 DMESGE("Unable to allocate mem for buffer LP");
995 return -ENOMEM;
996 }
997 break;
998 case TX_BEPRIORITY_RING_ADDR:
999 if(-1 == buffer_add(&(priv->txbepbufs),buf,dma_tmp,NULL)){
1000 DMESGE("Unable to allocate mem for buffer NP");
1001 return -ENOMEM;
1002 }
1003 break;
c8d86be3
GKH
1004 case TX_VIPRIORITY_RING_ADDR:
1005 if(-1 == buffer_add(&(priv->txvipbufs),buf,dma_tmp,NULL)){
1006 DMESGE("Unable to allocate mem for buffer LP");
1007 return -ENOMEM;
1008 }
1009 break;
1010 case TX_VOPRIORITY_RING_ADDR:
1011 if(-1 == buffer_add(&(priv->txvopbufs),buf,dma_tmp,NULL)){
1012 DMESGE("Unable to allocate mem for buffer NP");
1013 return -ENOMEM;
1014 }
1015 break;
c8d86be3
GKH
1016 case TX_HIGHPRIORITY_RING_ADDR:
1017 if(-1 == buffer_add(&(priv->txhpbufs),buf,dma_tmp,NULL)){
1018 DMESGE("Unable to allocate mem for buffer HP");
1019 return -ENOMEM;
1020 }
1021 break;
1022 case TX_BEACON_RING_ADDR:
1023 if(-1 == buffer_add(&(priv->txbeaconbufs),buf,dma_tmp,NULL)){
1024 DMESGE("Unable to allocate mem for buffer BP");
1025 return -ENOMEM;
1026 }
1027 break;
1028 }
1029 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1030 *(tmp+2) = (u32)dma_tmp;
1031 *(tmp+3) = bufsize;
1032
1033 if(i+1<count)
1034 *(tmp+4) = (u32)dma_desc+((i+1)*8*4);
1035 else
1036 *(tmp+4) = (u32)dma_desc;
1037
1038 tmp=tmp+8;
1039 }
1040
1041 switch(addr) {
1042 case TX_MANAGEPRIORITY_RING_ADDR:
1043 priv->txmapringdma=dma_desc;
1044 priv->txmapring=desc;
1045 break;
c8d86be3
GKH
1046 case TX_BKPRIORITY_RING_ADDR:
1047 priv->txbkpringdma=dma_desc;
1048 priv->txbkpring=desc;
1049 break;
c8d86be3
GKH
1050 case TX_BEPRIORITY_RING_ADDR:
1051 priv->txbepringdma=dma_desc;
1052 priv->txbepring=desc;
1053 break;
c8d86be3
GKH
1054 case TX_VIPRIORITY_RING_ADDR:
1055 priv->txvipringdma=dma_desc;
1056 priv->txvipring=desc;
1057 break;
c8d86be3
GKH
1058 case TX_VOPRIORITY_RING_ADDR:
1059 priv->txvopringdma=dma_desc;
1060 priv->txvopring=desc;
1061 break;
c8d86be3
GKH
1062 case TX_HIGHPRIORITY_RING_ADDR:
1063 priv->txhpringdma=dma_desc;
1064 priv->txhpring=desc;
1065 break;
c8d86be3
GKH
1066 case TX_BEACON_RING_ADDR:
1067 priv->txbeaconringdma=dma_desc;
1068 priv->txbeaconring=desc;
1069 break;
1070
1071 }
1072
c8d86be3
GKH
1073 return 0;
1074}
1075
c8d86be3
GKH
1076void free_tx_desc_rings(struct net_device *dev)
1077{
c8d86be3
GKH
1078 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1079 struct pci_dev *pdev=priv->pdev;
1080 int count = priv->txringcount;
1081
1082 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1083 priv->txmapring, priv->txmapringdma);
1084 buffer_free(dev,&(priv->txmapbufs),priv->txbuffsize,1);
1085
1086 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1087 priv->txbkpring, priv->txbkpringdma);
1088 buffer_free(dev,&(priv->txbkpbufs),priv->txbuffsize,1);
1089
1090 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1091 priv->txbepring, priv->txbepringdma);
1092 buffer_free(dev,&(priv->txbepbufs),priv->txbuffsize,1);
1093
1094 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1095 priv->txvipring, priv->txvipringdma);
1096 buffer_free(dev,&(priv->txvipbufs),priv->txbuffsize,1);
1097
1098 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1099 priv->txvopring, priv->txvopringdma);
1100 buffer_free(dev,&(priv->txvopbufs),priv->txbuffsize,1);
1101
1102 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1103 priv->txhpring, priv->txhpringdma);
1104 buffer_free(dev,&(priv->txhpbufs),priv->txbuffsize,1);
1105
1106 count = priv->txbeaconcount;
1107 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1108 priv->txbeaconring, priv->txbeaconringdma);
1109 buffer_free(dev,&(priv->txbeaconbufs),priv->txbuffsize,1);
1110}
1111
c8d86be3
GKH
1112void free_rx_desc_ring(struct net_device *dev)
1113{
1114 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1115 struct pci_dev *pdev = priv->pdev;
c8d86be3
GKH
1116 int count = priv->rxringcount;
1117
c8d86be3
GKH
1118 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1119 priv->rxring, priv->rxringdma);
c8d86be3
GKH
1120
1121 buffer_free(dev,&(priv->rxbuffer),priv->rxbuffersize,0);
1122}
1123
c8d86be3
GKH
1124short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count)
1125{
1126 int i;
1127 u32 *desc;
1128 u32 *tmp;
1129 dma_addr_t dma_desc,dma_tmp;
1130 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1131 struct pci_dev *pdev=priv->pdev;
1132 void *buf;
1133 u8 rx_desc_size;
1134
c8d86be3 1135 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3
GKH
1136
1137 if((bufsize & 0xfff) != bufsize){
1138 DMESGE ("RX buffer allocation too large");
1139 return -1;
1140 }
1141
1142 desc = (u32*)pci_alloc_consistent(pdev,sizeof(u32)*rx_desc_size*count+256,
1143 &dma_desc);
1144
fd882783 1145 if (dma_desc & 0xff)
c8d86be3
GKH
1146 /*
1147 * descriptor's buffer must be 256 byte aligned
1148 * should never happen since we specify the DMA mask
1149 */
be286fd2 1150 WARN(1, "DMA buffer is not aligned\n");
c8d86be3
GKH
1151
1152 priv->rxring=desc;
1153 priv->rxringdma=dma_desc;
1154 tmp=desc;
1155
fd882783 1156 for (i = 0; i < count; i++) {
c8d86be3
GKH
1157 if ((buf= kmalloc(bufsize * sizeof(u8),GFP_ATOMIC)) == NULL){
1158 DMESGE("Failed to kmalloc RX buffer");
1159 return -1;
1160 }
1161
1162 dma_tmp = pci_map_single(pdev,buf,bufsize * sizeof(u8),
1163 PCI_DMA_FROMDEVICE);
1164
c8d86be3
GKH
1165 if(-1 == buffer_add(&(priv->rxbuffer), buf,dma_tmp,
1166 &(priv->rxbufferhead))){
1167 DMESGE("Unable to allocate mem RX buf");
1168 return -1;
1169 }
1170 *tmp = 0; //zero pads the header of the descriptor
1171 *tmp = *tmp |( bufsize&0xfff);
1172 *(tmp+2) = (u32)dma_tmp;
1173 *tmp = *tmp |(1<<31); // descriptor void, owned by the NIC
1174
c8d86be3
GKH
1175 tmp=tmp+rx_desc_size;
1176 }
1177
1178 *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); // this is the last descriptor
1179
c8d86be3
GKH
1180 return 0;
1181}
1182
1183
1184void set_nic_rxring(struct net_device *dev)
1185{
1186 u8 pgreg;
1187 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1188
c8d86be3
GKH
1189 pgreg=read_nic_byte(dev, PGSELECT);
1190 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
1191
c8d86be3
GKH
1192 write_nic_dword(dev, RXRING_ADDR,priv->rxringdma);
1193}
1194
c8d86be3
GKH
1195void rtl8180_reset(struct net_device *dev)
1196{
c8d86be3
GKH
1197 u8 cr;
1198
c8d86be3
GKH
1199 rtl8180_irq_disable(dev);
1200
1201 cr=read_nic_byte(dev,CMD);
1202 cr = cr & 2;
1203 cr = cr | (1<<CMD_RST_SHIFT);
1204 write_nic_byte(dev,CMD,cr);
1205
1206 force_pci_posting(dev);
1207
1208 mdelay(200);
1209
1210 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1211 DMESGW("Card reset timeout!");
1212 else
1213 DMESG("Card successfully reset");
1214
c8d86be3
GKH
1215 rtl8180_set_mode(dev,EPROM_CMD_LOAD);
1216 force_pci_posting(dev);
1217 mdelay(200);
c8d86be3
GKH
1218}
1219
1220inline u16 ieeerate2rtlrate(int rate)
1221{
1222 switch(rate){
1223 case 10:
fd882783 1224 return 0;
c8d86be3 1225 case 20:
fd882783 1226 return 1;
c8d86be3 1227 case 55:
fd882783 1228 return 2;
c8d86be3 1229 case 110:
fd882783 1230 return 3;
c8d86be3 1231 case 60:
fd882783 1232 return 4;
c8d86be3 1233 case 90:
fd882783 1234 return 5;
c8d86be3 1235 case 120:
fd882783 1236 return 6;
c8d86be3 1237 case 180:
fd882783 1238 return 7;
c8d86be3 1239 case 240:
fd882783 1240 return 8;
c8d86be3 1241 case 360:
fd882783 1242 return 9;
c8d86be3 1243 case 480:
fd882783 1244 return 10;
c8d86be3 1245 case 540:
fd882783 1246 return 11;
c8d86be3 1247 default:
fd882783 1248 return 3;
c8d86be3
GKH
1249 }
1250}
1251
1252static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540,720};
fd882783 1253
c8d86be3
GKH
1254inline u16 rtl8180_rate2rate(short rate)
1255{
fd882783
BZ
1256 if (rate > 12)
1257 return 10;
c8d86be3
GKH
1258 return rtl_rate[rate];
1259}
fd882783 1260
c8d86be3
GKH
1261inline u8 rtl8180_IsWirelessBMode(u16 rate)
1262{
1263 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
1264 return 1;
fd882783
BZ
1265 else
1266 return 0;
c8d86be3 1267}
fd882783 1268
c8d86be3 1269u16 N_DBPSOfRate(u16 DataRate);
fd882783
BZ
1270
1271u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame,
1272 u8 bShortPreamble)
c8d86be3
GKH
1273{
1274 u16 FrameTime;
1275 u16 N_DBPS;
1276 u16 Ceiling;
1277
fd882783
BZ
1278 if (rtl8180_IsWirelessBMode(DataRate)) {
1279 if (bManagementFrame || !bShortPreamble || DataRate == 10)
1280 /* long preamble */
c8d86be3 1281 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
c8d86be3 1282 else
fd882783 1283 /* short preamble */
c8d86be3 1284 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
fd882783
BZ
1285
1286 if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */
1287 FrameTime++;
1288 } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */
c8d86be3
GKH
1289 N_DBPS = N_DBPSOfRate(DataRate);
1290 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
1291 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
1292 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
1293 }
1294 return FrameTime;
1295}
fd882783 1296
c8d86be3
GKH
1297u16 N_DBPSOfRate(u16 DataRate)
1298{
1299 u16 N_DBPS = 24;
1300
fd882783
BZ
1301 switch (DataRate) {
1302 case 60:
1303 N_DBPS = 24;
1304 break;
1305 case 90:
1306 N_DBPS = 36;
1307 break;
1308 case 120:
1309 N_DBPS = 48;
1310 break;
1311 case 180:
1312 N_DBPS = 72;
1313 break;
1314 case 240:
1315 N_DBPS = 96;
1316 break;
1317 case 360:
1318 N_DBPS = 144;
1319 break;
1320 case 480:
1321 N_DBPS = 192;
1322 break;
1323 case 540:
1324 N_DBPS = 216;
1325 break;
1326 default:
1327 break;
1328 }
c8d86be3 1329
fd882783 1330 return N_DBPS;
c8d86be3
GKH
1331}
1332
c8d86be3
GKH
1333//
1334// Description:
1335// For Netgear case, they want good-looking singal strength.
c8d86be3 1336//
fd882783 1337long NetgearSignalStrengthTranslate(long LastSS, long CurrSS)
c8d86be3
GKH
1338{
1339 long RetSS;
1340
1341 // Step 1. Scale mapping.
fd882783 1342 if (CurrSS >= 71 && CurrSS <= 100)
c8d86be3 1343 RetSS = 90 + ((CurrSS - 70) / 3);
fd882783 1344 else if (CurrSS >= 41 && CurrSS <= 70)
c8d86be3 1345 RetSS = 78 + ((CurrSS - 40) / 3);
fd882783 1346 else if (CurrSS >= 31 && CurrSS <= 40)
c8d86be3 1347 RetSS = 66 + (CurrSS - 30);
fd882783 1348 else if (CurrSS >= 21 && CurrSS <= 30)
c8d86be3 1349 RetSS = 54 + (CurrSS - 20);
fd882783 1350 else if (CurrSS >= 5 && CurrSS <= 20)
c8d86be3 1351 RetSS = 42 + (((CurrSS - 5) * 2) / 3);
fd882783 1352 else if (CurrSS == 4)
c8d86be3 1353 RetSS = 36;
fd882783 1354 else if (CurrSS == 3)
c8d86be3 1355 RetSS = 27;
fd882783 1356 else if (CurrSS == 2)
c8d86be3 1357 RetSS = 18;
fd882783 1358 else if (CurrSS == 1)
c8d86be3 1359 RetSS = 9;
c8d86be3 1360 else
c8d86be3 1361 RetSS = CurrSS;
c8d86be3
GKH
1362
1363 // Step 2. Smoothing.
1364 if(LastSS > 0)
c8d86be3 1365 RetSS = ((LastSS * 5) + (RetSS)+ 5) / 6;
c8d86be3
GKH
1366
1367 return RetSS;
1368}
fd882783 1369
c8d86be3
GKH
1370//
1371// Description:
1372// Translate 0-100 signal strength index into dBm.
1373//
fd882783 1374long TranslateToDbm8185(u8 SignalStrengthIndex)
c8d86be3 1375{
fd882783 1376 long SignalPower;
c8d86be3
GKH
1377
1378 // Translate to dBm (x=0.5y-95).
1379 SignalPower = (long)((SignalStrengthIndex + 1) >> 1);
1380 SignalPower -= 95;
1381
1382 return SignalPower;
1383}
fd882783 1384
c8d86be3
GKH
1385//
1386// Description:
1387// Perform signal smoothing for dynamic mechanism.
1388// This is different with PerformSignalSmoothing8185 in smoothing fomula.
1389// No dramatic adjustion is apply because dynamic mechanism need some degree
1390// of correctness. Ported from 8187B.
c8d86be3 1391//
fd882783
BZ
1392void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv,
1393 bool bCckRate)
c8d86be3 1394{
c8d86be3
GKH
1395 // Determin the current packet is CCK rate.
1396 priv->bCurCCKPkt = bCckRate;
1397
fd882783 1398 if (priv->UndecoratedSmoothedSS >= 0)
c8d86be3 1399 priv->UndecoratedSmoothedSS = ( (priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10) ) / 6;
c8d86be3 1400 else
c8d86be3 1401 priv->UndecoratedSmoothedSS = priv->SignalStrength * 10;
c8d86be3
GKH
1402
1403 priv->UndercorateSmoothedRxPower = ( (priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower* 11)) / 60;
1404
fd882783 1405 if (bCckRate)
c8d86be3 1406 priv->CurCCKRSSI = priv->RSSI;
c8d86be3 1407 else
c8d86be3 1408 priv->CurCCKRSSI = 0;
c8d86be3
GKH
1409}
1410
c8d86be3
GKH
1411
1412/* This is rough RX isr handling routine*/
1413void rtl8180_rx(struct net_device *dev)
1414{
1415 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1416 struct sk_buff *tmp_skb;
c8d86be3
GKH
1417 short first,last;
1418 u32 len;
1419 int lastlen;
1420 unsigned char quality, signal;
1421 u8 rate;
c8d86be3
GKH
1422 u32 *tmp,*tmp2;
1423 u8 rx_desc_size;
1424 u8 padding;
c8d86be3
GKH
1425 char rxpower = 0;
1426 u32 RXAGC = 0;
1427 long RxAGC_dBm = 0;
1428 u8 LNA=0, BB=0;
1429 u8 LNA_gain[4]={02, 17, 29, 39};
1430 u8 Antenna = 0;
0604384d 1431 struct ieee80211_hdr_4addr *hdr;
c8d86be3
GKH
1432 u16 fc,type;
1433 u8 bHwError = 0,bCRC = 0,bICV = 0;
c8d86be3
GKH
1434 bool bCckRate = false;
1435 u8 RSSI = 0;
fd882783 1436 long SignalStrengthIndex = 0;
c8d86be3
GKH
1437 struct ieee80211_rx_stats stats = {
1438 .signal = 0,
1439 .noise = -98,
1440 .rate = 0,
c8d86be3
GKH
1441 .freq = IEEE80211_24GHZ_BAND,
1442 };
1443
c8d86be3
GKH
1444 stats.nic_type = NIC_8185B;
1445 rx_desc_size = 8;
1446
c8d86be3 1447 if ((*(priv->rxringtail)) & (1<<31)) {
c8d86be3
GKH
1448 /* we have got an RX int, but the descriptor
1449 * we are pointing is empty*/
1450
1451 priv->stats.rxnodata++;
1452 priv->ieee80211->stats.rx_errors++;
1453
c8d86be3
GKH
1454 tmp2 = NULL;
1455 tmp = priv->rxringtail;
1456 do{
1457 if(tmp == priv->rxring)
c8d86be3
GKH
1458 tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size;
1459 else
1460 tmp -= rx_desc_size;
1461
1462 if(! (*tmp & (1<<31)))
1463 tmp2 = tmp;
1464 }while(tmp != priv->rxring);
1465
1466 if(tmp2) priv->rxringtail = tmp2;
c8d86be3
GKH
1467 }
1468
1469 /* while there are filled descriptors */
1470 while(!(*(priv->rxringtail) & (1<<31))){
1471 if(*(priv->rxringtail) & (1<<26))
1472 DMESGW("RX buffer overflow");
1473 if(*(priv->rxringtail) & (1<<12))
1474 priv->stats.rxicverr++;
1475
1476 if(*(priv->rxringtail) & (1<<27)){
1477 priv->stats.rxdmafail++;
1478 //DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail);
1479 goto drop;
1480 }
1481
1482 pci_dma_sync_single_for_cpu(priv->pdev,
1483 priv->rxbuffer->dma,
1484 priv->rxbuffersize * \
1485 sizeof(u8),
1486 PCI_DMA_FROMDEVICE);
1487
1488 first = *(priv->rxringtail) & (1<<29) ? 1:0;
1489 if(first) priv->rx_prevlen=0;
1490
1491 last = *(priv->rxringtail) & (1<<28) ? 1:0;
1492 if(last){
1493 lastlen=((*priv->rxringtail) &0xfff);
1494
1495 /* if the last descriptor (that should
1496 * tell us the total packet len) tell
1497 * us something less than the descriptors
1498 * len we had until now, then there is some
1499 * problem..
1500 * workaround to prevent kernel panic
1501 */
1502 if(lastlen < priv->rx_prevlen)
1503 len=0;
1504 else
1505 len=lastlen-priv->rx_prevlen;
1506
1507 if(*(priv->rxringtail) & (1<<13)) {
c8d86be3
GKH
1508 if ((*(priv->rxringtail) & 0xfff) <500)
1509 priv->stats.rxcrcerrmin++;
1510 else if ((*(priv->rxringtail) & 0x0fff) >1000)
1511 priv->stats.rxcrcerrmax++;
1512 else
1513 priv->stats.rxcrcerrmid++;
1514
1515 }
1516
1517 }else{
1518 len = priv->rxbuffersize;
1519 }
1520
c8d86be3
GKH
1521 if(first && last) {
1522 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1523 }else if(first) {
1524 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1525 if(padding) {
1526 len -= 2;
1527 }
1528 }else {
1529 padding = 0;
1530 }
c8d86be3 1531 padding = 0;
c8d86be3
GKH
1532 priv->rx_prevlen+=len;
1533
1534 if(priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100){
1535 /* HW is probably passing several buggy frames
1536 * without FD or LD flag set.
1537 * Throw this garbage away to prevent skb
1538 * memory exausting
1539 */
1540 if(!priv->rx_skb_complete)
1541 dev_kfree_skb_any(priv->rx_skb);
1542 priv->rx_skb_complete = 1;
1543 }
1544
c8d86be3 1545 signal=(unsigned char)(((*(priv->rxringtail+3))& (0x00ff0000))>>16);
1994130e 1546 signal = (signal & 0xfe) >> 1;
c8d86be3
GKH
1547
1548 quality=(unsigned char)((*(priv->rxringtail+3)) & (0xff));
1549
1550 stats.mac_time[0] = *(priv->rxringtail+1);
1551 stats.mac_time[1] = *(priv->rxringtail+2);
1552 rxpower =((char)(((*(priv->rxringtail+4))& (0x00ff0000))>>16))/2 - 42;
1553 RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>> 8)) & (0x7f);
1554
c8d86be3
GKH
1555 rate=((*(priv->rxringtail)) &
1556 ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20;
1557
1558 stats.rate = rtl8180_rate2rate(rate);
c8d86be3 1559 Antenna = (((*(priv->rxringtail +3))& (0x00008000)) == 0 )? 0:1 ;
c8d86be3
GKH
1560 if(!rtl8180_IsWirelessBMode(stats.rate))
1561 { // OFDM rate.
1562
1563 RxAGC_dBm = rxpower+1; //bias
1564 }
1565 else
1566 { // CCK rate.
1567 RxAGC_dBm = signal;//bit 0 discard
1568
1569 LNA = (u8) (RxAGC_dBm & 0x60 ) >> 5 ; //bit 6~ bit 5
1570 BB = (u8) (RxAGC_dBm & 0x1F); // bit 4 ~ bit 0
1571
1572 RxAGC_dBm = -( LNA_gain[LNA] + (BB *2) ); //Pin_11b=-(LNA_gain+BB_gain) (dBm)
1573
1574 RxAGC_dBm +=4; //bias
1575 }
1576
1577 if(RxAGC_dBm & 0x80) //absolute value
1578 RXAGC= ~(RxAGC_dBm)+1;
1579 bCckRate = rtl8180_IsWirelessBMode(stats.rate);
1580 // Translate RXAGC into 1-100.
1581 if(!rtl8180_IsWirelessBMode(stats.rate))
1582 { // OFDM rate.
1583 if(RXAGC>90)
1584 RXAGC=90;
1585 else if(RXAGC<25)
1586 RXAGC=25;
1587 RXAGC=(90-RXAGC)*100/65;
1588 }
1589 else
1590 { // CCK rate.
1591 if(RXAGC>95)
1592 RXAGC=95;
1593 else if(RXAGC<30)
1594 RXAGC=30;
1595 RXAGC=(95-RXAGC)*100/65;
1596 }
1597 priv->SignalStrength = (u8)RXAGC;
1994130e 1598 priv->RecvSignalPower = RxAGC_dBm;
c8d86be3
GKH
1599 priv->RxPower = rxpower;
1600 priv->RSSI = RSSI;
1994130e 1601 /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */
c8d86be3
GKH
1602 if(quality >= 127)
1603 quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now;
1604 else if(quality < 27)
1605 quality = 100;
1606 else
1607 quality = 127 - quality;
1608 priv->SignalQuality = quality;
c8d86be3
GKH
1609
1610 stats.signal = (u8)quality;//priv->wstats.qual.level = priv->SignalStrength;
1611 stats.signalstrength = RXAGC;
1612 if(stats.signalstrength > 100)
1613 stats.signalstrength = 100;
1614 stats.signalstrength = (stats.signalstrength * 70)/100 + 30;
1615 // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength);
1616 stats.rssi = priv->wstats.qual.qual = priv->SignalQuality;
1617 stats.noise = priv->wstats.qual.noise = 100 - priv ->wstats.qual.qual;
c8d86be3
GKH
1618 bHwError = (((*(priv->rxringtail))& (0x00000fff)) == 4080)| (((*(priv->rxringtail))& (0x04000000)) != 0 )
1619 | (((*(priv->rxringtail))& (0x08000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x10000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x20000000)) != 0 );
1620 bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13;
1621 bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12;
0604384d 1622 hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf;
c8d86be3
GKH
1623 fc = le16_to_cpu(hdr->frame_ctl);
1624 type = WLAN_FC_GET_TYPE(fc);
1625
1626 if((IEEE80211_FTYPE_CTL != type) &&
1627 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
1628 && (!bHwError) && (!bCRC)&& (!bICV))
1629 {
1994130e
LF
1630 /* Perform signal smoothing for dynamic
1631 * mechanism on demand. This is different
1632 * with PerformSignalSmoothing8185 in smoothing
1633 * fomula. No dramatic adjustion is apply
1634 * because dynamic mechanism need some degree
1635 * of correctness. */
c8d86be3
GKH
1636 PerformUndecoratedSignalSmoothing8185(priv,bCckRate);
1637 //
1638 // For good-looking singal strength.
1639 //
1640 SignalStrengthIndex = NetgearSignalStrengthTranslate(
1641 priv->LastSignalStrengthInPercent,
1642 priv->SignalStrength);
1643
1644 priv->LastSignalStrengthInPercent = SignalStrengthIndex;
1645 priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex);
1646 //
1647 // We need more correct power of received packets and the "SignalStrength" of RxStats is beautified,
1648 // so we record the correct power here.
1649 //
1650 priv->Stats_SignalQuality =(long) (priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6;
1651 priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower -1) / 6;
1652
1653 // Figure out which antenna that received the lasted packet.
1654 priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main.
c8d86be3
GKH
1655 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength);
1656 }
1657
c8d86be3
GKH
1658 if(first){
1659 if(!priv->rx_skb_complete){
1660 /* seems that HW sometimes fails to reiceve and
1661 doesn't provide the last descriptor */
c8d86be3
GKH
1662 dev_kfree_skb_any(priv->rx_skb);
1663 priv->stats.rxnolast++;
c8d86be3
GKH
1664 }
1665 /* support for prism header has been originally added by Christian */
1666 if(priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1667
c8d86be3
GKH
1668 }else{
1669 priv->rx_skb = dev_alloc_skb(len+2);
1670 if( !priv->rx_skb) goto drop;
c8d86be3
GKH
1671 }
1672
1673 priv->rx_skb_complete=0;
1674 priv->rx_skb->dev=dev;
1675 }else{
1676 /* if we are here we should have already RXed
1677 * the first frame.
1678 * If we get here and the skb is not allocated then
1679 * we have just throw out garbage (skb not allocated)
1680 * and we are still rxing garbage....
1681 */
1682 if(!priv->rx_skb_complete){
1683
1684 tmp_skb= dev_alloc_skb(priv->rx_skb->len +len+2);
1685
1686 if(!tmp_skb) goto drop;
1687
1688 tmp_skb->dev=dev;
c8d86be3 1689
c8d86be3
GKH
1690 memcpy(skb_put(tmp_skb,priv->rx_skb->len),
1691 priv->rx_skb->data,
1692 priv->rx_skb->len);
c8d86be3
GKH
1693
1694 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH
1695
1696 priv->rx_skb=tmp_skb;
1697 }
1698 }
ff954853 1699
c8d86be3 1700 if(!priv->rx_skb_complete) {
c8d86be3
GKH
1701 if(padding) {
1702 memcpy(skb_put(priv->rx_skb,len),
1703 (((unsigned char *)priv->rxbuffer->buf) + 2),len);
1704 } else {
c8d86be3
GKH
1705 memcpy(skb_put(priv->rx_skb,len),
1706 priv->rxbuffer->buf,len);
c8d86be3 1707 }
c8d86be3 1708 }
c8d86be3
GKH
1709
1710 if(last && !priv->rx_skb_complete){
c8d86be3
GKH
1711 if(priv->rx_skb->len > 4)
1712 skb_trim(priv->rx_skb,priv->rx_skb->len-4);
df574b8e 1713 if(!ieee80211_rtl_rx(priv->ieee80211,
1994130e 1714 priv->rx_skb, &stats))
c8d86be3 1715 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH
1716 priv->rx_skb_complete=1;
1717 }
1718
c8d86be3
GKH
1719 pci_dma_sync_single_for_device(priv->pdev,
1720 priv->rxbuffer->dma,
1721 priv->rxbuffersize * \
1722 sizeof(u8),
1723 PCI_DMA_FROMDEVICE);
1724
bbc9a991 1725drop: // this is used when we have not enough mem
c8d86be3
GKH
1726 /* restore the descriptor */
1727 *(priv->rxringtail+2)=priv->rxbuffer->dma;
1728 *(priv->rxringtail)=*(priv->rxringtail) &~ 0xfff;
1729 *(priv->rxringtail)=
1730 *(priv->rxringtail) | priv->rxbuffersize;
1731
1732 *(priv->rxringtail)=
1733 *(priv->rxringtail) | (1<<31);
c8d86be3
GKH
1734
1735 priv->rxringtail+=rx_desc_size;
1736 if(priv->rxringtail >=
1737 (priv->rxring)+(priv->rxringcount )*rx_desc_size)
1738 priv->rxringtail=priv->rxring;
1739
c8d86be3 1740 priv->rxbuffer=(priv->rxbuffer->next);
c8d86be3 1741 }
c8d86be3
GKH
1742}
1743
1744
1745void rtl8180_dma_kick(struct net_device *dev, int priority)
1746{
1747 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1748
1749 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
1750 write_nic_byte(dev, TX_DMA_POLLING,
1751 (1 << (priority + 1)) | priv->dma_poll_mask);
1752 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1753
1754 force_pci_posting(dev);
1755}
1756
c8d86be3
GKH
1757void rtl8180_data_hard_stop(struct net_device *dev)
1758{
1759 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1760
1761 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
1762 priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ;
1763 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH
1764 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1765}
1766
c8d86be3
GKH
1767void rtl8180_data_hard_resume(struct net_device *dev)
1768{
1769 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1770
1771 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH
1772 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ);
1773 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH
1774 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1775}
1776
c8d86be3
GKH
1777/* this function TX data frames when the ieee80211 stack requires this.
1778 * It checks also if we need to stop the ieee tx queue, eventually do it
1779 */
1780void rtl8180_hard_data_xmit(struct sk_buff *skb,struct net_device *dev, int
1781rate)
1782{
1783 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1784 int mode;
1785 struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data;
1786 short morefrag = (h->frame_ctl) & IEEE80211_FCTL_MOREFRAGS;
1787 unsigned long flags;
1788 int priority;
c8d86be3
GKH
1789
1790 mode = priv->ieee80211->iw_mode;
1791
1792 rate = ieeerate2rtlrate(rate);
1793 /*
1794 * This function doesn't require lock because we make
1795 * sure it's called with the tx_lock already acquired.
bbc9a991
AGR
1796 * this come from the kernel's hard_xmit callback (through
1797 * the ieee stack, or from the try_wake_queue (again through
c8d86be3
GKH
1798 * the ieee stack.
1799 */
c8d86be3 1800 priority = AC2Q(skb->priority);
c8d86be3
GKH
1801 spin_lock_irqsave(&priv->tx_lock,flags);
1802
1803 if(priv->ieee80211->bHwRadioOff)
1804 {
1805 spin_unlock_irqrestore(&priv->tx_lock,flags);
1806
1807 return;
1808 }
1809
c8d86be3 1810 if (!check_nic_enought_desc(dev, priority)){
c8d86be3
GKH
1811 DMESGW("Error: no descriptor left by previous TX (avail %d) ",
1812 get_curr_tx_free_desc(dev, priority));
df574b8e 1813 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3
GKH
1814 }
1815 rtl8180_tx(dev, skb->data, skb->len, priority, morefrag,0,rate);
1816 if (!check_nic_enought_desc(dev, priority))
df574b8e 1817 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3 1818
c8d86be3 1819 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3
GKH
1820}
1821
1822/* This is a rough attempt to TX a frame
1823 * This is called by the ieee 80211 stack to TX management frames.
1824 * If the ring is full packet are dropped (for data frame the queue
1825 * is stopped before this can happen). For this reason it is better
1826 * if the descriptors are larger than the largest management frame
1827 * we intend to TX: i'm unsure what the HW does if it will not found
1828 * the last fragment of a frame because it has been dropped...
1829 * Since queues for Management and Data frames are different we
1830 * might use a different lock than tx_lock (for example mgmt_tx_lock)
1831 */
1832/* these function may loops if invoked with 0 descriptors or 0 len buffer*/
1833int rtl8180_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
1834{
1835 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 1836 unsigned long flags;
c8d86be3
GKH
1837 int priority;
1838
c8d86be3 1839 priority = MANAGE_PRIORITY;
c8d86be3
GKH
1840
1841 spin_lock_irqsave(&priv->tx_lock,flags);
1842
fd882783 1843 if (priv->ieee80211->bHwRadioOff) {
c8d86be3 1844 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3 1845 dev_kfree_skb_any(skb);
ec634fe3 1846 return NETDEV_TX_OK;
c8d86be3
GKH
1847 }
1848
1849 rtl8180_tx(dev, skb->data, skb->len, priority,
1850 0, 0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
1851
1852 priv->ieee80211->stats.tx_bytes+=skb->len;
1853 priv->ieee80211->stats.tx_packets++;
1854 spin_unlock_irqrestore(&priv->tx_lock,flags);
1855
1856 dev_kfree_skb_any(skb);
ec634fe3 1857 return NETDEV_TX_OK;
c8d86be3
GKH
1858}
1859
1860// longpre 144+48 shortpre 72+24
1861u16 rtl8180_len2duration(u32 len, short rate,short* ext)
1862{
1863 u16 duration;
1864 u16 drift;
1865 *ext=0;
1866
1867 switch(rate){
1868 case 0://1mbps
1869 *ext=0;
1870 duration = ((len+4)<<4) /0x2;
1871 drift = ((len+4)<<4) % 0x2;
1872 if(drift ==0 ) break;
1873 duration++;
1874 break;
c8d86be3
GKH
1875 case 1://2mbps
1876 *ext=0;
1877 duration = ((len+4)<<4) /0x4;
1878 drift = ((len+4)<<4) % 0x4;
1879 if(drift ==0 ) break;
1880 duration++;
1881 break;
c8d86be3
GKH
1882 case 2: //5.5mbps
1883 *ext=0;
1884 duration = ((len+4)<<4) /0xb;
1885 drift = ((len+4)<<4) % 0xb;
1886 if(drift ==0 )
1887 break;
1888 duration++;
1889 break;
c8d86be3
GKH
1890 default:
1891 case 3://11mbps
1892 *ext=0;
1893 duration = ((len+4)<<4) /0x16;
1894 drift = ((len+4)<<4) % 0x16;
1895 if(drift ==0 )
1896 break;
1897 duration++;
1898 if(drift > 6)
1899 break;
1900 *ext=1;
1901 break;
1902 }
1903
1904 return duration;
1905}
1906
c8d86be3
GKH
1907void rtl8180_prepare_beacon(struct net_device *dev)
1908{
c8d86be3 1909 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
1910 struct sk_buff *skb;
1911
1912 u16 word = read_nic_word(dev, BcnItv);
1913 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
1914 word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval);//0x64;
1915 write_nic_word(dev, BcnItv, word);
1916
c8d86be3
GKH
1917 skb = ieee80211_get_beacon(priv->ieee80211);
1918 if(skb){
1919 rtl8180_tx(dev,skb->data,skb->len,BEACON_PRIORITY,
1920 0,0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
1921 dev_kfree_skb_any(skb);
1922 }
c8d86be3
GKH
1923}
1924
1925/* This function do the real dirty work: it enqueues a TX command
1926 * descriptor in the ring buffer, copyes the frame in a TX buffer
1927 * and kicks the NIC to ensure it does the DMA transfer.
1928 */
1929short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority,
1930 short morefrag, short descfrag, int rate)
1931{
1932 struct r8180_priv *priv = ieee80211_priv(dev);
1933 u32 *tail,*temp_tail;
1934 u32 *begin;
1935 u32 *buf;
1936 int i;
1937 int remain;
1938 int buflen;
1939 int count;
c8d86be3
GKH
1940 u16 duration;
1941 short ext;
1942 struct buffer* buflist;
c8d86be3
GKH
1943 struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf;
1944 u8 dest[ETH_ALEN];
1945 u8 bUseShortPreamble = 0;
1946 u8 bCTSEnable = 0;
1947 u8 bRTSEnable = 0;
c8d86be3
GKH
1948 u16 Duration = 0;
1949 u16 RtsDur = 0;
1950 u16 ThisFrameTime = 0;
1951 u16 TxDescDuration = 0;
1994130e 1952 u8 ownbit_flag = false;
c8d86be3
GKH
1953
1954 switch(priority) {
1955 case MANAGE_PRIORITY:
1956 tail=priv->txmapringtail;
1957 begin=priv->txmapring;
1958 buflist = priv->txmapbufstail;
1959 count = priv->txringcount;
1960 break;
c8d86be3
GKH
1961 case BK_PRIORITY:
1962 tail=priv->txbkpringtail;
1963 begin=priv->txbkpring;
1964 buflist = priv->txbkpbufstail;
1965 count = priv->txringcount;
1966 break;
c8d86be3
GKH
1967 case BE_PRIORITY:
1968 tail=priv->txbepringtail;
1969 begin=priv->txbepring;
1970 buflist = priv->txbepbufstail;
1971 count = priv->txringcount;
1972 break;
c8d86be3
GKH
1973 case VI_PRIORITY:
1974 tail=priv->txvipringtail;
1975 begin=priv->txvipring;
1976 buflist = priv->txvipbufstail;
1977 count = priv->txringcount;
1978 break;
c8d86be3
GKH
1979 case VO_PRIORITY:
1980 tail=priv->txvopringtail;
1981 begin=priv->txvopring;
1982 buflist = priv->txvopbufstail;
1983 count = priv->txringcount;
1984 break;
c8d86be3
GKH
1985 case HI_PRIORITY:
1986 tail=priv->txhpringtail;
1987 begin=priv->txhpring;
1988 buflist = priv->txhpbufstail;
1989 count = priv->txringcount;
1990 break;
c8d86be3
GKH
1991 case BEACON_PRIORITY:
1992 tail=priv->txbeaconringtail;
1993 begin=priv->txbeaconring;
1994 buflist = priv->txbeaconbufstail;
1995 count = priv->txbeaconcount;
1996 break;
c8d86be3
GKH
1997 default:
1998 return -1;
1999 break;
2000 }
2001
c8d86be3
GKH
2002 memcpy(&dest, frag_hdr->addr1, ETH_ALEN);
2003 if (is_multicast_ether_addr(dest) ||
2004 is_broadcast_ether_addr(dest))
2005 {
2006 Duration = 0;
2007 RtsDur = 0;
2008 bRTSEnable = 0;
2009 bCTSEnable = 0;
2010
2011 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2012 TxDescDuration = ThisFrameTime;
2013 } else {// Unicast packet
c8d86be3
GKH
2014 u16 AckTime;
2015
2016 //YJ,add,080828,for Keep alive
2017 priv->NumTxUnicast++;
2018
1994130e
LF
2019 /* Figure out ACK rate according to BSS basic rate
2020 * and Tx rate. */
c8d86be3 2021 AckTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
c8d86be3
GKH
2022
2023 if ( ((len + sCrcLng) > priv->rts) && priv->rts )
2024 { // RTS/CTS.
2025 u16 RtsTime, CtsTime;
2026 //u16 CtsRate;
2027 bRTSEnable = 1;
2028 bCTSEnable = 0;
2029
2030 // Rate and time required for RTS.
2031 RtsTime = ComputeTxTime( sAckCtsLng/8,priv->ieee80211->basic_rate, 0, 0);
2032 // Rate and time required for CTS.
2033 CtsTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
2034
2035 // Figure out time required to transmit this frame.
2036 ThisFrameTime = ComputeTxTime(len + sCrcLng,
2037 rtl8180_rate2rate(rate),
2038 0,
2039 bUseShortPreamble);
2040
2041 // RTS-CTS-ThisFrame-ACK.
2042 RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime;
2043
2044 TxDescDuration = RtsTime + RtsDur;
2045 }
2046 else {// Normal case.
2047 bCTSEnable = 0;
2048 bRTSEnable = 0;
2049 RtsDur = 0;
2050
2051 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2052 TxDescDuration = ThisFrameTime + aSifsTime + AckTime;
2053 }
2054
2055 if(!(frag_hdr->frame_ctl & IEEE80211_FCTL_MOREFRAGS)) { //no more fragment
2056 // ThisFrame-ACK.
2057 Duration = aSifsTime + AckTime;
2058 } else { // One or more fragments remained.
2059 u16 NextFragTime;
2060 NextFragTime = ComputeTxTime( len + sCrcLng, //pretend following packet length equal current packet
2061 rtl8180_rate2rate(rate),
2062 0,
2063 bUseShortPreamble );
2064
2065 //ThisFrag-ACk-NextFrag-ACK.
2066 Duration = NextFragTime + 3*aSifsTime + 2*AckTime;
2067 }
2068
2069 } // End of Unicast packet
2070
2071 frag_hdr->duration_id = Duration;
c8d86be3
GKH
2072
2073 buflen=priv->txbuffsize;
2074 remain=len;
2075 temp_tail = tail;
fd882783 2076
c8d86be3 2077 while(remain!=0){
c8d86be3
GKH
2078 mb();
2079 if(!buflist){
2080 DMESGE("TX buffer error, cannot TX frames. pri %d.", priority);
c8d86be3
GKH
2081 return -1;
2082 }
2083 buf=buflist->buf;
2084
fd882783
BZ
2085 if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) {
2086 DMESGW("No more TX desc, returning %x of %x",
2087 remain, len);
2088 priv->stats.txrdu++;
c8d86be3 2089 return remain;
c8d86be3
GKH
2090 }
2091
2092 *tail= 0; // zeroes header
2093 *(tail+1) = 0;
2094 *(tail+3) = 0;
2095 *(tail+5) = 0;
2096 *(tail+6) = 0;
2097 *(tail+7) = 0;
2098
d44eb889
LF
2099 /*FIXME: this should be triggered by HW encryption parameters.*/
2100 *tail |= (1<<15); /* no encrypt */
fd882783 2101
c8d86be3 2102 if(remain==len && !descfrag) {
1994130e 2103 ownbit_flag = false;
c8d86be3
GKH
2104 *tail = *tail| (1<<29) ; //fist segment of the packet
2105 *tail = *tail |(len);
2106 } else {
2107 ownbit_flag = true;
2108 }
2109
2110 for(i=0;i<buflen&& remain >0;i++,remain--){
2111 ((u8*)buf)[i]=txbuf[i]; //copy data into descriptor pointed DMAble buffer
2112 if(remain == 4 && i+4 >= buflen) break;
2113 /* ensure the last desc has at least 4 bytes payload */
2114
2115 }
2116 txbuf = txbuf + i;
2117 *(tail+3)=*(tail+3) &~ 0xfff;
2118 *(tail+3)=*(tail+3) | i; // buffer lenght
2119 // Use short preamble or not
2120 if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE)
2121 if (priv->plcp_preamble_mode==1 && rate!=0) // short mode now, not long!
b3184e1e 2122 ;// *tail |= (1<<16); // enable short preamble mode.
c8d86be3 2123
c8d86be3
GKH
2124 if(bCTSEnable) {
2125 *tail |= (1<<18);
2126 }
2127
2128 if(bRTSEnable) //rts enable
2129 {
2130 *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19);//RTS RATE
2131 *tail |= (1<<23);//rts enable
2132 *(tail+1) |=(RtsDur&0xffff);//RTS Duration
2133 }
2134 *(tail+3) |= ((TxDescDuration&0xffff)<<16); //DURATION
2135// *(tail+3) |= (0xe6<<16);
2136 *(tail+5) |= (11<<8);//(priv->retry_data<<8); //retry lim ;
c8d86be3
GKH
2137
2138 *tail = *tail | ((rate&0xf) << 24);
c8d86be3
GKH
2139
2140 /* hw_plcp_len is not used for rtl8180 chip */
2141 /* FIXME */
d44eb889 2142 if (!priv->hw_plcp_len) {
fd882783 2143 duration = rtl8180_len2duration(len, rate, &ext);
c8d86be3
GKH
2144 *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16);
2145 if(ext) *(tail+1) = *(tail+1) |(1<<31); //plcp length extension
2146 }
2147
2148 if(morefrag) *tail = (*tail) | (1<<17); // more fragment
2149 if(!remain) *tail = (*tail) | (1<<28); // last segment of frame
2150
c8d86be3
GKH
2151 *(tail+5) = *(tail+5)|(2<<27);
2152 *(tail+7) = *(tail+7)|(1<<4);
2153
2154 wmb();
2155 if(ownbit_flag)
2156 {
2157 *tail = *tail | (1<<31); // descriptor ready to be txed
2158 }
2159
c8d86be3
GKH
2160 if((tail - begin)/8 == count-1)
2161 tail=begin;
c8d86be3
GKH
2162 else
2163 tail=tail+8;
2164
2165 buflist=buflist->next;
2166
2167 mb();
2168
2169 switch(priority) {
2170 case MANAGE_PRIORITY:
2171 priv->txmapringtail=tail;
2172 priv->txmapbufstail=buflist;
2173 break;
c8d86be3
GKH
2174 case BK_PRIORITY:
2175 priv->txbkpringtail=tail;
2176 priv->txbkpbufstail=buflist;
2177 break;
c8d86be3
GKH
2178 case BE_PRIORITY:
2179 priv->txbepringtail=tail;
2180 priv->txbepbufstail=buflist;
2181 break;
c8d86be3
GKH
2182 case VI_PRIORITY:
2183 priv->txvipringtail=tail;
2184 priv->txvipbufstail=buflist;
2185 break;
c8d86be3
GKH
2186 case VO_PRIORITY:
2187 priv->txvopringtail=tail;
2188 priv->txvopbufstail=buflist;
2189 break;
c8d86be3
GKH
2190 case HI_PRIORITY:
2191 priv->txhpringtail=tail;
2192 priv->txhpbufstail = buflist;
2193 break;
c8d86be3
GKH
2194 case BEACON_PRIORITY:
2195 /* the HW seems to be happy with the 1st
2196 * descriptor filled and the 2nd empty...
2197 * So always update descriptor 1 and never
2198 * touch 2nd
2199 */
c8d86be3 2200 break;
c8d86be3 2201 }
c8d86be3
GKH
2202 }
2203 *temp_tail = *temp_tail | (1<<31); // descriptor ready to be txed
2204 rtl8180_dma_kick(dev,priority);
c8d86be3
GKH
2205
2206 return 0;
c8d86be3
GKH
2207}
2208
c8d86be3
GKH
2209void rtl8180_irq_rx_tasklet(struct r8180_priv * priv);
2210
c8d86be3
GKH
2211void rtl8180_link_change(struct net_device *dev)
2212{
2213 struct r8180_priv *priv = ieee80211_priv(dev);
2214 u16 beacon_interval;
c8d86be3 2215 struct ieee80211_network *net = &priv->ieee80211->current_network;
c8d86be3 2216
fd882783 2217 rtl8180_update_msr(dev);
c8d86be3
GKH
2218
2219 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2220
2221 write_nic_dword(dev,BSSID,((u32*)net->bssid)[0]);
2222 write_nic_word(dev,BSSID+4,((u16*)net->bssid)[2]);
2223
c8d86be3
GKH
2224 beacon_interval = read_nic_dword(dev,BEACON_INTERVAL);
2225 beacon_interval &= ~ BEACON_INTERVAL_MASK;
2226 beacon_interval |= net->beacon_interval;
2227 write_nic_dword(dev, BEACON_INTERVAL, beacon_interval);
2228
2229 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
2230
d44eb889 2231 rtl8180_set_chan(dev, priv->chan);
c8d86be3
GKH
2232}
2233
2234void rtl8180_rq_tx_ack(struct net_device *dev){
2235
2236 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 2237
c8d86be3
GKH
2238 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)|CONFIG4_PWRMGT);
2239 priv->ack_tx_to_ieee = 1;
2240}
2241
2242short rtl8180_is_tx_queue_empty(struct net_device *dev){
2243
2244 struct r8180_priv *priv = ieee80211_priv(dev);
2245 u32* d;
2246
2247 for (d = priv->txmapring;
2248 d < priv->txmapring + priv->txringcount;d+=8)
2249 if(*d & (1<<31)) return 0;
2250
2251 for (d = priv->txbkpring;
2252 d < priv->txbkpring + priv->txringcount;d+=8)
2253 if(*d & (1<<31)) return 0;
2254
2255 for (d = priv->txbepring;
2256 d < priv->txbepring + priv->txringcount;d+=8)
2257 if(*d & (1<<31)) return 0;
2258
2259 for (d = priv->txvipring;
2260 d < priv->txvipring + priv->txringcount;d+=8)
2261 if(*d & (1<<31)) return 0;
2262
2263 for (d = priv->txvopring;
2264 d < priv->txvopring + priv->txringcount;d+=8)
2265 if(*d & (1<<31)) return 0;
2266
2267 for (d = priv->txhpring;
2268 d < priv->txhpring + priv->txringcount;d+=8)
2269 if(*d & (1<<31)) return 0;
2270 return 1;
2271}
2272/* FIXME FIXME 5msecs is random */
2273#define HW_WAKE_DELAY 5
2274
2275void rtl8180_hw_wakeup(struct net_device *dev)
2276{
2277 unsigned long flags;
c8d86be3
GKH
2278 struct r8180_priv *priv = ieee80211_priv(dev);
2279
2280 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3 2281 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)&~CONFIG4_PWRMGT);
fd882783 2282 if (priv->rf_wakeup)
c8d86be3 2283 priv->rf_wakeup(dev);
c8d86be3
GKH
2284 spin_unlock_irqrestore(&priv->ps_lock,flags);
2285}
2286
2287void rtl8180_hw_sleep_down(struct net_device *dev)
2288{
2289 unsigned long flags;
c8d86be3
GKH
2290 struct r8180_priv *priv = ieee80211_priv(dev);
2291
2292 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3
GKH
2293 if(priv->rf_sleep)
2294 priv->rf_sleep(dev);
2295 spin_unlock_irqrestore(&priv->ps_lock,flags);
2296}
2297
c8d86be3
GKH
2298void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl)
2299{
c8d86be3 2300 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
2301 u32 rb = jiffies;
2302 unsigned long flags;
2303
2304 spin_lock_irqsave(&priv->ps_lock,flags);
2305
2306 /* Writing HW register with 0 equals to disable
2307 * the timer, that is not really what we want
2308 */
2309 tl -= MSECS(4+16+7);
2310
c8d86be3
GKH
2311 /* If the interval in witch we are requested to sleep is too
2312 * short then give up and remain awake
2313 */
2314 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
2315 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
2316 spin_unlock_irqrestore(&priv->ps_lock,flags);
2317 printk("too short to sleep\n");
2318 return;
2319 }
2320
c8d86be3
GKH
2321 {
2322 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
c8d86be3 2323
c8d86be3
GKH
2324 priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp);
2325
2326 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
2327 }
2328 /* if we suspect the TimerInt is gone beyond tl
2329 * while setting it, then give up
2330 */
fd882783 2331
c8d86be3
GKH
2332 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
2333 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
2334 spin_unlock_irqrestore(&priv->ps_lock,flags);
2335 return;
2336 }
c8d86be3
GKH
2337
2338 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq);
2339 spin_unlock_irqrestore(&priv->ps_lock,flags);
2340}
2341
c8d86be3
GKH
2342void rtl8180_wmm_param_update(struct work_struct * work)
2343{
2344 struct ieee80211_device * ieee = container_of(work, struct ieee80211_device,wmm_param_update_wq);
c8d86be3 2345 struct net_device *dev = ieee->dev;
c8d86be3
GKH
2346 u8 *ac_param = (u8 *)(ieee->current_network.wmm_param);
2347 u8 mode = ieee->current_network.mode;
2348 AC_CODING eACI;
2349 AC_PARAM AcParam;
2350 PAC_PARAM pAcParam;
2351 u8 i;
2352
c8d86be3
GKH
2353 if(!ieee->current_network.QoS_Enable){
2354 //legacy ac_xx_param update
2355 AcParam.longData = 0;
2356 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2357 AcParam.f.AciAifsn.f.ACM = 0;
2358 AcParam.f.Ecw.f.ECWmin = 3; // Follow 802.11 CWmin.
2359 AcParam.f.Ecw.f.ECWmax = 7; // Follow 802.11 CWmax.
2360 AcParam.f.TXOPLimit = 0;
2361 for(eACI = 0; eACI < AC_MAX; eACI++){
2362 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2363 {
2364 u8 u1bAIFS;
2365 u32 u4bAcParam;
2366 pAcParam = (PAC_PARAM)(&AcParam);
2367 // Retrive paramters to udpate.
2368 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN *(((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2369 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)|
2370 (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)|
2371 (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)|
2372 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2373 switch(eACI){
2374 case AC1_BK:
2375 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2376 break;
c8d86be3
GKH
2377 case AC0_BE:
2378 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2379 break;
c8d86be3
GKH
2380 case AC2_VI:
2381 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2382 break;
c8d86be3
GKH
2383 case AC3_VO:
2384 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2385 break;
c8d86be3
GKH
2386 default:
2387 printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI);
2388 break;
2389 }
2390 }
2391 }
2392 return;
2393 }
2394
2395 for(i = 0; i < AC_MAX; i++){
2396 //AcParam.longData = 0;
2397 pAcParam = (AC_PARAM * )ac_param;
2398 {
2399 AC_CODING eACI;
2400 u8 u1bAIFS;
2401 u32 u4bAcParam;
2402
2403 // Retrive paramters to udpate.
2404 eACI = pAcParam->f.AciAifsn.f.ACI;
2405 //Mode G/A: slotTimeTimer = 9; Mode B: 20
2406 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2407 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
2408 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2409 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2410 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2411
2412 switch(eACI){
2413 case AC1_BK:
2414 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2415 break;
c8d86be3
GKH
2416 case AC0_BE:
2417 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2418 break;
c8d86be3
GKH
2419 case AC2_VI:
2420 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2421 break;
c8d86be3
GKH
2422 case AC3_VO:
2423 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2424 break;
c8d86be3
GKH
2425 default:
2426 printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2427 break;
2428 }
2429 }
2430 ac_param += (sizeof(AC_PARAM));
2431 }
c8d86be3
GKH
2432}
2433
c8d86be3 2434void rtl8180_tx_irq_wq(struct work_struct *work);
c8d86be3
GKH
2435void rtl8180_restart_wq(struct work_struct *work);
2436//void rtl8180_rq_tx_ack(struct work_struct *work);
c8d86be3 2437void rtl8180_watch_dog_wq(struct work_struct *work);
c8d86be3 2438void rtl8180_hw_wakeup_wq(struct work_struct *work);
c8d86be3 2439void rtl8180_hw_sleep_wq(struct work_struct *work);
c8d86be3 2440void rtl8180_sw_antenna_wq(struct work_struct *work);
0370453f
BZ
2441void rtl8180_watch_dog(struct net_device *dev);
2442
c8d86be3
GKH
2443void watch_dog_adaptive(unsigned long data)
2444{
fd882783
BZ
2445 struct r8180_priv* priv = ieee80211_priv((struct net_device *)data);
2446
2447 if (!priv->up) {
c8d86be3
GKH
2448 DMESG("<----watch_dog_adaptive():driver is not up!\n");
2449 return;
2450 }
2451
c8d86be3 2452 // Tx High Power Mechanism.
c8d86be3 2453 if(CheckHighPower((struct net_device *)data))
c8d86be3 2454 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq);
c8d86be3 2455
c8d86be3 2456 // Tx Power Tracking on 87SE.
cffd4e16 2457 if (CheckTxPwrTracking((struct net_device *)data))
c8d86be3 2458 TxPwrTracking87SE((struct net_device *)data);
c8d86be3
GKH
2459
2460 // Perform DIG immediately.
c8d86be3 2461 if(CheckDig((struct net_device *)data) == true)
c8d86be3 2462 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq);
c8d86be3
GKH
2463 rtl8180_watch_dog((struct net_device *)data);
2464
c8d86be3
GKH
2465 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem);
2466
2467 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
2468 add_timer(&priv->watch_dog_timer);
c8d86be3
GKH
2469}
2470
c8d86be3
GKH
2471static CHANNEL_LIST ChannelPlan[] = {
2472 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, //FCC
2473 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
2474 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
2475 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Spain. Change to ETSI.
2476 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //France. Change to ETSI.
2477 {{14,36,40,44,48,52,56,60,64},9}, //MKK
2478 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},//MKK1
2479 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Israel.
2480 {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, // For 11a , TELEC
2481 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
2482 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} //world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826
2483};
2484
2485static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee)
2486{
2487 int i;
2488
2489 //lzm add 080826
2490 ieee->MinPassiveChnlNum=MAX_CHANNEL_NUMBER+1;
2491 ieee->IbssStartChnl=0;
2492
2493 switch (channel_plan)
2494 {
2495 case COUNTRY_CODE_FCC:
2496 case COUNTRY_CODE_IC:
2497 case COUNTRY_CODE_ETSI:
2498 case COUNTRY_CODE_SPAIN:
2499 case COUNTRY_CODE_FRANCE:
2500 case COUNTRY_CODE_MKK:
2501 case COUNTRY_CODE_MKK1:
2502 case COUNTRY_CODE_ISRAEL:
2503 case COUNTRY_CODE_TELEC:
2504 {
2505 Dot11d_Init(ieee);
2506 ieee->bGlobalDomain = false;
2507 if (ChannelPlan[channel_plan].Len != 0){
2508 // Clear old channel map
2509 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2510 // Set new channel map
2511 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
2512 {
2513 if(ChannelPlan[channel_plan].Channel[i] <= 14)
2514 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
2515 }
2516 }
2517 break;
2518 }
2519 case COUNTRY_CODE_GLOBAL_DOMAIN:
2520 {
2521 GET_DOT11D_INFO(ieee)->bEnabled = 0;
2522 Dot11d_Reset(ieee);
2523 ieee->bGlobalDomain = true;
2524 break;
2525 }
2526 case COUNTRY_CODE_WORLD_WIDE_13_INDEX://lzm add 080826
2527 {
2528 ieee->MinPassiveChnlNum=12;
2529 ieee->IbssStartChnl= 10;
2530 break;
2531 }
2532 default:
2533 {
2534 Dot11d_Init(ieee);
2535 ieee->bGlobalDomain = false;
2536 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2537 for (i=1;i<=14;i++)
2538 {
2539 GET_DOT11D_INFO(ieee)->channel_map[i] = 1;
2540 }
2541 break;
2542 }
2543 }
2544}
c8d86be3 2545
c8d86be3 2546void GPIOChangeRFWorkItemCallBack(struct work_struct *work);
c8d86be3
GKH
2547
2548//YJ,add,080828
2549static void rtl8180_statistics_init(struct Stats *pstats)
2550{
2551 memset(pstats, 0, sizeof(struct Stats));
2552}
fd882783 2553
c8d86be3
GKH
2554static void rtl8180_link_detect_init(plink_detect_t plink_detect)
2555{
2556 memset(plink_detect, 0, sizeof(link_detect_t));
2557 plink_detect->SlotNum = DEFAULT_SLOT_NUM;
2558}
2559//YJ,add,080828,end
2560
742821ce
LF
2561static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom)
2562{
2563 struct net_device *dev = eeprom->data;
2564 u8 reg = read_nic_byte(dev, EPROM_CMD);
2565
2566 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
2567 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
2568 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
2569 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
2570}
2571
2572static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom)
2573{
2574 struct net_device *dev = eeprom->data;
2575 u8 reg = 2 << 6;
2576
2577 if (eeprom->reg_data_in)
2578 reg |= RTL818X_EEPROM_CMD_WRITE;
2579 if (eeprom->reg_data_out)
2580 reg |= RTL818X_EEPROM_CMD_READ;
2581 if (eeprom->reg_data_clock)
2582 reg |= RTL818X_EEPROM_CMD_CK;
2583 if (eeprom->reg_chip_select)
2584 reg |= RTL818X_EEPROM_CMD_CS;
2585
2586 write_nic_byte(dev, EPROM_CMD, reg);
2587 read_nic_byte(dev, EPROM_CMD);
2588 udelay(10);
2589}
2590
c8d86be3
GKH
2591short rtl8180_init(struct net_device *dev)
2592{
2593 struct r8180_priv *priv = ieee80211_priv(dev);
2594 u16 word;
2595 u16 version;
c8d86be3
GKH
2596 u32 usValue;
2597 u16 tmpu16;
2598 int i, j;
742821ce
LF
2599 struct eeprom_93cx6 eeprom;
2600 u16 eeprom_val;
2601
2602 eeprom.data = dev;
2603 eeprom.register_read = rtl8187se_eeprom_register_read;
2604 eeprom.register_write = rtl8187se_eeprom_register_write;
2605 eeprom.width = PCI_EEPROM_WIDTH_93C46;
c8d86be3 2606
742821ce
LF
2607 eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val);
2608 priv->channel_plan = eeprom_val & 0xFF;
c8d86be3
GKH
2609 if(priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN){
2610 printk("rtl8180_init:Error channel plan! Set to default.\n");
2611 priv->channel_plan = 0;
2612 }
c8d86be3
GKH
2613
2614 DMESG("Channel plan is %d\n",priv->channel_plan);
2615 rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211);
c8d86be3 2616
c8d86be3
GKH
2617 //FIXME: these constants are placed in a bad pleace.
2618 priv->txbuffsize = 2048;//1024;
2619 priv->txringcount = 32;//32;
2620 priv->rxbuffersize = 2048;//1024;
2621 priv->rxringcount = 64;//32;
2622 priv->txbeaconcount = 2;
2623 priv->rx_skb_complete = 1;
c8d86be3 2624
c8d86be3
GKH
2625 priv->RFChangeInProgress = false;
2626 priv->SetRFPowerStateInProgress = false;
2627 priv->RFProgType = 0;
2628 priv->bInHctTest = false;
2629
2630 priv->irq_enabled=0;
2631
c8d86be3
GKH
2632 rtl8180_statistics_init(&priv->stats);
2633 rtl8180_link_detect_init(&priv->link_detect);
c8d86be3
GKH
2634
2635 priv->ack_tx_to_ieee = 0;
2636 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
2637 priv->ieee80211->iw_mode = IW_MODE_INFRA;
2638 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
2639 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2640 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2641 priv->ieee80211->active_scan = 1;
2642 priv->ieee80211->rate = 110; //11 mbps
2643 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION;
2644 priv->ieee80211->host_encrypt = 1;
2645 priv->ieee80211->host_decrypt = 1;
2646 priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup;
2647 priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack;
2648 priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep;
2649 priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty;
2650
2651 priv->hw_wep = hwwep;
2652 priv->prism_hdr=0;
2653 priv->dev=dev;
2654 priv->retry_rts = DEFAULT_RETRY_RTS;
2655 priv->retry_data = DEFAULT_RETRY_DATA;
2656 priv->RFChangeInProgress = false;
2657 priv->SetRFPowerStateInProgress = false;
2658 priv->RFProgType = 0;
2659 priv->bInHctTest = false;
2660 priv->bInactivePs = true;//false;
2661 priv->ieee80211->bInactivePs = priv->bInactivePs;
2662 priv->bSwRfProcessing = false;
2663 priv->eRFPowerState = eRfOff;
2664 priv->RfOffReason = 0;
2665 priv->LedStrategy = SW_LED_MODE0;
c8d86be3
GKH
2666 priv->TxPollingTimes = 0;//lzm add 080826
2667 priv->bLeisurePs = true;
2668 priv->dot11PowerSaveMode = eActive;
c8d86be3
GKH
2669 priv->AdMinCheckPeriod = 5;
2670 priv->AdMaxCheckPeriod = 10;
c8d86be3
GKH
2671 priv->AdMaxRxSsThreshold = 30;//60->30
2672 priv->AdRxSsThreshold = 20;//50->20
2673 priv->AdCheckPeriod = priv->AdMinCheckPeriod;
2674 priv->AdTickCount = 0;
2675 priv->AdRxSignalStrength = -1;
2676 priv->RegSwAntennaDiversityMechanism = 0;
2677 priv->RegDefaultAntenna = 0;
2678 priv->SignalStrength = 0;
2679 priv->AdRxOkCnt = 0;
2680 priv->CurrAntennaIndex = 0;
2681 priv->AdRxSsBeforeSwitched = 0;
2682 init_timer(&priv->SwAntennaDiversityTimer);
2683 priv->SwAntennaDiversityTimer.data = (unsigned long)dev;
2684 priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback;
c8d86be3
GKH
2685 priv->bDigMechanism = 1;
2686 priv->InitialGain = 6;
2687 priv->bXtalCalibration = false;
2688 priv->XtalCal_Xin = 0;
2689 priv->XtalCal_Xout = 0;
2690 priv->bTxPowerTrack = false;
2691 priv->ThermalMeter = 0;
2692 priv->FalseAlarmRegValue = 0;
2693 priv->RegDigOfdmFaUpTh = 0xc; // Upper threhold of OFDM false alarm, which is used in DIG.
2694 priv->DIG_NumberFallbackVote = 0;
2695 priv->DIG_NumberUpgradeVote = 0;
2696 priv->LastSignalStrengthInPercent = 0;
2697 priv->Stats_SignalStrength = 0;
2698 priv->LastRxPktAntenna = 0;
2699 priv->SignalQuality = 0; // in 0-100 index.
2700 priv->Stats_SignalQuality = 0;
2701 priv->RecvSignalPower = 0; // in dBm.
2702 priv->Stats_RecvSignalPower = 0;
2703 priv->AdMainAntennaRxOkCnt = 0;
2704 priv->AdAuxAntennaRxOkCnt = 0;
2705 priv->bHWAdSwitched = false;
2706 priv->bRegHighPowerMechanism = true;
2707 priv->RegHiPwrUpperTh = 77;
2708 priv->RegHiPwrLowerTh = 75;
2709 priv->RegRSSIHiPwrUpperTh = 70;
2710 priv->RegRSSIHiPwrLowerTh = 20;
2711 priv->bCurCCKPkt = false;
2712 priv->UndecoratedSmoothedSS = -1;
2713 priv->bToUpdateTxPwr = false;
2714 priv->CurCCKRSSI = 0;
2715 priv->RxPower = 0;
2716 priv->RSSI = 0;
c8d86be3
GKH
2717 priv->NumTxOkTotal = 0;
2718 priv->NumTxUnicast = 0;
2719 priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL;
2720 priv->PowerProfile = POWER_PROFILE_AC;
1994130e
LF
2721 priv->CurrRetryCnt = 0;
2722 priv->LastRetryCnt = 0;
2723 priv->LastTxokCnt = 0;
2724 priv->LastRxokCnt = 0;
2725 priv->LastRetryRate = 0;
2726 priv->bTryuping = 0;
2727 priv->CurrTxRate = 0;
2728 priv->CurrRetryRate = 0;
2729 priv->TryupingCount = 0;
2730 priv->TryupingCountNoData = 0;
2731 priv->TryDownCountLowData = 0;
2732 priv->LastTxOKBytes = 0;
2733 priv->LastFailTxRate = 0;
2734 priv->LastFailTxRateSS = 0;
2735 priv->FailTxRateCount = 0;
2736 priv->LastTxThroughput = 0;
2737 priv->NumTxOkBytesTotal = 0;
c8d86be3
GKH
2738 priv->ForcedDataRate = 0;
2739 priv->RegBModeGainStage = 1;
2740
1994130e 2741 priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
c8d86be3
GKH
2742 spin_lock_init(&priv->irq_lock);
2743 spin_lock_init(&priv->irq_th_lock);
2744 spin_lock_init(&priv->tx_lock);
2745 spin_lock_init(&priv->ps_lock);
2746 spin_lock_init(&priv->rf_ps_lock);
1994130e
LF
2747 sema_init(&priv->wx_sem, 1);
2748 sema_init(&priv->rf_state, 1);
2749 INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq);
2750 INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq);
2751 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,
2752 (void *)rtl8180_hw_wakeup_wq);
2753 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,
2754 (void *)rtl8180_hw_sleep_wq);
2755 INIT_WORK(&priv->ieee80211->wmm_param_update_wq,
2756 (void *)rtl8180_wmm_param_update);
2757 INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq,
2758 (void *)rtl8180_rate_adapter);
2759 INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq,
2760 (void *)rtl8180_hw_dig_wq);
2761 INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq,
2762 (void *)rtl8180_tx_pw_wq);
2763 INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem,
2764 (void *) GPIOChangeRFWorkItemCallBack);
c8d86be3
GKH
2765 tasklet_init(&priv->irq_rx_tasklet,
2766 (void(*)(unsigned long)) rtl8180_irq_rx_tasklet,
2767 (unsigned long)priv);
fd882783 2768
1994130e 2769 init_timer(&priv->watch_dog_timer);
c8d86be3
GKH
2770 priv->watch_dog_timer.data = (unsigned long)dev;
2771 priv->watch_dog_timer.function = watch_dog_adaptive;
c8d86be3 2772
1994130e
LF
2773 init_timer(&priv->rateadapter_timer);
2774 priv->rateadapter_timer.data = (unsigned long)dev;
2775 priv->rateadapter_timer.function = timer_rate_adaptive;
2776 priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD;
2777 priv->bEnhanceTxPwr = false;
c8d86be3
GKH
2778
2779 priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit;
2780 priv->ieee80211->set_chan = rtl8180_set_chan;
2781 priv->ieee80211->link_change = rtl8180_link_change;
2782 priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit;
2783 priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop;
2784 priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume;
2785
2786 priv->ieee80211->init_wmmparam_flag = 0;
2787
2788 priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon;
2789 priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable;
2790 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
2791
c8d86be3
GKH
2792 priv->MWIEnable = 0;
2793
2794 priv->ShortRetryLimit = 7;
2795 priv->LongRetryLimit = 7;
2796 priv->EarlyRxThreshold = 7;
2797
2798 priv->CSMethod = (0x01 << 29);
2799
1994130e
LF
2800 priv->TransmitConfig = TCR_DurProcMode_OFFSET |
2801 (7<<TCR_MXDMA_OFFSET) |
2802 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) |
2803 (priv->LongRetryLimit<<TCR_LRL_OFFSET) |
2804 (0 ? TCR_SAT : 0);
2805
2806 priv->ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF |
2807 RCR_AB | RCR_AM | RCR_APM |
2808 (7<<RCR_MXDMA_OFFSET) |
2809 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) |
2810 (priv->EarlyRxThreshold == 7 ?
2811 RCR_ONLYERLPKT : 0);
c8d86be3
GKH
2812
2813 priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER |
1994130e
LF
2814 IMR_THPDER | IMR_THPDOK |
2815 IMR_TVODER | IMR_TVODOK |
2816 IMR_TVIDER | IMR_TVIDOK |
2817 IMR_TBEDER | IMR_TBEDOK |
2818 IMR_TBKDER | IMR_TBKDOK |
2819 IMR_RDU |
2820 IMR_RER | IMR_ROK |
2821 IMR_RQoSOK;
c8d86be3
GKH
2822
2823 priv->InitialGain = 6;
c8d86be3 2824
d44eb889
LF
2825 DMESG("MAC controller is a RTL8187SE b/g");
2826 priv->phy_ver = 2;
c8d86be3 2827
d44eb889
LF
2828 priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION;
2829 priv->ieee80211->short_slot = 1;
c8d86be3 2830
c8d86be3 2831 // just for sync 85
c8d86be3
GKH
2832 priv->enable_gpio0 = 0;
2833
742821ce
LF
2834 eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val);
2835 usValue = eeprom_val;
c8d86be3 2836 DMESG("usValue is 0x%x\n",usValue);
c8d86be3 2837 //3Read AntennaDiversity
fd882783 2838
c8d86be3 2839 // SW Antenna Diversity.
fd882783 2840 if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE)
c8d86be3 2841 priv->EEPROMSwAntennaDiversity = false;
c8d86be3 2842 else
c8d86be3 2843 priv->EEPROMSwAntennaDiversity = true;
fd882783 2844
c8d86be3 2845 // Default Antenna to use.
fd882783 2846 if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1)
c8d86be3 2847 priv->EEPROMDefaultAntenna1 = false;
c8d86be3 2848 else
c8d86be3 2849 priv->EEPROMDefaultAntenna1 = true;
c8d86be3 2850
c8d86be3 2851 if( priv->RegSwAntennaDiversityMechanism == 0 ) // Auto
fd882783 2852 /* 0: default from EEPROM. */
c8d86be3 2853 priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity;
c8d86be3 2854 else
fd882783 2855 /* 1:disable antenna diversity, 2: enable antenna diversity. */
c8d86be3 2856 priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1)? false : true);
c8d86be3 2857
fd882783
BZ
2858 if (priv->RegDefaultAntenna == 0)
2859 /* 0: default from EEPROM. */
c8d86be3 2860 priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1;
c8d86be3 2861 else
fd882783 2862 /* 1: main, 2: aux. */
c8d86be3 2863 priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna== 2) ? true : false);
fd882783 2864
c8d86be3
GKH
2865 /* rtl8185 can calc plcp len in HW.*/
2866 priv->hw_plcp_len = 1;
2867
2868 priv->plcp_preamble_mode = 2;
2869 /*the eeprom type is stored in RCR register bit #6 */
fd882783 2870 if (RCR_9356SEL & read_nic_dword(dev, RCR))
c8d86be3 2871 priv->epromtype=EPROM_93c56;
fd882783 2872 else
c8d86be3 2873 priv->epromtype=EPROM_93c46;
c8d86be3 2874
742821ce
LF
2875 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)
2876 dev->dev_addr, 3);
c8d86be3
GKH
2877
2878 for(i=1,j=0; i<14; i+=2,j++){
742821ce 2879 eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word);
c8d86be3
GKH
2880 priv->chtxpwr[i]=word & 0xff;
2881 priv->chtxpwr[i+1]=(word & 0xff00)>>8;
c8d86be3 2882 }
d44eb889 2883 for (i = 1, j = 0; i < 14; i += 2, j++) {
742821ce 2884 eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word);
d44eb889 2885 priv->chtxpwr_ofdm[i] = word & 0xff;
1994130e 2886 priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8;
c8d86be3 2887 }
fd882783 2888
1994130e 2889 /* 3Read crystal calibtration and thermal meter indication on 87SE. */
742821ce 2890 eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16);
c8d86be3 2891
1994130e
LF
2892 /* Crystal calibration for Xin and Xout resp. */
2893 priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK;
2894 priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4;
2895 if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12)
2896 priv->bXtalCalibration = true;
c8d86be3 2897
1994130e
LF
2898 /* Thermal meter reference indication. */
2899 priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8);
2900 if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13)
2901 priv->bTxPowerTrack = true;
c8d86be3 2902
742821ce 2903 eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word);
c8d86be3
GKH
2904 priv->cck_txpwr_base = word & 0xf;
2905 priv->ofdm_txpwr_base = (word>>4) & 0xf;
c8d86be3 2906
742821ce 2907 eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version);
c8d86be3 2908 DMESG("EEPROM version %x",version);
d44eb889 2909 priv->rcr_csense = 3;
c8d86be3 2910
742821ce
LF
2911 eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val);
2912 priv->cs_treshold = (eeprom_val & 0xff00) >> 8;
c8d86be3 2913
742821ce 2914 eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val);
c8d86be3
GKH
2915 priv->rf_sleep = rtl8225z4_rf_sleep;
2916 priv->rf_wakeup = rtl8225z4_rf_wakeup;
c8d86be3
GKH
2917 DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!");
2918
2919 priv->rf_close = rtl8225z2_rf_close;
2920 priv->rf_init = rtl8225z2_rf_init;
2921 priv->rf_set_chan = rtl8225z2_rf_set_chan;
2922 priv->rf_set_sens = NULL;
c8d86be3 2923
c8d86be3
GKH
2924 if (0!=alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount))
2925 return -ENOMEM;
2926
2927 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2928 TX_MANAGEPRIORITY_RING_ADDR))
2929 return -ENOMEM;
2930
2931 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2932 TX_BKPRIORITY_RING_ADDR))
2933 return -ENOMEM;
2934
2935 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2936 TX_BEPRIORITY_RING_ADDR))
2937 return -ENOMEM;
2938
2939 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2940 TX_VIPRIORITY_RING_ADDR))
2941 return -ENOMEM;
2942
2943 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2944 TX_VOPRIORITY_RING_ADDR))
2945 return -ENOMEM;
2946
2947 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
2948 TX_HIGHPRIORITY_RING_ADDR))
2949 return -ENOMEM;
2950
2951 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount,
2952 TX_BEACON_RING_ADDR))
2953 return -ENOMEM;
2954
c8d86be3 2955 if(request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)){
c8d86be3
GKH
2956 DMESGE("Error allocating IRQ %d",dev->irq);
2957 return -1;
2958 }else{
2959 priv->irq=dev->irq;
2960 DMESG("IRQ %d",dev->irq);
2961 }
2962
c8d86be3 2963 return 0;
c8d86be3
GKH
2964}
2965
c8d86be3
GKH
2966void rtl8180_no_hw_wep(struct net_device *dev)
2967{
c8d86be3
GKH
2968}
2969
c8d86be3
GKH
2970void rtl8180_set_hw_wep(struct net_device *dev)
2971{
2972 struct r8180_priv *priv = ieee80211_priv(dev);
2973 u8 pgreg;
2974 u8 security;
2975 u32 key0_word4;
2976
2977 pgreg=read_nic_byte(dev, PGSELECT);
2978 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
2979
2980 key0_word4 = read_nic_dword(dev, KEY0+4+4+4);
2981 key0_word4 &= ~ 0xff;
2982 key0_word4 |= priv->key0[3]& 0xff;
2983 write_nic_dword(dev,KEY0,(priv->key0[0]));
2984 write_nic_dword(dev,KEY0+4,(priv->key0[1]));
2985 write_nic_dword(dev,KEY0+4+4,(priv->key0[2]));
2986 write_nic_dword(dev,KEY0+4+4+4,(key0_word4));
2987
c8d86be3
GKH
2988 security = read_nic_byte(dev,SECURITY);
2989 security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT);
2990 security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT);
2991 security &= ~ SECURITY_ENCRYP_MASK;
2992 security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT);
2993
2994 write_nic_byte(dev, SECURITY, security);
2995
2996 DMESG("key %x %x %x %x",read_nic_dword(dev,KEY0+4+4+4),
2997 read_nic_dword(dev,KEY0+4+4),read_nic_dword(dev,KEY0+4),
2998 read_nic_dword(dev,KEY0));
c8d86be3
GKH
2999}
3000
3001
3002void rtl8185_rf_pins_enable(struct net_device *dev)
3003{
3004// u16 tmp;
3005// tmp = read_nic_word(dev, RFPinsEnable);
3006 write_nic_word(dev, RFPinsEnable, 0x1fff);// | tmp);
c8d86be3
GKH
3007}
3008
c8d86be3
GKH
3009void rtl8185_set_anaparam2(struct net_device *dev, u32 a)
3010{
3011 u8 conf3;
3012
3013 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3014
3015 conf3 = read_nic_byte(dev, CONFIG3);
3016 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3017 write_nic_dword(dev, ANAPARAM2, a);
3018
3019 conf3 = read_nic_byte(dev, CONFIG3);
3020 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3021 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
3022}
3023
c8d86be3
GKH
3024void rtl8180_set_anaparam(struct net_device *dev, u32 a)
3025{
3026 u8 conf3;
3027
3028 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3029
3030 conf3 = read_nic_byte(dev, CONFIG3);
3031 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3032 write_nic_dword(dev, ANAPARAM, a);
3033
3034 conf3 = read_nic_byte(dev, CONFIG3);
3035 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3036 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3037}
3038
c8d86be3
GKH
3039void rtl8185_tx_antenna(struct net_device *dev, u8 ant)
3040{
3041 write_nic_byte(dev, TX_ANTENNA, ant);
3042 force_pci_posting(dev);
3043 mdelay(1);
3044}
3045
c8d86be3
GKH
3046void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data)
3047{
c8d86be3 3048 u32 phyw;
c8d86be3
GKH
3049
3050 adr |= 0x80;
3051
3052 phyw= ((data<<8) | adr);
c8d86be3 3053
c8d86be3
GKH
3054 // Note that, we must write 0xff7c after 0x7d-0x7f to write BB register.
3055 write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24));
3056 write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16));
3057 write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8));
3058 write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff) ));
5521a513 3059
c8d86be3
GKH
3060 /* this is ok to fail when we write AGC table. check for AGC table might be
3061 * done by masking with 0x7f instead of 0xff
3062 */
3063 //if(phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data,adr);
3064}
3065
c8d86be3
GKH
3066inline void write_phy_ofdm (struct net_device *dev, u8 adr, u32 data)
3067{
3068 data = data & 0xff;
3069 rtl8185_write_phy(dev, adr, data);
3070}
3071
c8d86be3
GKH
3072void write_phy_cck (struct net_device *dev, u8 adr, u32 data)
3073{
3074 data = data & 0xff;
3075 rtl8185_write_phy(dev, adr, data | 0x10000);
3076}
3077
c8d86be3
GKH
3078void rtl8185_set_rate(struct net_device *dev)
3079{
3080 int i;
3081 u16 word;
3082 int basic_rate,min_rr_rate,max_rr_rate;
3083
c8d86be3
GKH
3084 basic_rate = ieeerate2rtlrate(240);
3085 min_rr_rate = ieeerate2rtlrate(60);
3086 max_rr_rate = ieeerate2rtlrate(240);
3087
c8d86be3
GKH
3088 write_nic_byte(dev, RESP_RATE,
3089 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
3090
3091 word = read_nic_word(dev, BRSR);
3092 word &= ~BRSR_MBR_8185;
3093
c8d86be3
GKH
3094 for(i=0;i<=basic_rate;i++)
3095 word |= (1<<i);
3096
3097 write_nic_word(dev, BRSR, word);
c8d86be3
GKH
3098}
3099
c8d86be3
GKH
3100void rtl8180_adapter_start(struct net_device *dev)
3101{
3102 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
3103
3104 rtl8180_rtx_disable(dev);
3105 rtl8180_reset(dev);
3106
c8d86be3
GKH
3107 /* enable beacon timeout, beacon TX ok and err
3108 * LP tx ok and err, HP TX ok and err, NP TX ok and err,
3109 * RX ok and ERR, and GP timer */
3110 priv->irq_mask = 0x6fcf;
3111
3112 priv->dma_poll_mask = 0;
3113
3114 rtl8180_beacon_tx_disable(dev);
3115
c8d86be3
GKH
3116 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3117 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
3118 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
3119 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3120
3121 rtl8180_update_msr(dev);
3122
c8d86be3
GKH
3123 /* These might be unnecessary since we do in rx_enable / tx_enable */
3124 fix_rx_fifo(dev);
3125 fix_tx_fifo(dev);
c8d86be3
GKH
3126
3127 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3128
3129 /*
3130 The following is very strange. seems to be that 1 means test mode,
3131 but we need to acknolwledges the nic when a packet is ready
bbc9a991 3132 although we set it to 0
c8d86be3
GKH
3133 */
3134
3135 write_nic_byte(dev,
3136 CONFIG2, read_nic_byte(dev,CONFIG2) &~\
3137 (1<<CONFIG2_DMA_POLLING_MODE_SHIFT));
3138 //^the nic isn't in test mode
d44eb889 3139 write_nic_byte(dev,
c8d86be3
GKH
3140 CONFIG2, read_nic_byte(dev,CONFIG2)|(1<<4));
3141
3142 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3143
3144 write_nic_dword(dev,INT_TIMEOUT,0);
c8d86be3 3145
d44eb889 3146 write_nic_byte(dev, WPA_CONFIG, 0);
c8d86be3
GKH
3147
3148 rtl8180_no_hw_wep(dev);
3149
d44eb889
LF
3150 rtl8185_set_rate(dev);
3151 write_nic_byte(dev, RATE_FALLBACK, 0x81);
c8d86be3 3152
d44eb889 3153 write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6));
c8d86be3 3154
d44eb889
LF
3155 /*FIXME cfg 3 ClkRun enable - isn't it ReadOnly ? */
3156 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3157 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3)
3158 | (1 << CONFIG3_CLKRUN_SHIFT));
3159 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
3160
3161 priv->rf_init(dev);
3162
3163 if(priv->rf_set_sens != NULL)
3164 priv->rf_set_sens(dev,priv->sens);
3165 rtl8180_irq_enable(dev);
3166
3167 netif_start_queue(dev);
c8d86be3
GKH
3168}
3169
c8d86be3
GKH
3170/* this configures registers for beacon tx and enables it via
3171 * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might
3172 * be used to stop beacon transmission
3173 */
3174void rtl8180_start_tx_beacon(struct net_device *dev)
3175{
c8d86be3 3176 u16 word;
c8d86be3
GKH
3177
3178 DMESG("Enabling beacon TX");
c8d86be3
GKH
3179 rtl8180_prepare_beacon(dev);
3180 rtl8180_irq_disable(dev);
3181 rtl8180_beacon_tx_enable(dev);
c8d86be3 3182
c8d86be3
GKH
3183 word = read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd;
3184 write_nic_word(dev, AtimWnd,word);// word |=
c8d86be3
GKH
3185
3186 word = read_nic_word(dev, BintrItv);
3187 word &= ~BintrItv_BintrItv;
3188 word |= 1000;/*priv->ieee80211->current_network.beacon_interval *
3189 ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
3190 // FIXME: check if correct ^^ worked with 0x3e8;
3191 */
3192 write_nic_word(dev, BintrItv, word);
3193
c8d86be3
GKH
3194 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3195
c8d86be3 3196 rtl8185b_irq_enable(dev);
c8d86be3
GKH
3197}
3198
c8d86be3
GKH
3199static struct net_device_stats *rtl8180_stats(struct net_device *dev)
3200{
3201 struct r8180_priv *priv = ieee80211_priv(dev);
3202
3203 return &priv->ieee80211->stats;
3204}
3205//
3206// Change current and default preamble mode.
c8d86be3
GKH
3207//
3208bool
3209MgntActSet_802_11_PowerSaveMode(
3210 struct r8180_priv *priv,
3211 RT_PS_MODE rtPsMode
3212)
3213{
c8d86be3
GKH
3214 // Currently, we do not change power save mode on IBSS mode.
3215 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
c8d86be3 3216 return false;
c8d86be3 3217
c8d86be3 3218 priv->ieee80211->ps = rtPsMode;
5521a513 3219
c8d86be3
GKH
3220 return true;
3221}
3222
fd882783 3223void LeisurePSEnter(struct r8180_priv *priv)
c8d86be3 3224{
fd882783 3225 if (priv->bLeisurePs) {
c8d86be3 3226 if (priv->ieee80211->ps == IEEE80211_PS_DISABLED)
c8d86be3 3227 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);//IEEE80211_PS_ENABLE
c8d86be3
GKH
3228 }
3229}
3230
fd882783 3231void LeisurePSLeave(struct r8180_priv *priv)
c8d86be3 3232{
fd882783 3233 if (priv->bLeisurePs) {
c8d86be3 3234 if (priv->ieee80211->ps != IEEE80211_PS_DISABLED)
c8d86be3 3235 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED);
c8d86be3
GKH
3236 }
3237}
0370453f 3238
c8d86be3
GKH
3239void rtl8180_hw_wakeup_wq (struct work_struct *work)
3240{
bf6aede7 3241 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH
3242 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
3243 struct net_device *dev = ieee->dev;
c8d86be3 3244
c8d86be3 3245 rtl8180_hw_wakeup(dev);
c8d86be3
GKH
3246}
3247
c8d86be3
GKH
3248void rtl8180_hw_sleep_wq (struct work_struct *work)
3249{
bf6aede7 3250 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH
3251 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
3252 struct net_device *dev = ieee->dev;
c8d86be3
GKH
3253
3254 rtl8180_hw_sleep_down(dev);
3255}
3256
c8d86be3
GKH
3257static void MgntLinkKeepAlive(struct r8180_priv *priv )
3258{
3259 if (priv->keepAliveLevel == 0)
3260 return;
3261
3262 if(priv->ieee80211->state == IEEE80211_LINKED)
3263 {
3264 //
3265 // Keep-Alive.
3266 //
c8d86be3
GKH
3267
3268 if ( (priv->keepAliveLevel== 2) ||
3269 (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast &&
3270 priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast )
3271 )
3272 {
3273 priv->link_detect.IdleCount++;
3274
3275 //
3276 // Send a Keep-Alive packet packet to AP if we had been idle for a while.
3277 //
3278 if(priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1) )
3279 {
3280 priv->link_detect.IdleCount = 0;
3281 ieee80211_sta_ps_send_null_frame(priv->ieee80211, false);
3282 }
3283 }
3284 else
3285 {
3286 priv->link_detect.IdleCount = 0;
3287 }
3288 priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast;
3289 priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast;
3290 }
3291}
c8d86be3
GKH
3292
3293static u8 read_acadapter_file(char *filename);
fd882783 3294
c8d86be3
GKH
3295void rtl8180_watch_dog(struct net_device *dev)
3296{
3297 struct r8180_priv *priv = ieee80211_priv(dev);
3298 bool bEnterPS = false;
3299 bool bBusyTraffic = false;
3300 u32 TotalRxNum = 0;
3301 u16 SlotIndex = 0;
3302 u16 i = 0;
c8d86be3
GKH
3303 if(priv->ieee80211->actscanning == false){
3304 if((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)){
3305 IPSEnter(dev);
3306 }
3307 }
c8d86be3
GKH
3308 //YJ,add,080828,for link state check
3309 if((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)){
3310 SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum;
3311 priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod;
3312 for( i=0; i<priv->link_detect.SlotNum; i++ )
3313 TotalRxNum+= priv->link_detect.RxFrameNum[i];
fd882783 3314
c8d86be3
GKH
3315 if(TotalRxNum == 0){
3316 priv->ieee80211->state = IEEE80211_ASSOCIATING;
3317 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
3318 }
3319 }
3320
3321 //YJ,add,080828,for KeepAlive
3322 MgntLinkKeepAlive(priv);
3323
3324 //YJ,add,080828,for LPS
fd882783 3325 if (priv->PowerProfile == POWER_PROFILE_BATTERY)
c8d86be3 3326 priv->bLeisurePs = true;
fd882783 3327 else if (priv->PowerProfile == POWER_PROFILE_AC) {
c8d86be3
GKH
3328 LeisurePSLeave(priv);
3329 priv->bLeisurePs= false;
3330 }
c8d86be3 3331
c8d86be3
GKH
3332 if(priv->ieee80211->state == IEEE80211_LINKED){
3333 priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod;
c8d86be3
GKH
3334 if( priv->link_detect.NumRxOkInPeriod> 666 ||
3335 priv->link_detect.NumTxOkInPeriod> 666 ) {
3336 bBusyTraffic = true;
3337 }
3338 if(((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8)
3339 || (priv->link_detect.NumRxOkInPeriod > 2)) {
3340 bEnterPS= false;
fd882783 3341 } else
c8d86be3 3342 bEnterPS= true;
c8d86be3 3343
fd882783 3344 if (bEnterPS)
c8d86be3 3345 LeisurePSEnter(priv);
fd882783 3346 else
c8d86be3 3347 LeisurePSLeave(priv);
fd882783 3348 } else
c8d86be3 3349 LeisurePSLeave(priv);
c8d86be3
GKH
3350 priv->link_detect.bBusyTraffic = bBusyTraffic;
3351 priv->link_detect.NumRxOkInPeriod = 0;
3352 priv->link_detect.NumTxOkInPeriod = 0;
3353 priv->ieee80211->NumRxDataInPeriod = 0;
3354 priv->ieee80211->NumRxBcnInPeriod = 0;
c8d86be3 3355}
fd882783 3356
c8d86be3
GKH
3357int _rtl8180_up(struct net_device *dev)
3358{
3359 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
3360
3361 priv->up=1;
3362
3363 DMESG("Bringing up iface");
c8d86be3
GKH
3364 rtl8185b_adapter_start(dev);
3365 rtl8185b_rx_enable(dev);
3366 rtl8185b_tx_enable(dev);
c8d86be3
GKH
3367 if(priv->bInactivePs){
3368 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
3369 IPSLeave(dev);
3370 }
c8d86be3 3371 timer_rate_adaptive((unsigned long)dev);
c8d86be3 3372 watch_dog_adaptive((unsigned long)dev);
c8d86be3
GKH
3373 if(priv->bSwAntennaDiverity)
3374 SwAntennaDiversityTimerCallback(dev);
c8d86be3 3375 ieee80211_softmac_start_protocol(priv->ieee80211);
c8d86be3
GKH
3376 return 0;
3377}
3378
c8d86be3
GKH
3379int rtl8180_open(struct net_device *dev)
3380{
3381 struct r8180_priv *priv = ieee80211_priv(dev);
3382 int ret;
3383
3384 down(&priv->wx_sem);
3385 ret = rtl8180_up(dev);
3386 up(&priv->wx_sem);
3387 return ret;
c8d86be3
GKH
3388}
3389
c8d86be3
GKH
3390int rtl8180_up(struct net_device *dev)
3391{
3392 struct r8180_priv *priv = ieee80211_priv(dev);
3393
3394 if (priv->up == 1) return -1;
3395
3396 return _rtl8180_up(dev);
3397}
3398
c8d86be3
GKH
3399int rtl8180_close(struct net_device *dev)
3400{
3401 struct r8180_priv *priv = ieee80211_priv(dev);
3402 int ret;
3403
3404 down(&priv->wx_sem);
3405 ret = rtl8180_down(dev);
3406 up(&priv->wx_sem);
3407
3408 return ret;
c8d86be3
GKH
3409}
3410
3411int rtl8180_down(struct net_device *dev)
3412{
3413 struct r8180_priv *priv = ieee80211_priv(dev);
3414
fd882783
BZ
3415 if (priv->up == 0)
3416 return -1;
c8d86be3
GKH
3417
3418 priv->up=0;
3419
3420 ieee80211_softmac_stop_protocol(priv->ieee80211);
3421 /* FIXME */
3422 if (!netif_queue_stopped(dev))
3423 netif_stop_queue(dev);
3424 rtl8180_rtx_disable(dev);
3425 rtl8180_irq_disable(dev);
3426 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ
3427 del_timer_sync(&priv->rateadapter_timer);
3428 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH
3429 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3430 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3431 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3432 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3433 del_timer_sync(&priv->SwAntennaDiversityTimer);
3434 SetZebraRFPowerState8185(dev,eRfOff);
c8d86be3
GKH
3435 memset(&(priv->ieee80211->current_network),0,sizeof(struct ieee80211_network));
3436 priv->ieee80211->state = IEEE80211_NOLINK;
3437 return 0;
3438}
3439
c8d86be3
GKH
3440void rtl8180_restart_wq(struct work_struct *work)
3441{
3442 struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq);
3443 struct net_device *dev = priv->dev;
0370453f 3444
c8d86be3
GKH
3445 down(&priv->wx_sem);
3446
3447 rtl8180_commit(dev);
3448
3449 up(&priv->wx_sem);
3450}
3451
3452void rtl8180_restart(struct net_device *dev)
3453{
3454 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 3455
c8d86be3 3456 schedule_work(&priv->reset_wq);
c8d86be3
GKH
3457}
3458
c8d86be3
GKH
3459void rtl8180_commit(struct net_device *dev)
3460{
3461 struct r8180_priv *priv = ieee80211_priv(dev);
3462
fd882783
BZ
3463 if (priv->up == 0)
3464 return ;
3465
c8d86be3 3466 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ
3467 del_timer_sync(&priv->rateadapter_timer);
3468 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH
3469 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3470 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3471 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3472 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3473 del_timer_sync(&priv->SwAntennaDiversityTimer);
3474 ieee80211_softmac_stop_protocol(priv->ieee80211);
3475 rtl8180_irq_disable(dev);
3476 rtl8180_rtx_disable(dev);
3477 _rtl8180_up(dev);
3478}
3479
c8d86be3
GKH
3480static void r8180_set_multicast(struct net_device *dev)
3481{
3482 struct r8180_priv *priv = ieee80211_priv(dev);
3483 short promisc;
3484
c8d86be3
GKH
3485 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
3486
3487 if (promisc != priv->promisc)
3488 rtl8180_restart(dev);
3489
3490 priv->promisc = promisc;
c8d86be3
GKH
3491}
3492
c8d86be3
GKH
3493int r8180_set_mac_adr(struct net_device *dev, void *mac)
3494{
3495 struct r8180_priv *priv = ieee80211_priv(dev);
3496 struct sockaddr *addr = mac;
3497
3498 down(&priv->wx_sem);
3499
3500 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3501
3502 if(priv->ieee80211->iw_mode == IW_MODE_MASTER)
3503 memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN);
3504
3505 if (priv->up) {
3506 rtl8180_down(dev);
3507 rtl8180_up(dev);
3508 }
3509
3510 up(&priv->wx_sem);
3511
3512 return 0;
3513}
3514
3515/* based on ipw2200 driver */
3516int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3517{
3518 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
3519 struct iwreq *wrq = (struct iwreq *) rq;
3520 int ret=-1;
fd882783 3521
c8d86be3 3522 switch (cmd) {
fd882783 3523 case RTL_IOCTL_WPA_SUPPLICANT:
c8d86be3
GKH
3524 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
3525 return ret;
fd882783 3526 default:
c8d86be3
GKH
3527 return -EOPNOTSUPP;
3528 }
3529
3530 return -EOPNOTSUPP;
3531}
3532
727ae303
AB
3533static const struct net_device_ops rtl8180_netdev_ops = {
3534 .ndo_open = rtl8180_open,
3535 .ndo_stop = rtl8180_close,
3536 .ndo_get_stats = rtl8180_stats,
3537 .ndo_tx_timeout = rtl8180_restart,
3538 .ndo_do_ioctl = rtl8180_ioctl,
3539 .ndo_set_multicast_list = r8180_set_multicast,
3540 .ndo_set_mac_address = r8180_set_mac_adr,
3541 .ndo_validate_addr = eth_validate_addr,
3542 .ndo_change_mtu = eth_change_mtu,
df574b8e 3543 .ndo_start_xmit = ieee80211_rtl_xmit,
727ae303 3544};
c8d86be3
GKH
3545
3546static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
3547 const struct pci_device_id *id)
3548{
3549 unsigned long ioaddr = 0;
3550 struct net_device *dev = NULL;
3551 struct r8180_priv *priv= NULL;
c8d86be3
GKH
3552 u8 unit = 0;
3553
c8d86be3 3554 unsigned long pmem_start, pmem_len, pmem_flags;
c8d86be3
GKH
3555
3556 DMESG("Configuring chip resources");
3557
3558 if( pci_enable_device (pdev) ){
3559 DMESG("Failed to enable PCI device");
3560 return -EIO;
3561 }
3562
3563 pci_set_master(pdev);
c8d86be3
GKH
3564 pci_set_dma_mask(pdev, 0xffffff00ULL);
3565 pci_set_consistent_dma_mask(pdev,0xffffff00ULL);
3566 dev = alloc_ieee80211(sizeof(struct r8180_priv));
3567 if (!dev)
3568 return -ENOMEM;
3569 priv = ieee80211_priv(dev);
3570 priv->ieee80211 = netdev_priv(dev);
3571
c8d86be3
GKH
3572 pci_set_drvdata(pdev, dev);
3573 SET_NETDEV_DEV(dev, &pdev->dev);
3574
3575 priv = ieee80211_priv(dev);
fd882783 3576 priv->pdev = pdev;
c8d86be3
GKH
3577
3578 pmem_start = pci_resource_start(pdev, 1);
3579 pmem_len = pci_resource_len(pdev, 1);
3580 pmem_flags = pci_resource_flags (pdev, 1);
3581
3582 if (!(pmem_flags & IORESOURCE_MEM)) {
3583 DMESG("region #1 not a MMIO resource, aborting");
3584 goto fail;
3585 }
3586
c8d86be3
GKH
3587 if( ! request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) {
3588 DMESG("request_mem_region failed!");
3589 goto fail;
3590 }
3591
c8d86be3
GKH
3592 ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len);
3593 if( ioaddr == (unsigned long)NULL ){
3594 DMESG("ioremap failed!");
c8d86be3
GKH
3595 goto fail1;
3596 }
3597
3598 dev->mem_start = ioaddr; // shared mem start
3599 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end
3600
c8d86be3
GKH
3601 pci_read_config_byte(pdev, 0x05, &unit);
3602 pci_write_config_byte(pdev, 0x05, unit & (~0x04));
c8d86be3
GKH
3603
3604 dev->irq = pdev->irq;
3605 priv->irq = 0;
3606
727ae303 3607 dev->netdev_ops = &rtl8180_netdev_ops;
c8d86be3 3608 dev->wireless_handlers = &r8180_wx_handlers_def;
c8d86be3 3609
c8d86be3 3610 dev->type=ARPHRD_ETHER;
1994130e 3611 dev->watchdog_timeo = HZ*3;
c8d86be3
GKH
3612
3613 if (dev_alloc_name(dev, ifname) < 0){
3614 DMESG("Oops: devname already taken! Trying wlan%%d...\n");
3615 ifname = "wlan%d";
c8d86be3
GKH
3616 dev_alloc_name(dev, ifname);
3617 }
3618
c8d86be3
GKH
3619 if(rtl8180_init(dev)!=0){
3620 DMESG("Initialization failed");
3621 goto fail1;
3622 }
3623
3624 netif_carrier_off(dev);
3625
3626 register_netdev(dev);
3627
3628 rtl8180_proc_init_one(dev);
3629
3630 DMESG("Driver probe completed\n");
3631 return 0;
c8d86be3 3632fail1:
c8d86be3
GKH
3633 if( dev->mem_start != (unsigned long)NULL ){
3634 iounmap( (void *)dev->mem_start );
3635 release_mem_region( pci_resource_start(pdev, 1),
3636 pci_resource_len(pdev, 1) );
3637 }
c8d86be3
GKH
3638fail:
3639 if(dev){
c8d86be3
GKH
3640 if (priv->irq) {
3641 free_irq(dev->irq, dev);
3642 dev->irq=0;
3643 }
3644 free_ieee80211(dev);
3645 }
3646
3647 pci_disable_device(pdev);
3648
3649 DMESG("wlan driver load failed\n");
3650 pci_set_drvdata(pdev, NULL);
3651 return -ENODEV;
c8d86be3
GKH
3652}
3653
c8d86be3
GKH
3654static void __devexit rtl8180_pci_remove(struct pci_dev *pdev)
3655{
3656 struct r8180_priv *priv;
3657 struct net_device *dev = pci_get_drvdata(pdev);
c8d86be3 3658
fd882783 3659 if (dev) {
c8d86be3
GKH
3660 unregister_netdev(dev);
3661
fd882783 3662 priv = ieee80211_priv(dev);
c8d86be3
GKH
3663
3664 rtl8180_proc_remove_one(dev);
3665 rtl8180_down(dev);
3666 priv->rf_close(dev);
3667 rtl8180_reset(dev);
c8d86be3 3668 mdelay(10);
c8d86be3
GKH
3669
3670 if(priv->irq){
c8d86be3
GKH
3671 DMESG("Freeing irq %d",dev->irq);
3672 free_irq(dev->irq, dev);
3673 priv->irq=0;
c8d86be3
GKH
3674 }
3675
3676 free_rx_desc_ring(dev);
3677 free_tx_desc_rings(dev);
c8d86be3 3678
c8d86be3
GKH
3679 if( dev->mem_start != (unsigned long)NULL ){
3680 iounmap( (void *)dev->mem_start );
3681 release_mem_region( pci_resource_start(pdev, 1),
3682 pci_resource_len(pdev, 1) );
3683 }
c8d86be3
GKH
3684
3685 free_ieee80211(dev);
3686 }
3687 pci_disable_device(pdev);
3688
3689 DMESG("wlan driver removed\n");
3690}
3691
c8d86be3
GKH
3692/* fun with the built-in ieee80211 stack... */
3693extern int ieee80211_crypto_init(void);
3694extern void ieee80211_crypto_deinit(void);
3695extern int ieee80211_crypto_tkip_init(void);
3696extern void ieee80211_crypto_tkip_exit(void);
3697extern int ieee80211_crypto_ccmp_init(void);
3698extern void ieee80211_crypto_ccmp_exit(void);
3699extern int ieee80211_crypto_wep_init(void);
3700extern void ieee80211_crypto_wep_exit(void);
3701
3702static int __init rtl8180_pci_module_init(void)
3703{
3704 int ret;
3705
3706 ret = ieee80211_crypto_init();
3707 if (ret) {
3708 printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret);
3709 return ret;
3710 }
3711 ret = ieee80211_crypto_tkip_init();
3712 if (ret) {
3713 printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret);
3714 return ret;
3715 }
3716 ret = ieee80211_crypto_ccmp_init();
3717 if (ret) {
3718 printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret);
3719 return ret;
3720 }
3721 ret = ieee80211_crypto_wep_init();
3722 if (ret) {
3723 printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret);
3724 return ret;
3725 }
3726
bc568942 3727 printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n");
c8d86be3
GKH
3728 printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n");
3729 DMESG("Initializing module");
3730 DMESG("Wireless extensions version %d", WIRELESS_EXT);
3731 rtl8180_proc_module_init();
3732
fd882783 3733 if (pci_register_driver(&rtl8180_pci_driver)) {
c8d86be3 3734 DMESG("No device found");
c8d86be3
GKH
3735 return -ENODEV;
3736 }
3737 return 0;
3738}
3739
c8d86be3
GKH
3740static void __exit rtl8180_pci_module_exit(void)
3741{
3742 pci_unregister_driver (&rtl8180_pci_driver);
3743 rtl8180_proc_module_remove();
c8d86be3
GKH
3744 ieee80211_crypto_tkip_exit();
3745 ieee80211_crypto_ccmp_exit();
3746 ieee80211_crypto_wep_exit();
096c55d1 3747 ieee80211_crypto_deinit();
c8d86be3
GKH
3748 DMESG("Exiting");
3749}
3750
c8d86be3
GKH
3751void rtl8180_try_wake_queue(struct net_device *dev, int pri)
3752{
3753 unsigned long flags;
3754 short enough_desc;
3755 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3756
3757 spin_lock_irqsave(&priv->tx_lock,flags);
3758 enough_desc = check_nic_enought_desc(dev,pri);
3759 spin_unlock_irqrestore(&priv->tx_lock,flags);
3760
3761 if(enough_desc)
df574b8e 3762 ieee80211_rtl_wake_queue(priv->ieee80211);
c8d86be3
GKH
3763}
3764
c8d86be3
GKH
3765void rtl8180_tx_isr(struct net_device *dev, int pri,short error)
3766{
3767 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
3768 u32 *tail; //tail virtual addr
3769 u32 *head; //head virtual addr
3770 u32 *begin;//start of ring virtual addr
3771 u32 *nicv; //nic pointer virtual addr
c8d86be3
GKH
3772 u32 nic; //nic pointer physical addr
3773 u32 nicbegin;// start of ring physical addr
c8d86be3
GKH
3774 unsigned long flag;
3775 /* physical addr are ok on 32 bits since we set DMA mask*/
c8d86be3
GKH
3776 int offs;
3777 int j,i;
3778 int hd;
3779 if (error) priv->stats.txretry++; //tony 20060601
3780 spin_lock_irqsave(&priv->tx_lock,flag);
3781 switch(pri) {
3782 case MANAGE_PRIORITY:
3783 tail = priv->txmapringtail;
3784 begin = priv->txmapring;
3785 head = priv->txmapringhead;
3786 nic = read_nic_dword(dev,TX_MANAGEPRIORITY_RING_ADDR);
3787 nicbegin = priv->txmapringdma;
3788 break;
c8d86be3
GKH
3789 case BK_PRIORITY:
3790 tail = priv->txbkpringtail;
3791 begin = priv->txbkpring;
3792 head = priv->txbkpringhead;
3793 nic = read_nic_dword(dev,TX_BKPRIORITY_RING_ADDR);
3794 nicbegin = priv->txbkpringdma;
3795 break;
c8d86be3
GKH
3796 case BE_PRIORITY:
3797 tail = priv->txbepringtail;
3798 begin = priv->txbepring;
3799 head = priv->txbepringhead;
3800 nic = read_nic_dword(dev,TX_BEPRIORITY_RING_ADDR);
3801 nicbegin = priv->txbepringdma;
3802 break;
c8d86be3
GKH
3803 case VI_PRIORITY:
3804 tail = priv->txvipringtail;
3805 begin = priv->txvipring;
3806 head = priv->txvipringhead;
3807 nic = read_nic_dword(dev,TX_VIPRIORITY_RING_ADDR);
3808 nicbegin = priv->txvipringdma;
3809 break;
c8d86be3
GKH
3810 case VO_PRIORITY:
3811 tail = priv->txvopringtail;
3812 begin = priv->txvopring;
3813 head = priv->txvopringhead;
3814 nic = read_nic_dword(dev,TX_VOPRIORITY_RING_ADDR);
3815 nicbegin = priv->txvopringdma;
3816 break;
c8d86be3
GKH
3817 case HI_PRIORITY:
3818 tail = priv->txhpringtail;
3819 begin = priv->txhpring;
3820 head = priv->txhpringhead;
3821 nic = read_nic_dword(dev,TX_HIGHPRIORITY_RING_ADDR);
3822 nicbegin = priv->txhpringdma;
3823 break;
3824
3825 default:
3826 spin_unlock_irqrestore(&priv->tx_lock,flag);
3827 return ;
3828 }
fd882783 3829
c8d86be3
GKH
3830 nicv = (u32*) ((nic - nicbegin) + (u8*)begin);
3831 if((head <= tail && (nicv > tail || nicv < head)) ||
3832 (head > tail && (nicv > tail && nicv < head))){
c8d86be3 3833 DMESGW("nic has lost pointer");
c8d86be3
GKH
3834 spin_unlock_irqrestore(&priv->tx_lock,flag);
3835 rtl8180_restart(dev);
3836 return;
3837 }
3838
3839 /* we check all the descriptors between the head and the nic,
bbc9a991 3840 * but not the currently pointed by the nic (the next to be txed)
c8d86be3
GKH
3841 * and the previous of the pointed (might be in process ??)
3842 */
c8d86be3 3843 offs = (nic - nicbegin);
c8d86be3 3844 offs = offs / 8 /4;
c8d86be3
GKH
3845 hd = (head - begin) /8;
3846
3847 if(offs >= hd)
3848 j = offs - hd;
3849 else
3850 j = offs + (priv->txringcount -1 -hd);
c8d86be3
GKH
3851
3852 j-=2;
3853 if(j<0) j=0;
3854
c8d86be3
GKH
3855 for(i=0;i<j;i++)
3856 {
c8d86be3
GKH
3857 if((*head) & (1<<31))
3858 break;
3859 if(((*head)&(0x10000000)) != 0){
c8d86be3 3860 priv->CurrRetryCnt += (u16)((*head) & (0x000000ff));
fd882783 3861 if (!error)
c8d86be3 3862 priv->NumTxOkTotal++;
c8d86be3 3863 }
fd882783
BZ
3864
3865 if (!error)
c8d86be3 3866 priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff);
fd882783 3867
c8d86be3
GKH
3868 *head = *head &~ (1<<31);
3869
3870 if((head - begin)/8 == priv->txringcount-1)
3871 head=begin;
c8d86be3
GKH
3872 else
3873 head+=8;
3874 }
c8d86be3 3875
c8d86be3
GKH
3876 /* the head has been moved to the last certainly TXed
3877 * (or at least processed by the nic) packet.
3878 * The driver take forcefully owning of all these packets
3879 * If the packet previous of the nic pointer has been
3880 * processed this doesn't matter: it will be checked
3881 * here at the next round. Anyway if no more packet are
3882 * TXed no memory leak occour at all.
3883 */
3884
3885 switch(pri) {
3886 case MANAGE_PRIORITY:
3887 priv->txmapringhead = head;
fd882783 3888
c8d86be3 3889 if(priv->ack_tx_to_ieee){
c8d86be3 3890 if(rtl8180_is_tx_queue_empty(dev)){
c8d86be3
GKH
3891 priv->ack_tx_to_ieee = 0;
3892 ieee80211_ps_tx_ack(priv->ieee80211,!error);
3893 }
c8d86be3
GKH
3894 }
3895 break;
c8d86be3
GKH
3896 case BK_PRIORITY:
3897 priv->txbkpringhead = head;
3898 break;
c8d86be3
GKH
3899 case BE_PRIORITY:
3900 priv->txbepringhead = head;
3901 break;
c8d86be3
GKH
3902 case VI_PRIORITY:
3903 priv->txvipringhead = head;
3904 break;
c8d86be3
GKH
3905 case VO_PRIORITY:
3906 priv->txvopringhead = head;
3907 break;
c8d86be3
GKH
3908 case HI_PRIORITY:
3909 priv->txhpringhead = head;
3910 break;
3911 }
3912
c8d86be3 3913 spin_unlock_irqrestore(&priv->tx_lock,flag);
c8d86be3
GKH
3914}
3915
c8d86be3
GKH
3916void rtl8180_tx_irq_wq(struct work_struct *work)
3917{
bf6aede7 3918 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH
3919 struct ieee80211_device * ieee = (struct ieee80211_device*)
3920 container_of(dwork, struct ieee80211_device, watch_dog_wq);
3921 struct net_device *dev = ieee->dev;
0370453f 3922
c8d86be3
GKH
3923 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
3924}
3925irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs)
3926{
3927 struct net_device *dev = (struct net_device *) netdev;
3928 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3929 unsigned long flags;
3930 u32 inta;
3931
3932 /* We should return IRQ_NONE, but for now let me keep this */
3933 if(priv->irq_enabled == 0) return IRQ_HANDLED;
3934
3935 spin_lock_irqsave(&priv->irq_th_lock,flags);
3936
c8d86be3
GKH
3937 //ISR: 4bytes
3938 inta = read_nic_dword(dev, ISR);// & priv->IntrMask;
3939 write_nic_dword(dev,ISR,inta); // reset int situation
c8d86be3
GKH
3940
3941 priv->stats.shints++;
3942
c8d86be3
GKH
3943 if(!inta){
3944 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
3945 return IRQ_HANDLED;
3946 /*
3947 most probably we can safely return IRQ_NONE,
3948 but for now is better to avoid problems
3949 */
3950 }
3951
fd882783
BZ
3952 if (inta == 0xffff) {
3953 /* HW disappared */
3954 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
3955 return IRQ_HANDLED;
c8d86be3
GKH
3956 }
3957
3958 priv->stats.ints++;
c8d86be3
GKH
3959
3960 if(!netif_running(dev)) {
3961 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
3962 return IRQ_HANDLED;
3963 }
3964
fd882783 3965 if (inta & ISR_TimeOut)
c8d86be3 3966 write_nic_dword(dev, TimerInt, 0);
c8d86be3 3967
fd882783 3968 if (inta & ISR_TBDOK)
c8d86be3 3969 priv->stats.txbeacon++;
c8d86be3 3970
fd882783 3971 if (inta & ISR_TBDER)
c8d86be3 3972 priv->stats.txbeaconerr++;
c8d86be3 3973
fd882783 3974 if (inta & IMR_TMGDOK)
c8d86be3 3975 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
c8d86be3
GKH
3976
3977 if(inta & ISR_THPDER){
c8d86be3
GKH
3978 priv->stats.txhperr++;
3979 rtl8180_tx_isr(dev,HI_PRIORITY,1);
3980 priv->ieee80211->stats.tx_errors++;
3981 }
3982
3983 if(inta & ISR_THPDOK){ //High priority tx ok
c8d86be3
GKH
3984 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
3985 priv->stats.txhpokint++;
3986 rtl8180_tx_isr(dev,HI_PRIORITY,0);
3987 }
3988
3989 if(inta & ISR_RER) {
3990 priv->stats.rxerr++;
c8d86be3 3991 }
c8d86be3
GKH
3992 if(inta & ISR_TBKDER){ //corresponding to BK_PRIORITY
3993 priv->stats.txbkperr++;
3994 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH
3995 rtl8180_tx_isr(dev,BK_PRIORITY,1);
3996 rtl8180_try_wake_queue(dev, BE_PRIORITY);
3997 }
3998
3999 if(inta & ISR_TBEDER){ //corresponding to BE_PRIORITY
4000 priv->stats.txbeperr++;
4001 priv->ieee80211->stats.tx_errors++;
c8d86be3 4002 rtl8180_tx_isr(dev,BE_PRIORITY,1);
c8d86be3
GKH
4003 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4004 }
c8d86be3
GKH
4005 if(inta & ISR_TNPDER){ //corresponding to VO_PRIORITY
4006 priv->stats.txnperr++;
4007 priv->ieee80211->stats.tx_errors++;
c8d86be3 4008 rtl8180_tx_isr(dev,NORM_PRIORITY,1);
c8d86be3 4009 rtl8180_try_wake_queue(dev, NORM_PRIORITY);
c8d86be3
GKH
4010 }
4011
4012 if(inta & ISR_TLPDER){ //corresponding to VI_PRIORITY
4013 priv->stats.txlperr++;
4014 priv->ieee80211->stats.tx_errors++;
c8d86be3 4015 rtl8180_tx_isr(dev,LOW_PRIORITY,1);
c8d86be3
GKH
4016 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4017 }
4018
4019 if(inta & ISR_ROK){
c8d86be3
GKH
4020 priv->stats.rxint++;
4021 tasklet_schedule(&priv->irq_rx_tasklet);
4022 }
4023
4024 if(inta & ISR_RQoSOK ){
c8d86be3
GKH
4025 priv->stats.rxint++;
4026 tasklet_schedule(&priv->irq_rx_tasklet);
4027 }
4028 if(inta & ISR_BcnInt) {
c8d86be3
GKH
4029 rtl8180_prepare_beacon(dev);
4030 }
4031
4032 if(inta & ISR_RDU){
c8d86be3
GKH
4033 DMESGW("No RX descriptor available");
4034 priv->stats.rxrdu++;
c8d86be3 4035 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3 4036 }
fd882783 4037
c8d86be3 4038 if(inta & ISR_RXFOVW){
c8d86be3
GKH
4039 priv->stats.rxoverflow++;
4040 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3
GKH
4041 }
4042
fd882783
BZ
4043 if (inta & ISR_TXFOVW)
4044 priv->stats.txoverflow++;
c8d86be3
GKH
4045
4046 if(inta & ISR_TNPDOK){ //Normal priority tx ok
c8d86be3 4047 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH
4048 priv->stats.txnpokint++;
4049 rtl8180_tx_isr(dev,NORM_PRIORITY,0);
4050 }
4051
4052 if(inta & ISR_TLPDOK){ //Low priority tx ok
c8d86be3 4053 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH
4054 priv->stats.txlpokint++;
4055 rtl8180_tx_isr(dev,LOW_PRIORITY,0);
4056 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4057 }
4058
c8d86be3
GKH
4059 if(inta & ISR_TBKDOK){ //corresponding to BK_PRIORITY
4060 priv->stats.txbkpokint++;
c8d86be3
GKH
4061 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4062 rtl8180_tx_isr(dev,BK_PRIORITY,0);
4063 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4064 }
4065
4066 if(inta & ISR_TBEDOK){ //corresponding to BE_PRIORITY
4067 priv->stats.txbeperr++;
c8d86be3
GKH
4068 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4069 rtl8180_tx_isr(dev,BE_PRIORITY,0);
4070 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4071 }
c8d86be3
GKH
4072 force_pci_posting(dev);
4073 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4074
4075 return IRQ_HANDLED;
4076}
4077
c8d86be3
GKH
4078void rtl8180_irq_rx_tasklet(struct r8180_priv* priv)
4079{
c8d86be3 4080 rtl8180_rx(priv->dev);
c8d86be3
GKH
4081}
4082
c8d86be3
GKH
4083void GPIOChangeRFWorkItemCallBack(struct work_struct *work)
4084{
c8d86be3
GKH
4085 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work);
4086 struct net_device *dev = ieee->dev;
4087 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
4088 u8 btPSR;
4089 u8 btConfig0;
4090 RT_RF_POWER_STATE eRfPowerStateToSet;
4091 bool bActuallySet=false;
4092
4093 char *argv[3];
4094 static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh";
4095 static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL};
4096 static int readf_count = 0;
c8d86be3 4097
c8d86be3
GKH
4098 if(readf_count % 10 == 0)
4099 priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state");
4100
4101 readf_count = (readf_count+1)%0xffff;
1994130e 4102 /* We should turn off LED before polling FF51[4]. */
c8d86be3 4103
1994130e
LF
4104 /* Turn off LED. */
4105 btPSR = read_nic_byte(dev, PSR);
4106 write_nic_byte(dev, PSR, (btPSR & ~BIT3));
c8d86be3 4107
1994130e
LF
4108 /* It need to delay 4us suggested by Jong, 2008-01-16 */
4109 udelay(4);
c8d86be3 4110
1994130e
LF
4111 /* HW radio On/Off according to the value of FF51[4](config0) */
4112 btConfig0 = btPSR = read_nic_byte(dev, CONFIG0);
c8d86be3 4113
1994130e 4114 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff;
c8d86be3 4115
6de92dd6
LF
4116 /* Turn LED back on when radio enabled */
4117 if (eRfPowerStateToSet == eRfOn)
4118 write_nic_byte(dev, PSR, btPSR | BIT3);
4119
1994130e
LF
4120 if ((priv->ieee80211->bHwRadioOff == true) &&
4121 (eRfPowerStateToSet == eRfOn)) {
4122 priv->ieee80211->bHwRadioOff = false;
4123 bActuallySet = true;
4124 } else if ((priv->ieee80211->bHwRadioOff == false) &&
4125 (eRfPowerStateToSet == eRfOff)) {
4126 priv->ieee80211->bHwRadioOff = true;
4127 bActuallySet = true;
4128 }
c8d86be3 4129
1994130e
LF
4130 if (bActuallySet) {
4131 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
4132
4133 /* To update the UI status for Power status changed */
4134 if (priv->ieee80211->bHwRadioOff == true)
4135 argv[1] = "RFOFF";
4136 else
4137 argv[1] = "RFON";
4138 argv[0] = RadioPowerPath;
4139 argv[2] = NULL;
4140
4141 call_usermodehelper(RadioPowerPath, argv, envp, 1);
4142 }
c8d86be3
GKH
4143}
4144
4145static u8 read_acadapter_file(char *filename)
4146{
c8d86be3
GKH
4147 return 0;
4148}
4149
c8d86be3
GKH
4150module_init(rtl8180_pci_module_init);
4151module_exit(rtl8180_pci_module_exit);