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4e336dff | 1 | // SPDX-License-Identifier: GPL-2.0 |
b164935b AK |
2 | /* |
3 | * This file is subject to the terms and conditions of the GNU General Public | |
4 | * License. See the file "COPYING" in the main directory of this archive | |
5 | * for more details. | |
6 | * | |
7 | * Copyright (C) 2008 Cavium Networks | |
6570b4a9 AK |
8 | * |
9 | * Some parts of the code were originally released under BSD license: | |
10 | * | |
11 | * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights | |
12 | * reserved. | |
13 | * | |
14 | * Redistribution and use in source and binary forms, with or without | |
15 | * modification, are permitted provided that the following conditions are | |
16 | * met: | |
17 | * | |
18 | * * Redistributions of source code must retain the above copyright | |
19 | * notice, this list of conditions and the following disclaimer. | |
20 | * | |
21 | * * Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials provided | |
24 | * with the distribution. | |
25 | * | |
26 | * * Neither the name of Cavium Networks nor the names of | |
27 | * its contributors may be used to endorse or promote products | |
28 | * derived from this software without specific prior written | |
29 | * permission. | |
30 | * | |
31 | * This Software, including technical data, may be subject to U.S. export | |
32 | * control laws, including the U.S. Export Administration Act and its associated | |
33 | * regulations, and may be subject to export or import regulations in other | |
34 | * countries. | |
35 | * | |
36 | * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" | |
37 | * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR | |
38 | * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO | |
39 | * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION | |
40 | * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM | |
41 | * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, | |
42 | * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF | |
43 | * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR | |
44 | * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR | |
45 | * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. | |
b164935b | 46 | */ |
46665731 AK |
47 | |
48 | #include <linux/usb.h> | |
49 | #include <linux/slab.h> | |
b164935b | 50 | #include <linux/module.h> |
46665731 | 51 | #include <linux/usb/hcd.h> |
20f6b829 | 52 | #include <linux/prefetch.h> |
b164935b | 53 | #include <linux/platform_device.h> |
55fa328a | 54 | |
6570b4a9 | 55 | #include <asm/octeon/octeon.h> |
6570b4a9 | 56 | |
f1219103 | 57 | #include "octeon-hcd.h" |
6570b4a9 AK |
58 | |
59 | /** | |
60 | * enum cvmx_usb_speed - the possible USB device speeds | |
61 | * | |
62 | * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps | |
63 | * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps | |
64 | * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps | |
65 | */ | |
66 | enum cvmx_usb_speed { | |
67 | CVMX_USB_SPEED_HIGH = 0, | |
68 | CVMX_USB_SPEED_FULL = 1, | |
69 | CVMX_USB_SPEED_LOW = 2, | |
70 | }; | |
71 | ||
72 | /** | |
73 | * enum cvmx_usb_transfer - the possible USB transfer types | |
74 | * | |
75 | * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status | |
76 | * transfers | |
77 | * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low | |
78 | * priority periodic transfers | |
79 | * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority | |
80 | * transfers | |
81 | * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority | |
82 | * periodic transfers | |
83 | */ | |
84 | enum cvmx_usb_transfer { | |
85 | CVMX_USB_TRANSFER_CONTROL = 0, | |
86 | CVMX_USB_TRANSFER_ISOCHRONOUS = 1, | |
87 | CVMX_USB_TRANSFER_BULK = 2, | |
88 | CVMX_USB_TRANSFER_INTERRUPT = 3, | |
89 | }; | |
90 | ||
91 | /** | |
92 | * enum cvmx_usb_direction - the transfer directions | |
93 | * | |
94 | * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host | |
95 | * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon | |
96 | */ | |
97 | enum cvmx_usb_direction { | |
98 | CVMX_USB_DIRECTION_OUT, | |
99 | CVMX_USB_DIRECTION_IN, | |
100 | }; | |
101 | ||
102 | /** | |
add3ea32 | 103 | * enum cvmx_usb_status - possible callback function status codes |
6570b4a9 | 104 | * |
b186eb64 | 105 | * @CVMX_USB_STATUS_OK: The transaction / operation finished without |
6570b4a9 | 106 | * any errors |
add3ea32 AK |
107 | * @CVMX_USB_STATUS_SHORT: FIXME: This is currently not implemented |
108 | * @CVMX_USB_STATUS_CANCEL: The transaction was canceled while in flight | |
6570b4a9 | 109 | * by a user call to cvmx_usb_cancel |
add3ea32 | 110 | * @CVMX_USB_STATUS_ERROR: The transaction aborted with an unexpected |
6570b4a9 | 111 | * error status |
add3ea32 | 112 | * @CVMX_USB_STATUS_STALL: The transaction received a USB STALL response |
6570b4a9 | 113 | * from the device |
add3ea32 | 114 | * @CVMX_USB_STATUS_XACTERR: The transaction failed with an error from the |
6570b4a9 | 115 | * device even after a number of retries |
add3ea32 | 116 | * @CVMX_USB_STATUS_DATATGLERR: The transaction failed with a data toggle |
6570b4a9 | 117 | * error even after a number of retries |
add3ea32 AK |
118 | * @CVMX_USB_STATUS_BABBLEERR: The transaction failed with a babble error |
119 | * @CVMX_USB_STATUS_FRAMEERR: The transaction failed with a frame error | |
6570b4a9 AK |
120 | * even after a number of retries |
121 | */ | |
add3ea32 | 122 | enum cvmx_usb_status { |
b186eb64 | 123 | CVMX_USB_STATUS_OK, |
add3ea32 AK |
124 | CVMX_USB_STATUS_SHORT, |
125 | CVMX_USB_STATUS_CANCEL, | |
126 | CVMX_USB_STATUS_ERROR, | |
127 | CVMX_USB_STATUS_STALL, | |
128 | CVMX_USB_STATUS_XACTERR, | |
129 | CVMX_USB_STATUS_DATATGLERR, | |
130 | CVMX_USB_STATUS_BABBLEERR, | |
131 | CVMX_USB_STATUS_FRAMEERR, | |
6570b4a9 AK |
132 | }; |
133 | ||
134 | /** | |
135 | * struct cvmx_usb_port_status - the USB port status information | |
136 | * | |
137 | * @port_enabled: 1 = Usb port is enabled, 0 = disabled | |
138 | * @port_over_current: 1 = Over current detected, 0 = Over current not | |
139 | * detected. Octeon doesn't support over current detection. | |
140 | * @port_powered: 1 = Port power is being supplied to the device, 0 = | |
141 | * power is off. Octeon doesn't support turning port power | |
142 | * off. | |
143 | * @port_speed: Current port speed. | |
144 | * @connected: 1 = A device is connected to the port, 0 = No device is | |
145 | * connected. | |
146 | * @connect_change: 1 = Device connected state changed since the last set | |
147 | * status call. | |
148 | */ | |
149 | struct cvmx_usb_port_status { | |
cce66005 AK |
150 | u32 reserved : 25; |
151 | u32 port_enabled : 1; | |
152 | u32 port_over_current : 1; | |
153 | u32 port_powered : 1; | |
6570b4a9 | 154 | enum cvmx_usb_speed port_speed : 2; |
cce66005 AK |
155 | u32 connected : 1; |
156 | u32 connect_change : 1; | |
6570b4a9 AK |
157 | }; |
158 | ||
6570b4a9 AK |
159 | /** |
160 | * struct cvmx_usb_iso_packet - descriptor for Isochronous packets | |
161 | * | |
162 | * @offset: This is the offset in bytes into the main buffer where this data | |
163 | * is stored. | |
164 | * @length: This is the length in bytes of the data. | |
165 | * @status: This is the status of this individual packet transfer. | |
166 | */ | |
167 | struct cvmx_usb_iso_packet { | |
168 | int offset; | |
169 | int length; | |
add3ea32 | 170 | enum cvmx_usb_status status; |
6570b4a9 AK |
171 | }; |
172 | ||
6570b4a9 AK |
173 | /** |
174 | * enum cvmx_usb_initialize_flags - flags used by the initialization function | |
175 | * | |
176 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal | |
177 | * as clock source at USB_XO and | |
178 | * USB_XI. | |
179 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V | |
180 | * board clock source at USB_XO. | |
181 | * USB_XI should be tied to GND. | |
182 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field | |
183 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or | |
184 | * crystal | |
185 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock | |
186 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock | |
187 | * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for | |
188 | * data transfer use for the USB | |
189 | */ | |
190 | enum cvmx_usb_initialize_flags { | |
191 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0, | |
192 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1, | |
193 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3, | |
194 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3, | |
195 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3, | |
196 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3, | |
197 | /* Bits 3-4 used to encode the clock frequency */ | |
198 | CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5, | |
199 | }; | |
200 | ||
201 | /** | |
202 | * enum cvmx_usb_pipe_flags - internal flags for a pipe. | |
203 | * | |
3f9697b7 AK |
204 | * @CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is |
205 | * actively using hardware. | |
206 | * @CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high speed | |
207 | * pipe is in the ping state. | |
6570b4a9 AK |
208 | */ |
209 | enum cvmx_usb_pipe_flags { | |
3f9697b7 AK |
210 | CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17, |
211 | CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18, | |
6570b4a9 AK |
212 | }; |
213 | ||
6570b4a9 AK |
214 | /* Maximum number of times to retry failed transactions */ |
215 | #define MAX_RETRIES 3 | |
216 | ||
6570b4a9 AK |
217 | /* Maximum number of hardware channels supported by the USB block */ |
218 | #define MAX_CHANNELS 8 | |
219 | ||
6570b4a9 AK |
220 | /* |
221 | * The low level hardware can transfer a maximum of this number of bytes in each | |
222 | * transfer. The field is 19 bits wide | |
223 | */ | |
3c98ef90 | 224 | #define MAX_TRANSFER_BYTES ((1 << 19) - 1) |
6570b4a9 AK |
225 | |
226 | /* | |
227 | * The low level hardware can transfer a maximum of this number of packets in | |
228 | * each transfer. The field is 10 bits wide | |
229 | */ | |
3c98ef90 | 230 | #define MAX_TRANSFER_PACKETS ((1 << 10) - 1) |
6570b4a9 | 231 | |
6570b4a9 AK |
232 | /** |
233 | * Logical transactions may take numerous low level | |
234 | * transactions, especially when splits are concerned. This | |
235 | * enum represents all of the possible stages a transaction can | |
236 | * be in. Note that split completes are always even. This is so | |
237 | * the NAK handler can backup to the previous low level | |
238 | * transaction with a simple clearing of bit 0. | |
239 | */ | |
240 | enum cvmx_usb_stage { | |
241 | CVMX_USB_STAGE_NON_CONTROL, | |
242 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE, | |
243 | CVMX_USB_STAGE_SETUP, | |
244 | CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE, | |
245 | CVMX_USB_STAGE_DATA, | |
246 | CVMX_USB_STAGE_DATA_SPLIT_COMPLETE, | |
247 | CVMX_USB_STAGE_STATUS, | |
248 | CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE, | |
249 | }; | |
250 | ||
251 | /** | |
252 | * struct cvmx_usb_transaction - describes each pending USB transaction | |
253 | * regardless of type. These are linked together | |
254 | * to form a list of pending requests for a pipe. | |
255 | * | |
5669601d | 256 | * @node: List node for transactions in the pipe. |
6570b4a9 AK |
257 | * @type: Type of transaction, duplicated of the pipe. |
258 | * @flags: State flags for this transaction. | |
259 | * @buffer: User's physical buffer address to read/write. | |
260 | * @buffer_length: Size of the user's buffer in bytes. | |
261 | * @control_header: For control transactions, physical address of the 8 | |
262 | * byte standard header. | |
263 | * @iso_start_frame: For ISO transactions, the starting frame number. | |
264 | * @iso_number_packets: For ISO transactions, the number of packets in the | |
265 | * request. | |
266 | * @iso_packets: For ISO transactions, the sub packets in the request. | |
267 | * @actual_bytes: Actual bytes transfer for this transaction. | |
268 | * @stage: For control transactions, the current stage. | |
0cce1004 | 269 | * @urb: URB. |
6570b4a9 AK |
270 | */ |
271 | struct cvmx_usb_transaction { | |
5669601d | 272 | struct list_head node; |
6570b4a9 | 273 | enum cvmx_usb_transfer type; |
cce66005 | 274 | u64 buffer; |
6570b4a9 | 275 | int buffer_length; |
cce66005 | 276 | u64 control_header; |
6570b4a9 AK |
277 | int iso_start_frame; |
278 | int iso_number_packets; | |
279 | struct cvmx_usb_iso_packet *iso_packets; | |
280 | int xfersize; | |
281 | int pktcnt; | |
282 | int retries; | |
283 | int actual_bytes; | |
284 | enum cvmx_usb_stage stage; | |
0cce1004 | 285 | struct urb *urb; |
6570b4a9 AK |
286 | }; |
287 | ||
288 | /** | |
289 | * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon | |
290 | * and some USB device. It contains a list of pending | |
291 | * request to the device. | |
292 | * | |
4a23ee1b | 293 | * @node: List node for pipe list |
6570b4a9 | 294 | * @next: Pipe after this one in the list |
5669601d | 295 | * @transactions: List of pending transactions |
6570b4a9 AK |
296 | * @interval: For periodic pipes, the interval between packets in |
297 | * frames | |
298 | * @next_tx_frame: The next frame this pipe is allowed to transmit on | |
299 | * @flags: State flags for this pipe | |
300 | * @device_speed: Speed of device connected to this pipe | |
301 | * @transfer_type: Type of transaction supported by this pipe | |
302 | * @transfer_dir: IN or OUT. Ignored for Control | |
303 | * @multi_count: Max packet in a row for the device | |
304 | * @max_packet: The device's maximum packet size in bytes | |
305 | * @device_addr: USB device address at other end of pipe | |
306 | * @endpoint_num: USB endpoint number at other end of pipe | |
307 | * @hub_device_addr: Hub address this device is connected to | |
308 | * @hub_port: Hub port this device is connected to | |
309 | * @pid_toggle: This toggles between 0/1 on every packet send to track | |
310 | * the data pid needed | |
311 | * @channel: Hardware DMA channel for this pipe | |
312 | * @split_sc_frame: The low order bits of the frame number the split | |
313 | * complete should be sent on | |
314 | */ | |
315 | struct cvmx_usb_pipe { | |
4a23ee1b | 316 | struct list_head node; |
5669601d | 317 | struct list_head transactions; |
cce66005 AK |
318 | u64 interval; |
319 | u64 next_tx_frame; | |
6570b4a9 AK |
320 | enum cvmx_usb_pipe_flags flags; |
321 | enum cvmx_usb_speed device_speed; | |
322 | enum cvmx_usb_transfer transfer_type; | |
323 | enum cvmx_usb_direction transfer_dir; | |
324 | int multi_count; | |
cce66005 AK |
325 | u16 max_packet; |
326 | u8 device_addr; | |
327 | u8 endpoint_num; | |
328 | u8 hub_device_addr; | |
329 | u8 hub_port; | |
330 | u8 pid_toggle; | |
331 | u8 channel; | |
332 | s8 split_sc_frame; | |
6570b4a9 AK |
333 | }; |
334 | ||
6570b4a9 AK |
335 | struct cvmx_usb_tx_fifo { |
336 | struct { | |
337 | int channel; | |
338 | int size; | |
cce66005 | 339 | u64 address; |
3c98ef90 | 340 | } entry[MAX_CHANNELS + 1]; |
6570b4a9 AK |
341 | int head; |
342 | int tail; | |
343 | }; | |
344 | ||
345 | /** | |
8b07d2fe | 346 | * struct octeon_hcd - the state of the USB block |
6570b4a9 | 347 | * |
8b07d2fe | 348 | * lock: Serialization lock. |
6570b4a9 AK |
349 | * init_flags: Flags passed to initialize. |
350 | * index: Which USB block this is for. | |
351 | * idle_hardware_channels: Bit set for every idle hardware channel. | |
352 | * usbcx_hprt: Stored port status so we don't need to read a CSR to | |
353 | * determine splits. | |
354 | * pipe_for_channel: Map channels to pipes. | |
6570b4a9 | 355 | * pipe: Storage for pipes. |
6570b4a9 AK |
356 | * indent: Used by debug output to indent functions. |
357 | * port_status: Last port status used for change notification. | |
6570b4a9 AK |
358 | * idle_pipes: List of open pipes that have no transactions. |
359 | * active_pipes: Active pipes indexed by transfer type. | |
360 | * frame_number: Increments every SOF interrupt for time keeping. | |
361 | * active_split: Points to the current active split, or NULL. | |
362 | */ | |
8b07d2fe AK |
363 | struct octeon_hcd { |
364 | spinlock_t lock; /* serialization lock */ | |
6570b4a9 AK |
365 | int init_flags; |
366 | int index; | |
367 | int idle_hardware_channels; | |
368 | union cvmx_usbcx_hprt usbcx_hprt; | |
369 | struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS]; | |
6570b4a9 AK |
370 | int indent; |
371 | struct cvmx_usb_port_status port_status; | |
4a23ee1b AK |
372 | struct list_head idle_pipes; |
373 | struct list_head active_pipes[4]; | |
cce66005 | 374 | u64 frame_number; |
6570b4a9 AK |
375 | struct cvmx_usb_transaction *active_split; |
376 | struct cvmx_usb_tx_fifo periodic; | |
377 | struct cvmx_usb_tx_fifo nonperiodic; | |
378 | }; | |
379 | ||
6570b4a9 AK |
380 | /* |
381 | * This macro logically sets a single field in a CSR. It does the sequence | |
382 | * read, modify, and write | |
383 | */ | |
6068e818 | 384 | #define USB_SET_FIELD32(address, _union, field, value) \ |
6570b4a9 | 385 | do { \ |
6068e818 AK |
386 | union _union c; \ |
387 | \ | |
68d435dd | 388 | c.u32 = cvmx_usb_read_csr32(usb, address); \ |
6570b4a9 | 389 | c.s.field = value; \ |
68d435dd | 390 | cvmx_usb_write_csr32(usb, address, c.u32); \ |
6570b4a9 AK |
391 | } while (0) |
392 | ||
393 | /* Returns the IO address to push/pop stuff data from the FIFOs */ | |
e725cef3 | 394 | #define USB_FIFO_ADDRESS(channel, usb_index) \ |
3c98ef90 | 395 | (CVMX_USBCX_GOTGCTL(usb_index) + ((channel) + 1) * 0x1000) |
6570b4a9 | 396 | |
120ee599 AK |
397 | /** |
398 | * struct octeon_temp_buffer - a bounce buffer for USB transfers | |
120ee599 AK |
399 | * @orig_buffer: the original buffer passed by the USB stack |
400 | * @data: the newly allocated temporary buffer (excluding meta-data) | |
401 | * | |
402 | * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If | |
403 | * the buffer is too short, we need to allocate a temporary one, and this struct | |
404 | * represents it. | |
405 | */ | |
406 | struct octeon_temp_buffer { | |
120ee599 AK |
407 | void *orig_buffer; |
408 | u8 data[0]; | |
409 | }; | |
410 | ||
2e6ac45c AK |
411 | static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p) |
412 | { | |
413 | return container_of((void *)p, struct usb_hcd, hcd_priv); | |
414 | } | |
415 | ||
120ee599 AK |
416 | /** |
417 | * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer | |
418 | * (if needed) | |
419 | * @urb: URB. | |
420 | * @mem_flags: Memory allocation flags. | |
421 | * | |
422 | * This function allocates a temporary bounce buffer whenever it's needed | |
423 | * due to HW limitations. | |
424 | */ | |
425 | static int octeon_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) | |
426 | { | |
427 | struct octeon_temp_buffer *temp; | |
428 | ||
429 | if (urb->num_sgs || urb->sg || | |
430 | (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) || | |
431 | !(urb->transfer_buffer_length % sizeof(u32))) | |
432 | return 0; | |
433 | ||
434 | temp = kmalloc(ALIGN(urb->transfer_buffer_length, sizeof(u32)) + | |
435 | sizeof(*temp), mem_flags); | |
436 | if (!temp) | |
437 | return -ENOMEM; | |
438 | ||
120ee599 AK |
439 | temp->orig_buffer = urb->transfer_buffer; |
440 | if (usb_urb_dir_out(urb)) | |
441 | memcpy(temp->data, urb->transfer_buffer, | |
442 | urb->transfer_buffer_length); | |
443 | urb->transfer_buffer = temp->data; | |
444 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | /** | |
450 | * octeon_free_temp_buffer - free a temporary buffer used by USB transfers. | |
451 | * @urb: URB. | |
452 | * | |
453 | * Frees a buffer allocated by octeon_alloc_temp_buffer(). | |
454 | */ | |
455 | static void octeon_free_temp_buffer(struct urb *urb) | |
456 | { | |
457 | struct octeon_temp_buffer *temp; | |
b97c3c1a | 458 | size_t length; |
120ee599 AK |
459 | |
460 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
461 | return; | |
462 | ||
463 | temp = container_of(urb->transfer_buffer, struct octeon_temp_buffer, | |
464 | data); | |
b97c3c1a JH |
465 | if (usb_urb_dir_in(urb)) { |
466 | if (usb_pipeisoc(urb->pipe)) | |
467 | length = urb->transfer_buffer_length; | |
468 | else | |
469 | length = urb->actual_length; | |
470 | ||
471 | memcpy(temp->orig_buffer, urb->transfer_buffer, length); | |
472 | } | |
120ee599 AK |
473 | urb->transfer_buffer = temp->orig_buffer; |
474 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
31170da5 | 475 | kfree(temp); |
120ee599 AK |
476 | } |
477 | ||
478 | /** | |
479 | * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma(). | |
480 | * @hcd: USB HCD structure. | |
481 | * @urb: URB. | |
482 | * @mem_flags: Memory allocation flags. | |
483 | */ | |
484 | static int octeon_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
485 | gfp_t mem_flags) | |
486 | { | |
487 | int ret; | |
488 | ||
489 | ret = octeon_alloc_temp_buffer(urb, mem_flags); | |
490 | if (ret) | |
491 | return ret; | |
492 | ||
493 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
494 | if (ret) | |
495 | octeon_free_temp_buffer(urb); | |
496 | ||
497 | return ret; | |
498 | } | |
499 | ||
500 | /** | |
501 | * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma() | |
502 | * @hcd: USB HCD structure. | |
503 | * @urb: URB. | |
504 | */ | |
505 | static void octeon_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
506 | { | |
507 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
508 | octeon_free_temp_buffer(urb); | |
509 | } | |
510 | ||
6570b4a9 AK |
511 | /** |
512 | * Read a USB 32bit CSR. It performs the necessary address swizzle | |
513 | * for 32bit CSRs and logs the value in a readable format if | |
514 | * debugging is on. | |
515 | * | |
516 | * @usb: USB block this access is for | |
517 | * @address: 64bit address to read | |
518 | * | |
519 | * Returns: Result of the read | |
520 | */ | |
8b07d2fe | 521 | static inline u32 cvmx_usb_read_csr32(struct octeon_hcd *usb, u64 address) |
6570b4a9 | 522 | { |
cce66005 | 523 | u32 result = cvmx_read64_uint32(address ^ 4); |
6570b4a9 AK |
524 | return result; |
525 | } | |
526 | ||
6570b4a9 AK |
527 | /** |
528 | * Write a USB 32bit CSR. It performs the necessary address | |
529 | * swizzle for 32bit CSRs and logs the value in a readable format | |
530 | * if debugging is on. | |
531 | * | |
532 | * @usb: USB block this access is for | |
533 | * @address: 64bit address to write | |
534 | * @value: Value to write | |
535 | */ | |
8b07d2fe | 536 | static inline void cvmx_usb_write_csr32(struct octeon_hcd *usb, |
cce66005 | 537 | u64 address, u32 value) |
6570b4a9 AK |
538 | { |
539 | cvmx_write64_uint32(address ^ 4, value); | |
540 | cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index)); | |
541 | } | |
542 | ||
6570b4a9 AK |
543 | /** |
544 | * Return non zero if this pipe connects to a non HIGH speed | |
545 | * device through a high speed hub. | |
546 | * | |
547 | * @usb: USB block this access is for | |
548 | * @pipe: Pipe to check | |
549 | * | |
550 | * Returns: Non zero if we need to do split transactions | |
551 | */ | |
8b07d2fe | 552 | static inline int cvmx_usb_pipe_needs_split(struct octeon_hcd *usb, |
68d435dd | 553 | struct cvmx_usb_pipe *pipe) |
6570b4a9 | 554 | { |
aa87afe2 AK |
555 | return pipe->device_speed != CVMX_USB_SPEED_HIGH && |
556 | usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH; | |
6570b4a9 AK |
557 | } |
558 | ||
6570b4a9 AK |
559 | /** |
560 | * Trivial utility function to return the correct PID for a pipe | |
561 | * | |
562 | * @pipe: pipe to check | |
563 | * | |
564 | * Returns: PID for pipe | |
565 | */ | |
68d435dd | 566 | static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe) |
6570b4a9 AK |
567 | { |
568 | if (pipe->pid_toggle) | |
569 | return 2; /* Data1 */ | |
c9a114e7 | 570 | return 0; /* Data0 */ |
6570b4a9 AK |
571 | } |
572 | ||
3e195a80 GT |
573 | /* Loops through register until txfflsh or rxfflsh become zero.*/ |
574 | static int cvmx_wait_tx_rx(struct octeon_hcd *usb, int fflsh_type) | |
575 | { | |
576 | int result; | |
577 | u64 address = CVMX_USBCX_GRSTCTL(usb->index); | |
578 | u64 done = cvmx_get_cycle() + 100 * | |
579 | (u64)octeon_get_clock_rate / 1000000; | |
580 | union cvmx_usbcx_grstctl c; | |
581 | ||
582 | while (1) { | |
583 | c.u32 = cvmx_usb_read_csr32(usb, address); | |
584 | if (fflsh_type == 0 && c.s.txfflsh == 0) { | |
585 | result = 0; | |
586 | break; | |
587 | } else if (fflsh_type == 1 && c.s.rxfflsh == 0) { | |
588 | result = 0; | |
589 | break; | |
590 | } else if (cvmx_get_cycle() > done) { | |
591 | result = -1; | |
592 | break; | |
593 | } | |
594 | ||
595 | __delay(100); | |
596 | } | |
597 | return result; | |
598 | } | |
599 | ||
8b07d2fe | 600 | static void cvmx_fifo_setup(struct octeon_hcd *usb) |
2263251f AK |
601 | { |
602 | union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3; | |
603 | union cvmx_usbcx_gnptxfsiz npsiz; | |
604 | union cvmx_usbcx_hptxfsiz psiz; | |
605 | ||
606 | usbcx_ghwcfg3.u32 = cvmx_usb_read_csr32(usb, | |
607 | CVMX_USBCX_GHWCFG3(usb->index)); | |
608 | ||
609 | /* | |
610 | * Program the USBC_GRXFSIZ register to select the size of the receive | |
611 | * FIFO (25%). | |
612 | */ | |
6068e818 AK |
613 | USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz, |
614 | rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4); | |
2263251f AK |
615 | |
616 | /* | |
617 | * Program the USBC_GNPTXFSIZ register to select the size and the start | |
618 | * address of the non-periodic transmit FIFO for nonperiodic | |
619 | * transactions (50%). | |
620 | */ | |
621 | npsiz.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index)); | |
622 | npsiz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2; | |
623 | npsiz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4; | |
624 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), npsiz.u32); | |
625 | ||
626 | /* | |
627 | * Program the USBC_HPTXFSIZ register to select the size and start | |
628 | * address of the periodic transmit FIFO for periodic transactions | |
629 | * (25%). | |
630 | */ | |
631 | psiz.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index)); | |
632 | psiz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4; | |
633 | psiz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4; | |
634 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), psiz.u32); | |
635 | ||
636 | /* Flush all FIFOs */ | |
637 | USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), | |
6068e818 | 638 | cvmx_usbcx_grstctl, txfnum, 0x10); |
2263251f | 639 | USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), |
6068e818 | 640 | cvmx_usbcx_grstctl, txfflsh, 1); |
3e195a80 | 641 | cvmx_wait_tx_rx(usb, 0); |
2263251f | 642 | USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), |
6068e818 | 643 | cvmx_usbcx_grstctl, rxfflsh, 1); |
3e195a80 | 644 | cvmx_wait_tx_rx(usb, 1); |
2263251f AK |
645 | } |
646 | ||
eb04114f AK |
647 | /** |
648 | * Shutdown a USB port after a call to cvmx_usb_initialize(). | |
649 | * The port should be disabled with all pipes closed when this | |
650 | * function is called. | |
651 | * | |
652 | * @usb: USB device state populated by cvmx_usb_initialize(). | |
653 | * | |
654 | * Returns: 0 or a negative error code. | |
655 | */ | |
8b07d2fe | 656 | static int cvmx_usb_shutdown(struct octeon_hcd *usb) |
eb04114f AK |
657 | { |
658 | union cvmx_usbnx_clk_ctl usbn_clk_ctl; | |
659 | ||
660 | /* Make sure all pipes are closed */ | |
661 | if (!list_empty(&usb->idle_pipes) || | |
662 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS]) || | |
663 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT]) || | |
664 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_CONTROL]) || | |
665 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_BULK])) | |
666 | return -EBUSY; | |
667 | ||
668 | /* Disable the clocks and put them in power on reset */ | |
669 | usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index)); | |
670 | usbn_clk_ctl.s.enable = 1; | |
671 | usbn_clk_ctl.s.por = 1; | |
672 | usbn_clk_ctl.s.hclk_rst = 1; | |
673 | usbn_clk_ctl.s.prst = 0; | |
674 | usbn_clk_ctl.s.hrst = 0; | |
675 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); | |
676 | return 0; | |
677 | } | |
678 | ||
6570b4a9 AK |
679 | /** |
680 | * Initialize a USB port for use. This must be called before any | |
681 | * other access to the Octeon USB port is made. The port starts | |
682 | * off in the disabled state. | |
683 | * | |
6ad9c95b | 684 | * @dev: Pointer to struct device for logging purposes. |
8b07d2fe | 685 | * @usb: Pointer to struct octeon_hcd. |
6570b4a9 AK |
686 | * |
687 | * Returns: 0 or a negative error code. | |
688 | */ | |
6ad9c95b | 689 | static int cvmx_usb_initialize(struct device *dev, |
8b07d2fe | 690 | struct octeon_hcd *usb) |
6570b4a9 | 691 | { |
edc16d8d AK |
692 | int channel; |
693 | int divisor; | |
6ad9c95b | 694 | int retries = 0; |
edc16d8d | 695 | union cvmx_usbcx_hcfg usbcx_hcfg; |
6570b4a9 | 696 | union cvmx_usbnx_clk_ctl usbn_clk_ctl; |
6ad9c95b | 697 | union cvmx_usbcx_gintsts usbc_gintsts; |
edc16d8d AK |
698 | union cvmx_usbcx_gahbcfg usbcx_gahbcfg; |
699 | union cvmx_usbcx_gintmsk usbcx_gintmsk; | |
700 | union cvmx_usbcx_gusbcfg usbcx_gusbcfg; | |
6570b4a9 | 701 | union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status; |
6570b4a9 | 702 | |
6ad9c95b | 703 | retry: |
6570b4a9 AK |
704 | /* |
705 | * Power On Reset and PHY Initialization | |
706 | * | |
707 | * 1. Wait for DCOK to assert (nothing to do) | |
708 | * | |
709 | * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and | |
710 | * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0 | |
711 | */ | |
c4bdbdd9 | 712 | usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index)); |
6570b4a9 AK |
713 | usbn_clk_ctl.s.por = 1; |
714 | usbn_clk_ctl.s.hrst = 0; | |
715 | usbn_clk_ctl.s.prst = 0; | |
716 | usbn_clk_ctl.s.hclk_rst = 0; | |
717 | usbn_clk_ctl.s.enable = 0; | |
718 | /* | |
719 | * 2b. Select the USB reference clock/crystal parameters by writing | |
720 | * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON] | |
721 | */ | |
722 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) { | |
723 | /* | |
724 | * The USB port uses 12/24/48MHz 2.5V board clock | |
725 | * source at USB_XO. USB_XI should be tied to GND. | |
726 | * Most Octeon evaluation boards require this setting | |
727 | */ | |
7d7bc26b AK |
728 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || |
729 | OCTEON_IS_MODEL(OCTEON_CN56XX) || | |
730 | OCTEON_IS_MODEL(OCTEON_CN50XX)) | |
731 | /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */ | |
732 | usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */ | |
6570b4a9 AK |
733 | else |
734 | /* From CN52XX manual */ | |
34b70b9e | 735 | usbn_clk_ctl.s.p_rtype = 1; |
6570b4a9 | 736 | |
b5e79e6e AK |
737 | switch (usb->init_flags & |
738 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) { | |
6570b4a9 AK |
739 | case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: |
740 | usbn_clk_ctl.s.p_c_sel = 0; | |
741 | break; | |
742 | case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: | |
743 | usbn_clk_ctl.s.p_c_sel = 1; | |
744 | break; | |
745 | case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: | |
746 | usbn_clk_ctl.s.p_c_sel = 2; | |
747 | break; | |
748 | } | |
749 | } else { | |
750 | /* | |
751 | * The USB port uses a 12MHz crystal as clock source | |
752 | * at USB_XO and USB_XI | |
753 | */ | |
7d7bc26b | 754 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) |
6570b4a9 | 755 | /* From CN31XX,CN30XX manual */ |
7d7bc26b | 756 | usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */ |
6570b4a9 | 757 | else |
7d7bc26b | 758 | /* From CN56XX,CN52XX,CN50XX manuals. */ |
34b70b9e | 759 | usbn_clk_ctl.s.p_rtype = 0; |
6570b4a9 AK |
760 | |
761 | usbn_clk_ctl.s.p_c_sel = 0; | |
762 | } | |
763 | /* | |
764 | * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and | |
765 | * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down | |
766 | * such that USB is as close as possible to 125Mhz | |
767 | */ | |
edc16d8d AK |
768 | divisor = DIV_ROUND_UP(octeon_get_clock_rate(), 125000000); |
769 | /* Lower than 4 doesn't seem to work properly */ | |
770 | if (divisor < 4) | |
771 | divisor = 4; | |
772 | usbn_clk_ctl.s.divide = divisor; | |
773 | usbn_clk_ctl.s.divide2 = 0; | |
c4bdbdd9 | 774 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
edc16d8d | 775 | |
6570b4a9 AK |
776 | /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */ |
777 | usbn_clk_ctl.s.hclk_rst = 1; | |
c4bdbdd9 | 778 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 | 779 | /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */ |
0590cdfe | 780 | __delay(64); |
6570b4a9 AK |
781 | /* |
782 | * 3. Program the power-on reset field in the USBN clock-control | |
783 | * register: | |
784 | * USBN_CLK_CTL[POR] = 0 | |
785 | */ | |
786 | usbn_clk_ctl.s.por = 0; | |
c4bdbdd9 | 787 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
788 | /* 4. Wait 1 ms for PHY clock to start */ |
789 | mdelay(1); | |
790 | /* | |
791 | * 5. Program the Reset input from automatic test equipment field in the | |
792 | * USBP control and status register: | |
793 | * USBN_USBP_CTL_STATUS[ATE_RESET] = 1 | |
794 | */ | |
c4bdbdd9 AK |
795 | usbn_usbp_ctl_status.u64 = |
796 | cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index)); | |
6570b4a9 | 797 | usbn_usbp_ctl_status.s.ate_reset = 1; |
c4bdbdd9 AK |
798 | cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), |
799 | usbn_usbp_ctl_status.u64); | |
6570b4a9 | 800 | /* 6. Wait 10 cycles */ |
0590cdfe | 801 | __delay(10); |
6570b4a9 AK |
802 | /* |
803 | * 7. Clear ATE_RESET field in the USBN clock-control register: | |
804 | * USBN_USBP_CTL_STATUS[ATE_RESET] = 0 | |
805 | */ | |
806 | usbn_usbp_ctl_status.s.ate_reset = 0; | |
c4bdbdd9 AK |
807 | cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), |
808 | usbn_usbp_ctl_status.u64); | |
6570b4a9 AK |
809 | /* |
810 | * 8. Program the PHY reset field in the USBN clock-control register: | |
811 | * USBN_CLK_CTL[PRST] = 1 | |
812 | */ | |
813 | usbn_clk_ctl.s.prst = 1; | |
c4bdbdd9 | 814 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
815 | /* |
816 | * 9. Program the USBP control and status register to select host or | |
817 | * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for | |
818 | * device | |
819 | */ | |
820 | usbn_usbp_ctl_status.s.hst_mode = 0; | |
c4bdbdd9 AK |
821 | cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), |
822 | usbn_usbp_ctl_status.u64); | |
6570b4a9 AK |
823 | /* 10. Wait 1 us */ |
824 | udelay(1); | |
825 | /* | |
826 | * 11. Program the hreset_n field in the USBN clock-control register: | |
827 | * USBN_CLK_CTL[HRST] = 1 | |
828 | */ | |
829 | usbn_clk_ctl.s.hrst = 1; | |
c4bdbdd9 | 830 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
831 | /* 12. Proceed to USB core initialization */ |
832 | usbn_clk_ctl.s.enable = 1; | |
c4bdbdd9 | 833 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
834 | udelay(1); |
835 | ||
836 | /* | |
837 | * USB Core Initialization | |
838 | * | |
839 | * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to | |
840 | * determine USB core configuration parameters. | |
841 | * | |
842 | * Nothing needed | |
843 | * | |
844 | * 2. Program the following fields in the global AHB configuration | |
845 | * register (USBC_GAHBCFG) | |
846 | * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode | |
847 | * Burst length, USBC_GAHBCFG[HBSTLEN] = 0 | |
848 | * Nonperiodic TxFIFO empty level (slave mode only), | |
849 | * USBC_GAHBCFG[NPTXFEMPLVL] | |
850 | * Periodic TxFIFO empty level (slave mode only), | |
851 | * USBC_GAHBCFG[PTXFEMPLVL] | |
852 | * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 | |
853 | */ | |
edc16d8d AK |
854 | usbcx_gahbcfg.u32 = 0; |
855 | usbcx_gahbcfg.s.dmaen = !(usb->init_flags & | |
856 | CVMX_USB_INITIALIZE_FLAGS_NO_DMA); | |
857 | usbcx_gahbcfg.s.hbstlen = 0; | |
858 | usbcx_gahbcfg.s.nptxfemplvl = 1; | |
859 | usbcx_gahbcfg.s.ptxfemplvl = 1; | |
860 | usbcx_gahbcfg.s.glblintrmsk = 1; | |
861 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index), | |
862 | usbcx_gahbcfg.u32); | |
863 | ||
6570b4a9 AK |
864 | /* |
865 | * 3. Program the following fields in USBC_GUSBCFG register. | |
866 | * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0 | |
867 | * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0 | |
868 | * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5 | |
869 | * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0 | |
870 | */ | |
edc16d8d AK |
871 | usbcx_gusbcfg.u32 = cvmx_usb_read_csr32(usb, |
872 | CVMX_USBCX_GUSBCFG(usb->index)); | |
873 | usbcx_gusbcfg.s.toutcal = 0; | |
874 | usbcx_gusbcfg.s.ddrsel = 0; | |
875 | usbcx_gusbcfg.s.usbtrdtim = 0x5; | |
876 | usbcx_gusbcfg.s.phylpwrclksel = 0; | |
877 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index), | |
878 | usbcx_gusbcfg.u32); | |
879 | ||
6570b4a9 AK |
880 | /* |
881 | * 4. The software must unmask the following bits in the USBC_GINTMSK | |
882 | * register. | |
883 | * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1 | |
884 | * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1 | |
885 | */ | |
edc16d8d AK |
886 | usbcx_gintmsk.u32 = cvmx_usb_read_csr32(usb, |
887 | CVMX_USBCX_GINTMSK(usb->index)); | |
888 | usbcx_gintmsk.s.otgintmsk = 1; | |
889 | usbcx_gintmsk.s.modemismsk = 1; | |
890 | usbcx_gintmsk.s.hchintmsk = 1; | |
891 | usbcx_gintmsk.s.sofmsk = 0; | |
892 | /* We need RX FIFO interrupts if we don't have DMA */ | |
893 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) | |
894 | usbcx_gintmsk.s.rxflvlmsk = 1; | |
895 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index), | |
896 | usbcx_gintmsk.u32); | |
6570b4a9 | 897 | |
edc16d8d AK |
898 | /* |
899 | * Disable all channel interrupts. We'll enable them per channel later. | |
900 | */ | |
901 | for (channel = 0; channel < 8; channel++) | |
902 | cvmx_usb_write_csr32(usb, | |
903 | CVMX_USBCX_HCINTMSKX(channel, usb->index), | |
904 | 0); | |
6570b4a9 | 905 | |
edc16d8d AK |
906 | /* |
907 | * Host Port Initialization | |
908 | * | |
909 | * 1. Program the host-port interrupt-mask field to unmask, | |
910 | * USBC_GINTMSK[PRTINT] = 1 | |
911 | */ | |
912 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), | |
6068e818 | 913 | cvmx_usbcx_gintmsk, prtintmsk, 1); |
edc16d8d | 914 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
6068e818 | 915 | cvmx_usbcx_gintmsk, disconnintmsk, 1); |
6570b4a9 | 916 | |
edc16d8d AK |
917 | /* |
918 | * 2. Program the USBC_HCFG register to select full-speed host | |
919 | * or high-speed host. | |
920 | */ | |
921 | usbcx_hcfg.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index)); | |
922 | usbcx_hcfg.s.fslssupp = 0; | |
923 | usbcx_hcfg.s.fslspclksel = 0; | |
924 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32); | |
6570b4a9 | 925 | |
164814bb AK |
926 | cvmx_fifo_setup(usb); |
927 | ||
6ad9c95b AK |
928 | /* |
929 | * If the controller is getting port events right after the reset, it | |
930 | * means the initialization failed. Try resetting the controller again | |
931 | * in such case. This is seen to happen after cold boot on DSR-1000N. | |
932 | */ | |
933 | usbc_gintsts.u32 = cvmx_usb_read_csr32(usb, | |
934 | CVMX_USBCX_GINTSTS(usb->index)); | |
935 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), | |
936 | usbc_gintsts.u32); | |
937 | dev_dbg(dev, "gintsts after reset: 0x%x\n", (int)usbc_gintsts.u32); | |
938 | if (!usbc_gintsts.s.disconnint && !usbc_gintsts.s.prtint) | |
939 | return 0; | |
940 | if (retries++ >= 5) | |
941 | return -EAGAIN; | |
942 | dev_info(dev, "controller reset failed (gintsts=0x%x) - retrying\n", | |
943 | (int)usbc_gintsts.u32); | |
944 | msleep(50); | |
945 | cvmx_usb_shutdown(usb); | |
946 | msleep(50); | |
947 | goto retry; | |
6570b4a9 AK |
948 | } |
949 | ||
6570b4a9 | 950 | /** |
b0c8c72b | 951 | * Reset a USB port. After this call succeeds, the USB port is |
6570b4a9 AK |
952 | * online and servicing requests. |
953 | * | |
cb61c600 | 954 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 | 955 | */ |
8b07d2fe | 956 | static void cvmx_usb_reset_port(struct octeon_hcd *usb) |
6570b4a9 | 957 | { |
68d435dd AK |
958 | usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb, |
959 | CVMX_USBCX_HPRT(usb->index)); | |
6570b4a9 | 960 | |
6570b4a9 | 961 | /* Program the port reset bit to start the reset process */ |
6068e818 | 962 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt, |
b49f1133 | 963 | prtrst, 1); |
6570b4a9 AK |
964 | |
965 | /* | |
966 | * Wait at least 50ms (high speed), or 10ms (full speed) for the reset | |
967 | * process to complete. | |
968 | */ | |
969 | mdelay(50); | |
970 | ||
971 | /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */ | |
6068e818 | 972 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt, |
1da69aa9 | 973 | prtrst, 0); |
6570b4a9 | 974 | |
6570b4a9 AK |
975 | /* |
976 | * Read the port speed field to get the enumerated speed, | |
977 | * USBC_HPRT[PRTSPD]. | |
978 | */ | |
68d435dd AK |
979 | usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb, |
980 | CVMX_USBCX_HPRT(usb->index)); | |
6570b4a9 AK |
981 | } |
982 | ||
6570b4a9 AK |
983 | /** |
984 | * Disable a USB port. After this call the USB port will not | |
985 | * generate data transfers and will not generate events. | |
986 | * Transactions in process will fail and call their | |
987 | * associated callbacks. | |
988 | * | |
cb61c600 | 989 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
990 | * |
991 | * Returns: 0 or a negative error code. | |
992 | */ | |
8b07d2fe | 993 | static int cvmx_usb_disable(struct octeon_hcd *usb) |
6570b4a9 | 994 | { |
6570b4a9 | 995 | /* Disable the port */ |
6068e818 | 996 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt, |
1da69aa9 | 997 | prtena, 1); |
6570b4a9 AK |
998 | return 0; |
999 | } | |
1000 | ||
6570b4a9 AK |
1001 | /** |
1002 | * Get the current state of the USB port. Use this call to | |
1003 | * determine if the usb port has anything connected, is enabled, | |
1004 | * or has some sort of error condition. The return value of this | |
1005 | * call has "changed" bits to signal of the value of some fields | |
29a202fa | 1006 | * have changed between calls. |
6570b4a9 | 1007 | * |
cb61c600 | 1008 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1009 | * |
1010 | * Returns: Port status information | |
1011 | */ | |
8b07d2fe | 1012 | static struct cvmx_usb_port_status cvmx_usb_get_status(struct octeon_hcd *usb) |
6570b4a9 AK |
1013 | { |
1014 | union cvmx_usbcx_hprt usbc_hprt; | |
1015 | struct cvmx_usb_port_status result; | |
6570b4a9 AK |
1016 | |
1017 | memset(&result, 0, sizeof(result)); | |
1018 | ||
68d435dd | 1019 | usbc_hprt.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index)); |
6570b4a9 AK |
1020 | result.port_enabled = usbc_hprt.s.prtena; |
1021 | result.port_over_current = usbc_hprt.s.prtovrcurract; | |
1022 | result.port_powered = usbc_hprt.s.prtpwr; | |
1023 | result.port_speed = usbc_hprt.s.prtspd; | |
1024 | result.connected = usbc_hprt.s.prtconnsts; | |
1da69aa9 | 1025 | result.connect_change = |
1d5047c9 | 1026 | result.connected != usb->port_status.connected; |
6570b4a9 AK |
1027 | |
1028 | return result; | |
1029 | } | |
1030 | ||
6570b4a9 AK |
1031 | /** |
1032 | * Open a virtual pipe between the host and a USB device. A pipe | |
1033 | * must be opened before data can be transferred between a device | |
1034 | * and Octeon. | |
1035 | * | |
cb61c600 | 1036 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1037 | * @device_addr: |
1038 | * USB device address to open the pipe to | |
1039 | * (0-127). | |
1040 | * @endpoint_num: | |
1041 | * USB endpoint number to open the pipe to | |
1042 | * (0-15). | |
1043 | * @device_speed: | |
1044 | * The speed of the device the pipe is going | |
1045 | * to. This must match the device's speed, | |
1046 | * which may be different than the port speed. | |
1047 | * @max_packet: The maximum packet length the device can | |
1048 | * transmit/receive (low speed=0-8, full | |
1049 | * speed=0-1023, high speed=0-1024). This value | |
1050 | * comes from the standard endpoint descriptor | |
1051 | * field wMaxPacketSize bits <10:0>. | |
1052 | * @transfer_type: | |
1053 | * The type of transfer this pipe is for. | |
1054 | * @transfer_dir: | |
1055 | * The direction the pipe is in. This is not | |
1056 | * used for control pipes. | |
1057 | * @interval: For ISOCHRONOUS and INTERRUPT transfers, | |
1058 | * this is how often the transfer is scheduled | |
1059 | * for. All other transfers should specify | |
1060 | * zero. The units are in frames (8000/sec at | |
1061 | * high speed, 1000/sec for full speed). | |
1062 | * @multi_count: | |
1063 | * For high speed devices, this is the maximum | |
1064 | * allowed number of packet per microframe. | |
1065 | * Specify zero for non high speed devices. This | |
1066 | * value comes from the standard endpoint descriptor | |
1067 | * field wMaxPacketSize bits <12:11>. | |
1068 | * @hub_device_addr: | |
1069 | * Hub device address this device is connected | |
1070 | * to. Devices connected directly to Octeon | |
1071 | * use zero. This is only used when the device | |
1072 | * is full/low speed behind a high speed hub. | |
1073 | * The address will be of the high speed hub, | |
1074 | * not and full speed hubs after it. | |
1075 | * @hub_port: Which port on the hub the device is | |
1076 | * connected. Use zero for devices connected | |
1077 | * directly to Octeon. Like hub_device_addr, | |
1078 | * this is only used for full/low speed | |
1079 | * devices behind a high speed hub. | |
1080 | * | |
60f81507 | 1081 | * Returns: A non-NULL value is a pipe. NULL means an error. |
6570b4a9 | 1082 | */ |
8b07d2fe | 1083 | static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct octeon_hcd *usb, |
f5106435 PD |
1084 | int device_addr, |
1085 | int endpoint_num, | |
60f81507 AK |
1086 | enum cvmx_usb_speed |
1087 | device_speed, | |
1088 | int max_packet, | |
1089 | enum cvmx_usb_transfer | |
1090 | transfer_type, | |
1091 | enum cvmx_usb_direction | |
1092 | transfer_dir, | |
1093 | int interval, int multi_count, | |
1094 | int hub_device_addr, | |
1095 | int hub_port) | |
6570b4a9 AK |
1096 | { |
1097 | struct cvmx_usb_pipe *pipe; | |
6570b4a9 | 1098 | |
d2695a8a | 1099 | pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC); |
6570b4a9 | 1100 | if (!pipe) |
60f81507 | 1101 | return NULL; |
6570b4a9 | 1102 | if ((device_speed == CVMX_USB_SPEED_HIGH) && |
68ea3380 AK |
1103 | (transfer_dir == CVMX_USB_DIRECTION_OUT) && |
1104 | (transfer_type == CVMX_USB_TRANSFER_BULK)) | |
3f9697b7 | 1105 | pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; |
6570b4a9 AK |
1106 | pipe->device_addr = device_addr; |
1107 | pipe->endpoint_num = endpoint_num; | |
1108 | pipe->device_speed = device_speed; | |
1109 | pipe->max_packet = max_packet; | |
1110 | pipe->transfer_type = transfer_type; | |
1111 | pipe->transfer_dir = transfer_dir; | |
5669601d AK |
1112 | INIT_LIST_HEAD(&pipe->transactions); |
1113 | ||
6570b4a9 AK |
1114 | /* |
1115 | * All pipes use interval to rate limit NAK processing. Force an | |
1116 | * interval if one wasn't supplied | |
1117 | */ | |
1118 | if (!interval) | |
1119 | interval = 1; | |
68d435dd | 1120 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
3c98ef90 | 1121 | pipe->interval = interval * 8; |
6570b4a9 | 1122 | /* Force start splits to be schedule on uFrame 0 */ |
3c98ef90 | 1123 | pipe->next_tx_frame = ((usb->frame_number + 7) & ~7) + |
e725cef3 | 1124 | pipe->interval; |
6570b4a9 AK |
1125 | } else { |
1126 | pipe->interval = interval; | |
1127 | pipe->next_tx_frame = usb->frame_number + pipe->interval; | |
1128 | } | |
1129 | pipe->multi_count = multi_count; | |
1130 | pipe->hub_device_addr = hub_device_addr; | |
1131 | pipe->hub_port = hub_port; | |
1132 | pipe->pid_toggle = 0; | |
1133 | pipe->split_sc_frame = -1; | |
4a23ee1b | 1134 | list_add_tail(&pipe->node, &usb->idle_pipes); |
6570b4a9 AK |
1135 | |
1136 | /* | |
1137 | * We don't need to tell the hardware about this pipe yet since | |
1138 | * it doesn't have any submitted requests | |
1139 | */ | |
1140 | ||
60f81507 | 1141 | return pipe; |
6570b4a9 AK |
1142 | } |
1143 | ||
6570b4a9 AK |
1144 | /** |
1145 | * Poll the RX FIFOs and remove data as needed. This function is only used | |
1146 | * in non DMA mode. It is very important that this function be called quickly | |
1147 | * enough to prevent FIFO overflow. | |
1148 | * | |
cb61c600 | 1149 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 | 1150 | */ |
8b07d2fe | 1151 | static void cvmx_usb_poll_rx_fifo(struct octeon_hcd *usb) |
6570b4a9 AK |
1152 | { |
1153 | union cvmx_usbcx_grxstsph rx_status; | |
1154 | int channel; | |
1155 | int bytes; | |
cce66005 AK |
1156 | u64 address; |
1157 | u32 *ptr; | |
6570b4a9 | 1158 | |
68d435dd AK |
1159 | rx_status.u32 = cvmx_usb_read_csr32(usb, |
1160 | CVMX_USBCX_GRXSTSPH(usb->index)); | |
6570b4a9 AK |
1161 | /* Only read data if IN data is there */ |
1162 | if (rx_status.s.pktsts != 2) | |
1163 | return; | |
1164 | /* Check if no data is available */ | |
1165 | if (!rx_status.s.bcnt) | |
1166 | return; | |
1167 | ||
1168 | channel = rx_status.s.chnum; | |
1169 | bytes = rx_status.s.bcnt; | |
1170 | if (!bytes) | |
1171 | return; | |
1172 | ||
1173 | /* Get where the DMA engine would have written this data */ | |
c4bdbdd9 AK |
1174 | address = cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + |
1175 | channel * 8); | |
e725cef3 | 1176 | |
6570b4a9 | 1177 | ptr = cvmx_phys_to_ptr(address); |
c4bdbdd9 AK |
1178 | cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel * 8, |
1179 | address + bytes); | |
6570b4a9 AK |
1180 | |
1181 | /* Loop writing the FIFO data for this packet into memory */ | |
1182 | while (bytes > 0) { | |
68d435dd AK |
1183 | *ptr++ = cvmx_usb_read_csr32(usb, |
1184 | USB_FIFO_ADDRESS(channel, usb->index)); | |
6570b4a9 AK |
1185 | bytes -= 4; |
1186 | } | |
1187 | CVMX_SYNCW; | |
6570b4a9 AK |
1188 | } |
1189 | ||
6570b4a9 AK |
1190 | /** |
1191 | * Fill the TX hardware fifo with data out of the software | |
1192 | * fifos | |
1193 | * | |
cb61c600 | 1194 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1195 | * @fifo: Software fifo to use |
1196 | * @available: Amount of space in the hardware fifo | |
1197 | * | |
1198 | * Returns: Non zero if the hardware fifo was too small and needs | |
1199 | * to be serviced again. | |
1200 | */ | |
8b07d2fe | 1201 | static int cvmx_usb_fill_tx_hw(struct octeon_hcd *usb, |
68d435dd | 1202 | struct cvmx_usb_tx_fifo *fifo, int available) |
6570b4a9 AK |
1203 | { |
1204 | /* | |
1205 | * We're done either when there isn't anymore space or the software FIFO | |
1206 | * is empty | |
1207 | */ | |
1208 | while (available && (fifo->head != fifo->tail)) { | |
1209 | int i = fifo->tail; | |
cce66005 AK |
1210 | const u32 *ptr = cvmx_phys_to_ptr(fifo->entry[i].address); |
1211 | u64 csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, | |
1212 | usb->index) ^ 4; | |
6570b4a9 AK |
1213 | int words = available; |
1214 | ||
69e98df7 | 1215 | /* Limit the amount of data to what the SW fifo has */ |
6570b4a9 AK |
1216 | if (fifo->entry[i].size <= available) { |
1217 | words = fifo->entry[i].size; | |
1218 | fifo->tail++; | |
1219 | if (fifo->tail > MAX_CHANNELS) | |
1220 | fifo->tail = 0; | |
1221 | } | |
1222 | ||
1223 | /* Update the next locations and counts */ | |
1224 | available -= words; | |
1225 | fifo->entry[i].address += words * 4; | |
1226 | fifo->entry[i].size -= words; | |
1227 | ||
1228 | /* | |
1229 | * Write the HW fifo data. The read every three writes is due | |
1230 | * to an errata on CN3XXX chips | |
1231 | */ | |
1232 | while (words > 3) { | |
1233 | cvmx_write64_uint32(csr_address, *ptr++); | |
1234 | cvmx_write64_uint32(csr_address, *ptr++); | |
1235 | cvmx_write64_uint32(csr_address, *ptr++); | |
1da69aa9 RO |
1236 | cvmx_read64_uint64( |
1237 | CVMX_USBNX_DMA0_INB_CHN0(usb->index)); | |
6570b4a9 AK |
1238 | words -= 3; |
1239 | } | |
1240 | cvmx_write64_uint32(csr_address, *ptr++); | |
1241 | if (--words) { | |
1242 | cvmx_write64_uint32(csr_address, *ptr++); | |
1243 | if (--words) | |
1244 | cvmx_write64_uint32(csr_address, *ptr++); | |
1245 | } | |
1246 | cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index)); | |
1247 | } | |
1248 | return fifo->head != fifo->tail; | |
1249 | } | |
1250 | ||
6570b4a9 AK |
1251 | /** |
1252 | * Check the hardware FIFOs and fill them as needed | |
1253 | * | |
cb61c600 | 1254 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 | 1255 | */ |
8b07d2fe | 1256 | static void cvmx_usb_poll_tx_fifo(struct octeon_hcd *usb) |
6570b4a9 AK |
1257 | { |
1258 | if (usb->periodic.head != usb->periodic.tail) { | |
1259 | union cvmx_usbcx_hptxsts tx_status; | |
f5106435 | 1260 | |
68d435dd AK |
1261 | tx_status.u32 = cvmx_usb_read_csr32(usb, |
1262 | CVMX_USBCX_HPTXSTS(usb->index)); | |
1263 | if (cvmx_usb_fill_tx_hw(usb, &usb->periodic, | |
1264 | tx_status.s.ptxfspcavail)) | |
1da69aa9 | 1265 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
6068e818 | 1266 | cvmx_usbcx_gintmsk, ptxfempmsk, 1); |
6570b4a9 | 1267 | else |
1da69aa9 | 1268 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
6068e818 | 1269 | cvmx_usbcx_gintmsk, ptxfempmsk, 0); |
6570b4a9 AK |
1270 | } |
1271 | ||
1272 | if (usb->nonperiodic.head != usb->nonperiodic.tail) { | |
1273 | union cvmx_usbcx_gnptxsts tx_status; | |
f5106435 | 1274 | |
68d435dd AK |
1275 | tx_status.u32 = cvmx_usb_read_csr32(usb, |
1276 | CVMX_USBCX_GNPTXSTS(usb->index)); | |
1277 | if (cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, | |
1278 | tx_status.s.nptxfspcavail)) | |
1da69aa9 | 1279 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
6068e818 | 1280 | cvmx_usbcx_gintmsk, nptxfempmsk, 1); |
6570b4a9 | 1281 | else |
1da69aa9 | 1282 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
6068e818 | 1283 | cvmx_usbcx_gintmsk, nptxfempmsk, 0); |
6570b4a9 | 1284 | } |
6570b4a9 AK |
1285 | } |
1286 | ||
6570b4a9 AK |
1287 | /** |
1288 | * Fill the TX FIFO with an outgoing packet | |
1289 | * | |
cb61c600 | 1290 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1291 | * @channel: Channel number to get packet from |
1292 | */ | |
8b07d2fe | 1293 | static void cvmx_usb_fill_tx_fifo(struct octeon_hcd *usb, int channel) |
6570b4a9 AK |
1294 | { |
1295 | union cvmx_usbcx_hccharx hcchar; | |
1296 | union cvmx_usbcx_hcspltx usbc_hcsplt; | |
1297 | union cvmx_usbcx_hctsizx usbc_hctsiz; | |
1298 | struct cvmx_usb_tx_fifo *fifo; | |
1299 | ||
1300 | /* We only need to fill data on outbound channels */ | |
68d435dd | 1301 | hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 1302 | CVMX_USBCX_HCCHARX(channel, usb->index)); |
6570b4a9 AK |
1303 | if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT) |
1304 | return; | |
1305 | ||
1306 | /* OUT Splits only have data on the start and not the complete */ | |
68d435dd AK |
1307 | usbc_hcsplt.u32 = cvmx_usb_read_csr32(usb, |
1308 | CVMX_USBCX_HCSPLTX(channel, usb->index)); | |
6570b4a9 AK |
1309 | if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt) |
1310 | return; | |
1311 | ||
1312 | /* | |
1313 | * Find out how many bytes we need to fill and convert it into 32bit | |
1314 | * words. | |
1315 | */ | |
68d435dd AK |
1316 | usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, |
1317 | CVMX_USBCX_HCTSIZX(channel, usb->index)); | |
6570b4a9 AK |
1318 | if (!usbc_hctsiz.s.xfersize) |
1319 | return; | |
1320 | ||
1321 | if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) || | |
68ea3380 | 1322 | (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS)) |
6570b4a9 AK |
1323 | fifo = &usb->periodic; |
1324 | else | |
1325 | fifo = &usb->nonperiodic; | |
1326 | ||
1327 | fifo->entry[fifo->head].channel = channel; | |
c4bdbdd9 AK |
1328 | fifo->entry[fifo->head].address = |
1329 | cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + | |
1330 | channel * 8); | |
3c98ef90 | 1331 | fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize + 3) >> 2; |
6570b4a9 AK |
1332 | fifo->head++; |
1333 | if (fifo->head > MAX_CHANNELS) | |
1334 | fifo->head = 0; | |
1335 | ||
68d435dd | 1336 | cvmx_usb_poll_tx_fifo(usb); |
6570b4a9 AK |
1337 | } |
1338 | ||
1339 | /** | |
1340 | * Perform channel specific setup for Control transactions. All | |
68d435dd | 1341 | * the generic stuff will already have been done in cvmx_usb_start_channel(). |
6570b4a9 | 1342 | * |
cb61c600 | 1343 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1344 | * @channel: Channel to setup |
1345 | * @pipe: Pipe for control transaction | |
1346 | */ | |
8b07d2fe | 1347 | static void cvmx_usb_start_channel_control(struct octeon_hcd *usb, |
68d435dd AK |
1348 | int channel, |
1349 | struct cvmx_usb_pipe *pipe) | |
6570b4a9 | 1350 | { |
8b07d2fe | 1351 | struct usb_hcd *hcd = octeon_to_hcd(usb); |
ba0b8e42 | 1352 | struct device *dev = hcd->self.controller; |
5669601d AK |
1353 | struct cvmx_usb_transaction *transaction = |
1354 | list_first_entry(&pipe->transactions, typeof(*transaction), | |
1355 | node); | |
e301dfb2 | 1356 | struct usb_ctrlrequest *header = |
6570b4a9 | 1357 | cvmx_phys_to_ptr(transaction->control_header); |
1da69aa9 RO |
1358 | int bytes_to_transfer = transaction->buffer_length - |
1359 | transaction->actual_bytes; | |
6570b4a9 AK |
1360 | int packets_to_transfer; |
1361 | union cvmx_usbcx_hctsizx usbc_hctsiz; | |
1362 | ||
68d435dd AK |
1363 | usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, |
1364 | CVMX_USBCX_HCTSIZX(channel, usb->index)); | |
6570b4a9 AK |
1365 | |
1366 | switch (transaction->stage) { | |
1367 | case CVMX_USB_STAGE_NON_CONTROL: | |
1368 | case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE: | |
ba0b8e42 | 1369 | dev_err(dev, "%s: ERROR - Non control stage\n", __func__); |
6570b4a9 AK |
1370 | break; |
1371 | case CVMX_USB_STAGE_SETUP: | |
1372 | usbc_hctsiz.s.pid = 3; /* Setup */ | |
1373 | bytes_to_transfer = sizeof(*header); | |
1374 | /* All Control operations start with a setup going OUT */ | |
e725cef3 | 1375 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
6068e818 | 1376 | cvmx_usbcx_hccharx, epdir, |
e725cef3 | 1377 | CVMX_USB_DIRECTION_OUT); |
6570b4a9 AK |
1378 | /* |
1379 | * Setup send the control header instead of the buffer data. The | |
1380 | * buffer data will be used in the next stage | |
1381 | */ | |
c4bdbdd9 AK |
1382 | cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + |
1383 | channel * 8, | |
1384 | transaction->control_header); | |
6570b4a9 AK |
1385 | break; |
1386 | case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE: | |
1387 | usbc_hctsiz.s.pid = 3; /* Setup */ | |
1388 | bytes_to_transfer = 0; | |
1389 | /* All Control operations start with a setup going OUT */ | |
e725cef3 | 1390 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
6068e818 | 1391 | cvmx_usbcx_hccharx, epdir, |
e725cef3 PD |
1392 | CVMX_USB_DIRECTION_OUT); |
1393 | ||
1394 | USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), | |
6068e818 | 1395 | cvmx_usbcx_hcspltx, compsplt, 1); |
6570b4a9 AK |
1396 | break; |
1397 | case CVMX_USB_STAGE_DATA: | |
68d435dd AK |
1398 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
1399 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { | |
96ee2cc8 | 1400 | if (header->bRequestType & USB_DIR_IN) |
6570b4a9 AK |
1401 | bytes_to_transfer = 0; |
1402 | else if (bytes_to_transfer > pipe->max_packet) | |
1403 | bytes_to_transfer = pipe->max_packet; | |
1404 | } | |
1405 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), | |
6068e818 | 1406 | cvmx_usbcx_hccharx, epdir, |
96ee2cc8 | 1407 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1408 | CVMX_USB_DIRECTION_IN : |
1409 | CVMX_USB_DIRECTION_OUT)); | |
1410 | break; | |
1411 | case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE: | |
68d435dd | 1412 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
96ee2cc8 | 1413 | if (!(header->bRequestType & USB_DIR_IN)) |
6570b4a9 AK |
1414 | bytes_to_transfer = 0; |
1415 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), | |
6068e818 | 1416 | cvmx_usbcx_hccharx, epdir, |
96ee2cc8 | 1417 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1418 | CVMX_USB_DIRECTION_IN : |
1419 | CVMX_USB_DIRECTION_OUT)); | |
1da69aa9 | 1420 | USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), |
6068e818 | 1421 | cvmx_usbcx_hcspltx, compsplt, 1); |
6570b4a9 AK |
1422 | break; |
1423 | case CVMX_USB_STAGE_STATUS: | |
68d435dd | 1424 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
6570b4a9 | 1425 | bytes_to_transfer = 0; |
1da69aa9 | 1426 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
6068e818 | 1427 | cvmx_usbcx_hccharx, epdir, |
96ee2cc8 | 1428 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1429 | CVMX_USB_DIRECTION_OUT : |
1430 | CVMX_USB_DIRECTION_IN)); | |
1431 | break; | |
1432 | case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE: | |
68d435dd | 1433 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
6570b4a9 | 1434 | bytes_to_transfer = 0; |
1da69aa9 | 1435 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
6068e818 | 1436 | cvmx_usbcx_hccharx, epdir, |
96ee2cc8 | 1437 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1438 | CVMX_USB_DIRECTION_OUT : |
1439 | CVMX_USB_DIRECTION_IN)); | |
1da69aa9 | 1440 | USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), |
6068e818 | 1441 | cvmx_usbcx_hcspltx, compsplt, 1); |
6570b4a9 AK |
1442 | break; |
1443 | } | |
1444 | ||
1445 | /* | |
1446 | * Make sure the transfer never exceeds the byte limit of the hardware. | |
1447 | * Further bytes will be sent as continued transactions | |
1448 | */ | |
1449 | if (bytes_to_transfer > MAX_TRANSFER_BYTES) { | |
1450 | /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */ | |
1451 | bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet; | |
1452 | bytes_to_transfer *= pipe->max_packet; | |
1453 | } | |
1454 | ||
1455 | /* | |
1456 | * Calculate the number of packets to transfer. If the length is zero | |
1457 | * we still need to transfer one packet | |
1458 | */ | |
dea7503a TP |
1459 | packets_to_transfer = DIV_ROUND_UP(bytes_to_transfer, |
1460 | pipe->max_packet); | |
6de14f12 | 1461 | if (packets_to_transfer == 0) { |
6570b4a9 | 1462 | packets_to_transfer = 1; |
6de14f12 | 1463 | } else if ((packets_to_transfer > 1) && |
1da69aa9 | 1464 | (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { |
6570b4a9 AK |
1465 | /* |
1466 | * Limit to one packet when not using DMA. Channels must be | |
1467 | * restarted between every packet for IN transactions, so there | |
1468 | * is no reason to do multiple packets in a row | |
1469 | */ | |
1470 | packets_to_transfer = 1; | |
1471 | bytes_to_transfer = packets_to_transfer * pipe->max_packet; | |
1472 | } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) { | |
1473 | /* | |
1474 | * Limit the number of packet and data transferred to what the | |
1475 | * hardware can handle | |
1476 | */ | |
1477 | packets_to_transfer = MAX_TRANSFER_PACKETS; | |
1478 | bytes_to_transfer = packets_to_transfer * pipe->max_packet; | |
1479 | } | |
1480 | ||
1481 | usbc_hctsiz.s.xfersize = bytes_to_transfer; | |
1482 | usbc_hctsiz.s.pktcnt = packets_to_transfer; | |
1483 | ||
68d435dd AK |
1484 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), |
1485 | usbc_hctsiz.u32); | |
6570b4a9 AK |
1486 | } |
1487 | ||
6570b4a9 AK |
1488 | /** |
1489 | * Start a channel to perform the pipe's head transaction | |
1490 | * | |
cb61c600 | 1491 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1492 | * @channel: Channel to setup |
1493 | * @pipe: Pipe to start | |
1494 | */ | |
8b07d2fe | 1495 | static void cvmx_usb_start_channel(struct octeon_hcd *usb, int channel, |
68d435dd | 1496 | struct cvmx_usb_pipe *pipe) |
6570b4a9 | 1497 | { |
5669601d AK |
1498 | struct cvmx_usb_transaction *transaction = |
1499 | list_first_entry(&pipe->transactions, typeof(*transaction), | |
1500 | node); | |
6570b4a9 AK |
1501 | |
1502 | /* Make sure all writes to the DMA region get flushed */ | |
1503 | CVMX_SYNCW; | |
1504 | ||
1505 | /* Attach the channel to the pipe */ | |
1506 | usb->pipe_for_channel[channel] = pipe; | |
1507 | pipe->channel = channel; | |
3f9697b7 | 1508 | pipe->flags |= CVMX_USB_PIPE_FLAGS_SCHEDULED; |
6570b4a9 AK |
1509 | |
1510 | /* Mark this channel as in use */ | |
3c98ef90 | 1511 | usb->idle_hardware_channels &= ~(1 << channel); |
6570b4a9 AK |
1512 | |
1513 | /* Enable the channel interrupt bits */ | |
1514 | { | |
1515 | union cvmx_usbcx_hcintx usbc_hcint; | |
1516 | union cvmx_usbcx_hcintmskx usbc_hcintmsk; | |
1517 | union cvmx_usbcx_haintmsk usbc_haintmsk; | |
1518 | ||
1519 | /* Clear all channel status bits */ | |
68d435dd AK |
1520 | usbc_hcint.u32 = cvmx_usb_read_csr32(usb, |
1521 | CVMX_USBCX_HCINTX(channel, usb->index)); | |
e725cef3 | 1522 | |
68d435dd AK |
1523 | cvmx_usb_write_csr32(usb, |
1524 | CVMX_USBCX_HCINTX(channel, usb->index), | |
1525 | usbc_hcint.u32); | |
6570b4a9 AK |
1526 | |
1527 | usbc_hcintmsk.u32 = 0; | |
1528 | usbc_hcintmsk.s.chhltdmsk = 1; | |
1529 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { | |
1530 | /* | |
1531 | * Channels need these extra interrupts when we aren't | |
1532 | * in DMA mode. | |
1533 | */ | |
1534 | usbc_hcintmsk.s.datatglerrmsk = 1; | |
1535 | usbc_hcintmsk.s.frmovrunmsk = 1; | |
1536 | usbc_hcintmsk.s.bblerrmsk = 1; | |
1537 | usbc_hcintmsk.s.xacterrmsk = 1; | |
68d435dd | 1538 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
1539 | /* |
1540 | * Splits don't generate xfercompl, so we need | |
1541 | * ACK and NYET. | |
1542 | */ | |
1543 | usbc_hcintmsk.s.nyetmsk = 1; | |
1544 | usbc_hcintmsk.s.ackmsk = 1; | |
1545 | } | |
1546 | usbc_hcintmsk.s.nakmsk = 1; | |
1547 | usbc_hcintmsk.s.stallmsk = 1; | |
1548 | usbc_hcintmsk.s.xfercomplmsk = 1; | |
1549 | } | |
68d435dd | 1550 | cvmx_usb_write_csr32(usb, |
68ea3380 AK |
1551 | CVMX_USBCX_HCINTMSKX(channel, usb->index), |
1552 | usbc_hcintmsk.u32); | |
6570b4a9 AK |
1553 | |
1554 | /* Enable the channel interrupt to propagate */ | |
68d435dd | 1555 | usbc_haintmsk.u32 = cvmx_usb_read_csr32(usb, |
e725cef3 | 1556 | CVMX_USBCX_HAINTMSK(usb->index)); |
3c98ef90 | 1557 | usbc_haintmsk.s.haintmsk |= 1 << channel; |
68d435dd AK |
1558 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), |
1559 | usbc_haintmsk.u32); | |
6570b4a9 AK |
1560 | } |
1561 | ||
d712648a | 1562 | /* Setup the location the DMA engine uses. */ |
6570b4a9 | 1563 | { |
cce66005 AK |
1564 | u64 reg; |
1565 | u64 dma_address = transaction->buffer + | |
1566 | transaction->actual_bytes; | |
f5106435 | 1567 | |
6570b4a9 | 1568 | if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) |
e725cef3 PD |
1569 | dma_address = transaction->buffer + |
1570 | transaction->iso_packets[0].offset + | |
1571 | transaction->actual_bytes; | |
1572 | ||
d712648a AK |
1573 | if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) |
1574 | reg = CVMX_USBNX_DMA0_OUTB_CHN0(usb->index); | |
1575 | else | |
1576 | reg = CVMX_USBNX_DMA0_INB_CHN0(usb->index); | |
1577 | cvmx_write64_uint64(reg + channel * 8, dma_address); | |
6570b4a9 AK |
1578 | } |
1579 | ||
1580 | /* Setup both the size of the transfer and the SPLIT characteristics */ | |
1581 | { | |
1582 | union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0}; | |
1583 | union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0}; | |
1584 | int packets_to_transfer; | |
1da69aa9 RO |
1585 | int bytes_to_transfer = transaction->buffer_length - |
1586 | transaction->actual_bytes; | |
6570b4a9 AK |
1587 | |
1588 | /* | |
1589 | * ISOCHRONOUS transactions store each individual transfer size | |
1590 | * in the packet structure, not the global buffer_length | |
1591 | */ | |
1592 | if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) | |
1da69aa9 RO |
1593 | bytes_to_transfer = |
1594 | transaction->iso_packets[0].length - | |
1595 | transaction->actual_bytes; | |
6570b4a9 AK |
1596 | |
1597 | /* | |
1598 | * We need to do split transactions when we are talking to non | |
1599 | * high speed devices that are behind a high speed hub | |
1600 | */ | |
68d435dd | 1601 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
1602 | /* |
1603 | * On the start split phase (stage is even) record the | |
1604 | * frame number we will need to send the split complete. | |
1605 | * We only store the lower two bits since the time ahead | |
1606 | * can only be two frames | |
1607 | */ | |
3c98ef90 | 1608 | if ((transaction->stage & 1) == 0) { |
6570b4a9 | 1609 | if (transaction->type == CVMX_USB_TRANSFER_BULK) |
1da69aa9 RO |
1610 | pipe->split_sc_frame = |
1611 | (usb->frame_number + 1) & 0x7f; | |
6570b4a9 | 1612 | else |
1da69aa9 RO |
1613 | pipe->split_sc_frame = |
1614 | (usb->frame_number + 2) & 0x7f; | |
6de14f12 | 1615 | } else { |
6570b4a9 | 1616 | pipe->split_sc_frame = -1; |
6de14f12 | 1617 | } |
6570b4a9 AK |
1618 | |
1619 | usbc_hcsplt.s.spltena = 1; | |
1620 | usbc_hcsplt.s.hubaddr = pipe->hub_device_addr; | |
1621 | usbc_hcsplt.s.prtaddr = pipe->hub_port; | |
1da69aa9 RO |
1622 | usbc_hcsplt.s.compsplt = (transaction->stage == |
1623 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE); | |
6570b4a9 AK |
1624 | |
1625 | /* | |
1626 | * SPLIT transactions can only ever transmit one data | |
1627 | * packet so limit the transfer size to the max packet | |
1628 | * size | |
1629 | */ | |
1630 | if (bytes_to_transfer > pipe->max_packet) | |
1631 | bytes_to_transfer = pipe->max_packet; | |
1632 | ||
1633 | /* | |
1634 | * ISOCHRONOUS OUT splits are unique in that they limit | |
1635 | * data transfers to 188 byte chunks representing the | |
1636 | * begin/middle/end of the data or all | |
1637 | */ | |
1638 | if (!usbc_hcsplt.s.compsplt && | |
68ea3380 AK |
1639 | (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) && |
1640 | (pipe->transfer_type == | |
1641 | CVMX_USB_TRANSFER_ISOCHRONOUS)) { | |
6570b4a9 AK |
1642 | /* |
1643 | * Clear the split complete frame number as | |
1644 | * there isn't going to be a split complete | |
1645 | */ | |
1646 | pipe->split_sc_frame = -1; | |
1647 | /* | |
1648 | * See if we've started this transfer and sent | |
1649 | * data | |
1650 | */ | |
1651 | if (transaction->actual_bytes == 0) { | |
1652 | /* | |
1653 | * Nothing sent yet, this is either a | |
1654 | * begin or the entire payload | |
1655 | */ | |
1656 | if (bytes_to_transfer <= 188) | |
1657 | /* Entire payload in one go */ | |
1658 | usbc_hcsplt.s.xactpos = 3; | |
1659 | else | |
1660 | /* First part of payload */ | |
1661 | usbc_hcsplt.s.xactpos = 2; | |
1662 | } else { | |
1663 | /* | |
1664 | * Continuing the previous data, we must | |
1665 | * either be in the middle or at the end | |
1666 | */ | |
1667 | if (bytes_to_transfer <= 188) | |
1668 | /* End of payload */ | |
1669 | usbc_hcsplt.s.xactpos = 1; | |
1670 | else | |
1671 | /* Middle of payload */ | |
1672 | usbc_hcsplt.s.xactpos = 0; | |
1673 | } | |
1674 | /* | |
1675 | * Again, the transfer size is limited to 188 | |
1676 | * bytes | |
1677 | */ | |
1678 | if (bytes_to_transfer > 188) | |
1679 | bytes_to_transfer = 188; | |
1680 | } | |
1681 | } | |
1682 | ||
1683 | /* | |
1684 | * Make sure the transfer never exceeds the byte limit of the | |
1685 | * hardware. Further bytes will be sent as continued | |
1686 | * transactions | |
1687 | */ | |
1688 | if (bytes_to_transfer > MAX_TRANSFER_BYTES) { | |
1689 | /* | |
1690 | * Round MAX_TRANSFER_BYTES to a multiple of out packet | |
1691 | * size | |
1692 | */ | |
1da69aa9 RO |
1693 | bytes_to_transfer = MAX_TRANSFER_BYTES / |
1694 | pipe->max_packet; | |
6570b4a9 AK |
1695 | bytes_to_transfer *= pipe->max_packet; |
1696 | } | |
1697 | ||
1698 | /* | |
1699 | * Calculate the number of packets to transfer. If the length is | |
1700 | * zero we still need to transfer one packet | |
1701 | */ | |
1da69aa9 | 1702 | packets_to_transfer = |
dea7503a | 1703 | DIV_ROUND_UP(bytes_to_transfer, pipe->max_packet); |
6de14f12 | 1704 | if (packets_to_transfer == 0) { |
6570b4a9 | 1705 | packets_to_transfer = 1; |
6de14f12 | 1706 | } else if ((packets_to_transfer > 1) && |
68ea3380 AK |
1707 | (usb->init_flags & |
1708 | CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { | |
6570b4a9 AK |
1709 | /* |
1710 | * Limit to one packet when not using DMA. Channels must | |
1711 | * be restarted between every packet for IN | |
1712 | * transactions, so there is no reason to do multiple | |
1713 | * packets in a row | |
1714 | */ | |
1715 | packets_to_transfer = 1; | |
1da69aa9 RO |
1716 | bytes_to_transfer = packets_to_transfer * |
1717 | pipe->max_packet; | |
6570b4a9 AK |
1718 | } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) { |
1719 | /* | |
1720 | * Limit the number of packet and data transferred to | |
1721 | * what the hardware can handle | |
1722 | */ | |
1723 | packets_to_transfer = MAX_TRANSFER_PACKETS; | |
1da69aa9 RO |
1724 | bytes_to_transfer = packets_to_transfer * |
1725 | pipe->max_packet; | |
6570b4a9 AK |
1726 | } |
1727 | ||
1728 | usbc_hctsiz.s.xfersize = bytes_to_transfer; | |
1729 | usbc_hctsiz.s.pktcnt = packets_to_transfer; | |
1730 | ||
1731 | /* Update the DATA0/DATA1 toggle */ | |
68d435dd | 1732 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
6570b4a9 AK |
1733 | /* |
1734 | * High speed pipes may need a hardware ping before they start | |
1735 | */ | |
3f9697b7 | 1736 | if (pipe->flags & CVMX_USB_PIPE_FLAGS_NEED_PING) |
6570b4a9 AK |
1737 | usbc_hctsiz.s.dopng = 1; |
1738 | ||
68d435dd AK |
1739 | cvmx_usb_write_csr32(usb, |
1740 | CVMX_USBCX_HCSPLTX(channel, usb->index), | |
1741 | usbc_hcsplt.u32); | |
1742 | cvmx_usb_write_csr32(usb, | |
1743 | CVMX_USBCX_HCTSIZX(channel, usb->index), | |
1744 | usbc_hctsiz.u32); | |
6570b4a9 AK |
1745 | } |
1746 | ||
1747 | /* Setup the Host Channel Characteristics Register */ | |
1748 | { | |
1749 | union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0}; | |
1750 | ||
1751 | /* | |
1752 | * Set the startframe odd/even properly. This is only used for | |
1753 | * periodic | |
1754 | */ | |
3c98ef90 | 1755 | usbc_hcchar.s.oddfrm = usb->frame_number & 1; |
6570b4a9 AK |
1756 | |
1757 | /* | |
1758 | * Set the number of back to back packets allowed by this | |
1759 | * endpoint. Split transactions interpret "ec" as the number of | |
1760 | * immediate retries of failure. These retries happen too | |
1761 | * quickly, so we disable these entirely for splits | |
1762 | */ | |
68d435dd | 1763 | if (cvmx_usb_pipe_needs_split(usb, pipe)) |
6570b4a9 AK |
1764 | usbc_hcchar.s.ec = 1; |
1765 | else if (pipe->multi_count < 1) | |
1766 | usbc_hcchar.s.ec = 1; | |
1767 | else if (pipe->multi_count > 3) | |
1768 | usbc_hcchar.s.ec = 3; | |
1769 | else | |
1770 | usbc_hcchar.s.ec = pipe->multi_count; | |
1771 | ||
1772 | /* Set the rest of the endpoint specific settings */ | |
1773 | usbc_hcchar.s.devaddr = pipe->device_addr; | |
1774 | usbc_hcchar.s.eptype = transaction->type; | |
1da69aa9 RO |
1775 | usbc_hcchar.s.lspddev = |
1776 | (pipe->device_speed == CVMX_USB_SPEED_LOW); | |
6570b4a9 AK |
1777 | usbc_hcchar.s.epdir = pipe->transfer_dir; |
1778 | usbc_hcchar.s.epnum = pipe->endpoint_num; | |
1779 | usbc_hcchar.s.mps = pipe->max_packet; | |
68d435dd AK |
1780 | cvmx_usb_write_csr32(usb, |
1781 | CVMX_USBCX_HCCHARX(channel, usb->index), | |
1782 | usbc_hcchar.u32); | |
6570b4a9 AK |
1783 | } |
1784 | ||
1785 | /* Do transaction type specific fixups as needed */ | |
1786 | switch (transaction->type) { | |
1787 | case CVMX_USB_TRANSFER_CONTROL: | |
68d435dd | 1788 | cvmx_usb_start_channel_control(usb, channel, pipe); |
6570b4a9 AK |
1789 | break; |
1790 | case CVMX_USB_TRANSFER_BULK: | |
1791 | case CVMX_USB_TRANSFER_INTERRUPT: | |
1792 | break; | |
1793 | case CVMX_USB_TRANSFER_ISOCHRONOUS: | |
68d435dd | 1794 | if (!cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
1795 | /* |
1796 | * ISO transactions require different PIDs depending on | |
1797 | * direction and how many packets are needed | |
1798 | */ | |
1799 | if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) { | |
1800 | if (pipe->multi_count < 2) /* Need DATA0 */ | |
1da69aa9 RO |
1801 | USB_SET_FIELD32( |
1802 | CVMX_USBCX_HCTSIZX(channel, | |
1803 | usb->index), | |
6068e818 | 1804 | cvmx_usbcx_hctsizx, pid, 0); |
6570b4a9 | 1805 | else /* Need MDATA */ |
1da69aa9 RO |
1806 | USB_SET_FIELD32( |
1807 | CVMX_USBCX_HCTSIZX(channel, | |
1808 | usb->index), | |
6068e818 | 1809 | cvmx_usbcx_hctsizx, pid, 3); |
6570b4a9 AK |
1810 | } |
1811 | } | |
1812 | break; | |
1813 | } | |
1814 | { | |
68ea3380 | 1815 | union cvmx_usbcx_hctsizx usbc_hctsiz = { .u32 = |
68d435dd | 1816 | cvmx_usb_read_csr32(usb, |
68ea3380 AK |
1817 | CVMX_USBCX_HCTSIZX(channel, |
1818 | usb->index)) | |
1819 | }; | |
6570b4a9 AK |
1820 | transaction->xfersize = usbc_hctsiz.s.xfersize; |
1821 | transaction->pktcnt = usbc_hctsiz.s.pktcnt; | |
1822 | } | |
69e98df7 | 1823 | /* Remember when we start a split transaction */ |
68d435dd | 1824 | if (cvmx_usb_pipe_needs_split(usb, pipe)) |
6570b4a9 | 1825 | usb->active_split = transaction; |
1da69aa9 | 1826 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
6068e818 | 1827 | cvmx_usbcx_hccharx, chena, 1); |
6570b4a9 | 1828 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) |
68d435dd | 1829 | cvmx_usb_fill_tx_fifo(usb, channel); |
6570b4a9 AK |
1830 | } |
1831 | ||
6570b4a9 AK |
1832 | /** |
1833 | * Find a pipe that is ready to be scheduled to hardware. | |
cb61c600 | 1834 | * @usb: USB device state populated by cvmx_usb_initialize(). |
25adcca6 | 1835 | * @xfer_type: Transfer type |
6570b4a9 AK |
1836 | * |
1837 | * Returns: Pipe or NULL if none are ready | |
1838 | */ | |
68d435dd | 1839 | static struct cvmx_usb_pipe *cvmx_usb_find_ready_pipe( |
8b07d2fe | 1840 | struct octeon_hcd *usb, |
25adcca6 | 1841 | enum cvmx_usb_transfer xfer_type) |
6570b4a9 | 1842 | { |
25adcca6 | 1843 | struct list_head *list = usb->active_pipes + xfer_type; |
38492ccb | 1844 | u64 current_frame = usb->frame_number; |
4a23ee1b AK |
1845 | struct cvmx_usb_pipe *pipe; |
1846 | ||
1847 | list_for_each_entry(pipe, list, node) { | |
5669601d | 1848 | struct cvmx_usb_transaction *t = |
1da69aa9 RO |
1849 | list_first_entry(&pipe->transactions, typeof(*t), |
1850 | node); | |
3f9697b7 | 1851 | if (!(pipe->flags & CVMX_USB_PIPE_FLAGS_SCHEDULED) && t && |
68ea3380 AK |
1852 | (pipe->next_tx_frame <= current_frame) && |
1853 | ((pipe->split_sc_frame == -1) || | |
1854 | ((((int)current_frame - pipe->split_sc_frame) & 0x7f) < | |
1855 | 0x40)) && | |
1856 | (!usb->active_split || (usb->active_split == t))) { | |
20f6b829 | 1857 | prefetch(t); |
6570b4a9 AK |
1858 | return pipe; |
1859 | } | |
6570b4a9 AK |
1860 | } |
1861 | return NULL; | |
1862 | } | |
1863 | ||
d0737498 AK |
1864 | static struct cvmx_usb_pipe *cvmx_usb_next_pipe(struct octeon_hcd *usb, |
1865 | int is_sof) | |
1866 | { | |
1867 | struct cvmx_usb_pipe *pipe; | |
1868 | ||
1869 | /* Find a pipe needing service. */ | |
1870 | if (is_sof) { | |
1871 | /* | |
1872 | * Only process periodic pipes on SOF interrupts. This way we | |
1873 | * are sure that the periodic data is sent in the beginning of | |
1874 | * the frame. | |
1875 | */ | |
1876 | pipe = cvmx_usb_find_ready_pipe(usb, | |
1877 | CVMX_USB_TRANSFER_ISOCHRONOUS); | |
1878 | if (pipe) | |
1879 | return pipe; | |
1880 | pipe = cvmx_usb_find_ready_pipe(usb, | |
1881 | CVMX_USB_TRANSFER_INTERRUPT); | |
1882 | if (pipe) | |
1883 | return pipe; | |
1884 | } | |
1885 | pipe = cvmx_usb_find_ready_pipe(usb, CVMX_USB_TRANSFER_CONTROL); | |
1886 | if (pipe) | |
1887 | return pipe; | |
1888 | return cvmx_usb_find_ready_pipe(usb, CVMX_USB_TRANSFER_BULK); | |
1889 | } | |
1890 | ||
6570b4a9 AK |
1891 | /** |
1892 | * Called whenever a pipe might need to be scheduled to the | |
1893 | * hardware. | |
1894 | * | |
cb61c600 | 1895 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1896 | * @is_sof: True if this schedule was called on a SOF interrupt. |
1897 | */ | |
8b07d2fe | 1898 | static void cvmx_usb_schedule(struct octeon_hcd *usb, int is_sof) |
6570b4a9 AK |
1899 | { |
1900 | int channel; | |
1901 | struct cvmx_usb_pipe *pipe; | |
1902 | int need_sof; | |
1903 | enum cvmx_usb_transfer ttype; | |
1904 | ||
1905 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { | |
1906 | /* | |
1907 | * Without DMA we need to be careful to not schedule something | |
1908 | * at the end of a frame and cause an overrun. | |
1909 | */ | |
e725cef3 | 1910 | union cvmx_usbcx_hfnum hfnum = { |
68d435dd | 1911 | .u32 = cvmx_usb_read_csr32(usb, |
e725cef3 PD |
1912 | CVMX_USBCX_HFNUM(usb->index)) |
1913 | }; | |
1914 | ||
1915 | union cvmx_usbcx_hfir hfir = { | |
68d435dd | 1916 | .u32 = cvmx_usb_read_csr32(usb, |
e725cef3 PD |
1917 | CVMX_USBCX_HFIR(usb->index)) |
1918 | }; | |
f5106435 | 1919 | |
3c98ef90 | 1920 | if (hfnum.s.frrem < hfir.s.frint / 4) |
6570b4a9 AK |
1921 | goto done; |
1922 | } | |
1923 | ||
1924 | while (usb->idle_hardware_channels) { | |
1925 | /* Find an idle channel */ | |
1926 | channel = __fls(usb->idle_hardware_channels); | |
1927 | if (unlikely(channel > 7)) | |
1928 | break; | |
1929 | ||
d0737498 | 1930 | pipe = cvmx_usb_next_pipe(usb, is_sof); |
6570b4a9 AK |
1931 | if (!pipe) |
1932 | break; | |
1933 | ||
68d435dd | 1934 | cvmx_usb_start_channel(usb, channel, pipe); |
6570b4a9 AK |
1935 | } |
1936 | ||
1937 | done: | |
1938 | /* | |
1939 | * Only enable SOF interrupts when we have transactions pending in the | |
1940 | * future that might need to be scheduled | |
1941 | */ | |
1942 | need_sof = 0; | |
1da69aa9 | 1943 | for (ttype = CVMX_USB_TRANSFER_CONTROL; |
68ea3380 | 1944 | ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) { |
4a23ee1b | 1945 | list_for_each_entry(pipe, &usb->active_pipes[ttype], node) { |
6570b4a9 AK |
1946 | if (pipe->next_tx_frame > usb->frame_number) { |
1947 | need_sof = 1; | |
1948 | break; | |
1949 | } | |
6570b4a9 AK |
1950 | } |
1951 | } | |
1da69aa9 | 1952 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
6068e818 | 1953 | cvmx_usbcx_gintmsk, sofmsk, need_sof); |
6570b4a9 AK |
1954 | } |
1955 | ||
8b07d2fe | 1956 | static void octeon_usb_urb_complete_callback(struct octeon_hcd *usb, |
add3ea32 | 1957 | enum cvmx_usb_status status, |
60f81507 | 1958 | struct cvmx_usb_pipe *pipe, |
3e1674c0 AK |
1959 | struct cvmx_usb_transaction |
1960 | *transaction, | |
75ee5124 | 1961 | int bytes_transferred, |
0cce1004 | 1962 | struct urb *urb) |
75ee5124 | 1963 | { |
8b07d2fe | 1964 | struct usb_hcd *hcd = octeon_to_hcd(usb); |
75ee5124 | 1965 | struct device *dev = hcd->self.controller; |
75ee5124 | 1966 | |
b186eb64 | 1967 | if (likely(status == CVMX_USB_STATUS_OK)) |
8dcf4ece AK |
1968 | urb->actual_length = bytes_transferred; |
1969 | else | |
1970 | urb->actual_length = 0; | |
1971 | ||
75ee5124 AK |
1972 | urb->hcpriv = NULL; |
1973 | ||
75ee5124 | 1974 | /* For Isochronous transactions we need to update the URB packet status |
edb0d9d4 SA |
1975 | * list from data in our private copy |
1976 | */ | |
75ee5124 AK |
1977 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
1978 | int i; | |
1979 | /* | |
1980 | * The pointer to the private list is stored in the setup_packet | |
1981 | * field. | |
1982 | */ | |
1983 | struct cvmx_usb_iso_packet *iso_packet = | |
ec7c4d7d | 1984 | (struct cvmx_usb_iso_packet *)urb->setup_packet; |
75ee5124 AK |
1985 | /* Recalculate the transfer size by adding up each packet */ |
1986 | urb->actual_length = 0; | |
1987 | for (i = 0; i < urb->number_of_packets; i++) { | |
b186eb64 | 1988 | if (iso_packet[i].status == CVMX_USB_STATUS_OK) { |
75ee5124 | 1989 | urb->iso_frame_desc[i].status = 0; |
1da69aa9 RO |
1990 | urb->iso_frame_desc[i].actual_length = |
1991 | iso_packet[i].length; | |
1992 | urb->actual_length += | |
1993 | urb->iso_frame_desc[i].actual_length; | |
75ee5124 | 1994 | } else { |
3e1674c0 | 1995 | dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n", |
75ee5124 | 1996 | i, urb->number_of_packets, |
60f81507 | 1997 | iso_packet[i].status, pipe, |
3e1674c0 | 1998 | transaction, iso_packet[i].length); |
75ee5124 AK |
1999 | urb->iso_frame_desc[i].status = -EREMOTEIO; |
2000 | } | |
2001 | } | |
2002 | /* Free the private list now that we don't need it anymore */ | |
2003 | kfree(iso_packet); | |
2004 | urb->setup_packet = NULL; | |
2005 | } | |
6570b4a9 | 2006 | |
75ee5124 | 2007 | switch (status) { |
b186eb64 | 2008 | case CVMX_USB_STATUS_OK: |
75ee5124 AK |
2009 | urb->status = 0; |
2010 | break; | |
add3ea32 | 2011 | case CVMX_USB_STATUS_CANCEL: |
75ee5124 AK |
2012 | if (urb->status == 0) |
2013 | urb->status = -ENOENT; | |
2014 | break; | |
add3ea32 | 2015 | case CVMX_USB_STATUS_STALL: |
3e1674c0 AK |
2016 | dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n", |
2017 | pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2018 | urb->status = -EPIPE; |
2019 | break; | |
add3ea32 | 2020 | case CVMX_USB_STATUS_BABBLEERR: |
3e1674c0 AK |
2021 | dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n", |
2022 | pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2023 | urb->status = -EPIPE; |
2024 | break; | |
add3ea32 | 2025 | case CVMX_USB_STATUS_SHORT: |
3e1674c0 AK |
2026 | dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n", |
2027 | pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2028 | urb->status = -EREMOTEIO; |
2029 | break; | |
add3ea32 AK |
2030 | case CVMX_USB_STATUS_ERROR: |
2031 | case CVMX_USB_STATUS_XACTERR: | |
2032 | case CVMX_USB_STATUS_DATATGLERR: | |
2033 | case CVMX_USB_STATUS_FRAMEERR: | |
3e1674c0 AK |
2034 | dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n", |
2035 | status, pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2036 | urb->status = -EPROTO; |
2037 | break; | |
2038 | } | |
8b07d2fe AK |
2039 | usb_hcd_unlink_urb_from_ep(octeon_to_hcd(usb), urb); |
2040 | spin_unlock(&usb->lock); | |
2041 | usb_hcd_giveback_urb(octeon_to_hcd(usb), urb, urb->status); | |
2042 | spin_lock(&usb->lock); | |
6570b4a9 AK |
2043 | } |
2044 | ||
6570b4a9 AK |
2045 | /** |
2046 | * Signal the completion of a transaction and free it. The | |
2047 | * transaction will be removed from the pipe transaction list. | |
2048 | * | |
cb61c600 | 2049 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
2050 | * @pipe: Pipe the transaction is on |
2051 | * @transaction: | |
2052 | * Transaction that completed | |
2053 | * @complete_code: | |
2054 | * Completion code | |
2055 | */ | |
8b07d2fe | 2056 | static void cvmx_usb_complete(struct octeon_hcd *usb, |
e6bff5a0 AK |
2057 | struct cvmx_usb_pipe *pipe, |
2058 | struct cvmx_usb_transaction *transaction, | |
2059 | enum cvmx_usb_status complete_code) | |
6570b4a9 AK |
2060 | { |
2061 | /* If this was a split then clear our split in progress marker */ | |
2062 | if (usb->active_split == transaction) | |
2063 | usb->active_split = NULL; | |
2064 | ||
2065 | /* | |
2066 | * Isochronous transactions need extra processing as they might not be | |
2067 | * done after a single data transfer | |
2068 | */ | |
2069 | if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) { | |
2070 | /* Update the number of bytes transferred in this ISO packet */ | |
2071 | transaction->iso_packets[0].length = transaction->actual_bytes; | |
2072 | transaction->iso_packets[0].status = complete_code; | |
2073 | ||
2074 | /* | |
2075 | * If there are more ISOs pending and we succeeded, schedule the | |
2076 | * next one | |
2077 | */ | |
1da69aa9 | 2078 | if ((transaction->iso_number_packets > 1) && |
b186eb64 | 2079 | (complete_code == CVMX_USB_STATUS_OK)) { |
6570b4a9 AK |
2080 | /* No bytes transferred for this packet as of yet */ |
2081 | transaction->actual_bytes = 0; | |
2082 | /* One less ISO waiting to transfer */ | |
2083 | transaction->iso_number_packets--; | |
2084 | /* Increment to the next location in our packet array */ | |
2085 | transaction->iso_packets++; | |
2086 | transaction->stage = CVMX_USB_STAGE_NON_CONTROL; | |
15ef0cc1 | 2087 | return; |
6570b4a9 AK |
2088 | } |
2089 | } | |
2090 | ||
2091 | /* Remove the transaction from the pipe list */ | |
5669601d AK |
2092 | list_del(&transaction->node); |
2093 | if (list_empty(&pipe->transactions)) | |
4a23ee1b | 2094 | list_move_tail(&pipe->node, &usb->idle_pipes); |
60f81507 | 2095 | octeon_usb_urb_complete_callback(usb, complete_code, pipe, |
3e1674c0 | 2096 | transaction, |
75ee5124 | 2097 | transaction->actual_bytes, |
0cce1004 | 2098 | transaction->urb); |
a2dfef06 | 2099 | kfree(transaction); |
6570b4a9 AK |
2100 | } |
2101 | ||
6570b4a9 AK |
2102 | /** |
2103 | * Submit a usb transaction to a pipe. Called for all types | |
2104 | * of transactions. | |
2105 | * | |
2106 | * @usb: | |
60f81507 | 2107 | * @pipe: Which pipe to submit to. |
6570b4a9 AK |
2108 | * @type: Transaction type |
2109 | * @buffer: User buffer for the transaction | |
2110 | * @buffer_length: | |
2111 | * User buffer's length in bytes | |
2112 | * @control_header: | |
2113 | * For control transactions, the 8 byte standard header | |
2114 | * @iso_start_frame: | |
2115 | * For ISO transactions, the start frame | |
2116 | * @iso_number_packets: | |
2117 | * For ISO, the number of packet in the transaction. | |
2118 | * @iso_packets: | |
2119 | * A description of each ISO packet | |
0cce1004 | 2120 | * @urb: URB for the callback |
6570b4a9 | 2121 | * |
3e1674c0 | 2122 | * Returns: Transaction or NULL on failure. |
6570b4a9 | 2123 | */ |
68d435dd | 2124 | static struct cvmx_usb_transaction *cvmx_usb_submit_transaction( |
8b07d2fe | 2125 | struct octeon_hcd *usb, |
1da69aa9 RO |
2126 | struct cvmx_usb_pipe *pipe, |
2127 | enum cvmx_usb_transfer type, | |
cce66005 | 2128 | u64 buffer, |
1da69aa9 | 2129 | int buffer_length, |
cce66005 | 2130 | u64 control_header, |
1da69aa9 RO |
2131 | int iso_start_frame, |
2132 | int iso_number_packets, | |
2133 | struct cvmx_usb_iso_packet *iso_packets, | |
2134 | struct urb *urb) | |
6570b4a9 | 2135 | { |
6570b4a9 | 2136 | struct cvmx_usb_transaction *transaction; |
6570b4a9 | 2137 | |
6570b4a9 | 2138 | if (unlikely(pipe->transfer_type != type)) |
3e1674c0 | 2139 | return NULL; |
6570b4a9 | 2140 | |
a2dfef06 | 2141 | transaction = kzalloc(sizeof(*transaction), GFP_ATOMIC); |
6570b4a9 | 2142 | if (unlikely(!transaction)) |
3e1674c0 | 2143 | return NULL; |
6570b4a9 AK |
2144 | |
2145 | transaction->type = type; | |
2146 | transaction->buffer = buffer; | |
2147 | transaction->buffer_length = buffer_length; | |
2148 | transaction->control_header = control_header; | |
2149 | /* FIXME: This is not used, implement it. */ | |
2150 | transaction->iso_start_frame = iso_start_frame; | |
2151 | transaction->iso_number_packets = iso_number_packets; | |
2152 | transaction->iso_packets = iso_packets; | |
0cce1004 | 2153 | transaction->urb = urb; |
6570b4a9 AK |
2154 | if (transaction->type == CVMX_USB_TRANSFER_CONTROL) |
2155 | transaction->stage = CVMX_USB_STAGE_SETUP; | |
2156 | else | |
2157 | transaction->stage = CVMX_USB_STAGE_NON_CONTROL; | |
2158 | ||
5669601d AK |
2159 | if (!list_empty(&pipe->transactions)) { |
2160 | list_add_tail(&transaction->node, &pipe->transactions); | |
6570b4a9 | 2161 | } else { |
5669601d | 2162 | list_add_tail(&transaction->node, &pipe->transactions); |
4a23ee1b AK |
2163 | list_move_tail(&pipe->node, |
2164 | &usb->active_pipes[pipe->transfer_type]); | |
6570b4a9 | 2165 | |
5669601d AK |
2166 | /* |
2167 | * We may need to schedule the pipe if this was the head of the | |
2168 | * pipe. | |
2169 | */ | |
68d435dd | 2170 | cvmx_usb_schedule(usb, 0); |
5669601d | 2171 | } |
6570b4a9 | 2172 | |
3e1674c0 | 2173 | return transaction; |
6570b4a9 AK |
2174 | } |
2175 | ||
6570b4a9 AK |
2176 | /** |
2177 | * Call to submit a USB Bulk transfer to a pipe. | |
2178 | * | |
cb61c600 | 2179 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2180 | * @pipe: Handle to the pipe for the transfer. |
9ccca707 | 2181 | * @urb: URB. |
6570b4a9 | 2182 | * |
3e1674c0 | 2183 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2184 | */ |
1da69aa9 | 2185 | static struct cvmx_usb_transaction *cvmx_usb_submit_bulk( |
8b07d2fe | 2186 | struct octeon_hcd *usb, |
1da69aa9 RO |
2187 | struct cvmx_usb_pipe *pipe, |
2188 | struct urb *urb) | |
6570b4a9 | 2189 | { |
68d435dd AK |
2190 | return cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK, |
2191 | urb->transfer_dma, | |
2192 | urb->transfer_buffer_length, | |
2193 | 0, /* control_header */ | |
2194 | 0, /* iso_start_frame */ | |
2195 | 0, /* iso_number_packets */ | |
2196 | NULL, /* iso_packets */ | |
2197 | urb); | |
6570b4a9 AK |
2198 | } |
2199 | ||
6570b4a9 AK |
2200 | /** |
2201 | * Call to submit a USB Interrupt transfer to a pipe. | |
2202 | * | |
cb61c600 | 2203 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2204 | * @pipe: Handle to the pipe for the transfer. |
0cce1004 | 2205 | * @urb: URB returned when the callback is called. |
6570b4a9 | 2206 | * |
3e1674c0 | 2207 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2208 | */ |
1da69aa9 | 2209 | static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt( |
8b07d2fe | 2210 | struct octeon_hcd *usb, |
1da69aa9 RO |
2211 | struct cvmx_usb_pipe *pipe, |
2212 | struct urb *urb) | |
6570b4a9 | 2213 | { |
68d435dd AK |
2214 | return cvmx_usb_submit_transaction(usb, pipe, |
2215 | CVMX_USB_TRANSFER_INTERRUPT, | |
2216 | urb->transfer_dma, | |
2217 | urb->transfer_buffer_length, | |
2218 | 0, /* control_header */ | |
2219 | 0, /* iso_start_frame */ | |
2220 | 0, /* iso_number_packets */ | |
2221 | NULL, /* iso_packets */ | |
2222 | urb); | |
6570b4a9 AK |
2223 | } |
2224 | ||
6570b4a9 AK |
2225 | /** |
2226 | * Call to submit a USB Control transfer to a pipe. | |
2227 | * | |
cb61c600 | 2228 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2229 | * @pipe: Handle to the pipe for the transfer. |
2ae09e87 | 2230 | * @urb: URB. |
6570b4a9 | 2231 | * |
3e1674c0 | 2232 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2233 | */ |
1da69aa9 | 2234 | static struct cvmx_usb_transaction *cvmx_usb_submit_control( |
8b07d2fe | 2235 | struct octeon_hcd *usb, |
1da69aa9 RO |
2236 | struct cvmx_usb_pipe *pipe, |
2237 | struct urb *urb) | |
6570b4a9 | 2238 | { |
2ae09e87 | 2239 | int buffer_length = urb->transfer_buffer_length; |
cce66005 | 2240 | u64 control_header = urb->setup_dma; |
e301dfb2 | 2241 | struct usb_ctrlrequest *header = cvmx_phys_to_ptr(control_header); |
6570b4a9 | 2242 | |
96ee2cc8 | 2243 | if ((header->bRequestType & USB_DIR_IN) == 0) |
e301dfb2 | 2244 | buffer_length = le16_to_cpu(header->wLength); |
6570b4a9 | 2245 | |
68d435dd AK |
2246 | return cvmx_usb_submit_transaction(usb, pipe, |
2247 | CVMX_USB_TRANSFER_CONTROL, | |
2248 | urb->transfer_dma, buffer_length, | |
2249 | control_header, | |
2250 | 0, /* iso_start_frame */ | |
2251 | 0, /* iso_number_packets */ | |
2252 | NULL, /* iso_packets */ | |
2253 | urb); | |
6570b4a9 AK |
2254 | } |
2255 | ||
6570b4a9 AK |
2256 | /** |
2257 | * Call to submit a USB Isochronous transfer to a pipe. | |
2258 | * | |
cb61c600 | 2259 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2260 | * @pipe: Handle to the pipe for the transfer. |
0cce1004 | 2261 | * @urb: URB returned when the callback is called. |
6570b4a9 | 2262 | * |
3e1674c0 | 2263 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2264 | */ |
1da69aa9 | 2265 | static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous( |
8b07d2fe | 2266 | struct octeon_hcd *usb, |
1da69aa9 RO |
2267 | struct cvmx_usb_pipe *pipe, |
2268 | struct urb *urb) | |
6570b4a9 | 2269 | { |
e16b5e3f | 2270 | struct cvmx_usb_iso_packet *packets; |
6570b4a9 | 2271 | |
ec7c4d7d | 2272 | packets = (struct cvmx_usb_iso_packet *)urb->setup_packet; |
68d435dd AK |
2273 | return cvmx_usb_submit_transaction(usb, pipe, |
2274 | CVMX_USB_TRANSFER_ISOCHRONOUS, | |
2275 | urb->transfer_dma, | |
2276 | urb->transfer_buffer_length, | |
2277 | 0, /* control_header */ | |
2278 | urb->start_frame, | |
2279 | urb->number_of_packets, | |
2280 | packets, urb); | |
6570b4a9 AK |
2281 | } |
2282 | ||
6570b4a9 AK |
2283 | /** |
2284 | * Cancel one outstanding request in a pipe. Canceling a request | |
2285 | * can fail if the transaction has already completed before cancel | |
2286 | * is called. Even after a successful cancel call, it may take | |
2287 | * a frame or two for the cvmx_usb_poll() function to call the | |
2288 | * associated callback. | |
2289 | * | |
cb61c600 | 2290 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2291 | * @pipe: Pipe to cancel requests in. |
3e1674c0 | 2292 | * @transaction: Transaction to cancel, returned by the submit function. |
6570b4a9 AK |
2293 | * |
2294 | * Returns: 0 or a negative error code. | |
2295 | */ | |
8b07d2fe | 2296 | static int cvmx_usb_cancel(struct octeon_hcd *usb, |
60f81507 | 2297 | struct cvmx_usb_pipe *pipe, |
3e1674c0 | 2298 | struct cvmx_usb_transaction *transaction) |
6570b4a9 | 2299 | { |
6570b4a9 AK |
2300 | /* |
2301 | * If the transaction is the HEAD of the queue and scheduled. We need to | |
2302 | * treat it special | |
2303 | */ | |
5669601d | 2304 | if (list_first_entry(&pipe->transactions, typeof(*transaction), node) == |
3f9697b7 | 2305 | transaction && (pipe->flags & CVMX_USB_PIPE_FLAGS_SCHEDULED)) { |
6570b4a9 AK |
2306 | union cvmx_usbcx_hccharx usbc_hcchar; |
2307 | ||
2308 | usb->pipe_for_channel[pipe->channel] = NULL; | |
3f9697b7 | 2309 | pipe->flags &= ~CVMX_USB_PIPE_FLAGS_SCHEDULED; |
6570b4a9 AK |
2310 | |
2311 | CVMX_SYNCW; | |
2312 | ||
68d435dd | 2313 | usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2314 | CVMX_USBCX_HCCHARX(pipe->channel, usb->index)); |
6570b4a9 AK |
2315 | /* |
2316 | * If the channel isn't enabled then the transaction already | |
2317 | * completed. | |
2318 | */ | |
2319 | if (usbc_hcchar.s.chena) { | |
2320 | usbc_hcchar.s.chdis = 1; | |
68d435dd | 2321 | cvmx_usb_write_csr32(usb, |
68ea3380 AK |
2322 | CVMX_USBCX_HCCHARX(pipe->channel, |
2323 | usb->index), | |
2324 | usbc_hcchar.u32); | |
6570b4a9 AK |
2325 | } |
2326 | } | |
e6bff5a0 | 2327 | cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_CANCEL); |
6570b4a9 AK |
2328 | return 0; |
2329 | } | |
2330 | ||
6570b4a9 AK |
2331 | /** |
2332 | * Cancel all outstanding requests in a pipe. Logically all this | |
2333 | * does is call cvmx_usb_cancel() in a loop. | |
2334 | * | |
cb61c600 | 2335 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2336 | * @pipe: Pipe to cancel requests in. |
6570b4a9 AK |
2337 | * |
2338 | * Returns: 0 or a negative error code. | |
2339 | */ | |
8b07d2fe | 2340 | static int cvmx_usb_cancel_all(struct octeon_hcd *usb, |
60f81507 | 2341 | struct cvmx_usb_pipe *pipe) |
6570b4a9 | 2342 | { |
5669601d AK |
2343 | struct cvmx_usb_transaction *transaction, *next; |
2344 | ||
6570b4a9 | 2345 | /* Simply loop through and attempt to cancel each transaction */ |
5669601d AK |
2346 | list_for_each_entry_safe(transaction, next, &pipe->transactions, node) { |
2347 | int result = cvmx_usb_cancel(usb, pipe, transaction); | |
f5106435 | 2348 | |
6570b4a9 AK |
2349 | if (unlikely(result != 0)) |
2350 | return result; | |
2351 | } | |
2352 | return 0; | |
2353 | } | |
2354 | ||
6570b4a9 AK |
2355 | /** |
2356 | * Close a pipe created with cvmx_usb_open_pipe(). | |
2357 | * | |
cb61c600 | 2358 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2359 | * @pipe: Pipe to close. |
6570b4a9 AK |
2360 | * |
2361 | * Returns: 0 or a negative error code. EBUSY is returned if the pipe has | |
2362 | * outstanding transfers. | |
2363 | */ | |
8b07d2fe | 2364 | static int cvmx_usb_close_pipe(struct octeon_hcd *usb, |
60f81507 | 2365 | struct cvmx_usb_pipe *pipe) |
6570b4a9 | 2366 | { |
6570b4a9 | 2367 | /* Fail if the pipe has pending transactions */ |
5669601d | 2368 | if (!list_empty(&pipe->transactions)) |
6570b4a9 AK |
2369 | return -EBUSY; |
2370 | ||
4a23ee1b | 2371 | list_del(&pipe->node); |
d2695a8a | 2372 | kfree(pipe); |
6570b4a9 AK |
2373 | |
2374 | return 0; | |
2375 | } | |
2376 | ||
6570b4a9 AK |
2377 | /** |
2378 | * Get the current USB protocol level frame number. The frame | |
2379 | * number is always in the range of 0-0x7ff. | |
2380 | * | |
cb61c600 | 2381 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
2382 | * |
2383 | * Returns: USB frame number | |
2384 | */ | |
8b07d2fe | 2385 | static int cvmx_usb_get_frame_number(struct octeon_hcd *usb) |
6570b4a9 AK |
2386 | { |
2387 | int frame_number; | |
6570b4a9 AK |
2388 | union cvmx_usbcx_hfnum usbc_hfnum; |
2389 | ||
68d435dd | 2390 | usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index)); |
6570b4a9 AK |
2391 | frame_number = usbc_hfnum.s.frnum; |
2392 | ||
2393 | return frame_number; | |
2394 | } | |
2395 | ||
81a71bad AK |
2396 | static void cvmx_usb_transfer_control(struct octeon_hcd *usb, |
2397 | struct cvmx_usb_pipe *pipe, | |
2398 | struct cvmx_usb_transaction *transaction, | |
2399 | union cvmx_usbcx_hccharx usbc_hcchar, | |
2400 | int buffer_space_left, | |
2401 | int bytes_in_last_packet) | |
2402 | { | |
2403 | switch (transaction->stage) { | |
2404 | case CVMX_USB_STAGE_NON_CONTROL: | |
2405 | case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE: | |
2406 | /* This should be impossible */ | |
2407 | cvmx_usb_complete(usb, pipe, transaction, | |
2408 | CVMX_USB_STATUS_ERROR); | |
2409 | break; | |
2410 | case CVMX_USB_STAGE_SETUP: | |
2411 | pipe->pid_toggle = 1; | |
2412 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { | |
2413 | transaction->stage = | |
2414 | CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE; | |
2415 | } else { | |
2416 | struct usb_ctrlrequest *header = | |
2417 | cvmx_phys_to_ptr(transaction->control_header); | |
2418 | if (header->wLength) | |
2419 | transaction->stage = CVMX_USB_STAGE_DATA; | |
2420 | else | |
2421 | transaction->stage = CVMX_USB_STAGE_STATUS; | |
2422 | } | |
2423 | break; | |
2424 | case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE: | |
2425 | { | |
2426 | struct usb_ctrlrequest *header = | |
2427 | cvmx_phys_to_ptr(transaction->control_header); | |
2428 | if (header->wLength) | |
2429 | transaction->stage = CVMX_USB_STAGE_DATA; | |
2430 | else | |
2431 | transaction->stage = CVMX_USB_STAGE_STATUS; | |
2432 | } | |
2433 | break; | |
2434 | case CVMX_USB_STAGE_DATA: | |
2435 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { | |
2436 | transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE; | |
2437 | /* | |
2438 | * For setup OUT data that are splits, | |
2439 | * the hardware doesn't appear to count | |
2440 | * transferred data. Here we manually | |
2441 | * update the data transferred | |
2442 | */ | |
2443 | if (!usbc_hcchar.s.epdir) { | |
2444 | if (buffer_space_left < pipe->max_packet) | |
2445 | transaction->actual_bytes += | |
2446 | buffer_space_left; | |
2447 | else | |
2448 | transaction->actual_bytes += | |
2449 | pipe->max_packet; | |
2450 | } | |
2451 | } else if ((buffer_space_left == 0) || | |
2452 | (bytes_in_last_packet < pipe->max_packet)) { | |
2453 | pipe->pid_toggle = 1; | |
2454 | transaction->stage = CVMX_USB_STAGE_STATUS; | |
2455 | } | |
2456 | break; | |
2457 | case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE: | |
2458 | if ((buffer_space_left == 0) || | |
2459 | (bytes_in_last_packet < pipe->max_packet)) { | |
2460 | pipe->pid_toggle = 1; | |
2461 | transaction->stage = CVMX_USB_STAGE_STATUS; | |
2462 | } else { | |
2463 | transaction->stage = CVMX_USB_STAGE_DATA; | |
2464 | } | |
2465 | break; | |
2466 | case CVMX_USB_STAGE_STATUS: | |
2467 | if (cvmx_usb_pipe_needs_split(usb, pipe)) | |
2468 | transaction->stage = | |
2469 | CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE; | |
2470 | else | |
2471 | cvmx_usb_complete(usb, pipe, transaction, | |
2472 | CVMX_USB_STATUS_OK); | |
2473 | break; | |
2474 | case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE: | |
2475 | cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_OK); | |
2476 | break; | |
2477 | } | |
2478 | } | |
2479 | ||
8ed3094c AK |
2480 | static void cvmx_usb_transfer_bulk(struct octeon_hcd *usb, |
2481 | struct cvmx_usb_pipe *pipe, | |
2482 | struct cvmx_usb_transaction *transaction, | |
2483 | union cvmx_usbcx_hcintx usbc_hcint, | |
2484 | int buffer_space_left, | |
2485 | int bytes_in_last_packet) | |
2486 | { | |
2487 | /* | |
2488 | * The only time a bulk transfer isn't complete when it finishes with | |
2489 | * an ACK is during a split transaction. For splits we need to continue | |
2490 | * the transfer if more data is needed. | |
2491 | */ | |
2492 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { | |
2493 | if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL) | |
2494 | transaction->stage = | |
2495 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; | |
2496 | else if (buffer_space_left && | |
2497 | (bytes_in_last_packet == pipe->max_packet)) | |
2498 | transaction->stage = CVMX_USB_STAGE_NON_CONTROL; | |
2499 | else | |
2500 | cvmx_usb_complete(usb, pipe, transaction, | |
2501 | CVMX_USB_STATUS_OK); | |
2502 | } else { | |
2503 | if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) && | |
2504 | (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) && | |
2505 | (usbc_hcint.s.nak)) | |
2506 | pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; | |
2507 | if (!buffer_space_left || | |
2508 | (bytes_in_last_packet < pipe->max_packet)) | |
2509 | cvmx_usb_complete(usb, pipe, transaction, | |
2510 | CVMX_USB_STATUS_OK); | |
2511 | } | |
2512 | } | |
2513 | ||
dfce6267 AK |
2514 | static void cvmx_usb_transfer_intr(struct octeon_hcd *usb, |
2515 | struct cvmx_usb_pipe *pipe, | |
2516 | struct cvmx_usb_transaction *transaction, | |
2517 | int buffer_space_left, | |
2518 | int bytes_in_last_packet) | |
2519 | { | |
2520 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { | |
2521 | if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL) { | |
2522 | transaction->stage = | |
2523 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; | |
2524 | } else if (buffer_space_left && | |
2525 | (bytes_in_last_packet == pipe->max_packet)) { | |
2526 | transaction->stage = CVMX_USB_STAGE_NON_CONTROL; | |
2527 | } else { | |
2528 | pipe->next_tx_frame += pipe->interval; | |
2529 | cvmx_usb_complete(usb, pipe, transaction, | |
2530 | CVMX_USB_STATUS_OK); | |
2531 | } | |
2532 | } else if (!buffer_space_left || | |
2533 | (bytes_in_last_packet < pipe->max_packet)) { | |
2534 | pipe->next_tx_frame += pipe->interval; | |
2535 | cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_OK); | |
2536 | } | |
2537 | } | |
2538 | ||
dd588994 AK |
2539 | static void cvmx_usb_transfer_isoc(struct octeon_hcd *usb, |
2540 | struct cvmx_usb_pipe *pipe, | |
2541 | struct cvmx_usb_transaction *transaction, | |
2542 | int buffer_space_left, | |
2543 | int bytes_in_last_packet, | |
2544 | int bytes_this_transfer) | |
2545 | { | |
2546 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { | |
2547 | /* | |
2548 | * ISOCHRONOUS OUT splits don't require a complete split stage. | |
2549 | * Instead they use a sequence of begin OUT splits to transfer | |
2550 | * the data 188 bytes at a time. Once the transfer is complete, | |
2551 | * the pipe sleeps until the next schedule interval. | |
2552 | */ | |
2553 | if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) { | |
2554 | /* | |
2555 | * If no space left or this wasn't a max size packet | |
2556 | * then this transfer is complete. Otherwise start it | |
2557 | * again to send the next 188 bytes | |
2558 | */ | |
2559 | if (!buffer_space_left || (bytes_this_transfer < 188)) { | |
2560 | pipe->next_tx_frame += pipe->interval; | |
2561 | cvmx_usb_complete(usb, pipe, transaction, | |
2562 | CVMX_USB_STATUS_OK); | |
2563 | } | |
2564 | return; | |
2565 | } | |
2566 | if (transaction->stage == | |
2567 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) { | |
2568 | /* | |
2569 | * We are in the incoming data phase. Keep getting data | |
2570 | * until we run out of space or get a small packet | |
2571 | */ | |
2572 | if ((buffer_space_left == 0) || | |
2573 | (bytes_in_last_packet < pipe->max_packet)) { | |
2574 | pipe->next_tx_frame += pipe->interval; | |
2575 | cvmx_usb_complete(usb, pipe, transaction, | |
2576 | CVMX_USB_STATUS_OK); | |
2577 | } | |
2578 | } else { | |
2579 | transaction->stage = | |
2580 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; | |
2581 | } | |
2582 | } else { | |
2583 | pipe->next_tx_frame += pipe->interval; | |
2584 | cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_OK); | |
2585 | } | |
2586 | } | |
2587 | ||
6570b4a9 AK |
2588 | /** |
2589 | * Poll a channel for status | |
2590 | * | |
2591 | * @usb: USB device | |
2592 | * @channel: Channel to poll | |
2593 | * | |
2594 | * Returns: Zero on success | |
2595 | */ | |
8b07d2fe | 2596 | static int cvmx_usb_poll_channel(struct octeon_hcd *usb, int channel) |
6570b4a9 | 2597 | { |
8b07d2fe | 2598 | struct usb_hcd *hcd = octeon_to_hcd(usb); |
ba0b8e42 | 2599 | struct device *dev = hcd->self.controller; |
6570b4a9 AK |
2600 | union cvmx_usbcx_hcintx usbc_hcint; |
2601 | union cvmx_usbcx_hctsizx usbc_hctsiz; | |
2602 | union cvmx_usbcx_hccharx usbc_hcchar; | |
2603 | struct cvmx_usb_pipe *pipe; | |
2604 | struct cvmx_usb_transaction *transaction; | |
2605 | int bytes_this_transfer; | |
2606 | int bytes_in_last_packet; | |
2607 | int packets_processed; | |
2608 | int buffer_space_left; | |
2609 | ||
2610 | /* Read the interrupt status bits for the channel */ | |
68d435dd AK |
2611 | usbc_hcint.u32 = cvmx_usb_read_csr32(usb, |
2612 | CVMX_USBCX_HCINTX(channel, usb->index)); | |
6570b4a9 AK |
2613 | |
2614 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { | |
68d435dd | 2615 | usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2616 | CVMX_USBCX_HCCHARX(channel, usb->index)); |
6570b4a9 AK |
2617 | |
2618 | if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) { | |
2619 | /* | |
2620 | * There seems to be a bug in CN31XX which can cause | |
2621 | * interrupt IN transfers to get stuck until we do a | |
2622 | * write of HCCHARX without changing things | |
2623 | */ | |
68d435dd | 2624 | cvmx_usb_write_csr32(usb, |
68ea3380 AK |
2625 | CVMX_USBCX_HCCHARX(channel, |
2626 | usb->index), | |
2627 | usbc_hcchar.u32); | |
6570b4a9 AK |
2628 | return 0; |
2629 | } | |
2630 | ||
2631 | /* | |
2632 | * In non DMA mode the channels don't halt themselves. We need | |
2633 | * to manually disable channels that are left running | |
2634 | */ | |
2635 | if (!usbc_hcint.s.chhltd) { | |
2636 | if (usbc_hcchar.s.chena) { | |
2637 | union cvmx_usbcx_hcintmskx hcintmsk; | |
2638 | /* Disable all interrupts except CHHLTD */ | |
2639 | hcintmsk.u32 = 0; | |
2640 | hcintmsk.s.chhltdmsk = 1; | |
68d435dd | 2641 | cvmx_usb_write_csr32(usb, |
68ea3380 AK |
2642 | CVMX_USBCX_HCINTMSKX(channel, usb->index), |
2643 | hcintmsk.u32); | |
6570b4a9 | 2644 | usbc_hcchar.s.chdis = 1; |
68d435dd | 2645 | cvmx_usb_write_csr32(usb, |
68ea3380 AK |
2646 | CVMX_USBCX_HCCHARX(channel, usb->index), |
2647 | usbc_hcchar.u32); | |
6570b4a9 AK |
2648 | return 0; |
2649 | } else if (usbc_hcint.s.xfercompl) { | |
2650 | /* | |
2651 | * Successful IN/OUT with transfer complete. | |
2652 | * Channel halt isn't needed. | |
2653 | */ | |
2654 | } else { | |
ba0b8e42 AK |
2655 | dev_err(dev, "USB%d: Channel %d interrupt without halt\n", |
2656 | usb->index, channel); | |
6570b4a9 AK |
2657 | return 0; |
2658 | } | |
2659 | } | |
2660 | } else { | |
2661 | /* | |
2662 | * There is are no interrupts that we need to process when the | |
2663 | * channel is still running | |
2664 | */ | |
2665 | if (!usbc_hcint.s.chhltd) | |
2666 | return 0; | |
2667 | } | |
2668 | ||
2669 | /* Disable the channel interrupts now that it is done */ | |
68d435dd | 2670 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0); |
3c98ef90 | 2671 | usb->idle_hardware_channels |= (1 << channel); |
6570b4a9 AK |
2672 | |
2673 | /* Make sure this channel is tied to a valid pipe */ | |
2674 | pipe = usb->pipe_for_channel[channel]; | |
20f6b829 | 2675 | prefetch(pipe); |
6570b4a9 AK |
2676 | if (!pipe) |
2677 | return 0; | |
1da69aa9 RO |
2678 | transaction = list_first_entry(&pipe->transactions, |
2679 | typeof(*transaction), | |
5669601d | 2680 | node); |
20f6b829 | 2681 | prefetch(transaction); |
6570b4a9 AK |
2682 | |
2683 | /* | |
2684 | * Disconnect this pipe from the HW channel. Later the schedule | |
2685 | * function will figure out which pipe needs to go | |
2686 | */ | |
2687 | usb->pipe_for_channel[channel] = NULL; | |
3f9697b7 | 2688 | pipe->flags &= ~CVMX_USB_PIPE_FLAGS_SCHEDULED; |
6570b4a9 AK |
2689 | |
2690 | /* | |
2691 | * Read the channel config info so we can figure out how much data | |
1cf3273d | 2692 | * transferred |
6570b4a9 | 2693 | */ |
68d435dd | 2694 | usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2695 | CVMX_USBCX_HCCHARX(channel, usb->index)); |
68d435dd | 2696 | usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2697 | CVMX_USBCX_HCTSIZX(channel, usb->index)); |
6570b4a9 AK |
2698 | |
2699 | /* | |
2700 | * Calculating the number of bytes successfully transferred is dependent | |
2701 | * on the transfer direction | |
2702 | */ | |
2703 | packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt; | |
2704 | if (usbc_hcchar.s.epdir) { | |
2705 | /* | |
2706 | * IN transactions are easy. For every byte received the | |
2707 | * hardware decrements xfersize. All we need to do is subtract | |
2708 | * the current value of xfersize from its starting value and we | |
2709 | * know how many bytes were written to the buffer | |
2710 | */ | |
1da69aa9 RO |
2711 | bytes_this_transfer = transaction->xfersize - |
2712 | usbc_hctsiz.s.xfersize; | |
6570b4a9 AK |
2713 | } else { |
2714 | /* | |
2715 | * OUT transaction don't decrement xfersize. Instead pktcnt is | |
2716 | * decremented on every successful packet send. The hardware | |
2717 | * does this when it receives an ACK, or NYET. If it doesn't | |
2718 | * receive one of these responses pktcnt doesn't change | |
2719 | */ | |
2720 | bytes_this_transfer = packets_processed * usbc_hcchar.s.mps; | |
2721 | /* | |
2722 | * The last packet may not be a full transfer if we didn't have | |
2723 | * enough data | |
2724 | */ | |
2725 | if (bytes_this_transfer > transaction->xfersize) | |
2726 | bytes_this_transfer = transaction->xfersize; | |
2727 | } | |
2728 | /* Figure out how many bytes were in the last packet of the transfer */ | |
2729 | if (packets_processed) | |
1da69aa9 RO |
2730 | bytes_in_last_packet = bytes_this_transfer - |
2731 | (packets_processed - 1) * usbc_hcchar.s.mps; | |
6570b4a9 AK |
2732 | else |
2733 | bytes_in_last_packet = bytes_this_transfer; | |
2734 | ||
2735 | /* | |
2736 | * As a special case, setup transactions output the setup header, not | |
2737 | * the user's data. For this reason we don't count setup data as bytes | |
2738 | * transferred | |
2739 | */ | |
2740 | if ((transaction->stage == CVMX_USB_STAGE_SETUP) || | |
68ea3380 | 2741 | (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE)) |
6570b4a9 AK |
2742 | bytes_this_transfer = 0; |
2743 | ||
2744 | /* | |
2745 | * Add the bytes transferred to the running total. It is important that | |
2746 | * bytes_this_transfer doesn't count any data that needs to be | |
2747 | * retransmitted | |
2748 | */ | |
2749 | transaction->actual_bytes += bytes_this_transfer; | |
2750 | if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) | |
1da69aa9 RO |
2751 | buffer_space_left = transaction->iso_packets[0].length - |
2752 | transaction->actual_bytes; | |
6570b4a9 | 2753 | else |
1da69aa9 RO |
2754 | buffer_space_left = transaction->buffer_length - |
2755 | transaction->actual_bytes; | |
6570b4a9 AK |
2756 | |
2757 | /* | |
2758 | * We need to remember the PID toggle state for the next transaction. | |
2759 | * The hardware already updated it for the next transaction | |
2760 | */ | |
2761 | pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0); | |
2762 | ||
2763 | /* | |
2764 | * For high speed bulk out, assume the next transaction will need to do | |
2765 | * a ping before proceeding. If this isn't true the ACK processing below | |
2766 | * will clear this flag | |
2767 | */ | |
2768 | if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) && | |
68ea3380 AK |
2769 | (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) && |
2770 | (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT)) | |
3f9697b7 | 2771 | pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; |
6570b4a9 | 2772 | |
009e451c | 2773 | if (WARN_ON_ONCE(bytes_this_transfer < 0)) { |
f3b8edc0 AK |
2774 | /* |
2775 | * In some rare cases the DMA engine seems to get stuck and | |
2776 | * keeps substracting same byte count over and over again. In | |
2777 | * such case we just need to fail every transaction. | |
2778 | */ | |
e6bff5a0 AK |
2779 | cvmx_usb_complete(usb, pipe, transaction, |
2780 | CVMX_USB_STATUS_ERROR); | |
f3b8edc0 AK |
2781 | return 0; |
2782 | } | |
2783 | ||
6570b4a9 AK |
2784 | if (usbc_hcint.s.stall) { |
2785 | /* | |
2786 | * STALL as a response means this transaction cannot be | |
2787 | * completed because the device can't process transactions. Tell | |
2788 | * the user. Any data that was transferred will be counted on | |
2789 | * the actual bytes transferred | |
2790 | */ | |
2791 | pipe->pid_toggle = 0; | |
e6bff5a0 AK |
2792 | cvmx_usb_complete(usb, pipe, transaction, |
2793 | CVMX_USB_STATUS_STALL); | |
6570b4a9 AK |
2794 | } else if (usbc_hcint.s.xacterr) { |
2795 | /* | |
532edc93 AK |
2796 | * XactErr as a response means the device signaled |
2797 | * something wrong with the transfer. For example, PID | |
2798 | * toggle errors cause these. | |
6570b4a9 | 2799 | */ |
e6bff5a0 AK |
2800 | cvmx_usb_complete(usb, pipe, transaction, |
2801 | CVMX_USB_STATUS_XACTERR); | |
6570b4a9 AK |
2802 | } else if (usbc_hcint.s.bblerr) { |
2803 | /* Babble Error (BblErr) */ | |
e6bff5a0 AK |
2804 | cvmx_usb_complete(usb, pipe, transaction, |
2805 | CVMX_USB_STATUS_BABBLEERR); | |
6570b4a9 | 2806 | } else if (usbc_hcint.s.datatglerr) { |
d8c39d3f | 2807 | /* Data toggle error */ |
e6bff5a0 AK |
2808 | cvmx_usb_complete(usb, pipe, transaction, |
2809 | CVMX_USB_STATUS_DATATGLERR); | |
6570b4a9 AK |
2810 | } else if (usbc_hcint.s.nyet) { |
2811 | /* | |
2812 | * NYET as a response is only allowed in three cases: as a | |
2813 | * response to a ping, as a response to a split transaction, and | |
2814 | * as a response to a bulk out. The ping case is handled by | |
2815 | * hardware, so we only have splits and bulk out | |
2816 | */ | |
68d435dd | 2817 | if (!cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
2818 | transaction->retries = 0; |
2819 | /* | |
2820 | * If there is more data to go then we need to try | |
2821 | * again. Otherwise this transaction is complete | |
2822 | */ | |
1da69aa9 | 2823 | if ((buffer_space_left == 0) || |
68ea3380 | 2824 | (bytes_in_last_packet < pipe->max_packet)) |
e6bff5a0 AK |
2825 | cvmx_usb_complete(usb, pipe, |
2826 | transaction, | |
b186eb64 | 2827 | CVMX_USB_STATUS_OK); |
6570b4a9 AK |
2828 | } else { |
2829 | /* | |
2830 | * Split transactions retry the split complete 4 times | |
2831 | * then rewind to the start split and do the entire | |
2832 | * transactions again | |
2833 | */ | |
2834 | transaction->retries++; | |
2835 | if ((transaction->retries & 0x3) == 0) { | |
2836 | /* | |
2837 | * Rewind to the beginning of the transaction by | |
2838 | * anding off the split complete bit | |
2839 | */ | |
2840 | transaction->stage &= ~1; | |
2841 | pipe->split_sc_frame = -1; | |
2842 | } | |
2843 | } | |
2844 | } else if (usbc_hcint.s.ack) { | |
2845 | transaction->retries = 0; | |
2846 | /* | |
2847 | * The ACK bit can only be checked after the other error bits. | |
2848 | * This is because a multi packet transfer may succeed in a | |
2849 | * number of packets and then get a different response on the | |
2850 | * last packet. In this case both ACK and the last response bit | |
2851 | * will be set. If none of the other response bits is set, then | |
2852 | * the last packet must have been an ACK | |
2853 | * | |
2854 | * Since we got an ACK, we know we don't need to do a ping on | |
2855 | * this pipe | |
2856 | */ | |
3f9697b7 | 2857 | pipe->flags &= ~CVMX_USB_PIPE_FLAGS_NEED_PING; |
6570b4a9 AK |
2858 | |
2859 | switch (transaction->type) { | |
2860 | case CVMX_USB_TRANSFER_CONTROL: | |
81a71bad AK |
2861 | cvmx_usb_transfer_control(usb, pipe, transaction, |
2862 | usbc_hcchar, | |
2863 | buffer_space_left, | |
2864 | bytes_in_last_packet); | |
6570b4a9 AK |
2865 | break; |
2866 | case CVMX_USB_TRANSFER_BULK: | |
8ed3094c AK |
2867 | cvmx_usb_transfer_bulk(usb, pipe, transaction, |
2868 | usbc_hcint, buffer_space_left, | |
2869 | bytes_in_last_packet); | |
2870 | break; | |
6570b4a9 | 2871 | case CVMX_USB_TRANSFER_INTERRUPT: |
dfce6267 AK |
2872 | cvmx_usb_transfer_intr(usb, pipe, transaction, |
2873 | buffer_space_left, | |
2874 | bytes_in_last_packet); | |
6570b4a9 AK |
2875 | break; |
2876 | case CVMX_USB_TRANSFER_ISOCHRONOUS: | |
dd588994 AK |
2877 | cvmx_usb_transfer_isoc(usb, pipe, transaction, |
2878 | buffer_space_left, | |
2879 | bytes_in_last_packet, | |
2880 | bytes_this_transfer); | |
6570b4a9 AK |
2881 | break; |
2882 | } | |
2883 | } else if (usbc_hcint.s.nak) { | |
2884 | /* | |
2885 | * If this was a split then clear our split in progress marker. | |
2886 | */ | |
2887 | if (usb->active_split == transaction) | |
2888 | usb->active_split = NULL; | |
2889 | /* | |
2890 | * NAK as a response means the device couldn't accept the | |
2891 | * transaction, but it should be retried in the future. Rewind | |
2892 | * to the beginning of the transaction by anding off the split | |
2893 | * complete bit. Retry in the next interval | |
2894 | */ | |
2895 | transaction->retries = 0; | |
2896 | transaction->stage &= ~1; | |
2897 | pipe->next_tx_frame += pipe->interval; | |
2898 | if (pipe->next_tx_frame < usb->frame_number) | |
1da69aa9 RO |
2899 | pipe->next_tx_frame = usb->frame_number + |
2900 | pipe->interval - | |
2901 | (usb->frame_number - pipe->next_tx_frame) % | |
2902 | pipe->interval; | |
6570b4a9 AK |
2903 | } else { |
2904 | struct cvmx_usb_port_status port; | |
f5106435 | 2905 | |
cb61c600 | 2906 | port = cvmx_usb_get_status(usb); |
6570b4a9 AK |
2907 | if (port.port_enabled) { |
2908 | /* We'll retry the exact same transaction again */ | |
2909 | transaction->retries++; | |
2910 | } else { | |
2911 | /* | |
2912 | * We get channel halted interrupts with no result bits | |
2913 | * sets when the cable is unplugged | |
2914 | */ | |
e6bff5a0 AK |
2915 | cvmx_usb_complete(usb, pipe, transaction, |
2916 | CVMX_USB_STATUS_ERROR); | |
6570b4a9 AK |
2917 | } |
2918 | } | |
2919 | return 0; | |
2920 | } | |
2921 | ||
8b07d2fe | 2922 | static void octeon_usb_port_callback(struct octeon_hcd *usb) |
393e2146 | 2923 | { |
8b07d2fe AK |
2924 | spin_unlock(&usb->lock); |
2925 | usb_hcd_poll_rh_status(octeon_to_hcd(usb)); | |
2926 | spin_lock(&usb->lock); | |
393e2146 | 2927 | } |
6570b4a9 AK |
2928 | |
2929 | /** | |
2930 | * Poll the USB block for status and call all needed callback | |
2931 | * handlers. This function is meant to be called in the interrupt | |
2932 | * handler for the USB controller. It can also be called | |
2933 | * periodically in a loop for non-interrupt based operation. | |
2934 | * | |
cb61c600 | 2935 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
2936 | * |
2937 | * Returns: 0 or a negative error code. | |
2938 | */ | |
8b07d2fe | 2939 | static int cvmx_usb_poll(struct octeon_hcd *usb) |
6570b4a9 AK |
2940 | { |
2941 | union cvmx_usbcx_hfnum usbc_hfnum; | |
2942 | union cvmx_usbcx_gintsts usbc_gintsts; | |
6570b4a9 | 2943 | |
20f6b829 | 2944 | prefetch_range(usb, sizeof(*usb)); |
6570b4a9 AK |
2945 | |
2946 | /* Update the frame counter */ | |
68d435dd | 2947 | usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index)); |
3c98ef90 | 2948 | if ((usb->frame_number & 0x3fff) > usbc_hfnum.s.frnum) |
6570b4a9 AK |
2949 | usb->frame_number += 0x4000; |
2950 | usb->frame_number &= ~0x3fffull; | |
2951 | usb->frame_number |= usbc_hfnum.s.frnum; | |
2952 | ||
2953 | /* Read the pending interrupts */ | |
68d435dd AK |
2954 | usbc_gintsts.u32 = cvmx_usb_read_csr32(usb, |
2955 | CVMX_USBCX_GINTSTS(usb->index)); | |
6570b4a9 AK |
2956 | |
2957 | /* Clear the interrupts now that we know about them */ | |
68d435dd AK |
2958 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), |
2959 | usbc_gintsts.u32); | |
6570b4a9 AK |
2960 | |
2961 | if (usbc_gintsts.s.rxflvl) { | |
2962 | /* | |
2963 | * RxFIFO Non-Empty (RxFLvl) | |
2964 | * Indicates that there is at least one packet pending to be | |
2965 | * read from the RxFIFO. | |
2966 | * | |
2967 | * In DMA mode this is handled by hardware | |
2968 | */ | |
2969 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) | |
68d435dd | 2970 | cvmx_usb_poll_rx_fifo(usb); |
6570b4a9 AK |
2971 | } |
2972 | if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) { | |
2973 | /* Fill the Tx FIFOs when not in DMA mode */ | |
2974 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) | |
68d435dd | 2975 | cvmx_usb_poll_tx_fifo(usb); |
6570b4a9 AK |
2976 | } |
2977 | if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) { | |
2978 | union cvmx_usbcx_hprt usbc_hprt; | |
2979 | /* | |
2980 | * Disconnect Detected Interrupt (DisconnInt) | |
2981 | * Asserted when a device disconnect is detected. | |
2982 | * | |
2983 | * Host Port Interrupt (PrtInt) | |
2984 | * The core sets this bit to indicate a change in port status of | |
2985 | * one of the O2P USB core ports in Host mode. The application | |
2986 | * must read the Host Port Control and Status (HPRT) register to | |
2987 | * determine the exact event that caused this interrupt. The | |
2988 | * application must clear the appropriate status bit in the Host | |
2989 | * Port Control and Status register to clear this bit. | |
2990 | * | |
2991 | * Call the user's port callback | |
2992 | */ | |
393e2146 | 2993 | octeon_usb_port_callback(usb); |
6570b4a9 | 2994 | /* Clear the port change bits */ |
a00265de AK |
2995 | usbc_hprt.u32 = |
2996 | cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index)); | |
6570b4a9 | 2997 | usbc_hprt.s.prtena = 0; |
68d435dd AK |
2998 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), |
2999 | usbc_hprt.u32); | |
6570b4a9 AK |
3000 | } |
3001 | if (usbc_gintsts.s.hchint) { | |
3002 | /* | |
3003 | * Host Channels Interrupt (HChInt) | |
3004 | * The core sets this bit to indicate that an interrupt is | |
3005 | * pending on one of the channels of the core (in Host mode). | |
3006 | * The application must read the Host All Channels Interrupt | |
3007 | * (HAINT) register to determine the exact number of the channel | |
3008 | * on which the interrupt occurred, and then read the | |
3009 | * corresponding Host Channel-n Interrupt (HCINTn) register to | |
3010 | * determine the exact cause of the interrupt. The application | |
3011 | * must clear the appropriate status bit in the HCINTn register | |
3012 | * to clear this bit. | |
3013 | */ | |
3014 | union cvmx_usbcx_haint usbc_haint; | |
f5106435 | 3015 | |
68d435dd | 3016 | usbc_haint.u32 = cvmx_usb_read_csr32(usb, |
e725cef3 | 3017 | CVMX_USBCX_HAINT(usb->index)); |
6570b4a9 AK |
3018 | while (usbc_haint.u32) { |
3019 | int channel; | |
3020 | ||
3021 | channel = __fls(usbc_haint.u32); | |
68d435dd | 3022 | cvmx_usb_poll_channel(usb, channel); |
3c98ef90 | 3023 | usbc_haint.u32 ^= 1 << channel; |
6570b4a9 AK |
3024 | } |
3025 | } | |
3026 | ||
68d435dd | 3027 | cvmx_usb_schedule(usb, usbc_gintsts.s.sof); |
6570b4a9 AK |
3028 | |
3029 | return 0; | |
3030 | } | |
3031 | ||
b164935b AK |
3032 | /* convert between an HCD pointer and the corresponding struct octeon_hcd */ |
3033 | static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd) | |
3034 | { | |
3035 | return (struct octeon_hcd *)(hcd->hcd_priv); | |
3036 | } | |
3037 | ||
b164935b AK |
3038 | static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd) |
3039 | { | |
8b07d2fe | 3040 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
771378bb | 3041 | unsigned long flags; |
71e06db3 | 3042 | |
8b07d2fe AK |
3043 | spin_lock_irqsave(&usb->lock, flags); |
3044 | cvmx_usb_poll(usb); | |
3045 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb | 3046 | return IRQ_HANDLED; |
b164935b AK |
3047 | } |
3048 | ||
b164935b AK |
3049 | static int octeon_usb_start(struct usb_hcd *hcd) |
3050 | { | |
771378bb | 3051 | hcd->state = HC_STATE_RUNNING; |
771378bb | 3052 | return 0; |
b164935b AK |
3053 | } |
3054 | ||
3055 | static void octeon_usb_stop(struct usb_hcd *hcd) | |
3056 | { | |
771378bb | 3057 | hcd->state = HC_STATE_HALT; |
b164935b AK |
3058 | } |
3059 | ||
3060 | static int octeon_usb_get_frame_number(struct usb_hcd *hcd) | |
3061 | { | |
8b07d2fe | 3062 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
71e06db3 | 3063 | |
8b07d2fe | 3064 | return cvmx_usb_get_frame_number(usb); |
b164935b AK |
3065 | } |
3066 | ||
b164935b | 3067 | static int octeon_usb_urb_enqueue(struct usb_hcd *hcd, |
771378bb AK |
3068 | struct urb *urb, |
3069 | gfp_t mem_flags) | |
b164935b | 3070 | { |
8b07d2fe | 3071 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
71e06db3 | 3072 | struct device *dev = hcd->self.controller; |
3e1674c0 | 3073 | struct cvmx_usb_transaction *transaction = NULL; |
60f81507 | 3074 | struct cvmx_usb_pipe *pipe; |
771378bb | 3075 | unsigned long flags; |
6e0e1b00 | 3076 | struct cvmx_usb_iso_packet *iso_packet; |
771378bb | 3077 | struct usb_host_endpoint *ep = urb->ep; |
e5b90898 | 3078 | int rc; |
771378bb | 3079 | |
771378bb | 3080 | urb->status = 0; |
8b07d2fe | 3081 | spin_lock_irqsave(&usb->lock, flags); |
771378bb | 3082 | |
e5b90898 AK |
3083 | rc = usb_hcd_link_urb_to_ep(hcd, urb); |
3084 | if (rc) { | |
8b07d2fe | 3085 | spin_unlock_irqrestore(&usb->lock, flags); |
e5b90898 AK |
3086 | return rc; |
3087 | } | |
3088 | ||
771378bb | 3089 | if (!ep->hcpriv) { |
394d4e08 | 3090 | enum cvmx_usb_transfer transfer_type; |
4918072e | 3091 | enum cvmx_usb_speed speed; |
771378bb AK |
3092 | int split_device = 0; |
3093 | int split_port = 0; | |
f5106435 | 3094 | |
771378bb AK |
3095 | switch (usb_pipetype(urb->pipe)) { |
3096 | case PIPE_ISOCHRONOUS: | |
3097 | transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS; | |
3098 | break; | |
3099 | case PIPE_INTERRUPT: | |
3100 | transfer_type = CVMX_USB_TRANSFER_INTERRUPT; | |
3101 | break; | |
3102 | case PIPE_CONTROL: | |
3103 | transfer_type = CVMX_USB_TRANSFER_CONTROL; | |
3104 | break; | |
3105 | default: | |
3106 | transfer_type = CVMX_USB_TRANSFER_BULK; | |
3107 | break; | |
3108 | } | |
3109 | switch (urb->dev->speed) { | |
3110 | case USB_SPEED_LOW: | |
3111 | speed = CVMX_USB_SPEED_LOW; | |
3112 | break; | |
3113 | case USB_SPEED_FULL: | |
3114 | speed = CVMX_USB_SPEED_FULL; | |
3115 | break; | |
3116 | default: | |
3117 | speed = CVMX_USB_SPEED_HIGH; | |
3118 | break; | |
3119 | } | |
87e7e57a AK |
3120 | /* |
3121 | * For slow devices on high speed ports we need to find the hub | |
3122 | * that does the speed translation so we know where to send the | |
3123 | * split transactions. | |
3124 | */ | |
771378bb | 3125 | if (speed != CVMX_USB_SPEED_HIGH) { |
87e7e57a AK |
3126 | /* |
3127 | * Start at this device and work our way up the usb | |
3128 | * tree. | |
3129 | */ | |
771378bb | 3130 | struct usb_device *dev = urb->dev; |
f5106435 | 3131 | |
771378bb | 3132 | while (dev->parent) { |
87e7e57a AK |
3133 | /* |
3134 | * If our parent is high speed then he'll | |
3135 | * receive the splits. | |
3136 | */ | |
771378bb AK |
3137 | if (dev->parent->speed == USB_SPEED_HIGH) { |
3138 | split_device = dev->parent->devnum; | |
3139 | split_port = dev->portnum; | |
3140 | break; | |
3141 | } | |
87e7e57a AK |
3142 | /* |
3143 | * Move up the tree one level. If we make it all | |
3144 | * the way up the tree, then the port must not | |
3145 | * be in high speed mode and we don't need a | |
3146 | * split. | |
3147 | */ | |
771378bb AK |
3148 | dev = dev->parent; |
3149 | } | |
3150 | } | |
8b07d2fe | 3151 | pipe = cvmx_usb_open_pipe(usb, usb_pipedevice(urb->pipe), |
60f81507 | 3152 | usb_pipeendpoint(urb->pipe), speed, |
1da69aa9 RO |
3153 | le16_to_cpu(ep->desc.wMaxPacketSize) |
3154 | & 0x7ff, | |
60f81507 AK |
3155 | transfer_type, |
3156 | usb_pipein(urb->pipe) ? | |
3157 | CVMX_USB_DIRECTION_IN : | |
3158 | CVMX_USB_DIRECTION_OUT, | |
3159 | urb->interval, | |
1da69aa9 RO |
3160 | (le16_to_cpu(ep->desc.wMaxPacketSize) |
3161 | >> 11) & 0x3, | |
60f81507 AK |
3162 | split_device, split_port); |
3163 | if (!pipe) { | |
e5b90898 | 3164 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8b07d2fe | 3165 | spin_unlock_irqrestore(&usb->lock, flags); |
71e06db3 | 3166 | dev_dbg(dev, "Failed to create pipe\n"); |
771378bb AK |
3167 | return -ENOMEM; |
3168 | } | |
60f81507 | 3169 | ep->hcpriv = pipe; |
c7609eac | 3170 | } else { |
60f81507 | 3171 | pipe = ep->hcpriv; |
c7609eac | 3172 | } |
771378bb AK |
3173 | |
3174 | switch (usb_pipetype(urb->pipe)) { | |
3175 | case PIPE_ISOCHRONOUS: | |
71e06db3 | 3176 | dev_dbg(dev, "Submit isochronous to %d.%d\n", |
1da69aa9 RO |
3177 | usb_pipedevice(urb->pipe), |
3178 | usb_pipeendpoint(urb->pipe)); | |
87e7e57a AK |
3179 | /* |
3180 | * Allocate a structure to use for our private list of | |
3181 | * isochronous packets. | |
3182 | */ | |
73eee567 CM |
3183 | iso_packet = kmalloc_array(urb->number_of_packets, |
3184 | sizeof(struct cvmx_usb_iso_packet), | |
3185 | GFP_ATOMIC); | |
771378bb AK |
3186 | if (iso_packet) { |
3187 | int i; | |
3188 | /* Fill the list with the data from the URB */ | |
3189 | for (i = 0; i < urb->number_of_packets; i++) { | |
1da69aa9 RO |
3190 | iso_packet[i].offset = |
3191 | urb->iso_frame_desc[i].offset; | |
3192 | iso_packet[i].length = | |
3193 | urb->iso_frame_desc[i].length; | |
add3ea32 | 3194 | iso_packet[i].status = CVMX_USB_STATUS_ERROR; |
771378bb | 3195 | } |
87e7e57a AK |
3196 | /* |
3197 | * Store a pointer to the list in the URB setup_packet | |
3198 | * field. We know this currently isn't being used and | |
3199 | * this saves us a bunch of logic. | |
3200 | */ | |
771378bb | 3201 | urb->setup_packet = (char *)iso_packet; |
8b07d2fe | 3202 | transaction = cvmx_usb_submit_isochronous(usb, |
3e1674c0 | 3203 | pipe, urb); |
87e7e57a AK |
3204 | /* |
3205 | * If submit failed we need to free our private packet | |
3206 | * list. | |
3207 | */ | |
3e1674c0 | 3208 | if (!transaction) { |
771378bb AK |
3209 | urb->setup_packet = NULL; |
3210 | kfree(iso_packet); | |
3211 | } | |
3212 | } | |
3213 | break; | |
3214 | case PIPE_INTERRUPT: | |
71e06db3 | 3215 | dev_dbg(dev, "Submit interrupt to %d.%d\n", |
1da69aa9 RO |
3216 | usb_pipedevice(urb->pipe), |
3217 | usb_pipeendpoint(urb->pipe)); | |
8b07d2fe | 3218 | transaction = cvmx_usb_submit_interrupt(usb, pipe, urb); |
771378bb AK |
3219 | break; |
3220 | case PIPE_CONTROL: | |
71e06db3 | 3221 | dev_dbg(dev, "Submit control to %d.%d\n", |
1da69aa9 RO |
3222 | usb_pipedevice(urb->pipe), |
3223 | usb_pipeendpoint(urb->pipe)); | |
8b07d2fe | 3224 | transaction = cvmx_usb_submit_control(usb, pipe, urb); |
771378bb AK |
3225 | break; |
3226 | case PIPE_BULK: | |
71e06db3 | 3227 | dev_dbg(dev, "Submit bulk to %d.%d\n", |
1da69aa9 RO |
3228 | usb_pipedevice(urb->pipe), |
3229 | usb_pipeendpoint(urb->pipe)); | |
8b07d2fe | 3230 | transaction = cvmx_usb_submit_bulk(usb, pipe, urb); |
771378bb AK |
3231 | break; |
3232 | } | |
3e1674c0 | 3233 | if (!transaction) { |
e5b90898 | 3234 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8b07d2fe | 3235 | spin_unlock_irqrestore(&usb->lock, flags); |
71e06db3 | 3236 | dev_dbg(dev, "Failed to submit\n"); |
771378bb AK |
3237 | return -ENOMEM; |
3238 | } | |
3e1674c0 | 3239 | urb->hcpriv = transaction; |
8b07d2fe | 3240 | spin_unlock_irqrestore(&usb->lock, flags); |
771378bb | 3241 | return 0; |
b164935b AK |
3242 | } |
3243 | ||
1da69aa9 RO |
3244 | static int octeon_usb_urb_dequeue(struct usb_hcd *hcd, |
3245 | struct urb *urb, | |
3246 | int status) | |
b164935b | 3247 | { |
8b07d2fe | 3248 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
771378bb | 3249 | unsigned long flags; |
e5b90898 | 3250 | int rc; |
b164935b | 3251 | |
771378bb AK |
3252 | if (!urb->dev) |
3253 | return -EINVAL; | |
b164935b | 3254 | |
8b07d2fe | 3255 | spin_lock_irqsave(&usb->lock, flags); |
b164935b | 3256 | |
e5b90898 AK |
3257 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
3258 | if (rc) | |
3259 | goto out; | |
3260 | ||
771378bb | 3261 | urb->status = status; |
8b07d2fe | 3262 | cvmx_usb_cancel(usb, urb->ep->hcpriv, urb->hcpriv); |
b164935b | 3263 | |
e5b90898 | 3264 | out: |
8b07d2fe | 3265 | spin_unlock_irqrestore(&usb->lock, flags); |
b164935b | 3266 | |
e5b90898 | 3267 | return rc; |
b164935b AK |
3268 | } |
3269 | ||
1da69aa9 RO |
3270 | static void octeon_usb_endpoint_disable(struct usb_hcd *hcd, |
3271 | struct usb_host_endpoint *ep) | |
b164935b | 3272 | { |
71e06db3 AK |
3273 | struct device *dev = hcd->self.controller; |
3274 | ||
771378bb | 3275 | if (ep->hcpriv) { |
8b07d2fe | 3276 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
60f81507 | 3277 | struct cvmx_usb_pipe *pipe = ep->hcpriv; |
771378bb | 3278 | unsigned long flags; |
f5106435 | 3279 | |
8b07d2fe AK |
3280 | spin_lock_irqsave(&usb->lock, flags); |
3281 | cvmx_usb_cancel_all(usb, pipe); | |
3282 | if (cvmx_usb_close_pipe(usb, pipe)) | |
60f81507 | 3283 | dev_dbg(dev, "Closing pipe %p failed\n", pipe); |
8b07d2fe | 3284 | spin_unlock_irqrestore(&usb->lock, flags); |
771378bb AK |
3285 | ep->hcpriv = NULL; |
3286 | } | |
b164935b AK |
3287 | } |
3288 | ||
3289 | static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf) | |
3290 | { | |
8b07d2fe | 3291 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
51a19621 | 3292 | struct cvmx_usb_port_status port_status; |
771378bb | 3293 | unsigned long flags; |
b164935b | 3294 | |
8b07d2fe AK |
3295 | spin_lock_irqsave(&usb->lock, flags); |
3296 | port_status = cvmx_usb_get_status(usb); | |
3297 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb | 3298 | buf[0] = port_status.connect_change << 1; |
b164935b | 3299 | |
8522851e | 3300 | return buf[0] != 0; |
b164935b AK |
3301 | } |
3302 | ||
e725cef3 | 3303 | static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
68ea3380 | 3304 | u16 wIndex, char *buf, u16 wLength) |
b164935b | 3305 | { |
8b07d2fe | 3306 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
71e06db3 | 3307 | struct device *dev = hcd->self.controller; |
51a19621 | 3308 | struct cvmx_usb_port_status usb_port_status; |
771378bb AK |
3309 | int port_status; |
3310 | struct usb_hub_descriptor *desc; | |
3311 | unsigned long flags; | |
3312 | ||
3313 | switch (typeReq) { | |
3314 | case ClearHubFeature: | |
71e06db3 | 3315 | dev_dbg(dev, "ClearHubFeature\n"); |
771378bb AK |
3316 | switch (wValue) { |
3317 | case C_HUB_LOCAL_POWER: | |
3318 | case C_HUB_OVER_CURRENT: | |
3319 | /* Nothing required here */ | |
3320 | break; | |
3321 | default: | |
3322 | return -EINVAL; | |
3323 | } | |
3324 | break; | |
3325 | case ClearPortFeature: | |
71e06db3 | 3326 | dev_dbg(dev, "ClearPortFeature\n"); |
771378bb | 3327 | if (wIndex != 1) { |
71e06db3 | 3328 | dev_dbg(dev, " INVALID\n"); |
771378bb AK |
3329 | return -EINVAL; |
3330 | } | |
3331 | ||
3332 | switch (wValue) { | |
3333 | case USB_PORT_FEAT_ENABLE: | |
71e06db3 | 3334 | dev_dbg(dev, " ENABLE\n"); |
8b07d2fe AK |
3335 | spin_lock_irqsave(&usb->lock, flags); |
3336 | cvmx_usb_disable(usb); | |
3337 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb AK |
3338 | break; |
3339 | case USB_PORT_FEAT_SUSPEND: | |
71e06db3 | 3340 | dev_dbg(dev, " SUSPEND\n"); |
771378bb AK |
3341 | /* Not supported on Octeon */ |
3342 | break; | |
3343 | case USB_PORT_FEAT_POWER: | |
71e06db3 | 3344 | dev_dbg(dev, " POWER\n"); |
771378bb AK |
3345 | /* Not supported on Octeon */ |
3346 | break; | |
3347 | case USB_PORT_FEAT_INDICATOR: | |
71e06db3 | 3348 | dev_dbg(dev, " INDICATOR\n"); |
771378bb AK |
3349 | /* Port inidicator not supported */ |
3350 | break; | |
3351 | case USB_PORT_FEAT_C_CONNECTION: | |
71e06db3 | 3352 | dev_dbg(dev, " C_CONNECTION\n"); |
771378bb | 3353 | /* Clears drivers internal connect status change flag */ |
8b07d2fe AK |
3354 | spin_lock_irqsave(&usb->lock, flags); |
3355 | usb->port_status = cvmx_usb_get_status(usb); | |
3356 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb AK |
3357 | break; |
3358 | case USB_PORT_FEAT_C_RESET: | |
71e06db3 | 3359 | dev_dbg(dev, " C_RESET\n"); |
87e7e57a AK |
3360 | /* |
3361 | * Clears the driver's internal Port Reset Change flag. | |
3362 | */ | |
8b07d2fe AK |
3363 | spin_lock_irqsave(&usb->lock, flags); |
3364 | usb->port_status = cvmx_usb_get_status(usb); | |
3365 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb AK |
3366 | break; |
3367 | case USB_PORT_FEAT_C_ENABLE: | |
71e06db3 | 3368 | dev_dbg(dev, " C_ENABLE\n"); |
87e7e57a AK |
3369 | /* |
3370 | * Clears the driver's internal Port Enable/Disable | |
3371 | * Change flag. | |
3372 | */ | |
8b07d2fe AK |
3373 | spin_lock_irqsave(&usb->lock, flags); |
3374 | usb->port_status = cvmx_usb_get_status(usb); | |
3375 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb AK |
3376 | break; |
3377 | case USB_PORT_FEAT_C_SUSPEND: | |
71e06db3 | 3378 | dev_dbg(dev, " C_SUSPEND\n"); |
87e7e57a AK |
3379 | /* |
3380 | * Clears the driver's internal Port Suspend Change | |
3381 | * flag, which is set when resume signaling on the host | |
3382 | * port is complete. | |
3383 | */ | |
771378bb AK |
3384 | break; |
3385 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
71e06db3 | 3386 | dev_dbg(dev, " C_OVER_CURRENT\n"); |
771378bb | 3387 | /* Clears the driver's overcurrent Change flag */ |
8b07d2fe AK |
3388 | spin_lock_irqsave(&usb->lock, flags); |
3389 | usb->port_status = cvmx_usb_get_status(usb); | |
3390 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb AK |
3391 | break; |
3392 | default: | |
71e06db3 | 3393 | dev_dbg(dev, " UNKNOWN\n"); |
771378bb AK |
3394 | return -EINVAL; |
3395 | } | |
771378bb AK |
3396 | break; |
3397 | case GetHubDescriptor: | |
71e06db3 | 3398 | dev_dbg(dev, "GetHubDescriptor\n"); |
771378bb AK |
3399 | desc = (struct usb_hub_descriptor *)buf; |
3400 | desc->bDescLength = 9; | |
3401 | desc->bDescriptorType = 0x29; | |
3402 | desc->bNbrPorts = 1; | |
e5873388 | 3403 | desc->wHubCharacteristics = cpu_to_le16(0x08); |
771378bb AK |
3404 | desc->bPwrOn2PwrGood = 1; |
3405 | desc->bHubContrCurrent = 0; | |
3406 | desc->u.hs.DeviceRemovable[0] = 0; | |
3407 | desc->u.hs.DeviceRemovable[1] = 0xff; | |
3408 | break; | |
3409 | case GetHubStatus: | |
71e06db3 | 3410 | dev_dbg(dev, "GetHubStatus\n"); |
ec7c4d7d | 3411 | *(__le32 *)buf = 0; |
771378bb AK |
3412 | break; |
3413 | case GetPortStatus: | |
71e06db3 | 3414 | dev_dbg(dev, "GetPortStatus\n"); |
771378bb | 3415 | if (wIndex != 1) { |
71e06db3 | 3416 | dev_dbg(dev, " INVALID\n"); |
771378bb AK |
3417 | return -EINVAL; |
3418 | } | |
3419 | ||
8b07d2fe AK |
3420 | spin_lock_irqsave(&usb->lock, flags); |
3421 | usb_port_status = cvmx_usb_get_status(usb); | |
3422 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb AK |
3423 | port_status = 0; |
3424 | ||
3425 | if (usb_port_status.connect_change) { | |
3426 | port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); | |
71e06db3 | 3427 | dev_dbg(dev, " C_CONNECTION\n"); |
771378bb AK |
3428 | } |
3429 | ||
3430 | if (usb_port_status.port_enabled) { | |
3431 | port_status |= (1 << USB_PORT_FEAT_C_ENABLE); | |
71e06db3 | 3432 | dev_dbg(dev, " C_ENABLE\n"); |
771378bb AK |
3433 | } |
3434 | ||
3435 | if (usb_port_status.connected) { | |
3436 | port_status |= (1 << USB_PORT_FEAT_CONNECTION); | |
71e06db3 | 3437 | dev_dbg(dev, " CONNECTION\n"); |
771378bb AK |
3438 | } |
3439 | ||
3440 | if (usb_port_status.port_enabled) { | |
3441 | port_status |= (1 << USB_PORT_FEAT_ENABLE); | |
71e06db3 | 3442 | dev_dbg(dev, " ENABLE\n"); |
771378bb AK |
3443 | } |
3444 | ||
3445 | if (usb_port_status.port_over_current) { | |
3446 | port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); | |
71e06db3 | 3447 | dev_dbg(dev, " OVER_CURRENT\n"); |
771378bb AK |
3448 | } |
3449 | ||
3450 | if (usb_port_status.port_powered) { | |
3451 | port_status |= (1 << USB_PORT_FEAT_POWER); | |
71e06db3 | 3452 | dev_dbg(dev, " POWER\n"); |
771378bb AK |
3453 | } |
3454 | ||
3455 | if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) { | |
3456 | port_status |= USB_PORT_STAT_HIGH_SPEED; | |
71e06db3 | 3457 | dev_dbg(dev, " HIGHSPEED\n"); |
771378bb AK |
3458 | } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) { |
3459 | port_status |= (1 << USB_PORT_FEAT_LOWSPEED); | |
71e06db3 | 3460 | dev_dbg(dev, " LOWSPEED\n"); |
771378bb AK |
3461 | } |
3462 | ||
ec7c4d7d | 3463 | *((__le32 *)buf) = cpu_to_le32(port_status); |
771378bb AK |
3464 | break; |
3465 | case SetHubFeature: | |
71e06db3 | 3466 | dev_dbg(dev, "SetHubFeature\n"); |
771378bb AK |
3467 | /* No HUB features supported */ |
3468 | break; | |
3469 | case SetPortFeature: | |
71e06db3 | 3470 | dev_dbg(dev, "SetPortFeature\n"); |
771378bb | 3471 | if (wIndex != 1) { |
71e06db3 | 3472 | dev_dbg(dev, " INVALID\n"); |
771378bb AK |
3473 | return -EINVAL; |
3474 | } | |
3475 | ||
3476 | switch (wValue) { | |
3477 | case USB_PORT_FEAT_SUSPEND: | |
71e06db3 | 3478 | dev_dbg(dev, " SUSPEND\n"); |
771378bb AK |
3479 | return -EINVAL; |
3480 | case USB_PORT_FEAT_POWER: | |
71e06db3 | 3481 | dev_dbg(dev, " POWER\n"); |
0ed64a4c AK |
3482 | /* |
3483 | * Program the port power bit to drive VBUS on the USB. | |
3484 | */ | |
8b07d2fe | 3485 | spin_lock_irqsave(&usb->lock, flags); |
0ed64a4c | 3486 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), |
6068e818 | 3487 | cvmx_usbcx_hprt, prtpwr, 1); |
8b07d2fe | 3488 | spin_unlock_irqrestore(&usb->lock, flags); |
0ed64a4c | 3489 | return 0; |
771378bb | 3490 | case USB_PORT_FEAT_RESET: |
71e06db3 | 3491 | dev_dbg(dev, " RESET\n"); |
8b07d2fe AK |
3492 | spin_lock_irqsave(&usb->lock, flags); |
3493 | cvmx_usb_reset_port(usb); | |
3494 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb AK |
3495 | return 0; |
3496 | case USB_PORT_FEAT_INDICATOR: | |
71e06db3 | 3497 | dev_dbg(dev, " INDICATOR\n"); |
771378bb AK |
3498 | /* Not supported */ |
3499 | break; | |
3500 | default: | |
71e06db3 | 3501 | dev_dbg(dev, " UNKNOWN\n"); |
771378bb AK |
3502 | return -EINVAL; |
3503 | } | |
3504 | break; | |
3505 | default: | |
71e06db3 | 3506 | dev_dbg(dev, "Unknown root hub request\n"); |
771378bb AK |
3507 | return -EINVAL; |
3508 | } | |
3509 | return 0; | |
b164935b AK |
3510 | } |
3511 | ||
b164935b | 3512 | static const struct hc_driver octeon_hc_driver = { |
771378bb AK |
3513 | .description = "Octeon USB", |
3514 | .product_desc = "Octeon Host Controller", | |
3515 | .hcd_priv_size = sizeof(struct octeon_hcd), | |
3516 | .irq = octeon_usb_irq, | |
3517 | .flags = HCD_MEMORY | HCD_USB2, | |
3518 | .start = octeon_usb_start, | |
3519 | .stop = octeon_usb_stop, | |
3520 | .urb_enqueue = octeon_usb_urb_enqueue, | |
3521 | .urb_dequeue = octeon_usb_urb_dequeue, | |
3522 | .endpoint_disable = octeon_usb_endpoint_disable, | |
3523 | .get_frame_number = octeon_usb_get_frame_number, | |
3524 | .hub_status_data = octeon_usb_hub_status_data, | |
3525 | .hub_control = octeon_usb_hub_control, | |
120ee599 AK |
3526 | .map_urb_for_dma = octeon_map_urb_for_dma, |
3527 | .unmap_urb_for_dma = octeon_unmap_urb_for_dma, | |
b164935b AK |
3528 | }; |
3529 | ||
b91619c2 | 3530 | static int octeon_usb_probe(struct platform_device *pdev) |
b164935b | 3531 | { |
771378bb | 3532 | int status; |
b91619c2 DD |
3533 | int initialize_flags; |
3534 | int usb_num; | |
3535 | struct resource *res_mem; | |
3536 | struct device_node *usbn_node; | |
3537 | int irq = platform_get_irq(pdev, 0); | |
3538 | struct device *dev = &pdev->dev; | |
8b07d2fe | 3539 | struct octeon_hcd *usb; |
771378bb | 3540 | struct usb_hcd *hcd; |
b91619c2 DD |
3541 | u32 clock_rate = 48000000; |
3542 | bool is_crystal_clock = false; | |
3543 | const char *clock_type; | |
3544 | int i; | |
3545 | ||
a2fcca42 | 3546 | if (!dev->of_node) { |
b91619c2 DD |
3547 | dev_err(dev, "Error: empty of_node\n"); |
3548 | return -ENXIO; | |
3549 | } | |
3550 | usbn_node = dev->of_node->parent; | |
3551 | ||
3552 | i = of_property_read_u32(usbn_node, | |
bb778553 AK |
3553 | "clock-frequency", &clock_rate); |
3554 | if (i) | |
3555 | i = of_property_read_u32(usbn_node, | |
3556 | "refclk-frequency", &clock_rate); | |
b91619c2 | 3557 | if (i) { |
bb778553 | 3558 | dev_err(dev, "No USBN \"clock-frequency\"\n"); |
b91619c2 DD |
3559 | return -ENXIO; |
3560 | } | |
3561 | switch (clock_rate) { | |
3562 | case 12000000: | |
3563 | initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ; | |
3564 | break; | |
3565 | case 24000000: | |
3566 | initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ; | |
3567 | break; | |
3568 | case 48000000: | |
3569 | initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ; | |
3570 | break; | |
3571 | default: | |
bb778553 | 3572 | dev_err(dev, "Illegal USBN \"clock-frequency\" %u\n", |
68ea3380 | 3573 | clock_rate); |
b91619c2 | 3574 | return -ENXIO; |
b91619c2 DD |
3575 | } |
3576 | ||
3577 | i = of_property_read_string(usbn_node, | |
bb778553 AK |
3578 | "cavium,refclk-type", &clock_type); |
3579 | if (i) | |
3580 | i = of_property_read_string(usbn_node, | |
3581 | "refclk-type", &clock_type); | |
b91619c2 DD |
3582 | |
3583 | if (!i && strcmp("crystal", clock_type) == 0) | |
3584 | is_crystal_clock = true; | |
3585 | ||
3586 | if (is_crystal_clock) | |
3587 | initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI; | |
3588 | else | |
3589 | initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND; | |
3590 | ||
3591 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
a2fcca42 | 3592 | if (!res_mem) { |
b91619c2 DD |
3593 | dev_err(dev, "found no memory resource\n"); |
3594 | return -ENXIO; | |
3595 | } | |
3596 | usb_num = (res_mem->start >> 44) & 1; | |
3597 | ||
3598 | if (irq < 0) { | |
3599 | /* Defective device tree, but we know how to fix it. */ | |
3600 | irq_hw_number_t hwirq = usb_num ? (1 << 6) + 17 : 56; | |
f5106435 | 3601 | |
b91619c2 DD |
3602 | irq = irq_create_mapping(NULL, hwirq); |
3603 | } | |
771378bb | 3604 | |
87e7e57a AK |
3605 | /* |
3606 | * Set the DMA mask to 64bits so we get buffers already translated for | |
3607 | * DMA. | |
3608 | */ | |
771378bb AK |
3609 | dev->coherent_dma_mask = ~0; |
3610 | dev->dma_mask = &dev->coherent_dma_mask; | |
3611 | ||
b91619c2 DD |
3612 | /* |
3613 | * Only cn52XX and cn56XX have DWC_OTG USB hardware and the | |
3614 | * IOB priority registers. Under heavy network load USB | |
3615 | * hardware can be starved by the IOB causing a crash. Give | |
3616 | * it a priority boost if it has been waiting more than 400 | |
3617 | * cycles to avoid this situation. | |
3618 | * | |
3619 | * Testing indicates that a cnt_val of 8192 is not sufficient, | |
3620 | * but no failures are seen with 4096. We choose a value of | |
3621 | * 400 to give a safety factor of 10. | |
3622 | */ | |
3623 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) { | |
3624 | union cvmx_iob_n2c_l2c_pri_cnt pri_cnt; | |
3625 | ||
3626 | pri_cnt.u64 = 0; | |
3627 | pri_cnt.s.cnt_enb = 1; | |
3628 | pri_cnt.s.cnt_val = 400; | |
3629 | cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64); | |
3630 | } | |
3631 | ||
771378bb AK |
3632 | hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev)); |
3633 | if (!hcd) { | |
71e06db3 | 3634 | dev_dbg(dev, "Failed to allocate memory for HCD\n"); |
771378bb AK |
3635 | return -1; |
3636 | } | |
3637 | hcd->uses_new_polling = 1; | |
8b07d2fe | 3638 | usb = (struct octeon_hcd *)hcd->hcd_priv; |
771378bb | 3639 | |
8b07d2fe | 3640 | spin_lock_init(&usb->lock); |
771378bb | 3641 | |
8b07d2fe | 3642 | usb->init_flags = initialize_flags; |
b5e79e6e AK |
3643 | |
3644 | /* Initialize the USB state structure */ | |
8b07d2fe AK |
3645 | usb->index = usb_num; |
3646 | INIT_LIST_HEAD(&usb->idle_pipes); | |
3647 | for (i = 0; i < ARRAY_SIZE(usb->active_pipes); i++) | |
3648 | INIT_LIST_HEAD(&usb->active_pipes[i]); | |
b5e79e6e AK |
3649 | |
3650 | /* Due to an errata, CN31XX doesn't support DMA */ | |
3651 | if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { | |
8b07d2fe | 3652 | usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA; |
b5e79e6e | 3653 | /* Only use one channel with non DMA */ |
8b07d2fe | 3654 | usb->idle_hardware_channels = 0x1; |
b5e79e6e AK |
3655 | } else if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) { |
3656 | /* CN5XXX have an errata with channel 3 */ | |
8b07d2fe | 3657 | usb->idle_hardware_channels = 0xf7; |
b5e79e6e | 3658 | } else { |
8b07d2fe | 3659 | usb->idle_hardware_channels = 0xff; |
b5e79e6e AK |
3660 | } |
3661 | ||
8b07d2fe | 3662 | status = cvmx_usb_initialize(dev, usb); |
771378bb | 3663 | if (status) { |
71e06db3 | 3664 | dev_dbg(dev, "USB initialization failed with %d\n", status); |
9bbf84e6 | 3665 | usb_put_hcd(hcd); |
771378bb AK |
3666 | return -1; |
3667 | } | |
3668 | ||
b91619c2 | 3669 | status = usb_add_hcd(hcd, irq, 0); |
771378bb | 3670 | if (status) { |
71e06db3 | 3671 | dev_dbg(dev, "USB add HCD failed with %d\n", status); |
9bbf84e6 | 3672 | usb_put_hcd(hcd); |
771378bb AK |
3673 | return -1; |
3674 | } | |
3c9740a1 | 3675 | device_wakeup_enable(hcd->self.controller); |
771378bb | 3676 | |
b91619c2 | 3677 | dev_info(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq); |
771378bb AK |
3678 | |
3679 | return 0; | |
b164935b AK |
3680 | } |
3681 | ||
b91619c2 | 3682 | static int octeon_usb_remove(struct platform_device *pdev) |
b164935b | 3683 | { |
771378bb | 3684 | int status; |
b91619c2 | 3685 | struct device *dev = &pdev->dev; |
771378bb | 3686 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
8b07d2fe | 3687 | struct octeon_hcd *usb = hcd_to_octeon(hcd); |
771378bb | 3688 | unsigned long flags; |
b164935b | 3689 | |
771378bb | 3690 | usb_remove_hcd(hcd); |
8b07d2fe AK |
3691 | spin_lock_irqsave(&usb->lock, flags); |
3692 | status = cvmx_usb_shutdown(usb); | |
3693 | spin_unlock_irqrestore(&usb->lock, flags); | |
771378bb | 3694 | if (status) |
71e06db3 | 3695 | dev_dbg(dev, "USB shutdown failed with %d\n", status); |
b164935b | 3696 | |
9bbf84e6 | 3697 | usb_put_hcd(hcd); |
b164935b | 3698 | |
771378bb | 3699 | return 0; |
b164935b AK |
3700 | } |
3701 | ||
87794575 | 3702 | static const struct of_device_id octeon_usb_match[] = { |
b91619c2 DD |
3703 | { |
3704 | .compatible = "cavium,octeon-5750-usbc", | |
3705 | }, | |
3706 | {}, | |
b164935b | 3707 | }; |
1972308b | 3708 | MODULE_DEVICE_TABLE(of, octeon_usb_match); |
b164935b | 3709 | |
b91619c2 DD |
3710 | static struct platform_driver octeon_usb_driver = { |
3711 | .driver = { | |
a89e28e3 | 3712 | .name = "octeon-hcd", |
b91619c2 DD |
3713 | .of_match_table = octeon_usb_match, |
3714 | }, | |
3715 | .probe = octeon_usb_probe, | |
3716 | .remove = octeon_usb_remove, | |
3717 | }; | |
b164935b | 3718 | |
b91619c2 | 3719 | static int __init octeon_usb_driver_init(void) |
b164935b | 3720 | { |
b91619c2 DD |
3721 | if (usb_disabled()) |
3722 | return 0; | |
771378bb | 3723 | |
b91619c2 | 3724 | return platform_driver_register(&octeon_usb_driver); |
b164935b | 3725 | } |
b91619c2 | 3726 | module_init(octeon_usb_driver_init); |
b164935b | 3727 | |
b91619c2 | 3728 | static void __exit octeon_usb_driver_exit(void) |
b164935b | 3729 | { |
b91619c2 DD |
3730 | if (usb_disabled()) |
3731 | return; | |
71e06db3 | 3732 | |
b91619c2 | 3733 | platform_driver_unregister(&octeon_usb_driver); |
b164935b | 3734 | } |
b91619c2 | 3735 | module_exit(octeon_usb_driver_exit); |
b164935b AK |
3736 | |
3737 | MODULE_LICENSE("GPL"); | |
b91619c2 DD |
3738 | MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>"); |
3739 | MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver."); |