projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-block.git] / drivers / staging / octeon / ethernet.c
CommitLineData
80ff0fd3
DD		 1/**********************************************************************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2007 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26**********************************************************************/
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
f6ed1b3b 32#include <linux/phy.h>
5a0e3ad6 33#include <linux/slab.h>
80ff0fd3
DD		 34
35#include <net/dst.h>
36
37#include <asm/octeon/octeon.h>
38
39#include "ethernet-defines.h"
a620c163 40#include "octeon-ethernet.h"
80ff0fd3
DD		 41#include "ethernet-mem.h"
42#include "ethernet-rx.h"
43#include "ethernet-tx.h"
f696a108 44#include "ethernet-mdio.h"
80ff0fd3 45#include "ethernet-util.h"
80ff0fd3
DD		 46
47#include "cvmx-pip.h"
48#include "cvmx-pko.h"
49#include "cvmx-fau.h"
50#include "cvmx-ipd.h"
51#include "cvmx-helper.h"
52
f696a108 53#include "cvmx-gmxx-defs.h"
80ff0fd3
DD		 54#include "cvmx-smix-defs.h"
55
56#if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \
57 && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS
58int num_packet_buffers = CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS;
59#else
60int num_packet_buffers = 1024;
61#endif
62module_param(num_packet_buffers, int, 0444);
63MODULE_PARM_DESC(num_packet_buffers, "\n"
64 "\tNumber of packet buffers to allocate and store in the\n"
65 "\tFPA. By default, 1024 packet buffers are used unless\n"
66 "\tCONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS is defined.");
67
68int pow_receive_group = 15;
69module_param(pow_receive_group, int, 0444);
70MODULE_PARM_DESC(pow_receive_group, "\n"
71 "\tPOW group to receive packets from. All ethernet hardware\n"
72 "\twill be configured to send incomming packets to this POW\n"
73 "\tgroup. Also any other software can submit packets to this\n"
74 "\tgroup for the kernel to process.");
75
76int pow_send_group = -1;
77module_param(pow_send_group, int, 0644);
78MODULE_PARM_DESC(pow_send_group, "\n"
79 "\tPOW group to send packets to other software on. This\n"
80 "\tcontrols the creation of the virtual device pow0.\n"
81 "\talways_use_pow also depends on this value.");
82
83int always_use_pow;
84module_param(always_use_pow, int, 0444);
85MODULE_PARM_DESC(always_use_pow, "\n"
86 "\tWhen set, always send to the pow group. This will cause\n"
87 "\tpackets sent to real ethernet devices to be sent to the\n"
88 "\tPOW group instead of the hardware. Unless some other\n"
89 "\tapplication changes the config, packets will still be\n"
90 "\treceived from the low level hardware. Use this option\n"
91 "\tto allow a CVMX app to intercept all packets from the\n"
92 "\tlinux kernel. You must specify pow_send_group along with\n"
93 "\tthis option.");
94
95char pow_send_list[128] = "";
96module_param_string(pow_send_list, pow_send_list, sizeof(pow_send_list), 0444);
97MODULE_PARM_DESC(pow_send_list, "\n"
98 "\tComma separated list of ethernet devices that should use the\n"
99 "\tPOW for transmit instead of the actual ethernet hardware. This\n"
100 "\tis a per port version of always_use_pow. always_use_pow takes\n"
101 "\tprecedence over this list. For example, setting this to\n"
102 "\t\"eth2,spi3,spi7\" would cause these three devices to transmit\n"
103 "\tusing the pow_send_group.");
104
3368c784
DD		 105int max_rx_cpus = -1;
106module_param(max_rx_cpus, int, 0444);
107MODULE_PARM_DESC(max_rx_cpus, "\n"
108 "\t\tThe maximum number of CPUs to use for packet reception.\n"
109 "\t\tUse -1 to use all available CPUs.");
80ff0fd3 110
3368c784
DD		 111int rx_napi_weight = 32;
112module_param(rx_napi_weight, int, 0444);
113MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter.");
13c5939e
DD		 114
115/*
116 * The offset from mac_addr_base that should be used for the next port
117 * that is configured. By convention, if any mgmt ports exist on the
118 * chip, they get the first mac addresses, The ports controlled by
119 * this driver are numbered sequencially following any mgmt addresses
120 * that may exist.
121 */
122static unsigned int cvm_oct_mac_addr_offset;
123
80ff0fd3 124/**
f8c26486 125 * cvm_oct_poll_queue - Workqueue for polling operations.
80ff0fd3 126 */
f8c26486
DD		 127struct workqueue_struct *cvm_oct_poll_queue;
128
129/**
130 * cvm_oct_poll_queue_stopping - flag to indicate polling should stop.
131 *
132 * Set to one right before cvm_oct_poll_queue is destroyed.
80ff0fd3 133 */
f8c26486 134atomic_t cvm_oct_poll_queue_stopping = ATOMIC_INIT(0);
80ff0fd3
DD		 135
136/**
137 * Array of every ethernet device owned by this driver indexed by
138 * the ipd input port number.
139 */
140struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS];
141
4898c560
DD		 142u64 cvm_oct_tx_poll_interval;
143
f8c26486
DD		 144static void cvm_oct_rx_refill_worker(struct work_struct *work);
145static DECLARE_DELAYED_WORK(cvm_oct_rx_refill_work, cvm_oct_rx_refill_worker);
146
147static void cvm_oct_rx_refill_worker(struct work_struct *work)
80ff0fd3 148{
f8c26486
DD		 149 /*
150 * FPA 0 may have been drained, try to refill it if we need
151 * more than num_packet_buffers / 2, otherwise normal receive
152 * processing will refill it. If it were drained, no packets
153 * could be received so cvm_oct_napi_poll would never be
154 * invoked to do the refill.
155 */
156 cvm_oct_rx_refill_pool(num_packet_buffers / 2);
a620c163 157
f8c26486
DD		 158 if (!atomic_read(&cvm_oct_poll_queue_stopping))
159 queue_delayed_work(cvm_oct_poll_queue,
160 &cvm_oct_rx_refill_work, HZ);
80ff0fd3
DD		 161}
162
4898c560 163static void cvm_oct_periodic_worker(struct work_struct *work)
f8c26486
DD		 164{
165 struct octeon_ethernet *priv = container_of(work,
166 struct octeon_ethernet,
4898c560 167 port_periodic_work.work);
a620c163 168
f6ed1b3b 169 if (priv->poll)
f8c26486 170 priv->poll(cvm_oct_device[priv->port]);
a620c163 171
f8c26486 172 cvm_oct_device[priv->port]->netdev_ops->ndo_get_stats(cvm_oct_device[priv->port]);
4898c560 173
f8c26486 174 if (!atomic_read(&cvm_oct_poll_queue_stopping))
4898c560 175 queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ);
f8c26486 176 }
80ff0fd3 177
80ff0fd3
DD		 178static __init void cvm_oct_configure_common_hw(void)
179{
80ff0fd3
DD		 180 /* Setup the FPA */
181 cvmx_fpa_enable();
182 cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
183 num_packet_buffers);
184 cvm_oct_mem_fill_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
185 num_packet_buffers);
186 if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
187 cvm_oct_mem_fill_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
188 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128);
189
190 if (USE_RED)
191 cvmx_helper_setup_red(num_packet_buffers / 4,
192 num_packet_buffers / 8);
193
80ff0fd3
DD		 194}
195
196/**
ec977c5b
DD		 197 * cvm_oct_free_work- Free a work queue entry
198 *
199 * @work_queue_entry: Work queue entry to free
80ff0fd3 200 *
80ff0fd3
DD		 201 * Returns Zero on success, Negative on failure.
202 */
203int cvm_oct_free_work(void *work_queue_entry)
204{
205 cvmx_wqe_t *work = work_queue_entry;
206
207 int segments = work->word2.s.bufs;
208 union cvmx_buf_ptr segment_ptr = work->packet_ptr;
209
210 while (segments--) {
211 union cvmx_buf_ptr next_ptr = *(union cvmx_buf_ptr *)
212 cvmx_phys_to_ptr(segment_ptr.s.addr - 8);
213 if (unlikely(!segment_ptr.s.i))
214 cvmx_fpa_free(cvm_oct_get_buffer_ptr(segment_ptr),
215 segment_ptr.s.pool,
216 DONT_WRITEBACK(CVMX_FPA_PACKET_POOL_SIZE /
217 128));
218 segment_ptr = next_ptr;
219 }
220 cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1));
221
222 return 0;
223}
224EXPORT_SYMBOL(cvm_oct_free_work);
225
f696a108 226/**
ec977c5b 227 * cvm_oct_common_get_stats - get the low level ethernet statistics
f696a108 228 * @dev: Device to get the statistics from
ec977c5b 229 *
f696a108
DD		 230 * Returns Pointer to the statistics
231 */
232static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev)
233{
234 cvmx_pip_port_status_t rx_status;
235 cvmx_pko_port_status_t tx_status;
236 struct octeon_ethernet *priv = netdev_priv(dev);
237
238 if (priv->port < CVMX_PIP_NUM_INPUT_PORTS) {
239 if (octeon_is_simulation()) {
240 /* The simulator doesn't support statistics */
241 memset(&rx_status, 0, sizeof(rx_status));
242 memset(&tx_status, 0, sizeof(tx_status));
243 } else {
244 cvmx_pip_get_port_status(priv->port, 1, &rx_status);
245 cvmx_pko_get_port_status(priv->port, 1, &tx_status);
246 }
247
248 priv->stats.rx_packets += rx_status.inb_packets;
249 priv->stats.tx_packets += tx_status.packets;
250 priv->stats.rx_bytes += rx_status.inb_octets;
251 priv->stats.tx_bytes += tx_status.octets;
252 priv->stats.multicast += rx_status.multicast_packets;
253 priv->stats.rx_crc_errors += rx_status.inb_errors;
254 priv->stats.rx_frame_errors += rx_status.fcs_align_err_packets;
255
256 /*
257 * The drop counter must be incremented atomically
258 * since the RX tasklet also increments it.
259 */
260#ifdef CONFIG_64BIT
261 atomic64_add(rx_status.dropped_packets,
262 (atomic64_t *)&priv->stats.rx_dropped);
263#else
264 atomic_add(rx_status.dropped_packets,
265 (atomic_t *)&priv->stats.rx_dropped);
266#endif
267 }
268
269 return &priv->stats;
270}
271
272/**
ec977c5b 273 * cvm_oct_common_change_mtu - change the link MTU
f696a108
DD		 274 * @dev: Device to change
275 * @new_mtu: The new MTU
276 *
277 * Returns Zero on success
278 */
279static int cvm_oct_common_change_mtu(struct net_device *dev, int new_mtu)
280{
281 struct octeon_ethernet *priv = netdev_priv(dev);
282 int interface = INTERFACE(priv->port);
283 int index = INDEX(priv->port);
284#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
285 int vlan_bytes = 4;
286#else
287 int vlan_bytes = 0;
288#endif
289
290 /*
291 * Limit the MTU to make sure the ethernet packets are between
292 * 64 bytes and 65535 bytes.
293 */
294 if ((new_mtu + 14 + 4 + vlan_bytes < 64)
295 || (new_mtu + 14 + 4 + vlan_bytes > 65392)) {
296 pr_err("MTU must be between %d and %d.\n",
297 64 - 14 - 4 - vlan_bytes, 65392 - 14 - 4 - vlan_bytes);
298 return -EINVAL;
299 }
300 dev->mtu = new_mtu;
301
302 if ((interface < 2)
303 && (cvmx_helper_interface_get_mode(interface) !=
304 CVMX_HELPER_INTERFACE_MODE_SPI)) {
305 /* Add ethernet header and FCS, and VLAN if configured. */
306 int max_packet = new_mtu + 14 + 4 + vlan_bytes;
307
308 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
309 || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
310 /* Signal errors on packets larger than the MTU */
311 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface),
312 max_packet);
313 } else {
314 /*
315 * Set the hardware to truncate packets larger
316 * than the MTU and smaller the 64 bytes.
317 */
318 union cvmx_pip_frm_len_chkx frm_len_chk;
319 frm_len_chk.u64 = 0;
320 frm_len_chk.s.minlen = 64;
321 frm_len_chk.s.maxlen = max_packet;
322 cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface),
323 frm_len_chk.u64);
324 }
325 /*
326 * Set the hardware to truncate packets larger than
327 * the MTU. The jabber register must be set to a
328 * multiple of 8 bytes, so round up.
329 */
330 cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface),
331 (max_packet + 7) & ~7u);
332 }
333 return 0;
334}
335
336/**
ec977c5b 337 * cvm_oct_common_set_multicast_list - set the multicast list
f696a108
DD		 338 * @dev: Device to work on
339 */
340static void cvm_oct_common_set_multicast_list(struct net_device *dev)
341{
342 union cvmx_gmxx_prtx_cfg gmx_cfg;
343 struct octeon_ethernet *priv = netdev_priv(dev);
344 int interface = INTERFACE(priv->port);
345 int index = INDEX(priv->port);
346
347 if ((interface < 2)
348 && (cvmx_helper_interface_get_mode(interface) !=
349 CVMX_HELPER_INTERFACE_MODE_SPI)) {
350 union cvmx_gmxx_rxx_adr_ctl control;
351 control.u64 = 0;
352 control.s.bcst = 1; /* Allow broadcast MAC addresses */
353
d5907942 354 if (!netdev_mc_empty(dev) || (dev->flags & IFF_ALLMULTI) ||
f696a108
DD		 355 (dev->flags & IFF_PROMISC))
356 /* Force accept multicast packets */
357 control.s.mcst = 2;
358 else
359 /* Force reject multicat packets */
360 control.s.mcst = 1;
361
362 if (dev->flags & IFF_PROMISC)
363 /*
364 * Reject matches if promisc. Since CAM is
365 * shut off, should accept everything.
366 */
367 control.s.cam_mode = 0;
368 else
369 /* Filter packets based on the CAM */
370 control.s.cam_mode = 1;
371
372 gmx_cfg.u64 =
373 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
374 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
375 gmx_cfg.u64 & ~1ull);
376
377 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface),
378 control.u64);
379 if (dev->flags & IFF_PROMISC)
380 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN
381 (index, interface), 0);
382 else
383 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN
384 (index, interface), 1);
385
386 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
387 gmx_cfg.u64);
388 }
389}
390
391/**
ec977c5b
DD		 392 * cvm_oct_common_set_mac_address - set the hardware MAC address for a device
393 * @dev: The device in question.
394 * @addr: Address structure to change it too.
395
f696a108
DD		 396 * Returns Zero on success
397 */
398static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
399{
400 struct octeon_ethernet *priv = netdev_priv(dev);
401 union cvmx_gmxx_prtx_cfg gmx_cfg;
402 int interface = INTERFACE(priv->port);
403 int index = INDEX(priv->port);
404
405 memcpy(dev->dev_addr, addr + 2, 6);
406
407 if ((interface < 2)
408 && (cvmx_helper_interface_get_mode(interface) !=
409 CVMX_HELPER_INTERFACE_MODE_SPI)) {
410 int i;
411 uint8_t *ptr = addr;
412 uint64_t mac = 0;
413 for (i = 0; i < 6; i++)
414 mac = (mac << 8) | (uint64_t) (ptr[i + 2]);
415
416 gmx_cfg.u64 =
417 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
418 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
419 gmx_cfg.u64 & ~1ull);
420
421 cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac);
422 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface),
423 ptr[2]);
424 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface),
425 ptr[3]);
426 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface),
427 ptr[4]);
428 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface),
429 ptr[5]);
430 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface),
431 ptr[6]);
432 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface),
433 ptr[7]);
434 cvm_oct_common_set_multicast_list(dev);
435 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
436 gmx_cfg.u64);
437 }
438 return 0;
439}
440
441/**
ec977c5b 442 * cvm_oct_common_init - per network device initialization
f696a108 443 * @dev: Device to initialize
ec977c5b 444 *
f696a108
DD		 445 * Returns Zero on success
446 */
447int cvm_oct_common_init(struct net_device *dev)
448{
f696a108 449 struct octeon_ethernet *priv = netdev_priv(dev);
13c5939e
DD		 450 struct sockaddr sa;
451 u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) |
452 ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) |
453 ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) |
454 ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) |
455 ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) |
456 (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff);
457
458 mac += cvm_oct_mac_addr_offset;
459 sa.sa_data[0] = (mac >> 40) & 0xff;
460 sa.sa_data[1] = (mac >> 32) & 0xff;
461 sa.sa_data[2] = (mac >> 24) & 0xff;
462 sa.sa_data[3] = (mac >> 16) & 0xff;
463 sa.sa_data[4] = (mac >> 8) & 0xff;
464 sa.sa_data[5] = mac & 0xff;
465
466 if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count)
467 printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:"
468 " %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
469 sa.sa_data[0] & 0xff, sa.sa_data[1] & 0xff,
470 sa.sa_data[2] & 0xff, sa.sa_data[3] & 0xff,
471 sa.sa_data[4] & 0xff, sa.sa_data[5] & 0xff);
472 cvm_oct_mac_addr_offset++;
f696a108
DD		 473
474 /*
475 * Force the interface to use the POW send if always_use_pow
476 * was specified or it is in the pow send list.
477 */
478 if ((pow_send_group != -1)
479 && (always_use_pow || strstr(pow_send_list, dev->name)))
480 priv->queue = -1;
481
924cc268
DD		 482 if (priv->queue != -1) {
483 dev->features |= NETIF_F_SG;
484 if (USE_HW_TCPUDP_CHECKSUM)
485 dev->features |= NETIF_F_IP_CSUM;
486 }
f696a108 487
f696a108
DD		 488 /* We do our own locking, Linux doesn't need to */
489 dev->features |= NETIF_F_LLTX;
490 SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops);
491
f6ed1b3b 492 cvm_oct_phy_setup_device(dev);
13c5939e 493 dev->netdev_ops->ndo_set_mac_address(dev, &sa);
f696a108
DD		 494 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu);
495
496 /*
497 * Zero out stats for port so we won't mistakenly show
498 * counters from the bootloader.
499 */
500 memset(dev->netdev_ops->ndo_get_stats(dev), 0,
501 sizeof(struct net_device_stats));
502
503 return 0;
504}
505
506void cvm_oct_common_uninit(struct net_device *dev)
507{
f6ed1b3b
DD		 508 struct octeon_ethernet *priv = netdev_priv(dev);
509
510 if (priv->phydev)
511 phy_disconnect(priv->phydev);
f696a108
DD		 512}
513
514static const struct net_device_ops cvm_oct_npi_netdev_ops = {
515 .ndo_init = cvm_oct_common_init,
516 .ndo_uninit = cvm_oct_common_uninit,
517 .ndo_start_xmit = cvm_oct_xmit,
518 .ndo_set_multicast_list = cvm_oct_common_set_multicast_list,
519 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
520 .ndo_do_ioctl = cvm_oct_ioctl,
521 .ndo_change_mtu = cvm_oct_common_change_mtu,
522 .ndo_get_stats = cvm_oct_common_get_stats,
523#ifdef CONFIG_NET_POLL_CONTROLLER
524 .ndo_poll_controller = cvm_oct_poll_controller,
525#endif
526};
527static const struct net_device_ops cvm_oct_xaui_netdev_ops = {
528 .ndo_init = cvm_oct_xaui_init,
529 .ndo_uninit = cvm_oct_xaui_uninit,
530 .ndo_open = cvm_oct_xaui_open,
531 .ndo_stop = cvm_oct_xaui_stop,
532 .ndo_start_xmit = cvm_oct_xmit,
533 .ndo_set_multicast_list = cvm_oct_common_set_multicast_list,
534 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
535 .ndo_do_ioctl = cvm_oct_ioctl,
536 .ndo_change_mtu = cvm_oct_common_change_mtu,
537 .ndo_get_stats = cvm_oct_common_get_stats,
538#ifdef CONFIG_NET_POLL_CONTROLLER
539 .ndo_poll_controller = cvm_oct_poll_controller,
540#endif
541};
542static const struct net_device_ops cvm_oct_sgmii_netdev_ops = {
543 .ndo_init = cvm_oct_sgmii_init,
544 .ndo_uninit = cvm_oct_sgmii_uninit,
545 .ndo_open = cvm_oct_sgmii_open,
546 .ndo_stop = cvm_oct_sgmii_stop,
547 .ndo_start_xmit = cvm_oct_xmit,
548 .ndo_set_multicast_list = cvm_oct_common_set_multicast_list,
549 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
550 .ndo_do_ioctl = cvm_oct_ioctl,
551 .ndo_change_mtu = cvm_oct_common_change_mtu,
552 .ndo_get_stats = cvm_oct_common_get_stats,
553#ifdef CONFIG_NET_POLL_CONTROLLER
554 .ndo_poll_controller = cvm_oct_poll_controller,
555#endif
556};
557static const struct net_device_ops cvm_oct_spi_netdev_ops = {
558 .ndo_init = cvm_oct_spi_init,
559 .ndo_uninit = cvm_oct_spi_uninit,
560 .ndo_start_xmit = cvm_oct_xmit,
561 .ndo_set_multicast_list = cvm_oct_common_set_multicast_list,
562 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
563 .ndo_do_ioctl = cvm_oct_ioctl,
564 .ndo_change_mtu = cvm_oct_common_change_mtu,
565 .ndo_get_stats = cvm_oct_common_get_stats,
566#ifdef CONFIG_NET_POLL_CONTROLLER
567 .ndo_poll_controller = cvm_oct_poll_controller,
568#endif
569};
570static const struct net_device_ops cvm_oct_rgmii_netdev_ops = {
571 .ndo_init = cvm_oct_rgmii_init,
572 .ndo_uninit = cvm_oct_rgmii_uninit,
573 .ndo_open = cvm_oct_rgmii_open,
574 .ndo_stop = cvm_oct_rgmii_stop,
575 .ndo_start_xmit = cvm_oct_xmit,
576 .ndo_set_multicast_list = cvm_oct_common_set_multicast_list,
577 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
578 .ndo_do_ioctl = cvm_oct_ioctl,
579 .ndo_change_mtu = cvm_oct_common_change_mtu,
580 .ndo_get_stats = cvm_oct_common_get_stats,
581#ifdef CONFIG_NET_POLL_CONTROLLER
582 .ndo_poll_controller = cvm_oct_poll_controller,
583#endif
584};
585static const struct net_device_ops cvm_oct_pow_netdev_ops = {
586 .ndo_init = cvm_oct_common_init,
587 .ndo_start_xmit = cvm_oct_xmit_pow,
588 .ndo_set_multicast_list = cvm_oct_common_set_multicast_list,
589 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
590 .ndo_do_ioctl = cvm_oct_ioctl,
591 .ndo_change_mtu = cvm_oct_common_change_mtu,
592 .ndo_get_stats = cvm_oct_common_get_stats,
593#ifdef CONFIG_NET_POLL_CONTROLLER
594 .ndo_poll_controller = cvm_oct_poll_controller,
595#endif
596};
597
f6ed1b3b
DD		 598extern void octeon_mdiobus_force_mod_depencency(void);
599
80ff0fd3
DD		 600static int __init cvm_oct_init_module(void)
601{
602 int num_interfaces;
603 int interface;
604 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
605 int qos;
606
f6ed1b3b 607 octeon_mdiobus_force_mod_depencency();
80ff0fd3
DD		 608 pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION);
609
13c5939e
DD		 610 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
611 cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */
612 else if (OCTEON_IS_MODEL(OCTEON_CN56XX))
613 cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */
614 else
615 cvm_oct_mac_addr_offset = 0;
616
f8c26486
DD		 617 cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet");
618 if (cvm_oct_poll_queue == NULL) {
619 pr_err("octeon-ethernet: Cannot create workqueue");
620 return -ENOMEM;
621 }
622
80ff0fd3
DD		 623 cvm_oct_configure_common_hw();
624
625 cvmx_helper_initialize_packet_io_global();
626
627 /* Change the input group for all ports before input is enabled */
628 num_interfaces = cvmx_helper_get_number_of_interfaces();
629 for (interface = 0; interface < num_interfaces; interface++) {
630 int num_ports = cvmx_helper_ports_on_interface(interface);
631 int port;
632
633 for (port = cvmx_helper_get_ipd_port(interface, 0);
634 port < cvmx_helper_get_ipd_port(interface, num_ports);
635 port++) {
636 union cvmx_pip_prt_tagx pip_prt_tagx;
637 pip_prt_tagx.u64 =
638 cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
639 pip_prt_tagx.s.grp = pow_receive_group;
640 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
641 pip_prt_tagx.u64);
642 }
643 }
644
645 cvmx_helper_ipd_and_packet_input_enable();
646
647 memset(cvm_oct_device, 0, sizeof(cvm_oct_device));
648
649 /*
650 * Initialize the FAU used for counting packet buffers that
651 * need to be freed.
652 */
653 cvmx_fau_atomic_write32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
654
4898c560
DD		 655 /* Initialize the FAU used for counting tx SKBs that need to be freed */
656 cvmx_fau_atomic_write32(FAU_TOTAL_TX_TO_CLEAN, 0);
657
80ff0fd3
DD		 658 if ((pow_send_group != -1)) {
659 struct net_device *dev;
660 pr_info("\tConfiguring device for POW only access\n");
661 dev = alloc_etherdev(sizeof(struct octeon_ethernet));
662 if (dev) {
663 /* Initialize the device private structure. */
664 struct octeon_ethernet *priv = netdev_priv(dev);
80ff0fd3 665
f696a108 666 dev->netdev_ops = &cvm_oct_pow_netdev_ops;
80ff0fd3
DD		 667 priv->imode = CVMX_HELPER_INTERFACE_MODE_DISABLED;
668 priv->port = CVMX_PIP_NUM_INPUT_PORTS;
669 priv->queue = -1;
670 strcpy(dev->name, "pow%d");
671 for (qos = 0; qos < 16; qos++)
672 skb_queue_head_init(&priv->tx_free_list[qos]);
673
674 if (register_netdev(dev) < 0) {
6568a234 675 pr_err("Failed to register ethernet device for POW\n");
80ff0fd3
DD		 676 kfree(dev);
677 } else {
678 cvm_oct_device[CVMX_PIP_NUM_INPUT_PORTS] = dev;
6568a234
DD		 679 pr_info("%s: POW send group %d, receive group %d\n",
680 dev->name, pow_send_group,
681 pow_receive_group);
80ff0fd3
DD		 682 }
683 } else {
6568a234 684 pr_err("Failed to allocate ethernet device for POW\n");
80ff0fd3
DD		 685 }
686 }
687
688 num_interfaces = cvmx_helper_get_number_of_interfaces();
689 for (interface = 0; interface < num_interfaces; interface++) {
690 cvmx_helper_interface_mode_t imode =
691 cvmx_helper_interface_get_mode(interface);
692 int num_ports = cvmx_helper_ports_on_interface(interface);
693 int port;
694
695 for (port = cvmx_helper_get_ipd_port(interface, 0);
696 port < cvmx_helper_get_ipd_port(interface, num_ports);
697 port++) {
698 struct octeon_ethernet *priv;
699 struct net_device *dev =
700 alloc_etherdev(sizeof(struct octeon_ethernet));
701 if (!dev) {
6568a234 702 pr_err("Failed to allocate ethernet device for port %d\n", port);
80ff0fd3
DD		 703 continue;
704 }
80ff0fd3
DD		 705
706 /* Initialize the device private structure. */
707 priv = netdev_priv(dev);
80ff0fd3 708
4898c560
DD		 709 INIT_DELAYED_WORK(&priv->port_periodic_work,
710 cvm_oct_periodic_worker);
80ff0fd3
DD		 711 priv->imode = imode;
712 priv->port = port;
713 priv->queue = cvmx_pko_get_base_queue(priv->port);
714 priv->fau = fau - cvmx_pko_get_num_queues(port) * 4;
715 for (qos = 0; qos < 16; qos++)
716 skb_queue_head_init(&priv->tx_free_list[qos]);
717 for (qos = 0; qos < cvmx_pko_get_num_queues(port);
718 qos++)
719 cvmx_fau_atomic_write32(priv->fau + qos * 4, 0);
720
721 switch (priv->imode) {
722
723 /* These types don't support ports to IPD/PKO */
724 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
725 case CVMX_HELPER_INTERFACE_MODE_PCIE:
726 case CVMX_HELPER_INTERFACE_MODE_PICMG:
727 break;
728
729 case CVMX_HELPER_INTERFACE_MODE_NPI:
f696a108 730 dev->netdev_ops = &cvm_oct_npi_netdev_ops;
80ff0fd3
DD		 731 strcpy(dev->name, "npi%d");
732 break;
733
734 case CVMX_HELPER_INTERFACE_MODE_XAUI:
f696a108 735 dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
80ff0fd3
DD		 736 strcpy(dev->name, "xaui%d");
737 break;
738
739 case CVMX_HELPER_INTERFACE_MODE_LOOP:
f696a108 740 dev->netdev_ops = &cvm_oct_npi_netdev_ops;
80ff0fd3
DD		 741 strcpy(dev->name, "loop%d");
742 break;
743
744 case CVMX_HELPER_INTERFACE_MODE_SGMII:
f696a108 745 dev->netdev_ops = &cvm_oct_sgmii_netdev_ops;
80ff0fd3
DD		 746 strcpy(dev->name, "eth%d");
747 break;
748
749 case CVMX_HELPER_INTERFACE_MODE_SPI:
f696a108 750 dev->netdev_ops = &cvm_oct_spi_netdev_ops;
80ff0fd3
DD		 751 strcpy(dev->name, "spi%d");
752 break;
753
754 case CVMX_HELPER_INTERFACE_MODE_RGMII:
755 case CVMX_HELPER_INTERFACE_MODE_GMII:
f696a108 756 dev->netdev_ops = &cvm_oct_rgmii_netdev_ops;
80ff0fd3
DD		 757 strcpy(dev->name, "eth%d");
758 break;
759 }
760
f696a108 761 if (!dev->netdev_ops) {
80ff0fd3
DD		 762 kfree(dev);
763 } else if (register_netdev(dev) < 0) {
764 pr_err("Failed to register ethernet device "
765 "for interface %d, port %d\n",
766 interface, priv->port);
767 kfree(dev);
768 } else {
769 cvm_oct_device[priv->port] = dev;
770 fau -=
771 cvmx_pko_get_num_queues(priv->port) *
772 sizeof(uint32_t);
f8c26486 773 queue_delayed_work(cvm_oct_poll_queue,
4898c560 774 &priv->port_periodic_work, HZ);
80ff0fd3
DD		 775 }
776 }
777 }
778
4898c560 779 cvm_oct_tx_initialize();
3368c784 780 cvm_oct_rx_initialize();
80ff0fd3 781
4898c560
DD		 782 /*
783 * 150 uS: about 10 1500-byte packtes at 1GE.
784 */
785 cvm_oct_tx_poll_interval = 150 * (octeon_get_clock_rate() / 1000000);
80ff0fd3 786
f8c26486 787 queue_delayed_work(cvm_oct_poll_queue, &cvm_oct_rx_refill_work, HZ);
80ff0fd3
DD		 788
789 return 0;
790}
791
80ff0fd3
DD		 792static void __exit cvm_oct_cleanup_module(void)
793{
794 int port;
795
796 /* Disable POW interrupt */
797 cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
798
799 cvmx_ipd_disable();
800
801 /* Free the interrupt handler */
802 free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
803
f8c26486
DD		 804 atomic_inc_return(&cvm_oct_poll_queue_stopping);
805 cancel_delayed_work_sync(&cvm_oct_rx_refill_work);
806
80ff0fd3 807 cvm_oct_rx_shutdown();
4898c560
DD		 808 cvm_oct_tx_shutdown();
809
80ff0fd3
DD		 810 cvmx_pko_disable();
811
812 /* Free the ethernet devices */
813 for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) {
814 if (cvm_oct_device[port]) {
f8c26486
DD		 815 struct net_device *dev = cvm_oct_device[port];
816 struct octeon_ethernet *priv = netdev_priv(dev);
4898c560 817 cancel_delayed_work_sync(&priv->port_periodic_work);
f8c26486 818
4898c560 819 cvm_oct_tx_shutdown_dev(dev);
f8c26486
DD		 820 unregister_netdev(dev);
821 kfree(dev);
80ff0fd3
DD		 822 cvm_oct_device[port] = NULL;
823 }
824 }
825
f8c26486
DD		 826 destroy_workqueue(cvm_oct_poll_queue);
827
80ff0fd3 828 cvmx_pko_shutdown();
80ff0fd3
DD		 829
830 cvmx_ipd_free_ptr();
831
832 /* Free the HW pools */
833 cvm_oct_mem_empty_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
834 num_packet_buffers);
835 cvm_oct_mem_empty_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
836 num_packet_buffers);
837 if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
838 cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
839 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128);
840}
841
842MODULE_LICENSE("GPL");
843MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
844MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver.");
845module_init(cvm_oct_init_module);
846module_exit(cvm_oct_cleanup_module);
Linux 6.x block layer and io_uring tree(s)