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1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
7 | * Copyright (c) 2003-2008 Cavium Networks | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | #ifndef __CVMX_SPXX_DEFS_H__ | |
29 | #define __CVMX_SPXX_DEFS_H__ | |
30 | ||
31 | #define CVMX_SPXX_BCKPRS_CNT(block_id) \ | |
32 | CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) | |
33 | #define CVMX_SPXX_BIST_STAT(block_id) \ | |
34 | CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) | |
35 | #define CVMX_SPXX_CLK_CTL(block_id) \ | |
36 | CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) | |
37 | #define CVMX_SPXX_CLK_STAT(block_id) \ | |
38 | CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) | |
39 | #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ | |
40 | CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) | |
41 | #define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ | |
42 | CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) | |
43 | #define CVMX_SPXX_DRV_CTL(block_id) \ | |
44 | CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) | |
45 | #define CVMX_SPXX_ERR_CTL(block_id) \ | |
46 | CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) | |
47 | #define CVMX_SPXX_INT_DAT(block_id) \ | |
48 | CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull)) | |
49 | #define CVMX_SPXX_INT_MSK(block_id) \ | |
50 | CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull)) | |
51 | #define CVMX_SPXX_INT_REG(block_id) \ | |
52 | CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull)) | |
53 | #define CVMX_SPXX_INT_SYNC(block_id) \ | |
54 | CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull)) | |
55 | #define CVMX_SPXX_TPA_ACC(block_id) \ | |
56 | CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull)) | |
57 | #define CVMX_SPXX_TPA_MAX(block_id) \ | |
58 | CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull)) | |
59 | #define CVMX_SPXX_TPA_SEL(block_id) \ | |
60 | CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull)) | |
61 | #define CVMX_SPXX_TRN4_CTL(block_id) \ | |
62 | CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull)) | |
63 | ||
64 | union cvmx_spxx_bckprs_cnt { | |
65 | uint64_t u64; | |
66 | struct cvmx_spxx_bckprs_cnt_s { | |
67 | uint64_t reserved_32_63:32; | |
68 | uint64_t cnt:32; | |
69 | } s; | |
70 | struct cvmx_spxx_bckprs_cnt_s cn38xx; | |
71 | struct cvmx_spxx_bckprs_cnt_s cn38xxp2; | |
72 | struct cvmx_spxx_bckprs_cnt_s cn58xx; | |
73 | struct cvmx_spxx_bckprs_cnt_s cn58xxp1; | |
74 | }; | |
75 | ||
76 | union cvmx_spxx_bist_stat { | |
77 | uint64_t u64; | |
78 | struct cvmx_spxx_bist_stat_s { | |
79 | uint64_t reserved_3_63:61; | |
80 | uint64_t stat2:1; | |
81 | uint64_t stat1:1; | |
82 | uint64_t stat0:1; | |
83 | } s; | |
84 | struct cvmx_spxx_bist_stat_s cn38xx; | |
85 | struct cvmx_spxx_bist_stat_s cn38xxp2; | |
86 | struct cvmx_spxx_bist_stat_s cn58xx; | |
87 | struct cvmx_spxx_bist_stat_s cn58xxp1; | |
88 | }; | |
89 | ||
90 | union cvmx_spxx_clk_ctl { | |
91 | uint64_t u64; | |
92 | struct cvmx_spxx_clk_ctl_s { | |
93 | uint64_t reserved_17_63:47; | |
94 | uint64_t seetrn:1; | |
95 | uint64_t reserved_12_15:4; | |
96 | uint64_t clkdly:5; | |
97 | uint64_t runbist:1; | |
98 | uint64_t statdrv:1; | |
99 | uint64_t statrcv:1; | |
100 | uint64_t sndtrn:1; | |
101 | uint64_t drptrn:1; | |
102 | uint64_t rcvtrn:1; | |
103 | uint64_t srxdlck:1; | |
104 | } s; | |
105 | struct cvmx_spxx_clk_ctl_s cn38xx; | |
106 | struct cvmx_spxx_clk_ctl_s cn38xxp2; | |
107 | struct cvmx_spxx_clk_ctl_s cn58xx; | |
108 | struct cvmx_spxx_clk_ctl_s cn58xxp1; | |
109 | }; | |
110 | ||
111 | union cvmx_spxx_clk_stat { | |
112 | uint64_t u64; | |
113 | struct cvmx_spxx_clk_stat_s { | |
114 | uint64_t reserved_11_63:53; | |
115 | uint64_t stxcal:1; | |
116 | uint64_t reserved_9_9:1; | |
117 | uint64_t srxtrn:1; | |
118 | uint64_t s4clk1:1; | |
119 | uint64_t s4clk0:1; | |
120 | uint64_t d4clk1:1; | |
121 | uint64_t d4clk0:1; | |
122 | uint64_t reserved_0_3:4; | |
123 | } s; | |
124 | struct cvmx_spxx_clk_stat_s cn38xx; | |
125 | struct cvmx_spxx_clk_stat_s cn38xxp2; | |
126 | struct cvmx_spxx_clk_stat_s cn58xx; | |
127 | struct cvmx_spxx_clk_stat_s cn58xxp1; | |
128 | }; | |
129 | ||
130 | union cvmx_spxx_dbg_deskew_ctl { | |
131 | uint64_t u64; | |
132 | struct cvmx_spxx_dbg_deskew_ctl_s { | |
133 | uint64_t reserved_30_63:34; | |
134 | uint64_t fallnop:1; | |
135 | uint64_t fall8:1; | |
136 | uint64_t reserved_26_27:2; | |
137 | uint64_t sstep_go:1; | |
138 | uint64_t sstep:1; | |
139 | uint64_t reserved_22_23:2; | |
140 | uint64_t clrdly:1; | |
141 | uint64_t dec:1; | |
142 | uint64_t inc:1; | |
143 | uint64_t mux:1; | |
144 | uint64_t offset:5; | |
145 | uint64_t bitsel:5; | |
146 | uint64_t offdly:6; | |
147 | uint64_t dllfrc:1; | |
148 | uint64_t dlldis:1; | |
149 | } s; | |
150 | struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; | |
151 | struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; | |
152 | struct cvmx_spxx_dbg_deskew_ctl_s cn58xx; | |
153 | struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1; | |
154 | }; | |
155 | ||
156 | union cvmx_spxx_dbg_deskew_state { | |
157 | uint64_t u64; | |
158 | struct cvmx_spxx_dbg_deskew_state_s { | |
159 | uint64_t reserved_9_63:55; | |
160 | uint64_t testres:1; | |
161 | uint64_t unxterm:1; | |
162 | uint64_t muxsel:2; | |
163 | uint64_t offset:5; | |
164 | } s; | |
165 | struct cvmx_spxx_dbg_deskew_state_s cn38xx; | |
166 | struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; | |
167 | struct cvmx_spxx_dbg_deskew_state_s cn58xx; | |
168 | struct cvmx_spxx_dbg_deskew_state_s cn58xxp1; | |
169 | }; | |
170 | ||
171 | union cvmx_spxx_drv_ctl { | |
172 | uint64_t u64; | |
173 | struct cvmx_spxx_drv_ctl_s { | |
174 | uint64_t reserved_0_63:64; | |
175 | } s; | |
176 | struct cvmx_spxx_drv_ctl_cn38xx { | |
177 | uint64_t reserved_16_63:48; | |
178 | uint64_t stx4ncmp:4; | |
179 | uint64_t stx4pcmp:4; | |
180 | uint64_t srx4cmp:8; | |
181 | } cn38xx; | |
182 | struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; | |
183 | struct cvmx_spxx_drv_ctl_cn58xx { | |
184 | uint64_t reserved_24_63:40; | |
185 | uint64_t stx4ncmp:4; | |
186 | uint64_t stx4pcmp:4; | |
187 | uint64_t reserved_10_15:6; | |
188 | uint64_t srx4cmp:10; | |
189 | } cn58xx; | |
190 | struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; | |
191 | }; | |
192 | ||
193 | union cvmx_spxx_err_ctl { | |
194 | uint64_t u64; | |
195 | struct cvmx_spxx_err_ctl_s { | |
196 | uint64_t reserved_9_63:55; | |
197 | uint64_t prtnxa:1; | |
198 | uint64_t dipcls:1; | |
199 | uint64_t dippay:1; | |
200 | uint64_t reserved_4_5:2; | |
201 | uint64_t errcnt:4; | |
202 | } s; | |
203 | struct cvmx_spxx_err_ctl_s cn38xx; | |
204 | struct cvmx_spxx_err_ctl_s cn38xxp2; | |
205 | struct cvmx_spxx_err_ctl_s cn58xx; | |
206 | struct cvmx_spxx_err_ctl_s cn58xxp1; | |
207 | }; | |
208 | ||
209 | union cvmx_spxx_int_dat { | |
210 | uint64_t u64; | |
211 | struct cvmx_spxx_int_dat_s { | |
212 | uint64_t reserved_32_63:32; | |
213 | uint64_t mul:1; | |
214 | uint64_t reserved_14_30:17; | |
215 | uint64_t calbnk:2; | |
216 | uint64_t rsvop:4; | |
217 | uint64_t prt:8; | |
218 | } s; | |
219 | struct cvmx_spxx_int_dat_s cn38xx; | |
220 | struct cvmx_spxx_int_dat_s cn38xxp2; | |
221 | struct cvmx_spxx_int_dat_s cn58xx; | |
222 | struct cvmx_spxx_int_dat_s cn58xxp1; | |
223 | }; | |
224 | ||
225 | union cvmx_spxx_int_msk { | |
226 | uint64_t u64; | |
227 | struct cvmx_spxx_int_msk_s { | |
228 | uint64_t reserved_12_63:52; | |
229 | uint64_t calerr:1; | |
230 | uint64_t syncerr:1; | |
231 | uint64_t diperr:1; | |
232 | uint64_t tpaovr:1; | |
233 | uint64_t rsverr:1; | |
234 | uint64_t drwnng:1; | |
235 | uint64_t clserr:1; | |
236 | uint64_t spiovr:1; | |
237 | uint64_t reserved_2_3:2; | |
238 | uint64_t abnorm:1; | |
239 | uint64_t prtnxa:1; | |
240 | } s; | |
241 | struct cvmx_spxx_int_msk_s cn38xx; | |
242 | struct cvmx_spxx_int_msk_s cn38xxp2; | |
243 | struct cvmx_spxx_int_msk_s cn58xx; | |
244 | struct cvmx_spxx_int_msk_s cn58xxp1; | |
245 | }; | |
246 | ||
247 | union cvmx_spxx_int_reg { | |
248 | uint64_t u64; | |
249 | struct cvmx_spxx_int_reg_s { | |
250 | uint64_t reserved_32_63:32; | |
251 | uint64_t spf:1; | |
252 | uint64_t reserved_12_30:19; | |
253 | uint64_t calerr:1; | |
254 | uint64_t syncerr:1; | |
255 | uint64_t diperr:1; | |
256 | uint64_t tpaovr:1; | |
257 | uint64_t rsverr:1; | |
258 | uint64_t drwnng:1; | |
259 | uint64_t clserr:1; | |
260 | uint64_t spiovr:1; | |
261 | uint64_t reserved_2_3:2; | |
262 | uint64_t abnorm:1; | |
263 | uint64_t prtnxa:1; | |
264 | } s; | |
265 | struct cvmx_spxx_int_reg_s cn38xx; | |
266 | struct cvmx_spxx_int_reg_s cn38xxp2; | |
267 | struct cvmx_spxx_int_reg_s cn58xx; | |
268 | struct cvmx_spxx_int_reg_s cn58xxp1; | |
269 | }; | |
270 | ||
271 | union cvmx_spxx_int_sync { | |
272 | uint64_t u64; | |
273 | struct cvmx_spxx_int_sync_s { | |
274 | uint64_t reserved_12_63:52; | |
275 | uint64_t calerr:1; | |
276 | uint64_t syncerr:1; | |
277 | uint64_t diperr:1; | |
278 | uint64_t tpaovr:1; | |
279 | uint64_t rsverr:1; | |
280 | uint64_t drwnng:1; | |
281 | uint64_t clserr:1; | |
282 | uint64_t spiovr:1; | |
283 | uint64_t reserved_2_3:2; | |
284 | uint64_t abnorm:1; | |
285 | uint64_t prtnxa:1; | |
286 | } s; | |
287 | struct cvmx_spxx_int_sync_s cn38xx; | |
288 | struct cvmx_spxx_int_sync_s cn38xxp2; | |
289 | struct cvmx_spxx_int_sync_s cn58xx; | |
290 | struct cvmx_spxx_int_sync_s cn58xxp1; | |
291 | }; | |
292 | ||
293 | union cvmx_spxx_tpa_acc { | |
294 | uint64_t u64; | |
295 | struct cvmx_spxx_tpa_acc_s { | |
296 | uint64_t reserved_32_63:32; | |
297 | uint64_t cnt:32; | |
298 | } s; | |
299 | struct cvmx_spxx_tpa_acc_s cn38xx; | |
300 | struct cvmx_spxx_tpa_acc_s cn38xxp2; | |
301 | struct cvmx_spxx_tpa_acc_s cn58xx; | |
302 | struct cvmx_spxx_tpa_acc_s cn58xxp1; | |
303 | }; | |
304 | ||
305 | union cvmx_spxx_tpa_max { | |
306 | uint64_t u64; | |
307 | struct cvmx_spxx_tpa_max_s { | |
308 | uint64_t reserved_32_63:32; | |
309 | uint64_t max:32; | |
310 | } s; | |
311 | struct cvmx_spxx_tpa_max_s cn38xx; | |
312 | struct cvmx_spxx_tpa_max_s cn38xxp2; | |
313 | struct cvmx_spxx_tpa_max_s cn58xx; | |
314 | struct cvmx_spxx_tpa_max_s cn58xxp1; | |
315 | }; | |
316 | ||
317 | union cvmx_spxx_tpa_sel { | |
318 | uint64_t u64; | |
319 | struct cvmx_spxx_tpa_sel_s { | |
320 | uint64_t reserved_4_63:60; | |
321 | uint64_t prtsel:4; | |
322 | } s; | |
323 | struct cvmx_spxx_tpa_sel_s cn38xx; | |
324 | struct cvmx_spxx_tpa_sel_s cn38xxp2; | |
325 | struct cvmx_spxx_tpa_sel_s cn58xx; | |
326 | struct cvmx_spxx_tpa_sel_s cn58xxp1; | |
327 | }; | |
328 | ||
329 | union cvmx_spxx_trn4_ctl { | |
330 | uint64_t u64; | |
331 | struct cvmx_spxx_trn4_ctl_s { | |
332 | uint64_t reserved_13_63:51; | |
333 | uint64_t trntest:1; | |
334 | uint64_t jitter:3; | |
335 | uint64_t clr_boot:1; | |
336 | uint64_t set_boot:1; | |
337 | uint64_t maxdist:5; | |
338 | uint64_t macro_en:1; | |
339 | uint64_t mux_en:1; | |
340 | } s; | |
341 | struct cvmx_spxx_trn4_ctl_s cn38xx; | |
342 | struct cvmx_spxx_trn4_ctl_s cn38xxp2; | |
343 | struct cvmx_spxx_trn4_ctl_s cn58xx; | |
344 | struct cvmx_spxx_trn4_ctl_s cn58xxp1; | |
345 | }; | |
346 | ||
347 | #endif |