projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'platform-drivers-x86-v4.19-1' of git://git.infradead.org/linux-platform...
[linux-2.6-block.git] / drivers / staging / netlogic / xlr_net.c
CommitLineData
6f98b1a2
GR		 1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#include <linux/phy.h>
35#include <linux/delay.h>
36#include <linux/netdevice.h>
37#include <linux/smp.h>
38#include <linux/ethtool.h>
39#include <linux/module.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/jiffies.h>
43#include <linux/interrupt.h>
44#include <linux/platform_device.h>
45
46#include <asm/mipsregs.h>
2db0083d
A		 47/*
48 * fmn.h - For FMN credit configuration and registering fmn_handler.
6f98b1a2
GR		 49 * FMN is communication mechanism that allows processing agents within
50 * XLR/XLS to communicate each other.
51 */
52#include <asm/netlogic/xlr/fmn.h>
53
54#include "platform_net.h"
55#include "xlr_net.h"
56
57/*
58 * The readl/writel implementation byteswaps on XLR/XLS, so
59 * we need to use __raw_ IO to read the NAE registers
60 * because they are in the big-endian MMIO area on the SoC.
61 */
62static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
63{
64 __raw_writel(val, base + reg);
65}
66
67static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
68{
69 return __raw_readl(base + reg);
70}
71
3a694d0c 72static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
6f98b1a2
GR		 73{
74 u32 tmp;
75
76 tmp = xlr_nae_rdreg(base_addr, off);
77 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
78}
79
f8397bc6 80#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
6f98b1a2
GR		 81
82static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
83{
84 struct nlm_fmn_msg msg;
85 int ret = 0, num_try = 0, stnid;
86 unsigned long paddr, mflags;
87
88 paddr = virt_to_bus(addr);
89 msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
90 msg.msg1 = 0;
91 msg.msg2 = 0;
92 msg.msg3 = 0;
93 stnid = priv->nd->rfr_station;
94 do {
b9add4c3 95 mflags = nlm_cop2_enable_irqsave();
6f98b1a2 96 ret = nlm_fmn_send(1, 0, stnid, &msg);
b9add4c3 97 nlm_cop2_disable_irqrestore(mflags);
6f98b1a2
GR		 98 if (ret == 0)
99 return 0;
100 } while (++num_try < 10000);
101
04309886 102 netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
6f98b1a2
GR		 103 return ret;
104}
105
f8397bc6 106static inline unsigned char *xlr_alloc_skb(void)
6f98b1a2
GR		 107{
108 struct sk_buff *skb;
f8397bc6
GR		 109 int buf_len = sizeof(struct sk_buff *);
110 unsigned char *skb_data;
6f98b1a2
GR		 111
112 /* skb->data is cache aligned */
113 skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
fdaef43d 114 if (!skb)
6f98b1a2 115 return NULL;
f8397bc6
GR		 116 skb_data = skb->data;
117 skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
118 skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
119 memcpy(skb_data, &skb, buf_len);
120
121 return skb->data;
6f98b1a2
GR		 122}
123
3a694d0c
LGL		 124static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
125 struct nlm_fmn_msg *msg, void *arg)
6f98b1a2 126{
f8397bc6
GR		 127 struct sk_buff *skb;
128 void *skb_data = NULL;
6f98b1a2
GR		 129 struct net_device *ndev;
130 struct xlr_net_priv *priv;
f8397bc6
GR		 131 u32 port, length;
132 unsigned char *addr;
62e259ed 133 struct xlr_adapter *adapter = arg;
6f98b1a2
GR		 134
135 length = (msg->msg0 >> 40) & 0x3fff;
136 if (length == 0) {
137 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
f8397bc6 138 addr = addr - MAC_SKB_BACK_PTR_SIZE;
c8550db5 139 skb = (struct sk_buff *)(*(unsigned long *)addr);
f8397bc6
GR		 140 dev_kfree_skb_any((struct sk_buff *)addr);
141 } else {
142 addr = (unsigned char *)
143 bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
6f98b1a2 144 length = length - BYTE_OFFSET - MAC_CRC_LEN;
f8397bc6
GR		 145 port = ((int)msg->msg0) & 0x0f;
146 addr = addr - MAC_SKB_BACK_PTR_SIZE;
c8550db5 147 skb = (struct sk_buff *)(*(unsigned long *)addr);
f8397bc6 148 skb->dev = adapter->netdev[port];
4b032eb7 149 if (!skb->dev)
f8397bc6 150 return;
6f98b1a2
GR		 151 ndev = skb->dev;
152 priv = netdev_priv(ndev);
153
154 /* 16 byte IP header align */
155 skb_reserve(skb, BYTE_OFFSET);
156 skb_put(skb, length);
157 skb->protocol = eth_type_trans(skb, skb->dev);
6f98b1a2
GR		 158 netif_rx(skb);
159 /* Fill rx ring */
f8397bc6
GR		 160 skb_data = xlr_alloc_skb();
161 if (skb_data)
162 send_to_rfr_fifo(priv, skb_data);
6f98b1a2 163 }
6f98b1a2
GR		 164}
165
3fe01e24
AL		 166static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
167{
168 return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
169}
170
f8397bc6
GR		 171/*
172 * Ethtool operation
173 */
f7417a55
PR		 174static int xlr_get_link_ksettings(struct net_device *ndev,
175 struct ethtool_link_ksettings *ecmd)
6f98b1a2
GR		 176{
177 struct xlr_net_priv *priv = netdev_priv(ndev);
3fe01e24 178 struct phy_device *phydev = xlr_get_phydev(priv);
6f98b1a2
GR		 179
180 if (!phydev)
181 return -ENODEV;
5514174f 182
183 phy_ethtool_ksettings_get(phydev, ecmd);
184
185 return 0;
6f98b1a2 186}
c56051c0 187
f7417a55
PR		 188static int xlr_set_link_ksettings(struct net_device *ndev,
189 const struct ethtool_link_ksettings *ecmd)
6f98b1a2
GR		 190{
191 struct xlr_net_priv *priv = netdev_priv(ndev);
3fe01e24 192 struct phy_device *phydev = xlr_get_phydev(priv);
6f98b1a2
GR		 193
194 if (!phydev)
195 return -ENODEV;
f7417a55 196 return phy_ethtool_ksettings_set(phydev, ecmd);
6f98b1a2
GR		 197}
198
608bc956 199static const struct ethtool_ops xlr_ethtool_ops = {
f7417a55
PR		 200 .get_link_ksettings = xlr_get_link_ksettings,
201 .set_link_ksettings = xlr_set_link_ksettings,
6f98b1a2
GR		 202};
203
f8397bc6
GR		 204/*
205 * Net operations
206 */
6f98b1a2
GR		 207static int xlr_net_fill_rx_ring(struct net_device *ndev)
208{
f8397bc6 209 void *skb_data;
6f98b1a2
GR		 210 struct xlr_net_priv *priv = netdev_priv(ndev);
211 int i;
212
800325fc 213 for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
f8397bc6
GR		 214 skb_data = xlr_alloc_skb();
215 if (!skb_data) {
04309886 216 netdev_err(ndev, "SKB allocation failed\n");
6f98b1a2 217 return -ENOMEM;
f8397bc6
GR		 218 }
219 send_to_rfr_fifo(priv, skb_data);
6f98b1a2 220 }
04309886 221 netdev_info(ndev, "Rx ring setup done\n");
6f98b1a2
GR		 222 return 0;
223}
224
225static int xlr_net_open(struct net_device *ndev)
226{
227 u32 err;
228 struct xlr_net_priv *priv = netdev_priv(ndev);
3fe01e24 229 struct phy_device *phydev = xlr_get_phydev(priv);
6f98b1a2
GR		 230
231 /* schedule a link state check */
232 phy_start(phydev);
233
234 err = phy_start_aneg(phydev);
235 if (err) {
236 pr_err("Autoneg failed\n");
237 return err;
238 }
6f98b1a2
GR		 239 /* Setup the speed from PHY to internal reg*/
240 xlr_set_gmac_speed(priv);
f8397bc6 241
6f98b1a2 242 netif_tx_start_all_queues(ndev);
f8397bc6 243
6f98b1a2
GR		 244 return 0;
245}
246
247static int xlr_net_stop(struct net_device *ndev)
248{
249 struct xlr_net_priv *priv = netdev_priv(ndev);
3fe01e24 250 struct phy_device *phydev = xlr_get_phydev(priv);
6f98b1a2
GR		 251
252 phy_stop(phydev);
253 netif_tx_stop_all_queues(ndev);
254 return 0;
255}
256
257static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
3a694d0c 258 struct sk_buff *skb)
6f98b1a2
GR		 259{
260 unsigned long physkb = virt_to_phys(skb);
261 int cpu_core = nlm_core_id();
262 int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
d63bc1fb 263
6f98b1a2
GR		 264 msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
265 ((u64)127 << 54) | /* No Free back */
266 (u64)skb->len << 40 | /* Length of data */
267 ((u64)addr));
268 msg->msg1 = (((u64)1 << 63) |
269 ((u64)fr_stn_id << 54) | /* Free back id */
270 (u64)0 << 40 | /* Set len to 0 */
271 ((u64)physkb & 0xffffffff)); /* 32bit address */
06409808
LGL		 272 msg->msg2 = 0;
273 msg->msg3 = 0;
6f98b1a2
GR		 274}
275
6f98b1a2 276static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
3a694d0c 277 struct net_device *ndev)
6f98b1a2
GR		 278{
279 struct nlm_fmn_msg msg;
280 struct xlr_net_priv *priv = netdev_priv(ndev);
281 int ret;
6f98b1a2
GR		 282 u32 flags;
283
6f98b1a2 284 xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
b9add4c3 285 flags = nlm_cop2_enable_irqsave();
f8397bc6 286 ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
b9add4c3 287 nlm_cop2_disable_irqrestore(flags);
6f98b1a2
GR		 288 if (ret)
289 dev_kfree_skb_any(skb);
290 return NETDEV_TX_OK;
291}
292
6f98b1a2
GR		 293static void xlr_hw_set_mac_addr(struct net_device *ndev)
294{
295 struct xlr_net_priv *priv = netdev_priv(ndev);
296
297 /* set mac station address */
298 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
3a694d0c
LGL		 299 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
300 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
6f98b1a2 301 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
3a694d0c 302 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
6f98b1a2
GR		 303
304 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
305 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
306 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
307 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
308
309 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
3a694d0c
LGL		 310 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
311 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
312 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
6f98b1a2
GR		 313
314 if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
3a694d0c 315 priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
bf8b2bb6 316 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
6f98b1a2
GR		 317}
318
319static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
320{
321 int err;
322
323 err = eth_mac_addr(ndev, data);
324 if (err)
325 return err;
326 xlr_hw_set_mac_addr(ndev);
327 return 0;
328}
329
330static void xlr_set_rx_mode(struct net_device *ndev)
331{
332 struct xlr_net_priv *priv = netdev_priv(ndev);
333 u32 regval;
334
335 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
336
337 if (ndev->flags & IFF_PROMISC) {
338 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
339 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
340 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
341 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
342 } else {
343 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
344 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
345 }
346
347 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
348}
349
350static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
351{
352 struct xlr_net_priv *priv = netdev_priv(ndev);
353
354 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
355 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
356 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
357 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
358 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
359 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
b728b54f 360 RX_DROP_PACKET_COUNTER);
6f98b1a2 361 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
b728b54f 362 TX_DROP_FRAME_COUNTER);
6f98b1a2
GR		 363
364 stats->multicast = xlr_nae_rdreg(priv->base_addr,
b728b54f 365 RX_MULTICAST_PACKET_COUNTER);
6f98b1a2 366 stats->collisions = xlr_nae_rdreg(priv->base_addr,
b728b54f 367 TX_TOTAL_COLLISION_COUNTER);
6f98b1a2
GR		 368
369 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 370 RX_FRAME_LENGTH_ERROR_COUNTER);
6f98b1a2 371 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 372 RX_DROP_PACKET_COUNTER);
6f98b1a2 373 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 374 RX_FCS_ERROR_COUNTER);
6f98b1a2 375 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 376 RX_ALIGNMENT_ERROR_COUNTER);
6f98b1a2
GR		 377
378 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 379 RX_DROP_PACKET_COUNTER);
6f98b1a2 380 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 381 RX_CARRIER_SENSE_ERROR_COUNTER);
6f98b1a2
GR		 382
383 stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
b728b54f
FCB		 384 stats->rx_frame_errors + stats->rx_fifo_errors +
385 stats->rx_missed_errors);
6f98b1a2
GR		 386
387 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
388 TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
389 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 390 TX_DROP_FRAME_COUNTER);
6f98b1a2 391 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
b728b54f 392 TX_DROP_FRAME_COUNTER);
6f98b1a2
GR		 393}
394
8b70d696 395static const struct net_device_ops xlr_netdev_ops = {
6f98b1a2
GR		 396 .ndo_open = xlr_net_open,
397 .ndo_stop = xlr_net_stop,
398 .ndo_start_xmit = xlr_net_start_xmit,
a4ea8a3d 399 .ndo_select_queue = dev_pick_tx_cpu_id,
6f98b1a2
GR		 400 .ndo_set_mac_address = xlr_net_set_mac_addr,
401 .ndo_set_rx_mode = xlr_set_rx_mode,
bc1f4470 402 .ndo_get_stats64 = xlr_stats,
6f98b1a2
GR		 403};
404
f8397bc6
GR		 405/*
406 * Gmac init
407 */
6f98b1a2 408static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
3a694d0c 409 int reg_start_1, int reg_size, int size)
6f98b1a2
GR		 410{
411 void *spill;
412 u32 *base;
413 unsigned long phys_addr;
414 u32 spill_size;
415
416 base = priv->base_addr;
417 spill_size = size;
418 spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
11b49d9b 419 if (!spill) {
6f98b1a2 420 pr_err("Unable to allocate memory for spill area!\n");
11b49d9b
LGL		 421 return ZERO_SIZE_PTR;
422 }
6f98b1a2
GR		 423
424 spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
425 phys_addr = virt_to_phys(spill);
426 dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
3a694d0c 427 size, phys_addr);
6f98b1a2
GR		 428 xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
429 xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
430 xlr_nae_wreg(base, reg_size, spill_size);
431
432 return spill;
433}
434
435/*
436 * Configure the 6 FIFO's that are used by the network accelarator to
437 * communicate with the rest of the XLx device. 4 of the FIFO's are for
438 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
439 * the NA with free descriptors.
440 */
441static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
442{
443 priv->frin_spill = xlr_config_spill(priv,
b728b54f
FCB		 444 R_REG_FRIN_SPILL_MEM_START_0,
445 R_REG_FRIN_SPILL_MEM_START_1,
446 R_REG_FRIN_SPILL_MEM_SIZE,
447 MAX_FRIN_SPILL * sizeof(u64));
6f98b1a2 448 priv->frout_spill = xlr_config_spill(priv,
b728b54f
FCB		 449 R_FROUT_SPILL_MEM_START_0,
450 R_FROUT_SPILL_MEM_START_1,
451 R_FROUT_SPILL_MEM_SIZE,
452 MAX_FROUT_SPILL * sizeof(u64));
6f98b1a2 453 priv->class_0_spill = xlr_config_spill(priv,
b728b54f
FCB		 454 R_CLASS0_SPILL_MEM_START_0,
455 R_CLASS0_SPILL_MEM_START_1,
456 R_CLASS0_SPILL_MEM_SIZE,
457 MAX_CLASS_0_SPILL * sizeof(u64));
6f98b1a2 458 priv->class_1_spill = xlr_config_spill(priv,
b728b54f
FCB		 459 R_CLASS1_SPILL_MEM_START_0,
460 R_CLASS1_SPILL_MEM_START_1,
461 R_CLASS1_SPILL_MEM_SIZE,
462 MAX_CLASS_1_SPILL * sizeof(u64));
6f98b1a2 463 priv->class_2_spill = xlr_config_spill(priv,
b728b54f
FCB		 464 R_CLASS2_SPILL_MEM_START_0,
465 R_CLASS2_SPILL_MEM_START_1,
466 R_CLASS2_SPILL_MEM_SIZE,
467 MAX_CLASS_2_SPILL * sizeof(u64));
6f98b1a2 468 priv->class_3_spill = xlr_config_spill(priv,
b728b54f
FCB		 469 R_CLASS3_SPILL_MEM_START_0,
470 R_CLASS3_SPILL_MEM_START_1,
471 R_CLASS3_SPILL_MEM_SIZE,
472 MAX_CLASS_3_SPILL * sizeof(u64));
6f98b1a2
GR		 473}
474
2db0083d
A		 475/*
476 * Configure PDE to Round-Robin distribution of packets to the
477 * available cpu
478 */
6f98b1a2
GR		 479static void xlr_config_pde(struct xlr_net_priv *priv)
480{
481 int i = 0;
482 u64 bkt_map = 0;
483
484 /* Each core has 8 buckets(station) */
485 for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
486 bkt_map |= (0xff << (i * 8));
487
488 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
489 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
3a694d0c 490 ((bkt_map >> 32) & 0xffffffff));
6f98b1a2
GR		 491
492 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
493 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
3a694d0c 494 ((bkt_map >> 32) & 0xffffffff));
6f98b1a2
GR		 495
496 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
497 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
3a694d0c 498 ((bkt_map >> 32) & 0xffffffff));
6f98b1a2
GR		 499
500 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
501 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
3a694d0c 502 ((bkt_map >> 32) & 0xffffffff));
6f98b1a2
GR		 503}
504
2db0083d
A		 505/*
506 * Setup the Message ring credits, bucket size and other
507 * common configuration
508 */
f8397bc6 509static int xlr_config_common(struct xlr_net_priv *priv)
6f98b1a2
GR		 510{
511 struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
512 int start_stn_id = gmac->start_stn_id;
513 int end_stn_id = gmac->end_stn_id;
514 int *bucket_size = priv->nd->bucket_size;
f8397bc6 515 int i, j, err;
6f98b1a2
GR		 516
517 /* Setting non-core MsgBktSize(0x321 - 0x325) */
518 for (i = start_stn_id; i <= end_stn_id; i++) {
519 xlr_nae_wreg(priv->base_addr,
3a694d0c
LGL		 520 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
521 bucket_size[i]);
6f98b1a2
GR		 522 }
523
2db0083d
A		 524 /*
525 * Setting non-core Credit counter register
526 * Distributing Gmac's credit to CPU's
527 */
6f98b1a2
GR		 528 for (i = 0; i < 8; i++) {
529 for (j = 0; j < 8; j++)
530 xlr_nae_wreg(priv->base_addr,
3a694d0c
LGL		 531 (R_CC_CPU0_0 + (i * 8)) + j,
532 gmac->credit_config[(i * 8) + j]);
6f98b1a2
GR		 533 }
534
535 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
536 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
537 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
538 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
539 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
540 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
541
f8397bc6
GR		 542 err = xlr_net_fill_rx_ring(priv->ndev);
543 if (err)
544 return err;
6f98b1a2 545 nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
3a694d0c 546 priv->adapter);
f8397bc6 547 return 0;
6f98b1a2
GR		 548}
549
550static void xlr_config_translate_table(struct xlr_net_priv *priv)
551{
552 u32 cpu_mask;
553 u32 val;
554 int bkts[32]; /* one bucket is assumed for each cpu */
555 int b1, b2, c1, c2, i, j, k;
556 int use_bkt;
557
558 use_bkt = 0;
559 cpu_mask = priv->nd->cpu_mask;
560
561 pr_info("Using %s-based distribution\n",
3a694d0c 562 (use_bkt) ? "bucket" : "class");
6f98b1a2
GR		 563 j = 0;
564 for (i = 0; i < 32; i++) {
565 if ((1 << i) & cpu_mask) {
566 /* for each cpu, mark the 4+threadid bucket */
567 bkts[j] = ((i / 4) * 8) + (i % 4);
568 j++;
569 }
570 }
571
572 /*configure the 128 * 9 Translation table to send to available buckets*/
573 k = 0;
574 c1 = 3;
575 c2 = 0;
576 for (i = 0; i < 64; i++) {
2db0083d
A		 577 /*
578 * On use_bkt set the b0, b1 are used, else
6f98b1a2
GR		 579 * the 4 classes are used, here implemented
580 * a logic to distribute the packets to the
581 * buckets equally or based on the class
582 */
583 c1 = (c1 + 1) & 3;
584 c2 = (c1 + 1) & 3;
585 b1 = bkts[k];
586 k = (k + 1) % j;
587 b2 = bkts[k];
588 k = (k + 1) % j;
6f98b1a2
GR		 589
590 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
591 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
592 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
3a694d0c 593 i, b1, b2, c1, c2);
6f98b1a2
GR		 594 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
595 c1 = c2;
596 }
597}
598
599static void xlr_config_parser(struct xlr_net_priv *priv)
600{
601 u32 val;
602
603 /* Mark it as ETHERNET type */
604 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
605
606 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
607 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
3a694d0c 608 ((0x7f << 8) | (1 << 1)));
6f98b1a2
GR		 609
610 /* configure the parser : L2 Type is configured in the bootloader */
611 /* extract IP: src, dest protocol */
612 xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
3a694d0c
LGL		 613 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
614 (0x0800 << 0));
6f98b1a2 615 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
3a694d0c
LGL		 616 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
617 (16 << 4) | 4);
6f98b1a2
GR		 618
619 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
620 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
621 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
622 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
623 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
624 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
625
626 xlr_config_translate_table(priv);
627}
628
629static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
630{
631 unsigned long timeout, stoptime, checktime;
632 int timedout;
633
634 /* 100ms timeout*/
635 timeout = msecs_to_jiffies(100);
636 stoptime = jiffies + timeout;
637 timedout = 0;
638
639 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
640
641 /* Write the data which starts the write cycle */
c8550db5 642 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
6f98b1a2
GR		 643
644 /* poll for the read cycle to complete */
645 while (!timedout) {
646 checktime = jiffies;
647 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
648 break;
649 timedout = time_after(checktime, stoptime);
650 }
651 if (timedout) {
652 pr_info("Phy device write err: device busy");
653 return -EBUSY;
654 }
655
656 return 0;
657}
658
659static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
660{
661 unsigned long timeout, stoptime, checktime;
662 int timedout;
663
664 /* 100ms timeout*/
665 timeout = msecs_to_jiffies(100);
666 stoptime = jiffies + timeout;
667 timedout = 0;
668
669 /* setup the phy reg to be used */
670 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
3a694d0c 671 (phy_addr << 8) | (regnum << 0));
6f98b1a2
GR		 672
673 /* Issue the read command */
674 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
3a694d0c 675 (1 << O_MII_MGMT_COMMAND__rstat));
6f98b1a2 676
6f98b1a2
GR		 677 /* poll for the read cycle to complete */
678 while (!timedout) {
679 checktime = jiffies;
680 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
681 break;
682 timedout = time_after(checktime, stoptime);
683 }
684 if (timedout) {
685 pr_info("Phy device read err: device busy");
686 return -EBUSY;
687 }
688
689 /* clear the read cycle */
690 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
691
692 /* Read the data */
693 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
694}
695
696static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
697{
698 struct xlr_net_priv *priv = bus->priv;
699 int ret;
700
701 ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
702 dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
3a694d0c 703 phy_addr, regnum, val, ret);
6f98b1a2
GR		 704 return ret;
705}
706
707static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
708{
709 struct xlr_net_priv *priv = bus->priv;
710 int ret;
711
712 ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
713 dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
3a694d0c 714 phy_addr, regnum, ret);
6f98b1a2
GR		 715 return ret;
716}
717
2db0083d
A		 718/*
719 * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
6f98b1a2
GR		 720 * which can be configured either SGMII or RGMII, considered SGMII
721 * by default, if board setup to RGMII the port_type need to set
722 * accordingly.Serdes and PCS layer need to configured for SGMII
723 */
724static void xlr_sgmii_init(struct xlr_net_priv *priv)
725{
726 int phy;
727
728 xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
729 xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
730 xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
731 xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
732 xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
733 xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
734 xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
735 xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
736 xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
737 xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
738 xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
739
740 /* program GPIO values for serdes init parameters */
741 xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
742 xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
743
744 xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
745 xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
746
747 /* enable autoneg - more magic */
e1a083be 748 phy = priv->phy_addr % 4 + 27;
6f98b1a2
GR		 749 xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
750 xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
751}
752
753void xlr_set_gmac_speed(struct xlr_net_priv *priv)
754{
3fe01e24 755 struct phy_device *phydev = xlr_get_phydev(priv);
6f98b1a2
GR		 756 int speed;
757
758 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
759 xlr_sgmii_init(priv);
760
761 if (phydev->speed != priv->phy_speed) {
6f98b1a2
GR		 762 speed = phydev->speed;
763 if (speed == SPEED_1000) {
764 /* Set interface to Byte mode */
765 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
766 priv->phy_speed = speed;
767 } else if (speed == SPEED_100 || speed == SPEED_10) {
768 /* Set interface to Nibble mode */
769 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
770 priv->phy_speed = speed;
771 }
88789fab 772 /* Set SGMII speed in Interface control reg */
6f98b1a2
GR		 773 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
774 if (speed == SPEED_10)
775 xlr_nae_wreg(priv->base_addr,
3a694d0c
LGL		 776 R_INTERFACE_CONTROL,
777 SGMII_SPEED_10);
6f98b1a2
GR		 778 if (speed == SPEED_100)
779 xlr_nae_wreg(priv->base_addr,
3a694d0c
LGL		 780 R_INTERFACE_CONTROL,
781 SGMII_SPEED_100);
6f98b1a2
GR		 782 if (speed == SPEED_1000)
783 xlr_nae_wreg(priv->base_addr,
3a694d0c
LGL		 784 R_INTERFACE_CONTROL,
785 SGMII_SPEED_1000);
6f98b1a2
GR		 786 }
787 if (speed == SPEED_10)
788 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
789 if (speed == SPEED_100)
790 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
791 if (speed == SPEED_1000)
792 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
793 }
794 pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
795}
796
797static void xlr_gmac_link_adjust(struct net_device *ndev)
798{
799 struct xlr_net_priv *priv = netdev_priv(ndev);
3fe01e24 800 struct phy_device *phydev = xlr_get_phydev(priv);
6f98b1a2
GR		 801 u32 intreg;
802
803 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
804 if (phydev->link) {
805 if (phydev->speed != priv->phy_speed) {
6f98b1a2 806 xlr_set_gmac_speed(priv);
f8397bc6 807 pr_info("gmac%d : Link up\n", priv->port_id);
6f98b1a2
GR		 808 }
809 } else {
6f98b1a2 810 xlr_set_gmac_speed(priv);
f8397bc6 811 pr_info("gmac%d : Link down\n", priv->port_id);
6f98b1a2
GR		 812 }
813}
814
815static int xlr_mii_probe(struct xlr_net_priv *priv)
816{
3fe01e24 817 struct phy_device *phydev = xlr_get_phydev(priv);
6f98b1a2
GR		 818
819 if (!phydev) {
820 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
821 return -ENODEV;
822 }
823
824 /* Attach MAC to PHY */
84eff6d1 825 phydev = phy_connect(priv->ndev, phydev_name(phydev),
968b4e6b 826 xlr_gmac_link_adjust, priv->nd->phy_interface);
6f98b1a2
GR		 827
828 if (IS_ERR(phydev)) {
829 pr_err("could not attach PHY\n");
830 return PTR_ERR(phydev);
831 }
832 phydev->supported &= (ADVERTISED_10baseT_Full
833 | ADVERTISED_10baseT_Half
834 | ADVERTISED_100baseT_Full
835 | ADVERTISED_100baseT_Half
836 | ADVERTISED_1000baseT_Full
837 | ADVERTISED_Autoneg
838 | ADVERTISED_MII);
839
840 phydev->advertising = phydev->supported;
2220943a 841 phy_attached_info(phydev);
6f98b1a2
GR		 842 return 0;
843}
844
845static int xlr_setup_mdio(struct xlr_net_priv *priv,
3a694d0c 846 struct platform_device *pdev)
6f98b1a2
GR		 847{
848 int err;
849
6f98b1a2
GR		 850 priv->mii_bus = mdiobus_alloc();
851 if (!priv->mii_bus) {
852 pr_err("mdiobus alloc failed\n");
853 return -ENOMEM;
854 }
855
856 priv->mii_bus->priv = priv;
857 priv->mii_bus->name = "xlr-mdio";
858 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
3a694d0c 859 priv->mii_bus->name, priv->port_id);
6f98b1a2
GR		 860 priv->mii_bus->read = xlr_mii_read;
861 priv->mii_bus->write = xlr_mii_write;
862 priv->mii_bus->parent = &pdev->dev;
6f98b1a2
GR		 863
864 /* Scan only the enabled address */
865 priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
866
867 /* setting clock divisor to 54 */
868 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
869
870 err = mdiobus_register(priv->mii_bus);
871 if (err) {
872 mdiobus_free(priv->mii_bus);
873 pr_err("mdio bus registration failed\n");
874 return err;
875 }
876
9d2ea4de 877 pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
6f98b1a2
GR		 878 err = xlr_mii_probe(priv);
879 if (err) {
880 mdiobus_free(priv->mii_bus);
881 return err;
882 }
883 return 0;
884}
885
886static void xlr_port_enable(struct xlr_net_priv *priv)
887{
888 u32 prid = (read_c0_prid() & 0xf000);
889
890 /* Setup MAC_CONFIG reg if (xls & rgmii) */
891 if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
3a694d0c 892 priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
6f98b1a2 893 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
3a694d0c
LGL		 894 (1 << O_RX_CONTROL__RGMII),
895 (1 << O_RX_CONTROL__RGMII));
6f98b1a2
GR		 896
897 /* Rx Tx enable */
898 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
3a694d0c
LGL		 899 ((1 << O_MAC_CONFIG_1__rxen) |
900 (1 << O_MAC_CONFIG_1__txen) |
901 (1 << O_MAC_CONFIG_1__rxfc) |
902 (1 << O_MAC_CONFIG_1__txfc)),
903 ((1 << O_MAC_CONFIG_1__rxen) |
904 (1 << O_MAC_CONFIG_1__txen) |
905 (1 << O_MAC_CONFIG_1__rxfc) |
906 (1 << O_MAC_CONFIG_1__txfc)));
6f98b1a2
GR		 907
908 /* Setup tx control reg */
909 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
a5cecac6
LGL		 910 ((1 << O_TX_CONTROL__TXENABLE) |
911 (512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
6f98b1a2
GR		 912
913 /* Setup rx control reg */
914 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
a5cecac6
LGL		 915 1 << O_RX_CONTROL__RXENABLE,
916 1 << O_RX_CONTROL__RXENABLE);
6f98b1a2
GR		 917}
918
919static void xlr_port_disable(struct xlr_net_priv *priv)
920{
921 /* Setup MAC_CONFIG reg */
922 /* Rx Tx disable*/
923 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
3a694d0c
LGL		 924 ((1 << O_MAC_CONFIG_1__rxen) |
925 (1 << O_MAC_CONFIG_1__txen) |
926 (1 << O_MAC_CONFIG_1__rxfc) |
927 (1 << O_MAC_CONFIG_1__txfc)), 0x0);
6f98b1a2
GR		 928
929 /* Setup tx control reg */
930 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
a5cecac6
LGL		 931 ((1 << O_TX_CONTROL__TXENABLE) |
932 (512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
6f98b1a2
GR		 933
934 /* Setup rx control reg */
935 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
a5cecac6 936 1 << O_RX_CONTROL__RXENABLE, 0);
6f98b1a2
GR		 937}
938
f8397bc6
GR		 939/*
940 * Initialization of gmac
941 */
6f98b1a2 942static int xlr_gmac_init(struct xlr_net_priv *priv,
3a694d0c 943 struct platform_device *pdev)
6f98b1a2
GR		 944{
945 int ret;
946
947 pr_info("Initializing the gmac%d\n", priv->port_id);
948
949 xlr_port_disable(priv);
f8397bc6 950
6f98b1a2 951 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
a5cecac6
LGL		 952 (1 << O_DESC_PACK_CTRL__MAXENTRY) |
953 (BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
954 (1600 << O_DESC_PACK_CTRL__REGULARSIZE));
6f98b1a2
GR		 955
956 ret = xlr_setup_mdio(priv, pdev);
957 if (ret)
958 return ret;
959 xlr_port_enable(priv);
960
961 /* Enable Full-duplex/1000Mbps/CRC */
962 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
963 /* speed 2.5Mhz */
964 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
965 /* Setup Interrupt mask reg */
a5cecac6
LGL		 966 xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
967 (1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
968 (1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
969 (1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
6f98b1a2
GR		 970
971 /* Clear all stats */
a5cecac6 972 xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
3a694d0c 973 xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
6f98b1a2
GR		 974 return 0;
975}
976
977static int xlr_net_probe(struct platform_device *pdev)
978{
979 struct xlr_net_priv *priv = NULL;
980 struct net_device *ndev;
981 struct resource *res;
f8397bc6
GR		 982 struct xlr_adapter *adapter;
983 int err, port;
6f98b1a2 984
f8397bc6
GR		 985 pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
986 /*
987 * Allocate our adapter data structure and attach it to the device.
988 */
5841b903 989 adapter = devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
1cbe7adb
MM		 990 if (!adapter)
991 return -ENOMEM;
6f98b1a2 992
f8397bc6
GR		 993 /*
994 * XLR and XLS have 1 and 2 NAE controller respectively
995 * Each controller has 4 gmac ports, mapping each controller
996 * under one parent device, 4 gmac ports under one device.
997 */
800325fc 998 for (port = 0; port < pdev->num_resources / 2; port++) {
f8397bc6
GR		 999 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1000 if (!ndev) {
0b204161
PS		 1001 dev_err(&pdev->dev,
1002 "Allocation of Ethernet device failed\n");
f8397bc6
GR		 1003 return -ENOMEM;
1004 }
6f98b1a2 1005
f8397bc6
GR		 1006 priv = netdev_priv(ndev);
1007 priv->pdev = pdev;
1008 priv->ndev = ndev;
1009 priv->port_id = (pdev->id * 4) + port;
1010 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1011 res = platform_get_resource(pdev, IORESOURCE_MEM, port);
f8397bc6
GR		 1012 priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
1013 if (IS_ERR(priv->base_addr)) {
1014 err = PTR_ERR(priv->base_addr);
1015 goto err_gmac;
1016 }
1017 priv->adapter = adapter;
1018 adapter->netdev[port] = ndev;
6f98b1a2 1019
f8397bc6 1020 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
4b032eb7 1021 if (!res) {
0b204161
PS		 1022 dev_err(&pdev->dev, "No irq resource for MAC %d\n",
1023 priv->port_id);
f8397bc6
GR		 1024 err = -ENODEV;
1025 goto err_gmac;
1026 }
6f98b1a2 1027
f8397bc6 1028 ndev->irq = res->start;
6f98b1a2 1029
f8397bc6
GR		 1030 priv->phy_addr = priv->nd->phy_addr[port];
1031 priv->tx_stnid = priv->nd->tx_stnid[port];
1032 priv->mii_addr = priv->nd->mii_addr;
1033 priv->serdes_addr = priv->nd->serdes_addr;
1034 priv->pcs_addr = priv->nd->pcs_addr;
1035 priv->gpio_addr = priv->nd->gpio_addr;
6f98b1a2 1036
f8397bc6
GR		 1037 ndev->netdev_ops = &xlr_netdev_ops;
1038 ndev->watchdog_timeo = HZ;
1039
1040 /* Setup Mac address and Rx mode */
1041 eth_hw_addr_random(ndev);
1042 xlr_hw_set_mac_addr(ndev);
1043 xlr_set_rx_mode(ndev);
6f98b1a2 1044
f8397bc6
GR		 1045 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1046 ndev->ethtool_ops = &xlr_ethtool_ops;
1047 SET_NETDEV_DEV(ndev, &pdev->dev);
6f98b1a2 1048
6f98b1a2
GR		 1049 xlr_config_fifo_spill_area(priv);
1050 /* Configure PDE to Round-Robin pkt distribution */
1051 xlr_config_pde(priv);
1052 xlr_config_parser(priv);
f8397bc6
GR		 1053
1054 /* Call init with respect to port */
1055 if (strcmp(res->name, "gmac") == 0) {
1056 err = xlr_gmac_init(priv, pdev);
1057 if (err) {
0b204161
PS		 1058 dev_err(&pdev->dev, "gmac%d init failed\n",
1059 priv->port_id);
f8397bc6
GR		 1060 goto err_gmac;
1061 }
1062 }
1063
1064 if (priv->port_id == 0 || priv->port_id == 4) {
1065 err = xlr_config_common(priv);
1066 if (err)
1067 goto err_netdev;
1068 }
1069
1070 err = register_netdev(ndev);
6f98b1a2 1071 if (err) {
0b204161
PS		 1072 dev_err(&pdev->dev,
1073 "Registering netdev failed for gmac%d\n",
1074 priv->port_id);
f8397bc6 1075 goto err_netdev;
6f98b1a2 1076 }
f8397bc6 1077 platform_set_drvdata(pdev, priv);
6f98b1a2
GR		 1078 }
1079
6f98b1a2
GR		 1080 return 0;
1081
1082err_netdev:
1083 mdiobus_free(priv->mii_bus);
1084err_gmac:
1085 free_netdev(ndev);
1086 return err;
1087}
1088
1089static int xlr_net_remove(struct platform_device *pdev)
1090{
1091 struct xlr_net_priv *priv = platform_get_drvdata(pdev);
ebb10d8e 1092
6f98b1a2
GR		 1093 unregister_netdev(priv->ndev);
1094 mdiobus_unregister(priv->mii_bus);
1095 mdiobus_free(priv->mii_bus);
1096 free_netdev(priv->ndev);
1097 return 0;
1098}
1099
1100static struct platform_driver xlr_net_driver = {
1101 .probe = xlr_net_probe,
1102 .remove = xlr_net_remove,
1103 .driver = {
1104 .name = "xlr-net",
6f98b1a2
GR		 1105 },
1106};
1107
1108module_platform_driver(xlr_net_driver);
1109
1110MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1111MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1112MODULE_LICENSE("Dual BSD/GPL");
1113MODULE_ALIAS("platform:xlr-net");
Linux 6.x block layer and io_uring tree(s)