Commit | Line | Data |
---|---|---|
7d6bc569 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
335bbd9e SP |
2 | /* |
3 | * BRIEF MODULE DESCRIPTION | |
03f152e3 JC |
4 | * PCI init for Ralink RT2880 solution |
5 | * | |
335bbd9e | 6 | * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw) |
03f152e3 | 7 | * |
03f152e3 JC |
8 | * May 2007 Bruce Chang |
9 | * Initial Release | |
10 | * | |
11 | * May 2009 Bruce Chang | |
12 | * support RT2880/RT3883 PCIe | |
13 | * | |
14 | * May 2011 Bruce Chang | |
15 | * support RT6855/MT7620 PCIe | |
03f152e3 JC |
16 | */ |
17 | ||
cd7d07db | 18 | #include <linux/bitops.h> |
03f152e3 | 19 | #include <linux/delay.h> |
07420a02 | 20 | #include <linux/gpio/consumer.h> |
bd1a05bd | 21 | #include <linux/iopoll.h> |
cd7d07db | 22 | #include <linux/module.h> |
03f152e3 | 23 | #include <linux/of.h> |
8571c62d SP |
24 | #include <linux/of_address.h> |
25 | #include <linux/of_irq.h> | |
cd7d07db SP |
26 | #include <linux/of_pci.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/pci.h> | |
61f9bde6 | 29 | #include <linux/phy/phy.h> |
03f152e3 | 30 | #include <linux/platform_device.h> |
cd7d07db | 31 | #include <linux/reset.h> |
b483b4e4 | 32 | #include <linux/sys_soc.h> |
c0f784ba | 33 | #include <mt7621.h> |
cd7d07db | 34 | #include <ralink_regs.h> |
03f152e3 | 35 | |
8571c62d SP |
36 | #include "../../pci/pci.h" |
37 | ||
89e9f6e6 | 38 | /* sysctl */ |
07420a02 | 39 | #define MT7621_GPIO_MODE 0x60 |
89e9f6e6 | 40 | |
a4b2eb91 SP |
41 | /* MediaTek specific configuration registers */ |
42 | #define PCIE_FTS_NUM 0x70c | |
43 | #define PCIE_FTS_NUM_MASK GENMASK(15, 8) | |
0ae0cf50 | 44 | #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8) |
a4b2eb91 | 45 | |
a934d901 | 46 | /* rt_sysc_membase relative registers */ |
36e92f61 | 47 | #define RALINK_CLKCFG1 0x30 |
a934d901 SP |
48 | |
49 | /* Host-PCI bridge registers */ | |
152f3893 SP |
50 | #define RALINK_PCI_PCICFG_ADDR 0x0000 |
51 | #define RALINK_PCI_PCIMSK_ADDR 0x000C | |
a934d901 SP |
52 | #define RALINK_PCI_CONFIG_ADDR 0x0020 |
53 | #define RALINK_PCI_CONFIG_DATA 0x0024 | |
54 | #define RALINK_PCI_MEMBASE 0x0028 | |
55 | #define RALINK_PCI_IOBASE 0x002C | |
d4e3a1f6 | 56 | |
a934d901 | 57 | /* PCICFG virtual bridges */ |
9a5e71a6 SP |
58 | #define PCIE_P2P_MAX 3 |
59 | #define PCIE_P2P_BR_DEVNUM_SHIFT(p) (16 + (p) * 4) | |
60 | #define PCIE_P2P_BR_DEVNUM0_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(0) | |
61 | #define PCIE_P2P_BR_DEVNUM1_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(1) | |
62 | #define PCIE_P2P_BR_DEVNUM2_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(2) | |
63 | #define PCIE_P2P_BR_DEVNUM_MASK 0xf | |
64 | #define PCIE_P2P_BR_DEVNUM_MASK_FULL (0xfff << PCIE_P2P_BR_DEVNUM0_SHIFT) | |
e2200279 | 65 | |
a934d901 SP |
66 | /* PCIe RC control registers */ |
67 | #define MT7621_PCIE_OFFSET 0x2000 | |
68 | #define MT7621_NEXT_PORT 0x1000 | |
69 | ||
e38bb175 SP |
70 | #define RALINK_PCI_BAR0SETUP_ADDR 0x0010 |
71 | #define RALINK_PCI_IMBASEBAR0_ADDR 0x0018 | |
72 | #define RALINK_PCI_ID 0x0030 | |
73 | #define RALINK_PCI_CLASS 0x0034 | |
74 | #define RALINK_PCI_SUBID 0x0038 | |
75 | #define RALINK_PCI_STATUS 0x0050 | |
d4e3a1f6 | 76 | |
a934d901 | 77 | /* Some definition values */ |
301c15be SP |
78 | #define PCIE_REVISION_ID BIT(0) |
79 | #define PCIE_CLASS_CODE (0x60400 << 8) | |
80 | #define PCIE_BAR_MAP_MAX GENMASK(30, 16) | |
81 | #define PCIE_BAR_ENABLE BIT(0) | |
82 | #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) | |
83 | #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) | |
bd1a05bd | 84 | #define PCIE_PORT_LINKUP BIT(0) |
301c15be | 85 | |
a934d901 | 86 | #define MEMORY_BASE 0x0 |
07420a02 SP |
87 | #define PERST_MODE_MASK GENMASK(11, 10) |
88 | #define PERST_MODE_GPIO BIT(10) | |
475fe234 | 89 | #define PERST_DELAY_MS 100 |
6b767904 | 90 | |
8571c62d SP |
91 | /** |
92 | * struct mt7621_pcie_port - PCIe port information | |
ad9c87e1 | 93 | * @base: I/O mapped register base |
8571c62d SP |
94 | * @list: port list |
95 | * @pcie: pointer to PCIe host info | |
61f9bde6 | 96 | * @phy: pointer to PHY control block |
ad9c87e1 | 97 | * @pcie_rst: pointer to port reset control |
b27e35f9 | 98 | * @gpio_rst: gpio reset |
ad9c87e1 | 99 | * @slot: port slot |
a41a1f86 | 100 | * @enabled: indicates if port is enabled |
8571c62d SP |
101 | */ |
102 | struct mt7621_pcie_port { | |
103 | void __iomem *base; | |
104 | struct list_head list; | |
105 | struct mt7621_pcie *pcie; | |
61f9bde6 | 106 | struct phy *phy; |
ad9c87e1 | 107 | struct reset_control *pcie_rst; |
b27e35f9 | 108 | struct gpio_desc *gpio_rst; |
ad9c87e1 | 109 | u32 slot; |
a41a1f86 | 110 | bool enabled; |
8571c62d SP |
111 | }; |
112 | ||
113 | /** | |
114 | * struct mt7621_pcie - PCIe host information | |
115 | * @base: IO Mapped Register Base | |
116 | * @io: IO resource | |
117 | * @mem: non-prefetchable memory resource | |
118 | * @busn: bus range | |
119 | * @offset: IO / Memory offset | |
120 | * @dev: Pointer to PCIe device | |
09dd629e | 121 | * @io_map_base: virtual memory base address for io |
8571c62d | 122 | * @ports: pointer to PCIe port information |
b483b4e4 SP |
123 | * @resets_inverted: depends on chip revision |
124 | * reset lines are inverted. | |
8571c62d SP |
125 | */ |
126 | struct mt7621_pcie { | |
127 | void __iomem *base; | |
128 | struct device *dev; | |
129 | struct resource io; | |
130 | struct resource mem; | |
131 | struct resource busn; | |
132 | struct { | |
133 | resource_size_t mem; | |
134 | resource_size_t io; | |
135 | } offset; | |
09dd629e | 136 | unsigned long io_map_base; |
8571c62d | 137 | struct list_head ports; |
b483b4e4 | 138 | bool resets_inverted; |
8571c62d SP |
139 | }; |
140 | ||
52ed727c SP |
141 | static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) |
142 | { | |
143 | return readl(pcie->base + reg); | |
144 | } | |
145 | ||
146 | static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) | |
147 | { | |
148 | writel(val, pcie->base + reg); | |
149 | } | |
150 | ||
9a5e71a6 SP |
151 | static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set) |
152 | { | |
153 | u32 val = readl(pcie->base + reg); | |
154 | ||
155 | val &= ~clr; | |
156 | val |= set; | |
157 | writel(val, pcie->base + reg); | |
158 | } | |
159 | ||
c8242bef SP |
160 | static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg) |
161 | { | |
162 | return readl(port->base + reg); | |
163 | } | |
164 | ||
165 | static inline void pcie_port_write(struct mt7621_pcie_port *port, | |
166 | u32 val, u32 reg) | |
167 | { | |
168 | writel(val, port->base + reg); | |
169 | } | |
170 | ||
2427d174 SP |
171 | static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot, |
172 | unsigned int func, unsigned int where) | |
173 | { | |
174 | return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) | | |
175 | (func << 8) | (where & 0xfc) | 0x80000000; | |
176 | } | |
177 | ||
8571c62d SP |
178 | static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, |
179 | unsigned int devfn, int where) | |
180 | { | |
181 | struct mt7621_pcie *pcie = bus->sysdata; | |
182 | u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), | |
183 | PCI_FUNC(devfn), where); | |
184 | ||
185 | writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR); | |
186 | ||
8594351a | 187 | return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); |
8571c62d | 188 | } |
03f152e3 | 189 | |
8571c62d SP |
190 | struct pci_ops mt7621_pci_ops = { |
191 | .map_bus = mt7621_pcie_map_bus, | |
192 | .read = pci_generic_config_read, | |
193 | .write = pci_generic_config_write, | |
03f152e3 JC |
194 | }; |
195 | ||
ce3368dc | 196 | static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) |
03f152e3 | 197 | { |
c0431f4f | 198 | u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); |
9f999b41 SP |
199 | |
200 | pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); | |
8594351a | 201 | return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); |
03f152e3 JC |
202 | } |
203 | ||
ce3368dc SP |
204 | static void write_config(struct mt7621_pcie *pcie, unsigned int dev, |
205 | u32 reg, u32 val) | |
03f152e3 | 206 | { |
f8427fae | 207 | u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); |
9f999b41 SP |
208 | |
209 | pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); | |
8594351a | 210 | pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); |
03f152e3 JC |
211 | } |
212 | ||
b27e35f9 | 213 | static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port) |
07420a02 | 214 | { |
b27e35f9 SP |
215 | if (port->gpio_rst) |
216 | gpiod_set_value(port->gpio_rst, 1); | |
07420a02 SP |
217 | } |
218 | ||
b27e35f9 | 219 | static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port) |
07420a02 | 220 | { |
b27e35f9 SP |
221 | if (port->gpio_rst) |
222 | gpiod_set_value(port->gpio_rst, 0); | |
07420a02 SP |
223 | } |
224 | ||
225 | static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port) | |
226 | { | |
227 | return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0; | |
228 | } | |
229 | ||
5ca61dff SP |
230 | static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port) |
231 | { | |
232 | rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1); | |
233 | } | |
234 | ||
36e92f61 SP |
235 | static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port) |
236 | { | |
237 | rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1); | |
238 | } | |
239 | ||
e51844bf SP |
240 | static inline void mt7621_control_assert(struct mt7621_pcie_port *port) |
241 | { | |
b483b4e4 | 242 | struct mt7621_pcie *pcie = port->pcie; |
e51844bf | 243 | |
b483b4e4 | 244 | if (pcie->resets_inverted) |
e51844bf SP |
245 | reset_control_assert(port->pcie_rst); |
246 | else | |
247 | reset_control_deassert(port->pcie_rst); | |
248 | } | |
249 | ||
250 | static inline void mt7621_control_deassert(struct mt7621_pcie_port *port) | |
251 | { | |
b483b4e4 | 252 | struct mt7621_pcie *pcie = port->pcie; |
e51844bf | 253 | |
b483b4e4 | 254 | if (pcie->resets_inverted) |
e51844bf SP |
255 | reset_control_deassert(port->pcie_rst); |
256 | else | |
257 | reset_control_assert(port->pcie_rst); | |
258 | } | |
259 | ||
d9365507 | 260 | static void setup_cm_memory_region(struct mt7621_pcie *pcie) |
03f152e3 | 261 | { |
d9365507 SP |
262 | struct resource *mem_resource = &pcie->mem; |
263 | struct device *dev = pcie->dev; | |
03f152e3 | 264 | resource_size_t mask; |
8571c62d | 265 | |
03f152e3 | 266 | if (mips_cps_numiocu(0)) { |
d2bac2fd SP |
267 | /* |
268 | * FIXME: hardware doesn't accept mask values with 1s after | |
d4e3a1f6 | 269 | * 0s (e.g. 0xffef), so it would be great to warn if that's |
d2bac2fd SP |
270 | * about to happen |
271 | */ | |
03f152e3 JC |
272 | mask = ~(mem_resource->end - mem_resource->start); |
273 | ||
274 | write_gcr_reg1_base(mem_resource->start); | |
275 | write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); | |
d9365507 | 276 | dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", |
d4e3a1f6 N |
277 | (unsigned long long)read_gcr_reg1_base(), |
278 | (unsigned long long)read_gcr_reg1_mask()); | |
03f152e3 JC |
279 | } |
280 | } | |
281 | ||
8571c62d SP |
282 | static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie) |
283 | { | |
284 | struct device *dev = pcie->dev; | |
285 | struct device_node *node = dev->of_node; | |
286 | struct of_pci_range_parser parser; | |
287 | struct of_pci_range range; | |
288 | int err; | |
289 | ||
290 | if (of_pci_range_parser_init(&parser, node)) { | |
291 | dev_err(dev, "missing \"ranges\" property\n"); | |
292 | return -EINVAL; | |
293 | } | |
294 | ||
295 | for_each_of_pci_range(&parser, &range) { | |
8571c62d SP |
296 | switch (range.flags & IORESOURCE_TYPE_BITS) { |
297 | case IORESOURCE_IO: | |
09dd629e SP |
298 | pcie->io_map_base = |
299 | (unsigned long)ioremap(range.cpu_addr, | |
300 | range.size); | |
301 | of_pci_range_to_resource(&range, node, &pcie->io); | |
302 | pcie->io.start = range.cpu_addr; | |
303 | pcie->io.end = range.cpu_addr + range.size - 1; | |
8571c62d SP |
304 | pcie->offset.io = 0x00000000UL; |
305 | break; | |
306 | case IORESOURCE_MEM: | |
09dd629e | 307 | of_pci_range_to_resource(&range, node, &pcie->mem); |
8571c62d SP |
308 | pcie->offset.mem = 0x00000000UL; |
309 | break; | |
310 | } | |
8571c62d SP |
311 | } |
312 | ||
313 | err = of_pci_parse_bus_range(node, &pcie->busn); | |
314 | if (err < 0) { | |
315 | dev_err(dev, "failed to parse bus ranges property: %d\n", err); | |
316 | pcie->busn.name = node->name; | |
317 | pcie->busn.start = 0; | |
318 | pcie->busn.end = 0xff; | |
319 | pcie->busn.flags = IORESOURCE_BUS; | |
320 | } | |
321 | ||
09dd629e SP |
322 | set_io_port_base(pcie->io_map_base); |
323 | ||
8571c62d SP |
324 | return 0; |
325 | } | |
326 | ||
ad9c87e1 SP |
327 | static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, |
328 | struct device_node *node, | |
329 | int slot) | |
330 | { | |
331 | struct mt7621_pcie_port *port; | |
332 | struct device *dev = pcie->dev; | |
333 | struct device_node *pnode = dev->of_node; | |
334 | struct resource regs; | |
61f9bde6 | 335 | char name[10]; |
ad9c87e1 SP |
336 | int err; |
337 | ||
338 | port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); | |
339 | if (!port) | |
340 | return -ENOMEM; | |
341 | ||
342 | err = of_address_to_resource(pnode, slot + 1, ®s); | |
343 | if (err) { | |
344 | dev_err(dev, "missing \"reg\" property\n"); | |
345 | return err; | |
346 | } | |
347 | ||
348 | port->base = devm_ioremap_resource(dev, ®s); | |
349 | if (IS_ERR(port->base)) | |
350 | return PTR_ERR(port->base); | |
351 | ||
352 | snprintf(name, sizeof(name), "pcie%d", slot); | |
ad9c87e1 SP |
353 | port->pcie_rst = devm_reset_control_get_exclusive(dev, name); |
354 | if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) { | |
355 | dev_err(dev, "failed to get pcie%d reset control\n", slot); | |
356 | return PTR_ERR(port->pcie_rst); | |
357 | } | |
358 | ||
61f9bde6 SP |
359 | snprintf(name, sizeof(name), "pcie-phy%d", slot); |
360 | port->phy = devm_phy_get(dev, name); | |
bf516f41 | 361 | if (IS_ERR(port->phy) && slot != 1) |
61f9bde6 SP |
362 | return PTR_ERR(port->phy); |
363 | ||
b27e35f9 SP |
364 | port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, |
365 | GPIOD_OUT_LOW); | |
825c6f47 | 366 | if (IS_ERR(port->gpio_rst)) { |
6bdf0ddd SP |
367 | dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot); |
368 | return PTR_ERR(port->gpio_rst); | |
825c6f47 | 369 | } |
b27e35f9 | 370 | |
ad9c87e1 SP |
371 | port->slot = slot; |
372 | port->pcie = pcie; | |
373 | ||
374 | INIT_LIST_HEAD(&port->list); | |
375 | list_add_tail(&port->list, &pcie->ports); | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
8571c62d SP |
380 | static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) |
381 | { | |
382 | struct device *dev = pcie->dev; | |
ad9c87e1 | 383 | struct device_node *node = dev->of_node, *child; |
8571c62d | 384 | struct resource regs; |
8571c62d SP |
385 | int err; |
386 | ||
8571c62d SP |
387 | err = of_address_to_resource(node, 0, ®s); |
388 | if (err) { | |
389 | dev_err(dev, "missing \"reg\" property\n"); | |
390 | return err; | |
391 | } | |
392 | ||
393 | pcie->base = devm_ioremap_resource(dev, ®s); | |
394 | if (IS_ERR(pcie->base)) | |
395 | return PTR_ERR(pcie->base); | |
396 | ||
ad9c87e1 SP |
397 | for_each_available_child_of_node(node, child) { |
398 | int slot; | |
399 | ||
400 | err = of_pci_get_devfn(child); | |
401 | if (err < 0) { | |
2125a441 | 402 | of_node_put(child); |
ad9c87e1 SP |
403 | dev_err(dev, "failed to parse devfn: %d\n", err); |
404 | return err; | |
405 | } | |
406 | ||
407 | slot = PCI_SLOT(err); | |
408 | ||
409 | err = mt7621_pcie_parse_port(pcie, child, slot); | |
2125a441 ND |
410 | if (err) { |
411 | of_node_put(child); | |
ad9c87e1 | 412 | return err; |
2125a441 | 413 | } |
ad9c87e1 SP |
414 | } |
415 | ||
8571c62d SP |
416 | return 0; |
417 | } | |
418 | ||
4fdf3abc | 419 | static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) |
745eeeac SP |
420 | { |
421 | struct mt7621_pcie *pcie = port->pcie; | |
422 | struct device *dev = pcie->dev; | |
423 | u32 slot = port->slot; | |
61f9bde6 | 424 | int err; |
745eeeac | 425 | |
61f9bde6 SP |
426 | err = phy_init(port->phy); |
427 | if (err) { | |
428 | dev_err(dev, "failed to initialize port%d phy\n", slot); | |
07420a02 | 429 | return err; |
61f9bde6 SP |
430 | } |
431 | ||
432 | err = phy_power_on(port->phy); | |
433 | if (err) { | |
434 | dev_err(dev, "failed to power on port%d phy\n", slot); | |
cdf6f83b | 435 | phy_exit(port->phy); |
07420a02 | 436 | return err; |
745eeeac SP |
437 | } |
438 | ||
61f9bde6 | 439 | port->enabled = true; |
3beb6da5 | 440 | |
745eeeac SP |
441 | return 0; |
442 | } | |
443 | ||
b27e35f9 SP |
444 | static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie) |
445 | { | |
446 | struct mt7621_pcie_port *port; | |
447 | ||
448 | list_for_each_entry(port, &pcie->ports, list) { | |
449 | /* PCIe RC reset assert */ | |
450 | mt7621_control_assert(port); | |
451 | ||
452 | /* PCIe EP reset assert */ | |
453 | mt7621_rst_gpio_pcie_assert(port); | |
454 | } | |
455 | ||
475fe234 | 456 | mdelay(PERST_DELAY_MS); |
b27e35f9 SP |
457 | } |
458 | ||
459 | static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie) | |
460 | { | |
461 | struct mt7621_pcie_port *port; | |
462 | ||
463 | list_for_each_entry(port, &pcie->ports, list) | |
464 | mt7621_control_deassert(port); | |
465 | } | |
466 | ||
467 | static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie) | |
468 | { | |
469 | struct mt7621_pcie_port *port; | |
470 | ||
471 | list_for_each_entry(port, &pcie->ports, list) | |
472 | mt7621_rst_gpio_pcie_deassert(port); | |
473 | ||
475fe234 | 474 | mdelay(PERST_DELAY_MS); |
b27e35f9 SP |
475 | } |
476 | ||
cd910f19 SP |
477 | static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) |
478 | { | |
479 | struct device *dev = pcie->dev; | |
480 | struct mt7621_pcie_port *port, *tmp; | |
481 | int err; | |
482 | ||
07420a02 SP |
483 | rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE); |
484 | ||
b27e35f9 SP |
485 | mt7621_pcie_reset_assert(pcie); |
486 | mt7621_pcie_reset_rc_deassert(pcie); | |
07420a02 | 487 | |
cd910f19 SP |
488 | list_for_each_entry_safe(port, tmp, &pcie->ports, list) { |
489 | u32 slot = port->slot; | |
490 | ||
bf516f41 SP |
491 | if (slot == 1) { |
492 | port->enabled = true; | |
493 | continue; | |
494 | } | |
495 | ||
cd910f19 SP |
496 | err = mt7621_pcie_init_port(port); |
497 | if (err) { | |
498 | dev_err(dev, "Initiating port %d failed\n", slot); | |
499 | list_del(&port->list); | |
500 | } | |
501 | } | |
b8d97d43 | 502 | |
b27e35f9 | 503 | mt7621_pcie_reset_ep_deassert(pcie); |
07420a02 SP |
504 | |
505 | list_for_each_entry(port, &pcie->ports, list) { | |
506 | u32 slot = port->slot; | |
507 | ||
508 | if (!mt7621_pcie_port_is_linkup(port)) { | |
509 | dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", | |
510 | slot); | |
5737cfe8 SP |
511 | if (slot != 1) |
512 | phy_power_off(port->phy); | |
07420a02 | 513 | mt7621_control_assert(port); |
36e92f61 | 514 | mt7621_pcie_port_clk_disable(port); |
07420a02 SP |
515 | port->enabled = false; |
516 | } | |
517 | } | |
cd910f19 SP |
518 | } |
519 | ||
07420a02 | 520 | static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) |
802a2f7b SP |
521 | { |
522 | struct mt7621_pcie *pcie = port->pcie; | |
523 | u32 slot = port->slot; | |
524 | u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT); | |
525 | u32 val; | |
802a2f7b SP |
526 | |
527 | /* enable pcie interrupt */ | |
528 | val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); | |
529 | val |= PCIE_PORT_INT_EN(slot); | |
530 | pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); | |
531 | ||
532 | /* map 2G DDR region */ | |
533 | pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, | |
534 | offset + RALINK_PCI_BAR0SETUP_ADDR); | |
535 | pcie_write(pcie, MEMORY_BASE, | |
536 | offset + RALINK_PCI_IMBASEBAR0_ADDR); | |
537 | ||
538 | /* configure class code and revision ID */ | |
539 | pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, | |
540 | offset + RALINK_PCI_CLASS); | |
802a2f7b SP |
541 | } |
542 | ||
a41a1f86 SP |
543 | static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) |
544 | { | |
545 | struct device *dev = pcie->dev; | |
546 | struct mt7621_pcie_port *port; | |
547 | u8 num_slots_enabled = 0; | |
a41a1f86 SP |
548 | u32 slot; |
549 | u32 val; | |
550 | ||
09dd629e SP |
551 | /* Setup MEMWIN and IOWIN */ |
552 | pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); | |
553 | pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE); | |
554 | ||
a41a1f86 | 555 | list_for_each_entry(port, &pcie->ports, list) { |
a41a1f86 | 556 | if (port->enabled) { |
5ca61dff | 557 | mt7621_pcie_port_clk_enable(port); |
07420a02 | 558 | mt7621_pcie_enable_port(port); |
7846a982 | 559 | dev_info(dev, "PCIE%d enabled\n", port->slot); |
a41a1f86 SP |
560 | num_slots_enabled++; |
561 | } | |
562 | } | |
563 | ||
564 | for (slot = 0; slot < num_slots_enabled; slot++) { | |
7c106cbb SP |
565 | val = read_config(pcie, slot, PCI_COMMAND); |
566 | val |= PCI_COMMAND_MASTER; | |
567 | write_config(pcie, slot, PCI_COMMAND, val); | |
a4b2eb91 SP |
568 | /* configure RC FTS number to 250 when it leaves L0s */ |
569 | val = read_config(pcie, slot, PCIE_FTS_NUM); | |
570 | val &= ~PCIE_FTS_NUM_MASK; | |
571 | val |= PCIE_FTS_NUM_L0(0x50); | |
572 | write_config(pcie, slot, PCIE_FTS_NUM, val); | |
a41a1f86 SP |
573 | } |
574 | } | |
575 | ||
e2200279 SP |
576 | static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie) |
577 | { | |
578 | u32 pcie_link_status = 0; | |
9a5e71a6 SP |
579 | u32 n; |
580 | int i; | |
581 | u32 p2p_br_devnum[PCIE_P2P_MAX]; | |
e2200279 SP |
582 | struct mt7621_pcie_port *port; |
583 | ||
584 | list_for_each_entry(port, &pcie->ports, list) { | |
585 | u32 slot = port->slot; | |
586 | ||
587 | if (port->enabled) | |
588 | pcie_link_status |= BIT(slot); | |
589 | } | |
590 | ||
591 | if (pcie_link_status == 0) | |
592 | return -1; | |
593 | ||
9a5e71a6 SP |
594 | n = 0; |
595 | for (i = 0; i < PCIE_P2P_MAX; i++) | |
596 | if (pcie_link_status & BIT(i)) | |
597 | p2p_br_devnum[i] = n++; | |
598 | ||
599 | for (i = 0; i < PCIE_P2P_MAX; i++) | |
600 | if ((pcie_link_status & BIT(i)) == 0) | |
601 | p2p_br_devnum[i] = n++; | |
602 | ||
0432184f | 603 | pcie_rmw(pcie, RALINK_PCI_PCICFG_ADDR, |
9a5e71a6 SP |
604 | PCIE_P2P_BR_DEVNUM_MASK_FULL, |
605 | (p2p_br_devnum[0] << PCIE_P2P_BR_DEVNUM0_SHIFT) | | |
606 | (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) | | |
607 | (p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT)); | |
e2200279 SP |
608 | |
609 | return 0; | |
610 | } | |
611 | ||
8571c62d SP |
612 | static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie, |
613 | struct list_head *res) | |
614 | { | |
615 | struct device *dev = pcie->dev; | |
8571c62d SP |
616 | |
617 | pci_add_resource_offset(res, &pcie->io, pcie->offset.io); | |
618 | pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem); | |
619 | pci_add_resource(res, &pcie->busn); | |
620 | ||
7f9b5833 | 621 | return devm_request_pci_bus_resources(dev, res); |
8571c62d SP |
622 | } |
623 | ||
624 | static int mt7621_pcie_register_host(struct pci_host_bridge *host, | |
625 | struct list_head *res) | |
626 | { | |
627 | struct mt7621_pcie *pcie = pci_host_bridge_priv(host); | |
628 | ||
629 | list_splice_init(res, &host->windows); | |
630 | host->busnr = pcie->busn.start; | |
631 | host->dev.parent = pcie->dev; | |
632 | host->ops = &mt7621_pci_ops; | |
4cafd03a | 633 | host->map_irq = of_irq_parse_and_map_pci; |
8571c62d SP |
634 | host->swizzle_irq = pci_common_swizzle; |
635 | host->sysdata = pcie; | |
636 | ||
637 | return pci_host_probe(host); | |
638 | } | |
639 | ||
b483b4e4 SP |
640 | static const struct soc_device_attribute mt7621_pci_quirks_match[] = { |
641 | { .soc_id = "mt7621", .revision = "E2" } | |
642 | }; | |
643 | ||
03f152e3 JC |
644 | static int mt7621_pci_probe(struct platform_device *pdev) |
645 | { | |
8571c62d | 646 | struct device *dev = &pdev->dev; |
b483b4e4 | 647 | const struct soc_device_attribute *attr; |
8571c62d SP |
648 | struct mt7621_pcie *pcie; |
649 | struct pci_host_bridge *bridge; | |
650 | int err; | |
8571c62d SP |
651 | LIST_HEAD(res); |
652 | ||
653 | if (!dev->of_node) | |
654 | return -ENODEV; | |
655 | ||
656 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); | |
657 | if (!bridge) | |
a80775d6 | 658 | return -ENOMEM; |
03f152e3 | 659 | |
8571c62d SP |
660 | pcie = pci_host_bridge_priv(bridge); |
661 | pcie->dev = dev; | |
662 | platform_set_drvdata(pdev, pcie); | |
663 | INIT_LIST_HEAD(&pcie->ports); | |
664 | ||
b483b4e4 SP |
665 | attr = soc_device_match(mt7621_pci_quirks_match); |
666 | if (attr) | |
667 | pcie->resets_inverted = true; | |
668 | ||
8571c62d SP |
669 | err = mt7621_pcie_parse_dt(pcie); |
670 | if (err) { | |
671 | dev_err(dev, "Parsing DT failed\n"); | |
672 | return err; | |
673 | } | |
674 | ||
09dd629e SP |
675 | err = mt7621_pci_parse_request_of_pci_ranges(pcie); |
676 | if (err) { | |
677 | dev_err(dev, "Error requesting pci resources from ranges"); | |
6bdf0ddd | 678 | return err; |
09dd629e SP |
679 | } |
680 | ||
8571c62d | 681 | /* set resources limits */ |
09dd629e SP |
682 | ioport_resource.start = pcie->io.start; |
683 | ioport_resource.end = pcie->io.end; | |
03f152e3 | 684 | |
cd910f19 | 685 | mt7621_pcie_init_ports(pcie); |
03f152e3 | 686 | |
e2200279 SP |
687 | err = mt7621_pcie_init_virtual_bridges(pcie); |
688 | if (err) { | |
689 | dev_err(dev, "Nothing is connected in virtual bridges. Exiting..."); | |
6bdf0ddd | 690 | return 0; |
03f152e3 | 691 | } |
03f152e3 | 692 | |
a41a1f86 | 693 | mt7621_pcie_enable_ports(pcie); |
03f152e3 | 694 | |
d9365507 | 695 | setup_cm_memory_region(pcie); |
8571c62d SP |
696 | |
697 | err = mt7621_pcie_request_resources(pcie, &res); | |
698 | if (err) { | |
699 | dev_err(dev, "Error requesting resources\n"); | |
6bdf0ddd | 700 | return err; |
8571c62d | 701 | } |
03f152e3 | 702 | |
8571c62d SP |
703 | err = mt7621_pcie_register_host(bridge, &res); |
704 | if (err) { | |
705 | dev_err(dev, "Error registering host\n"); | |
6bdf0ddd | 706 | return err; |
8571c62d SP |
707 | } |
708 | ||
6bdf0ddd | 709 | return 0; |
03f152e3 JC |
710 | } |
711 | ||
03f152e3 JC |
712 | static const struct of_device_id mt7621_pci_ids[] = { |
713 | { .compatible = "mediatek,mt7621-pci" }, | |
714 | {}, | |
715 | }; | |
716 | MODULE_DEVICE_TABLE(of, mt7621_pci_ids); | |
717 | ||
718 | static struct platform_driver mt7621_pci_driver = { | |
719 | .probe = mt7621_pci_probe, | |
720 | .driver = { | |
721 | .name = "mt7621-pci", | |
03f152e3 JC |
722 | .of_match_table = of_match_ptr(mt7621_pci_ids), |
723 | }, | |
724 | }; | |
725 | ||
3856f4e6 | 726 | builtin_platform_driver(mt7621_pci_driver); |