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d974ce4f KP |
1 | /* |
2 | * Copyright (c) 2003-2013 Broadcom Corporation | |
3 | * | |
4 | * Copyright (c) 2009-2010 Micron Technology, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | #include <linux/mtd/nand.h> | |
22 | #include <linux/spi/spi.h> | |
23 | ||
24 | #include "mt29f_spinand.h" | |
25 | ||
26 | #define BUFSIZE (10 * 64 * 2048) | |
27 | #define CACHE_BUF 2112 | |
28 | /* | |
29 | * OOB area specification layout: Total 32 available free bytes. | |
30 | */ | |
d974ce4f KP |
31 | |
32 | static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd) | |
33 | { | |
a83dfa92 | 34 | struct nand_chip *chip = mtd_to_nand(mtd); |
f07dcb90 | 35 | struct spinand_info *info = nand_get_controller_data(chip); |
d974ce4f KP |
36 | struct spinand_state *state = (struct spinand_state *)info->priv; |
37 | ||
38 | return state; | |
39 | } | |
40 | ||
3685ebc4 RD |
41 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC |
42 | static int enable_hw_ecc; | |
43 | static int enable_read_hw_ecc; | |
44 | ||
d974ce4f KP |
45 | static struct nand_ecclayout spinand_oob_64 = { |
46 | .eccbytes = 24, | |
47 | .eccpos = { | |
48 | 1, 2, 3, 4, 5, 6, | |
49 | 17, 18, 19, 20, 21, 22, | |
50 | 33, 34, 35, 36, 37, 38, | |
51 | 49, 50, 51, 52, 53, 54, }, | |
52 | .oobavail = 32, | |
53 | .oobfree = { | |
54 | {.offset = 8, | |
55 | .length = 8}, | |
56 | {.offset = 24, | |
57 | .length = 8}, | |
58 | {.offset = 40, | |
59 | .length = 8}, | |
60 | {.offset = 56, | |
61 | .length = 8}, | |
62 | } | |
63 | }; | |
64 | #endif | |
65 | ||
fdfda9a6 MPG |
66 | /** |
67 | * spinand_cmd - process a command to send to the SPI Nand | |
d974ce4f KP |
68 | * Description: |
69 | * Set up the command buffer to send to the SPI controller. | |
70 | * The command buffer has to initialized to 0. | |
71 | */ | |
72 | ||
73 | static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd) | |
74 | { | |
75 | struct spi_message message; | |
76 | struct spi_transfer x[4]; | |
77 | u8 dummy = 0xff; | |
78 | ||
79 | spi_message_init(&message); | |
80 | memset(x, 0, sizeof(x)); | |
81 | ||
82 | x[0].len = 1; | |
83 | x[0].tx_buf = &cmd->cmd; | |
84 | spi_message_add_tail(&x[0], &message); | |
85 | ||
86 | if (cmd->n_addr) { | |
87 | x[1].len = cmd->n_addr; | |
88 | x[1].tx_buf = cmd->addr; | |
89 | spi_message_add_tail(&x[1], &message); | |
90 | } | |
91 | ||
92 | if (cmd->n_dummy) { | |
93 | x[2].len = cmd->n_dummy; | |
94 | x[2].tx_buf = &dummy; | |
95 | spi_message_add_tail(&x[2], &message); | |
96 | } | |
97 | ||
98 | if (cmd->n_tx) { | |
99 | x[3].len = cmd->n_tx; | |
100 | x[3].tx_buf = cmd->tx_buf; | |
101 | spi_message_add_tail(&x[3], &message); | |
102 | } | |
103 | ||
104 | if (cmd->n_rx) { | |
105 | x[3].len = cmd->n_rx; | |
106 | x[3].rx_buf = cmd->rx_buf; | |
107 | spi_message_add_tail(&x[3], &message); | |
108 | } | |
109 | ||
110 | return spi_sync(spi, &message); | |
111 | } | |
112 | ||
fdfda9a6 MPG |
113 | /** |
114 | * spinand_read_id - Read SPI Nand ID | |
d974ce4f | 115 | * Description: |
fdfda9a6 | 116 | * read two ID bytes from the SPI Nand device |
d974ce4f KP |
117 | */ |
118 | static int spinand_read_id(struct spi_device *spi_nand, u8 *id) | |
119 | { | |
120 | int retval; | |
121 | u8 nand_id[3]; | |
122 | struct spinand_cmd cmd = {0}; | |
123 | ||
124 | cmd.cmd = CMD_READ_ID; | |
125 | cmd.n_rx = 3; | |
126 | cmd.rx_buf = &nand_id[0]; | |
127 | ||
128 | retval = spinand_cmd(spi_nand, &cmd); | |
129 | if (retval < 0) { | |
130 | dev_err(&spi_nand->dev, "error %d reading id\n", retval); | |
131 | return retval; | |
132 | } | |
133 | id[0] = nand_id[1]; | |
134 | id[1] = nand_id[2]; | |
135 | return retval; | |
136 | } | |
137 | ||
fdfda9a6 MPG |
138 | /** |
139 | * spinand_read_status - send command 0xf to the SPI Nand status register | |
d974ce4f KP |
140 | * Description: |
141 | * After read, write, or erase, the Nand device is expected to set the | |
142 | * busy status. | |
143 | * This function is to allow reading the status of the command: read, | |
144 | * write, and erase. | |
145 | * Once the status turns to be ready, the other status bits also are | |
146 | * valid status bits. | |
147 | */ | |
74f63bd6 | 148 | static int spinand_read_status(struct spi_device *spi_nand, u8 *status) |
d974ce4f KP |
149 | { |
150 | struct spinand_cmd cmd = {0}; | |
151 | int ret; | |
152 | ||
153 | cmd.cmd = CMD_READ_REG; | |
154 | cmd.n_addr = 1; | |
155 | cmd.addr[0] = REG_STATUS; | |
156 | cmd.n_rx = 1; | |
157 | cmd.rx_buf = status; | |
158 | ||
159 | ret = spinand_cmd(spi_nand, &cmd); | |
160 | if (ret < 0) | |
161 | dev_err(&spi_nand->dev, "err: %d read status register\n", ret); | |
162 | ||
163 | return ret; | |
164 | } | |
165 | ||
166 | #define MAX_WAIT_JIFFIES (40 * HZ) | |
167 | static int wait_till_ready(struct spi_device *spi_nand) | |
168 | { | |
169 | unsigned long deadline; | |
170 | int retval; | |
171 | u8 stat = 0; | |
172 | ||
173 | deadline = jiffies + MAX_WAIT_JIFFIES; | |
174 | do { | |
175 | retval = spinand_read_status(spi_nand, &stat); | |
176 | if (retval < 0) | |
177 | return -1; | |
178 | else if (!(stat & 0x1)) | |
179 | break; | |
180 | ||
181 | cond_resched(); | |
182 | } while (!time_after_eq(jiffies, deadline)); | |
183 | ||
184 | if ((stat & 0x1) == 0) | |
185 | return 0; | |
186 | ||
187 | return -1; | |
188 | } | |
522f0050 | 189 | |
d974ce4f | 190 | /** |
fdfda9a6 | 191 | * spinand_get_otp - send command 0xf to read the SPI Nand OTP register |
d974ce4f KP |
192 | * Description: |
193 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
194 | * Enable chip internal ECC, set the bit to 1 | |
195 | * Disable chip internal ECC, clear the bit to 0 | |
196 | */ | |
197 | static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp) | |
198 | { | |
199 | struct spinand_cmd cmd = {0}; | |
200 | int retval; | |
201 | ||
202 | cmd.cmd = CMD_READ_REG; | |
203 | cmd.n_addr = 1; | |
204 | cmd.addr[0] = REG_OTP; | |
205 | cmd.n_rx = 1; | |
206 | cmd.rx_buf = otp; | |
207 | ||
208 | retval = spinand_cmd(spi_nand, &cmd); | |
209 | if (retval < 0) | |
210 | dev_err(&spi_nand->dev, "error %d get otp\n", retval); | |
211 | return retval; | |
212 | } | |
213 | ||
214 | /** | |
fdfda9a6 | 215 | * spinand_set_otp - send command 0x1f to write the SPI Nand OTP register |
d974ce4f KP |
216 | * Description: |
217 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
218 | * Enable chip internal ECC, set the bit to 1 | |
219 | * Disable chip internal ECC, clear the bit to 0 | |
220 | */ | |
221 | static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp) | |
222 | { | |
223 | int retval; | |
224 | struct spinand_cmd cmd = {0}; | |
225 | ||
61cb8d9a MPG |
226 | cmd.cmd = CMD_WRITE_REG; |
227 | cmd.n_addr = 1; | |
228 | cmd.addr[0] = REG_OTP; | |
229 | cmd.n_tx = 1; | |
230 | cmd.tx_buf = otp; | |
d974ce4f KP |
231 | |
232 | retval = spinand_cmd(spi_nand, &cmd); | |
233 | if (retval < 0) | |
234 | dev_err(&spi_nand->dev, "error %d set otp\n", retval); | |
235 | ||
236 | return retval; | |
237 | } | |
238 | ||
239 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
240 | /** | |
fdfda9a6 | 241 | * spinand_enable_ecc - send command 0x1f to write the SPI Nand OTP register |
d974ce4f KP |
242 | * Description: |
243 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
244 | * Enable chip internal ECC, set the bit to 1 | |
245 | * Disable chip internal ECC, clear the bit to 0 | |
246 | */ | |
247 | static int spinand_enable_ecc(struct spi_device *spi_nand) | |
248 | { | |
249 | int retval; | |
250 | u8 otp = 0; | |
251 | ||
252 | retval = spinand_get_otp(spi_nand, &otp); | |
253 | if (retval < 0) | |
254 | return retval; | |
255 | ||
72267c27 | 256 | if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) |
d974ce4f | 257 | return 0; |
72267c27 | 258 | otp |= OTP_ECC_MASK; |
259 | retval = spinand_set_otp(spi_nand, &otp); | |
260 | if (retval < 0) | |
261 | return retval; | |
262 | return spinand_get_otp(spi_nand, &otp); | |
d974ce4f KP |
263 | } |
264 | #endif | |
265 | ||
266 | static int spinand_disable_ecc(struct spi_device *spi_nand) | |
267 | { | |
268 | int retval; | |
269 | u8 otp = 0; | |
270 | ||
271 | retval = spinand_get_otp(spi_nand, &otp); | |
272 | if (retval < 0) | |
273 | return retval; | |
274 | ||
275 | if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) { | |
276 | otp &= ~OTP_ECC_MASK; | |
277 | retval = spinand_set_otp(spi_nand, &otp); | |
278 | if (retval < 0) | |
279 | return retval; | |
280 | return spinand_get_otp(spi_nand, &otp); | |
72267c27 | 281 | } |
282 | return 0; | |
d974ce4f KP |
283 | } |
284 | ||
285 | /** | |
fdfda9a6 | 286 | * spinand_write_enable - send command 0x06 to enable write or erase the |
d974ce4f KP |
287 | * Nand cells |
288 | * Description: | |
289 | * Before write and erase the Nand cells, the write enable has to be set. | |
290 | * After the write or erase, the write enable bit is automatically | |
291 | * cleared (status register bit 2) | |
292 | * Set the bit 2 of the status register has the same effect | |
293 | */ | |
294 | static int spinand_write_enable(struct spi_device *spi_nand) | |
295 | { | |
296 | struct spinand_cmd cmd = {0}; | |
297 | ||
298 | cmd.cmd = CMD_WR_ENABLE; | |
299 | return spinand_cmd(spi_nand, &cmd); | |
300 | } | |
301 | ||
302 | static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id) | |
303 | { | |
304 | struct spinand_cmd cmd = {0}; | |
305 | u16 row; | |
306 | ||
307 | row = page_id; | |
308 | cmd.cmd = CMD_READ; | |
309 | cmd.n_addr = 3; | |
310 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
311 | cmd.addr[2] = (u8)(row & 0x00ff); | |
312 | ||
313 | return spinand_cmd(spi_nand, &cmd); | |
314 | } | |
315 | ||
fdfda9a6 MPG |
316 | /** |
317 | * spinand_read_from_cache - send command 0x03 to read out the data from the | |
318 | * cache register (2112 bytes max) | |
d974ce4f KP |
319 | * Description: |
320 | * The read can specify 1 to 2112 bytes of data read at the corresponding | |
321 | * locations. | |
322 | * No tRd delay. | |
323 | */ | |
324 | static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id, | |
92fdd777 | 325 | u16 byte_id, u16 len, u8 *rbuf) |
d974ce4f KP |
326 | { |
327 | struct spinand_cmd cmd = {0}; | |
328 | u16 column; | |
329 | ||
330 | column = byte_id; | |
331 | cmd.cmd = CMD_READ_RDM; | |
332 | cmd.n_addr = 3; | |
333 | cmd.addr[0] = (u8)((column & 0xff00) >> 8); | |
334 | cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4); | |
335 | cmd.addr[1] = (u8)(column & 0x00ff); | |
336 | cmd.addr[2] = (u8)(0xff); | |
337 | cmd.n_dummy = 0; | |
338 | cmd.n_rx = len; | |
339 | cmd.rx_buf = rbuf; | |
340 | ||
341 | return spinand_cmd(spi_nand, &cmd); | |
342 | } | |
343 | ||
fdfda9a6 MPG |
344 | /** |
345 | * spinand_read_page - read a page | |
d974ce4f KP |
346 | * @page_id: the physical page number |
347 | * @offset: the location from 0 to 2111 | |
348 | * @len: number of bytes to read | |
349 | * @rbuf: read buffer to hold @len bytes | |
350 | * | |
351 | * Description: | |
fdfda9a6 | 352 | * The read includes two commands to the Nand - 0x13 and 0x03 commands |
d974ce4f KP |
353 | * Poll to read status to wait for tRD time. |
354 | */ | |
355 | static int spinand_read_page(struct spi_device *spi_nand, u16 page_id, | |
92fdd777 | 356 | u16 offset, u16 len, u8 *rbuf) |
d974ce4f KP |
357 | { |
358 | int ret; | |
359 | u8 status = 0; | |
360 | ||
361 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
362 | if (enable_read_hw_ecc) { | |
363 | if (spinand_enable_ecc(spi_nand) < 0) | |
364 | dev_err(&spi_nand->dev, "enable HW ECC failed!"); | |
365 | } | |
366 | #endif | |
367 | ret = spinand_read_page_to_cache(spi_nand, page_id); | |
368 | if (ret < 0) | |
369 | return ret; | |
370 | ||
371 | if (wait_till_ready(spi_nand)) | |
372 | dev_err(&spi_nand->dev, "WAIT timedout!!!\n"); | |
373 | ||
374 | while (1) { | |
375 | ret = spinand_read_status(spi_nand, &status); | |
376 | if (ret < 0) { | |
377 | dev_err(&spi_nand->dev, | |
92fdd777 | 378 | "err %d read status register\n", ret); |
d974ce4f KP |
379 | return ret; |
380 | } | |
381 | ||
382 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
383 | if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) { | |
384 | dev_err(&spi_nand->dev, "ecc error, page=%d\n", | |
92fdd777 | 385 | page_id); |
d974ce4f KP |
386 | return 0; |
387 | } | |
388 | break; | |
389 | } | |
390 | } | |
391 | ||
392 | ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf); | |
393 | if (ret < 0) { | |
394 | dev_err(&spi_nand->dev, "read from cache failed!!\n"); | |
395 | return ret; | |
396 | } | |
397 | ||
398 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
399 | if (enable_read_hw_ecc) { | |
400 | ret = spinand_disable_ecc(spi_nand); | |
401 | if (ret < 0) { | |
402 | dev_err(&spi_nand->dev, "disable ecc failed!!\n"); | |
403 | return ret; | |
404 | } | |
405 | enable_read_hw_ecc = 0; | |
406 | } | |
407 | #endif | |
408 | return ret; | |
409 | } | |
410 | ||
fdfda9a6 MPG |
411 | /** |
412 | * spinand_program_data_to_cache - write a page to cache | |
d974ce4f KP |
413 | * @byte_id: the location to write to the cache |
414 | * @len: number of bytes to write | |
fdfda9a6 | 415 | * @wbuf: write buffer holding @len bytes |
d974ce4f KP |
416 | * |
417 | * Description: | |
418 | * The write command used here is 0x84--indicating that the cache is | |
419 | * not cleared first. | |
420 | * Since it is writing the data to cache, there is no tPROG time. | |
421 | */ | |
422 | static int spinand_program_data_to_cache(struct spi_device *spi_nand, | |
92fdd777 ERR |
423 | u16 page_id, u16 byte_id, |
424 | u16 len, u8 *wbuf) | |
d974ce4f KP |
425 | { |
426 | struct spinand_cmd cmd = {0}; | |
427 | u16 column; | |
428 | ||
429 | column = byte_id; | |
430 | cmd.cmd = CMD_PROG_PAGE_CLRCACHE; | |
431 | cmd.n_addr = 2; | |
432 | cmd.addr[0] = (u8)((column & 0xff00) >> 8); | |
433 | cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4); | |
434 | cmd.addr[1] = (u8)(column & 0x00ff); | |
435 | cmd.n_tx = len; | |
436 | cmd.tx_buf = wbuf; | |
437 | ||
438 | return spinand_cmd(spi_nand, &cmd); | |
439 | } | |
440 | ||
441 | /** | |
fdfda9a6 | 442 | * spinand_program_execute - write a page from cache to the Nand array |
d974ce4f KP |
443 | * @page_id: the physical page location to write the page. |
444 | * | |
445 | * Description: | |
446 | * The write command used here is 0x10--indicating the cache is writing to | |
447 | * the Nand array. | |
448 | * Need to wait for tPROG time to finish the transaction. | |
449 | */ | |
450 | static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id) | |
451 | { | |
452 | struct spinand_cmd cmd = {0}; | |
453 | u16 row; | |
454 | ||
455 | row = page_id; | |
456 | cmd.cmd = CMD_PROG_PAGE_EXC; | |
457 | cmd.n_addr = 3; | |
458 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
459 | cmd.addr[2] = (u8)(row & 0x00ff); | |
460 | ||
461 | return spinand_cmd(spi_nand, &cmd); | |
462 | } | |
463 | ||
464 | /** | |
fdfda9a6 | 465 | * spinand_program_page - write a page |
d974ce4f KP |
466 | * @page_id: the physical page location to write the page. |
467 | * @offset: the location from the cache starting from 0 to 2111 | |
468 | * @len: the number of bytes to write | |
fdfda9a6 | 469 | * @buf: the buffer holding @len bytes |
d974ce4f KP |
470 | * |
471 | * Description: | |
472 | * The commands used here are 0x06, 0x84, and 0x10--indicating that | |
473 | * the write enable is first sent, the write cache command, and the | |
474 | * write execute command. | |
475 | * Poll to wait for the tPROG time to finish the transaction. | |
476 | */ | |
477 | static int spinand_program_page(struct spi_device *spi_nand, | |
92fdd777 | 478 | u16 page_id, u16 offset, u16 len, u8 *buf) |
d974ce4f KP |
479 | { |
480 | int retval; | |
481 | u8 status = 0; | |
74f63bd6 | 482 | u8 *wbuf; |
d974ce4f KP |
483 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC |
484 | unsigned int i, j; | |
485 | ||
d974ce4f | 486 | wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL); |
e5b3eceb MPG |
487 | if (!wbuf) |
488 | return -ENOMEM; | |
489 | ||
490 | enable_read_hw_ecc = 0; | |
d974ce4f KP |
491 | spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf); |
492 | ||
493 | for (i = offset, j = 0; i < len; i++, j++) | |
494 | wbuf[i] &= buf[j]; | |
495 | ||
496 | if (enable_hw_ecc) { | |
497 | retval = spinand_enable_ecc(spi_nand); | |
498 | if (retval < 0) { | |
499 | dev_err(&spi_nand->dev, "enable ecc failed!!\n"); | |
500 | return retval; | |
501 | } | |
502 | } | |
503 | #else | |
504 | wbuf = buf; | |
505 | #endif | |
506 | retval = spinand_write_enable(spi_nand); | |
507 | if (retval < 0) { | |
508 | dev_err(&spi_nand->dev, "write enable failed!!\n"); | |
509 | return retval; | |
510 | } | |
511 | if (wait_till_ready(spi_nand)) | |
512 | dev_err(&spi_nand->dev, "wait timedout!!!\n"); | |
513 | ||
514 | retval = spinand_program_data_to_cache(spi_nand, page_id, | |
92fdd777 | 515 | offset, len, wbuf); |
d974ce4f KP |
516 | if (retval < 0) |
517 | return retval; | |
518 | retval = spinand_program_execute(spi_nand, page_id); | |
519 | if (retval < 0) | |
520 | return retval; | |
521 | while (1) { | |
522 | retval = spinand_read_status(spi_nand, &status); | |
523 | if (retval < 0) { | |
524 | dev_err(&spi_nand->dev, | |
92fdd777 | 525 | "error %d reading status register\n", retval); |
d974ce4f KP |
526 | return retval; |
527 | } | |
528 | ||
529 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
530 | if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) { | |
531 | dev_err(&spi_nand->dev, | |
532 | "program error, page %d\n", page_id); | |
533 | return -1; | |
72267c27 | 534 | } |
535 | break; | |
d974ce4f KP |
536 | } |
537 | } | |
538 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
539 | if (enable_hw_ecc) { | |
540 | retval = spinand_disable_ecc(spi_nand); | |
541 | if (retval < 0) { | |
542 | dev_err(&spi_nand->dev, "disable ecc failed!!\n"); | |
543 | return retval; | |
544 | } | |
545 | enable_hw_ecc = 0; | |
546 | } | |
547 | #endif | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | /** | |
fdfda9a6 | 553 | * spinand_erase_block_erase - erase a page |
d974ce4f KP |
554 | * @block_id: the physical block location to erase. |
555 | * | |
556 | * Description: | |
557 | * The command used here is 0xd8--indicating an erase command to erase | |
558 | * one block--64 pages | |
559 | * Need to wait for tERS. | |
560 | */ | |
561 | static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id) | |
562 | { | |
563 | struct spinand_cmd cmd = {0}; | |
564 | u16 row; | |
565 | ||
566 | row = block_id; | |
567 | cmd.cmd = CMD_ERASE_BLK; | |
568 | cmd.n_addr = 3; | |
569 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
570 | cmd.addr[2] = (u8)(row & 0x00ff); | |
571 | ||
572 | return spinand_cmd(spi_nand, &cmd); | |
573 | } | |
574 | ||
575 | /** | |
fdfda9a6 | 576 | * spinand_erase_block - erase a page |
d974ce4f KP |
577 | * @block_id: the physical block location to erase. |
578 | * | |
579 | * Description: | |
580 | * The commands used here are 0x06 and 0xd8--indicating an erase | |
581 | * command to erase one block--64 pages | |
582 | * It will first to enable the write enable bit (0x06 command), | |
583 | * and then send the 0xd8 erase command | |
584 | * Poll to wait for the tERS time to complete the tranaction. | |
585 | */ | |
586 | static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id) | |
587 | { | |
588 | int retval; | |
589 | u8 status = 0; | |
590 | ||
591 | retval = spinand_write_enable(spi_nand); | |
592 | if (wait_till_ready(spi_nand)) | |
593 | dev_err(&spi_nand->dev, "wait timedout!!!\n"); | |
594 | ||
595 | retval = spinand_erase_block_erase(spi_nand, block_id); | |
596 | while (1) { | |
597 | retval = spinand_read_status(spi_nand, &status); | |
598 | if (retval < 0) { | |
599 | dev_err(&spi_nand->dev, | |
92fdd777 | 600 | "error %d reading status register\n", retval); |
d974ce4f KP |
601 | return retval; |
602 | } | |
603 | ||
604 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
605 | if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) { | |
606 | dev_err(&spi_nand->dev, | |
607 | "erase error, block %d\n", block_id); | |
608 | return -1; | |
72267c27 | 609 | } |
610 | break; | |
d974ce4f KP |
611 | } |
612 | } | |
613 | return 0; | |
614 | } | |
615 | ||
616 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
617 | static int spinand_write_page_hwecc(struct mtd_info *mtd, | |
92fdd777 | 618 | struct nand_chip *chip, |
02f0d3f7 LT |
619 | const u8 *buf, int oob_required, |
620 | int page) | |
d974ce4f | 621 | { |
74f63bd6 | 622 | const u8 *p = buf; |
d974ce4f KP |
623 | int eccsize = chip->ecc.size; |
624 | int eccsteps = chip->ecc.steps; | |
625 | ||
626 | enable_hw_ecc = 1; | |
627 | chip->write_buf(mtd, p, eccsize * eccsteps); | |
628 | return 0; | |
629 | } | |
630 | ||
631 | static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
92fdd777 | 632 | u8 *buf, int oob_required, int page) |
d974ce4f | 633 | { |
1f5cf802 DN |
634 | int retval; |
635 | u8 status; | |
74f63bd6 | 636 | u8 *p = buf; |
d974ce4f KP |
637 | int eccsize = chip->ecc.size; |
638 | int eccsteps = chip->ecc.steps; | |
f07dcb90 | 639 | struct spinand_info *info = nand_get_controller_data(chip); |
d974ce4f KP |
640 | |
641 | enable_read_hw_ecc = 1; | |
642 | ||
643 | chip->read_buf(mtd, p, eccsize * eccsteps); | |
644 | if (oob_required) | |
645 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
646 | ||
647 | while (1) { | |
648 | retval = spinand_read_status(info->spi, &status); | |
1f5cf802 DN |
649 | if (retval < 0) { |
650 | dev_err(&mtd->dev, | |
92fdd777 | 651 | "error %d reading status register\n", retval); |
1f5cf802 DN |
652 | return retval; |
653 | } | |
654 | ||
d974ce4f KP |
655 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { |
656 | if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) { | |
657 | pr_info("spinand: ECC error\n"); | |
658 | mtd->ecc_stats.failed++; | |
659 | } else if ((status & STATUS_ECC_MASK) == | |
660 | STATUS_ECC_1BIT_CORRECTED) | |
661 | mtd->ecc_stats.corrected++; | |
662 | break; | |
663 | } | |
664 | } | |
665 | return 0; | |
d974ce4f KP |
666 | } |
667 | #endif | |
668 | ||
669 | static void spinand_select_chip(struct mtd_info *mtd, int dev) | |
670 | { | |
671 | } | |
672 | ||
74f63bd6 | 673 | static u8 spinand_read_byte(struct mtd_info *mtd) |
d974ce4f KP |
674 | { |
675 | struct spinand_state *state = mtd_to_state(mtd); | |
676 | u8 data; | |
677 | ||
678 | data = state->buf[state->buf_ptr]; | |
679 | state->buf_ptr++; | |
680 | return data; | |
681 | } | |
682 | ||
d974ce4f KP |
683 | static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
684 | { | |
f07dcb90 | 685 | struct spinand_info *info = nand_get_controller_data(chip); |
d974ce4f KP |
686 | |
687 | unsigned long timeo = jiffies; | |
688 | int retval, state = chip->state; | |
689 | u8 status; | |
690 | ||
691 | if (state == FL_ERASING) | |
692 | timeo += (HZ * 400) / 1000; | |
693 | else | |
694 | timeo += (HZ * 20) / 1000; | |
695 | ||
696 | while (time_before(jiffies, timeo)) { | |
697 | retval = spinand_read_status(info->spi, &status); | |
1f5cf802 DN |
698 | if (retval < 0) { |
699 | dev_err(&mtd->dev, | |
92fdd777 | 700 | "error %d reading status register\n", retval); |
1f5cf802 DN |
701 | return retval; |
702 | } | |
703 | ||
d974ce4f KP |
704 | if ((status & STATUS_OIP_MASK) == STATUS_READY) |
705 | return 0; | |
706 | ||
707 | cond_resched(); | |
708 | } | |
709 | return 0; | |
710 | } | |
711 | ||
74f63bd6 | 712 | static void spinand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) |
d974ce4f | 713 | { |
d974ce4f | 714 | struct spinand_state *state = mtd_to_state(mtd); |
aeb49155 | 715 | |
d974ce4f KP |
716 | memcpy(state->buf + state->buf_ptr, buf, len); |
717 | state->buf_ptr += len; | |
718 | } | |
719 | ||
74f63bd6 | 720 | static void spinand_read_buf(struct mtd_info *mtd, u8 *buf, int len) |
d974ce4f KP |
721 | { |
722 | struct spinand_state *state = mtd_to_state(mtd); | |
aeb49155 | 723 | |
d974ce4f KP |
724 | memcpy(buf, state->buf + state->buf_ptr, len); |
725 | state->buf_ptr += len; | |
726 | } | |
727 | ||
728 | /* | |
729 | * spinand_reset- send RESET command "0xff" to the Nand device. | |
730 | */ | |
731 | static void spinand_reset(struct spi_device *spi_nand) | |
732 | { | |
733 | struct spinand_cmd cmd = {0}; | |
734 | ||
735 | cmd.cmd = CMD_RESET; | |
736 | ||
737 | if (spinand_cmd(spi_nand, &cmd) < 0) | |
738 | pr_info("spinand reset failed!\n"); | |
739 | ||
740 | /* elapse 1ms before issuing any other command */ | |
c75e0577 | 741 | usleep_range(1000, 2000); |
d974ce4f KP |
742 | |
743 | if (wait_till_ready(spi_nand)) | |
744 | dev_err(&spi_nand->dev, "wait timedout!\n"); | |
745 | } | |
746 | ||
747 | static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
92fdd777 | 748 | int column, int page) |
d974ce4f | 749 | { |
a83dfa92 | 750 | struct nand_chip *chip = mtd_to_nand(mtd); |
f07dcb90 | 751 | struct spinand_info *info = nand_get_controller_data(chip); |
d974ce4f KP |
752 | struct spinand_state *state = (struct spinand_state *)info->priv; |
753 | ||
754 | switch (command) { | |
755 | /* | |
756 | * READ0 - read in first 0x800 bytes | |
757 | */ | |
758 | case NAND_CMD_READ1: | |
759 | case NAND_CMD_READ0: | |
760 | state->buf_ptr = 0; | |
761 | spinand_read_page(info->spi, page, 0x0, 0x840, state->buf); | |
762 | break; | |
763 | /* READOOB reads only the OOB because no ECC is performed. */ | |
764 | case NAND_CMD_READOOB: | |
765 | state->buf_ptr = 0; | |
766 | spinand_read_page(info->spi, page, 0x800, 0x40, state->buf); | |
767 | break; | |
768 | case NAND_CMD_RNDOUT: | |
769 | state->buf_ptr = column; | |
770 | break; | |
771 | case NAND_CMD_READID: | |
772 | state->buf_ptr = 0; | |
a511536f | 773 | spinand_read_id(info->spi, state->buf); |
d974ce4f KP |
774 | break; |
775 | case NAND_CMD_PARAM: | |
776 | state->buf_ptr = 0; | |
777 | break; | |
778 | /* ERASE1 stores the block and page address */ | |
779 | case NAND_CMD_ERASE1: | |
780 | spinand_erase_block(info->spi, page); | |
781 | break; | |
782 | /* ERASE2 uses the block and page address from ERASE1 */ | |
783 | case NAND_CMD_ERASE2: | |
784 | break; | |
785 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
786 | case NAND_CMD_SEQIN: | |
787 | state->col = column; | |
788 | state->row = page; | |
789 | state->buf_ptr = 0; | |
790 | break; | |
791 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
792 | case NAND_CMD_PAGEPROG: | |
793 | spinand_program_page(info->spi, state->row, state->col, | |
92fdd777 | 794 | state->buf_ptr, state->buf); |
d974ce4f KP |
795 | break; |
796 | case NAND_CMD_STATUS: | |
797 | spinand_get_otp(info->spi, state->buf); | |
798 | if (!(state->buf[0] & 0x80)) | |
799 | state->buf[0] = 0x80; | |
800 | state->buf_ptr = 0; | |
801 | break; | |
802 | /* RESET command */ | |
803 | case NAND_CMD_RESET: | |
804 | if (wait_till_ready(info->spi)) | |
805 | dev_err(&info->spi->dev, "WAIT timedout!!!\n"); | |
806 | /* a minimum of 250us must elapse before issuing RESET cmd*/ | |
c75e0577 | 807 | usleep_range(250, 1000); |
d974ce4f KP |
808 | spinand_reset(info->spi); |
809 | break; | |
810 | default: | |
811 | dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command); | |
812 | } | |
813 | } | |
814 | ||
815 | /** | |
fdfda9a6 | 816 | * spinand_lock_block - send write register 0x1f command to the Nand device |
d974ce4f KP |
817 | * |
818 | * Description: | |
819 | * After power up, all the Nand blocks are locked. This function allows | |
820 | * one to unlock the blocks, and so it can be written or erased. | |
821 | */ | |
822 | static int spinand_lock_block(struct spi_device *spi_nand, u8 lock) | |
823 | { | |
824 | struct spinand_cmd cmd = {0}; | |
825 | int ret; | |
826 | u8 otp = 0; | |
827 | ||
828 | ret = spinand_get_otp(spi_nand, &otp); | |
829 | ||
830 | cmd.cmd = CMD_WRITE_REG; | |
831 | cmd.n_addr = 1; | |
832 | cmd.addr[0] = REG_BLOCK_LOCK; | |
833 | cmd.n_tx = 1; | |
834 | cmd.tx_buf = &lock; | |
835 | ||
836 | ret = spinand_cmd(spi_nand, &cmd); | |
837 | if (ret < 0) | |
838 | dev_err(&spi_nand->dev, "error %d lock block\n", ret); | |
839 | ||
840 | return ret; | |
841 | } | |
522f0050 | 842 | |
fdfda9a6 | 843 | /** |
d974ce4f KP |
844 | * spinand_probe - [spinand Interface] |
845 | * @spi_nand: registered device driver. | |
846 | * | |
847 | * Description: | |
fdfda9a6 | 848 | * Set up the device driver parameters to make the device available. |
d974ce4f KP |
849 | */ |
850 | static int spinand_probe(struct spi_device *spi_nand) | |
851 | { | |
852 | struct mtd_info *mtd; | |
853 | struct nand_chip *chip; | |
854 | struct spinand_info *info; | |
855 | struct spinand_state *state; | |
d974ce4f KP |
856 | |
857 | info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info), | |
92fdd777 | 858 | GFP_KERNEL); |
d974ce4f KP |
859 | if (!info) |
860 | return -ENOMEM; | |
861 | ||
862 | info->spi = spi_nand; | |
863 | ||
864 | spinand_lock_block(spi_nand, BL_ALL_UNLOCKED); | |
865 | ||
866 | state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state), | |
92fdd777 | 867 | GFP_KERNEL); |
d974ce4f KP |
868 | if (!state) |
869 | return -ENOMEM; | |
870 | ||
871 | info->priv = state; | |
872 | state->buf_ptr = 0; | |
873 | state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL); | |
874 | if (!state->buf) | |
875 | return -ENOMEM; | |
876 | ||
877 | chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip), | |
92fdd777 | 878 | GFP_KERNEL); |
d974ce4f KP |
879 | if (!chip) |
880 | return -ENOMEM; | |
881 | ||
882 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
883 | chip->ecc.mode = NAND_ECC_HW; | |
884 | chip->ecc.size = 0x200; | |
885 | chip->ecc.bytes = 0x6; | |
886 | chip->ecc.steps = 0x4; | |
887 | ||
888 | chip->ecc.strength = 1; | |
889 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; | |
890 | chip->ecc.layout = &spinand_oob_64; | |
891 | chip->ecc.read_page = spinand_read_page_hwecc; | |
892 | chip->ecc.write_page = spinand_write_page_hwecc; | |
893 | #else | |
894 | chip->ecc.mode = NAND_ECC_SOFT; | |
895 | if (spinand_disable_ecc(spi_nand) < 0) | |
896 | pr_info("%s: disable ecc failed!\n", __func__); | |
897 | #endif | |
898 | ||
a61ae81a | 899 | nand_set_flash_node(chip, spi_nand->dev.of_node); |
f07dcb90 | 900 | nand_set_controller_data(chip, info); |
d974ce4f KP |
901 | chip->read_buf = spinand_read_buf; |
902 | chip->write_buf = spinand_write_buf; | |
903 | chip->read_byte = spinand_read_byte; | |
904 | chip->cmdfunc = spinand_cmdfunc; | |
905 | chip->waitfunc = spinand_wait; | |
906 | chip->options |= NAND_CACHEPRG; | |
907 | chip->select_chip = spinand_select_chip; | |
908 | ||
ba4ed860 | 909 | mtd = nand_to_mtd(chip); |
d974ce4f KP |
910 | |
911 | dev_set_drvdata(&spi_nand->dev, mtd); | |
912 | ||
efefcaee | 913 | mtd->dev.parent = &spi_nand->dev; |
d974ce4f KP |
914 | mtd->oobsize = 64; |
915 | ||
916 | if (nand_scan(mtd, 1)) | |
917 | return -ENXIO; | |
918 | ||
a61ae81a | 919 | return mtd_device_register(mtd, NULL, 0); |
d974ce4f KP |
920 | } |
921 | ||
fdfda9a6 MPG |
922 | /** |
923 | * spinand_remove - remove the device driver | |
d974ce4f KP |
924 | * @spi: the spi device. |
925 | * | |
926 | * Description: | |
fdfda9a6 | 927 | * Remove the device driver parameters and free up allocated memories. |
d974ce4f KP |
928 | */ |
929 | static int spinand_remove(struct spi_device *spi) | |
930 | { | |
931 | mtd_device_unregister(dev_get_drvdata(&spi->dev)); | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
936 | static const struct of_device_id spinand_dt[] = { | |
937 | { .compatible = "spinand,mt29f", }, | |
ffd07de6 | 938 | {} |
d974ce4f | 939 | }; |
1e498d4b | 940 | MODULE_DEVICE_TABLE(of, spinand_dt); |
d974ce4f KP |
941 | |
942 | /* | |
943 | * Device name structure description | |
944 | */ | |
945 | static struct spi_driver spinand_driver = { | |
946 | .driver = { | |
947 | .name = "mt29f", | |
d974ce4f KP |
948 | .of_match_table = spinand_dt, |
949 | }, | |
950 | .probe = spinand_probe, | |
951 | .remove = spinand_remove, | |
952 | }; | |
953 | ||
4a54b615 | 954 | module_spi_driver(spinand_driver); |
d974ce4f KP |
955 | |
956 | MODULE_DESCRIPTION("SPI NAND driver for Micron"); | |
957 | MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>"); | |
958 | MODULE_LICENSE("GPL v2"); |