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Merge branch 'core-objtool-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / staging / media / rkisp1 / rkisp1-capture.c
CommitLineData
56e3b29f
HK		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Rockchip ISP1 Driver - V4l capture device
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 *
7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
9 */
10
11#include <linux/delay.h>
12#include <linux/pm_runtime.h>
13#include <media/v4l2-common.h>
14#include <media/v4l2-event.h>
15#include <media/v4l2-fh.h>
16#include <media/v4l2-ioctl.h>
17#include <media/v4l2-mc.h>
18#include <media/v4l2-subdev.h>
19#include <media/videobuf2-dma-contig.h>
20
21#include "rkisp1-common.h"
22
23/*
24 * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath.
25 *
26 * differences between selfpath and mainpath
27 * available mp sink input: isp
28 * available sp sink input : isp, dma(TODO)
29 * available mp sink pad fmts: yuv422, raw
30 * available sp sink pad fmts: yuv422, yuv420......
31 * available mp source fmts: yuv, raw, jpeg(TODO)
32 * available sp source fmts: yuv, rgb
33 */
34
35#define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath"
36#define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath"
37
38#define RKISP1_MIN_BUFFERS_NEEDED 3
39
40enum rkisp1_plane {
41 RKISP1_PLANE_Y = 0,
42 RKISP1_PLANE_CB = 1,
43 RKISP1_PLANE_CR = 2
44};
45
46/*
47 * @fourcc: pixel format
48 * @fmt_type: helper filed for pixel format
49 * @uv_swap: if cb cr swaped, for yuv
50 * @write_format: defines how YCbCr self picture data is written to memory
51 * @output_format: defines sp output format
52 */
53struct rkisp1_capture_fmt_cfg {
54 u32 fourcc;
55 u8 fmt_type;
56 u8 uv_swap;
57 u32 write_format;
58 u32 output_format;
59};
60
61struct rkisp1_capture_ops {
62 void (*config)(struct rkisp1_capture *cap);
63 void (*stop)(struct rkisp1_capture *cap);
64 void (*enable)(struct rkisp1_capture *cap);
65 void (*disable)(struct rkisp1_capture *cap);
66 void (*set_data_path)(struct rkisp1_capture *cap);
67 bool (*is_stopped)(struct rkisp1_capture *cap);
68};
69
70struct rkisp1_capture_config {
71 const struct rkisp1_capture_fmt_cfg *fmts;
72 int fmt_size;
73 struct {
74 u32 y_size_init;
75 u32 cb_size_init;
76 u32 cr_size_init;
77 u32 y_base_ad_init;
78 u32 cb_base_ad_init;
79 u32 cr_base_ad_init;
80 u32 y_offs_cnt_init;
81 u32 cb_offs_cnt_init;
82 u32 cr_offs_cnt_init;
83 } mi;
84};
85
86static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
87 /* yuv422 */
88 {
89 .fourcc = V4L2_PIX_FMT_YUYV,
90 .fmt_type = RKISP1_FMT_YUV,
91 .uv_swap = 0,
92 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
93 }, {
94 .fourcc = V4L2_PIX_FMT_YVYU,
95 .fmt_type = RKISP1_FMT_YUV,
96 .uv_swap = 1,
97 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
98 }, {
99 .fourcc = V4L2_PIX_FMT_VYUY,
100 .fmt_type = RKISP1_FMT_YUV,
101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
102 }, {
103 .fourcc = V4L2_PIX_FMT_YUV422P,
104 .fmt_type = RKISP1_FMT_YUV,
105 .uv_swap = 0,
106 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
107 }, {
108 .fourcc = V4L2_PIX_FMT_NV16,
109 .fmt_type = RKISP1_FMT_YUV,
110 .uv_swap = 0,
111 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
112 }, {
113 .fourcc = V4L2_PIX_FMT_NV61,
114 .fmt_type = RKISP1_FMT_YUV,
115 .uv_swap = 1,
116 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
117 }, {
118 .fourcc = V4L2_PIX_FMT_YVU422M,
119 .fmt_type = RKISP1_FMT_YUV,
120 .uv_swap = 1,
121 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
122 },
123 /* yuv420 */
124 {
125 .fourcc = V4L2_PIX_FMT_NV21,
126 .fmt_type = RKISP1_FMT_YUV,
127 .uv_swap = 1,
128 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
129 }, {
130 .fourcc = V4L2_PIX_FMT_NV12,
131 .fmt_type = RKISP1_FMT_YUV,
132 .uv_swap = 0,
133 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
134 }, {
135 .fourcc = V4L2_PIX_FMT_NV21M,
136 .fmt_type = RKISP1_FMT_YUV,
137 .uv_swap = 1,
138 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
139 }, {
140 .fourcc = V4L2_PIX_FMT_NV12M,
141 .fmt_type = RKISP1_FMT_YUV,
142 .uv_swap = 0,
143 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
144 }, {
145 .fourcc = V4L2_PIX_FMT_YUV420,
146 .fmt_type = RKISP1_FMT_YUV,
147 .uv_swap = 0,
148 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
149 }, {
150 .fourcc = V4L2_PIX_FMT_YVU420,
151 .fmt_type = RKISP1_FMT_YUV,
152 .uv_swap = 1,
153 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
154 },
155 /* yuv444 */
156 {
157 .fourcc = V4L2_PIX_FMT_YUV444M,
158 .fmt_type = RKISP1_FMT_YUV,
159 .uv_swap = 0,
160 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
161 },
162 /* yuv400 */
163 {
164 .fourcc = V4L2_PIX_FMT_GREY,
165 .fmt_type = RKISP1_FMT_YUV,
166 .uv_swap = 0,
167 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
168 },
169 /* raw */
170 {
171 .fourcc = V4L2_PIX_FMT_SRGGB8,
172 .fmt_type = RKISP1_FMT_BAYER,
173 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
174 }, {
175 .fourcc = V4L2_PIX_FMT_SGRBG8,
176 .fmt_type = RKISP1_FMT_BAYER,
177 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
178 }, {
179 .fourcc = V4L2_PIX_FMT_SGBRG8,
180 .fmt_type = RKISP1_FMT_BAYER,
181 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
182 }, {
183 .fourcc = V4L2_PIX_FMT_SBGGR8,
184 .fmt_type = RKISP1_FMT_BAYER,
185 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
186 }, {
187 .fourcc = V4L2_PIX_FMT_SRGGB10,
188 .fmt_type = RKISP1_FMT_BAYER,
189 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
190 }, {
191 .fourcc = V4L2_PIX_FMT_SGRBG10,
192 .fmt_type = RKISP1_FMT_BAYER,
193 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
194 }, {
195 .fourcc = V4L2_PIX_FMT_SGBRG10,
196 .fmt_type = RKISP1_FMT_BAYER,
197 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
198 }, {
199 .fourcc = V4L2_PIX_FMT_SBGGR10,
200 .fmt_type = RKISP1_FMT_BAYER,
201 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
202 }, {
203 .fourcc = V4L2_PIX_FMT_SRGGB12,
204 .fmt_type = RKISP1_FMT_BAYER,
205 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
206 }, {
207 .fourcc = V4L2_PIX_FMT_SGRBG12,
208 .fmt_type = RKISP1_FMT_BAYER,
209 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
210 }, {
211 .fourcc = V4L2_PIX_FMT_SGBRG12,
212 .fmt_type = RKISP1_FMT_BAYER,
213 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
214 }, {
215 .fourcc = V4L2_PIX_FMT_SBGGR12,
216 .fmt_type = RKISP1_FMT_BAYER,
217 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
218 },
219};
220
221static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = {
222 /* yuv422 */
223 {
224 .fourcc = V4L2_PIX_FMT_YUYV,
225 .fmt_type = RKISP1_FMT_YUV,
226 .uv_swap = 0,
227 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
228 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
229 }, {
230 .fourcc = V4L2_PIX_FMT_YVYU,
231 .fmt_type = RKISP1_FMT_YUV,
232 .uv_swap = 1,
233 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
234 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
235 }, {
236 .fourcc = V4L2_PIX_FMT_VYUY,
237 .fmt_type = RKISP1_FMT_YUV,
238 .uv_swap = 1,
239 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
240 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
241 }, {
242 .fourcc = V4L2_PIX_FMT_YUV422P,
243 .fmt_type = RKISP1_FMT_YUV,
244 .uv_swap = 0,
245 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
246 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
247 }, {
248 .fourcc = V4L2_PIX_FMT_NV16,
249 .fmt_type = RKISP1_FMT_YUV,
250 .uv_swap = 0,
251 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
252 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
253 }, {
254 .fourcc = V4L2_PIX_FMT_NV61,
255 .fmt_type = RKISP1_FMT_YUV,
256 .uv_swap = 1,
257 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
258 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
259 }, {
260 .fourcc = V4L2_PIX_FMT_YVU422M,
261 .fmt_type = RKISP1_FMT_YUV,
262 .uv_swap = 1,
263 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
264 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
265 },
266 /* yuv420 */
267 {
268 .fourcc = V4L2_PIX_FMT_NV21,
269 .fmt_type = RKISP1_FMT_YUV,
270 .uv_swap = 1,
271 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
272 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
273 }, {
274 .fourcc = V4L2_PIX_FMT_NV12,
275 .fmt_type = RKISP1_FMT_YUV,
276 .uv_swap = 0,
277 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
278 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
279 }, {
280 .fourcc = V4L2_PIX_FMT_NV21M,
281 .fmt_type = RKISP1_FMT_YUV,
282 .uv_swap = 1,
283 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
284 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
285 }, {
286 .fourcc = V4L2_PIX_FMT_NV12M,
287 .fmt_type = RKISP1_FMT_YUV,
288 .uv_swap = 0,
289 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
290 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
291 }, {
292 .fourcc = V4L2_PIX_FMT_YUV420,
293 .fmt_type = RKISP1_FMT_YUV,
294 .uv_swap = 0,
295 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
296 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
297 }, {
298 .fourcc = V4L2_PIX_FMT_YVU420,
299 .fmt_type = RKISP1_FMT_YUV,
300 .uv_swap = 1,
301 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
302 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
303 },
304 /* yuv444 */
305 {
306 .fourcc = V4L2_PIX_FMT_YUV444M,
307 .fmt_type = RKISP1_FMT_YUV,
308 .uv_swap = 0,
309 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
310 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV444,
311 },
312 /* yuv400 */
313 {
314 .fourcc = V4L2_PIX_FMT_GREY,
315 .fmt_type = RKISP1_FMT_YUV,
316 .uv_swap = 0,
317 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
318 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV400,
319 },
320 /* rgb */
321 {
322 .fourcc = V4L2_PIX_FMT_RGB24,
323 .fmt_type = RKISP1_FMT_RGB,
324 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
325 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888,
326 }, {
327 .fourcc = V4L2_PIX_FMT_RGB565,
328 .fmt_type = RKISP1_FMT_RGB,
329 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
330 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565,
331 }, {
332 .fourcc = V4L2_PIX_FMT_BGR666,
333 .fmt_type = RKISP1_FMT_RGB,
334 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
335 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB666,
336 },
337};
338
339static const struct rkisp1_capture_config rkisp1_capture_config_mp = {
340 .fmts = rkisp1_mp_fmts,
341 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts),
342 .mi = {
343 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT,
344 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT,
345 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT,
346 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT,
347 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT,
348 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT,
349 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT,
350 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT,
351 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT,
352 },
353};
354
355static const struct rkisp1_capture_config rkisp1_capture_config_sp = {
356 .fmts = rkisp1_sp_fmts,
357 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts),
358 .mi = {
359 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT,
360 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT,
361 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT,
362 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT,
363 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT,
364 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT,
365 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT,
366 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT,
367 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT,
368 },
369};
370
371static inline struct rkisp1_vdev_node *
372rkisp1_vdev_to_node(struct video_device *vdev)
373{
374 return container_of(vdev, struct rkisp1_vdev_node, vdev);
375}
376
377/* ----------------------------------------------------------------------------
378 * Stream operations for self-picture path (sp) and main-picture path (mp)
379 */
380
381static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap)
382{
383 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
384
385 mi_ctrl &= ~GENMASK(17, 16);
386 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64;
387
388 mi_ctrl &= ~GENMASK(19, 18);
389 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64;
390
391 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN |
392 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN;
393
394 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
395}
396
397static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm,
398 unsigned int component)
399{
400 /*
401 * If packed format, then plane_fmt[0].sizeimage is the sum of all
402 * components, so we need to calculate just the size of Y component.
403 * See rkisp1_fill_pixfmt().
404 */
405 if (!component && pixm->num_planes == 1)
406 return pixm->plane_fmt[0].bytesperline * pixm->height;
407 return pixm->plane_fmt[component].sizeimage;
408}
409
410static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap)
411{
412 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC);
413
414 mi_imsc |= RKISP1_CIF_MI_FRAME(cap);
415 rkisp1_write(cap->rkisp1, mi_imsc, RKISP1_CIF_MI_IMSC);
416}
417
418static void rkisp1_mp_config(struct rkisp1_capture *cap)
419{
420 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
421 struct rkisp1_device *rkisp1 = cap->rkisp1;
422 u32 reg;
423
424 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
425 cap->config->mi.y_size_init);
426 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
427 cap->config->mi.cb_size_init);
428 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR),
429 cap->config->mi.cr_size_init);
430
431 rkisp1_irq_frame_end_enable(cap);
432 if (cap->pix.cfg->uv_swap) {
433 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
434
435 reg = (reg & ~BIT(0)) |
436 RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
437 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
438 }
439
440 rkisp1_mi_config_ctrl(cap);
441
442 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
443 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK;
444 reg |= cap->pix.cfg->write_format;
445 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL);
446
447 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
448 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE;
449 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL);
450}
451
452static void rkisp1_sp_config(struct rkisp1_capture *cap)
453{
454 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
455 struct rkisp1_device *rkisp1 = cap->rkisp1;
456 u32 mi_ctrl;
457
458 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
459 cap->config->mi.y_size_init);
460 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
461 cap->config->mi.cb_size_init);
462 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR),
463 cap->config->mi.cr_size_init);
464
465 rkisp1_write(rkisp1, pixm->width, RKISP1_CIF_MI_SP_Y_PIC_WIDTH);
466 rkisp1_write(rkisp1, pixm->height, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT);
467 rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH);
468
469 rkisp1_irq_frame_end_enable(cap);
470 if (cap->pix.cfg->uv_swap) {
471 u32 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
472
473 rkisp1_write(rkisp1, reg & ~BIT(1),
474 RKISP1_CIF_MI_XTD_FORMAT_CTRL);
475 }
476
477 rkisp1_mi_config_ctrl(cap);
478
479 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
480 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK;
481 mi_ctrl |= cap->pix.cfg->write_format |
482 RKISP1_MI_CTRL_SP_INPUT_YUV422 |
483 cap->pix.cfg->output_format |
484 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
485 rkisp1_write(rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
486}
487
488static void rkisp1_mp_disable(struct rkisp1_capture *cap)
489{
490 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
491
492 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE |
493 RKISP1_CIF_MI_CTRL_RAW_ENABLE);
494 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
495}
496
497static void rkisp1_sp_disable(struct rkisp1_capture *cap)
498{
499 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
500
501 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE;
502 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
503}
504
505static void rkisp1_mp_enable(struct rkisp1_capture *cap)
506{
507 const struct rkisp1_capture_fmt_cfg *isp_fmt = cap->pix.cfg;
508 u32 mi_ctrl;
509
510 rkisp1_mp_disable(cap);
511
512 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
513 if (isp_fmt->fmt_type == RKISP1_FMT_BAYER)
514 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE;
515 /* YUV */
516 else
517 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE;
518
519 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
520}
521
522static void rkisp1_sp_enable(struct rkisp1_capture *cap)
523{
524 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
525
526 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE;
527 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
528}
529
530static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap)
531{
532 if (!cap->is_streaming)
533 return;
534 rkisp1_write(cap->rkisp1,
535 RKISP1_CIF_MI_FRAME(cap), RKISP1_CIF_MI_ICR);
536 cap->ops->disable(cap);
537}
538
539static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap)
540{
541 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED |
542 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
543
544 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en);
545}
546
547static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap)
548{
549 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) &
550 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED);
551}
552
553static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap)
554{
555 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
556
557 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP |
558 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI;
559 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
560}
561
562static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap)
563{
564 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
565
566 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP;
567 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
568}
569
570static struct rkisp1_capture_ops rkisp1_capture_ops_mp = {
571 .config = rkisp1_mp_config,
572 .enable = rkisp1_mp_enable,
573 .disable = rkisp1_mp_disable,
574 .stop = rkisp1_mp_sp_stop,
575 .set_data_path = rkisp1_mp_set_data_path,
576 .is_stopped = rkisp1_mp_is_stopped,
577};
578
579static struct rkisp1_capture_ops rkisp1_capture_ops_sp = {
580 .config = rkisp1_sp_config,
581 .enable = rkisp1_sp_enable,
582 .disable = rkisp1_sp_disable,
583 .stop = rkisp1_mp_sp_stop,
584 .set_data_path = rkisp1_sp_set_data_path,
585 .is_stopped = rkisp1_sp_is_stopped,
586};
587
588/* ----------------------------------------------------------------------------
589 * Frame buffer operations
590 */
591
592static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap)
593{
594 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
595 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy;
596
597 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
598 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
599 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
600
601 /* The driver never access vaddr, no mapping is required */
602 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev,
603 dummy_buf->size,
604 &dummy_buf->dma_addr,
605 GFP_KERNEL,
606 DMA_ATTR_NO_KERNEL_MAPPING);
607 if (!dummy_buf->vaddr)
608 return -ENOMEM;
609
610 return 0;
611}
612
613static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap)
614{
615 dma_free_attrs(cap->rkisp1->dev,
616 cap->buf.dummy.size, cap->buf.dummy.vaddr,
617 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING);
618}
619
620static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
621{
622 /*
623 * Use the dummy space allocated by dma_alloc_coherent to
624 * throw data if there is no available buffer.
625 */
626 if (cap->buf.next) {
627 u32 *buff_addr = cap->buf.next->buff_addr;
628
629 rkisp1_write(cap->rkisp1,
630 buff_addr[RKISP1_PLANE_Y],
631 cap->config->mi.y_base_ad_init);
632 rkisp1_write(cap->rkisp1,
633 buff_addr[RKISP1_PLANE_CB],
634 cap->config->mi.cb_base_ad_init);
635 rkisp1_write(cap->rkisp1,
636 buff_addr[RKISP1_PLANE_CR],
637 cap->config->mi.cr_base_ad_init);
638 } else {
639 rkisp1_write(cap->rkisp1,
640 cap->buf.dummy.dma_addr,
641 cap->config->mi.y_base_ad_init);
642 rkisp1_write(cap->rkisp1,
643 cap->buf.dummy.dma_addr,
644 cap->config->mi.cb_base_ad_init);
645 rkisp1_write(cap->rkisp1,
646 cap->buf.dummy.dma_addr,
647 cap->config->mi.cr_base_ad_init);
648 }
649
650 /* Set plane offsets */
651 rkisp1_write(cap->rkisp1, 0, cap->config->mi.y_offs_cnt_init);
652 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cb_offs_cnt_init);
653 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cr_offs_cnt_init);
654}
655
656/*
657 * This function is called when a frame end comes. The next frame
658 * is processing and we should set up buffer for next-next frame,
659 * otherwise it will overflow.
660 */
661static void rkisp1_handle_buffer(struct rkisp1_capture *cap)
662{
663 struct rkisp1_isp *isp = &cap->rkisp1->isp;
664 struct rkisp1_buffer *curr_buf = cap->buf.curr;
665 unsigned long flags;
666
667 spin_lock_irqsave(&cap->buf.lock, flags);
668
669 if (curr_buf) {
670 curr_buf->vb.sequence = atomic_read(&isp->frame_sequence);
671 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns();
672 curr_buf->vb.field = V4L2_FIELD_NONE;
673 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
674 } else {
675 cap->rkisp1->debug.frame_drop[cap->id]++;
676 }
677
678 cap->buf.curr = cap->buf.next;
679 cap->buf.next = NULL;
680
681 if (!list_empty(&cap->buf.queue)) {
682 cap->buf.next = list_first_entry(&cap->buf.queue,
683 struct rkisp1_buffer,
684 queue);
685 list_del(&cap->buf.next->queue);
686 }
687 spin_unlock_irqrestore(&cap->buf.lock, flags);
688
689 rkisp1_set_next_buf(cap);
690}
691
692void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
693{
694 unsigned int i;
695 u32 status;
696
697 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS);
698 rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR);
699
700 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
701 struct rkisp1_capture *cap = &rkisp1->capture_devs[i];
702
703 if (!(status & RKISP1_CIF_MI_FRAME(cap)))
704 continue;
705 if (!cap->is_stopping) {
706 rkisp1_handle_buffer(cap);
707 continue;
708 }
709 /*
710 * Make sure stream is actually stopped, whose state
711 * can be read from the shadow register, before
712 * wake_up() thread which would immediately free all
713 * frame buffers. stop() takes effect at the next
714 * frame end that sync the configurations to shadow
715 * regs.
716 */
717 if (!cap->ops->is_stopped(cap)) {
718 cap->ops->stop(cap);
719 continue;
720 }
721 cap->is_stopping = false;
722 cap->is_streaming = false;
723 wake_up(&cap->done);
724 }
725}
726
727/* ----------------------------------------------------------------------------
728 * Vb2 operations
729 */
730
731static int rkisp1_vb2_queue_setup(struct vb2_queue *queue,
732 unsigned int *num_buffers,
733 unsigned int *num_planes,
734 unsigned int sizes[],
735 struct device *alloc_devs[])
736{
737 struct rkisp1_capture *cap = queue->drv_priv;
738 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
739 unsigned int i;
740
741 if (*num_planes) {
742 if (*num_planes != pixm->num_planes)
743 return -EINVAL;
744
745 for (i = 0; i < pixm->num_planes; i++)
746 if (sizes[i] < pixm->plane_fmt[i].sizeimage)
747 return -EINVAL;
748 } else {
749 *num_planes = pixm->num_planes;
750 for (i = 0; i < pixm->num_planes; i++)
751 sizes[i] = pixm->plane_fmt[i].sizeimage;
752 }
753
754 return 0;
755}
756
757static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb)
758{
759 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
760 struct rkisp1_buffer *ispbuf =
761 container_of(vbuf, struct rkisp1_buffer, vb);
762 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
763 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
764 unsigned long flags;
765 unsigned int i;
766
767 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
768 for (i = 0; i < pixm->num_planes; i++)
769 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
770
771 /* Convert to non-MPLANE */
772 if (pixm->num_planes == 1) {
773 ispbuf->buff_addr[RKISP1_PLANE_CB] =
774 ispbuf->buff_addr[RKISP1_PLANE_Y] +
775 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y);
776 ispbuf->buff_addr[RKISP1_PLANE_CR] =
777 ispbuf->buff_addr[RKISP1_PLANE_CB] +
778 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB);
779 }
780
781 spin_lock_irqsave(&cap->buf.lock, flags);
782
783 /*
784 * If there's no next buffer assigned, queue this buffer directly
785 * as the next buffer, and update the memory interface.
786 */
787 if (cap->is_streaming && !cap->buf.next &&
788 atomic_read(&cap->rkisp1->isp.frame_sequence) == -1) {
789 cap->buf.next = ispbuf;
790 rkisp1_set_next_buf(cap);
791 } else {
792 list_add_tail(&ispbuf->queue, &cap->buf.queue);
793 }
794 spin_unlock_irqrestore(&cap->buf.lock, flags);
795}
796
797static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb)
798{
799 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
800 unsigned int i;
801
802 for (i = 0; i < cap->pix.fmt.num_planes; i++) {
803 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage;
804
805 if (vb2_plane_size(vb, i) < size) {
806 dev_err(cap->rkisp1->dev,
807 "User buffer too small (%ld < %ld)\n",
808 vb2_plane_size(vb, i), size);
809 return -EINVAL;
810 }
811 vb2_set_plane_payload(vb, i, size);
812 }
813
814 return 0;
815}
816
817static void rkisp1_return_all_buffers(struct rkisp1_capture *cap,
818 enum vb2_buffer_state state)
819{
820 unsigned long flags;
821 struct rkisp1_buffer *buf;
822
823 spin_lock_irqsave(&cap->buf.lock, flags);
824 if (cap->buf.curr) {
825 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state);
826 cap->buf.curr = NULL;
827 }
828 if (cap->buf.next) {
829 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state);
830 cap->buf.next = NULL;
831 }
832 while (!list_empty(&cap->buf.queue)) {
833 buf = list_first_entry(&cap->buf.queue,
834 struct rkisp1_buffer, queue);
835 list_del(&buf->queue);
836 vb2_buffer_done(&buf->vb.vb2_buf, state);
837 }
838 spin_unlock_irqrestore(&cap->buf.lock, flags);
839}
840
841/*
842 * rkisp1_pipeline_sink_walk - Walk through the pipeline and call cb
843 * @from: entity at which to start pipeline walk
844 * @until: entity at which to stop pipeline walk
845 *
846 * Walk the entities chain starting at the pipeline video node and stop
847 * all subdevices in the chain.
848 *
849 * If the until argument isn't NULL, stop the pipeline walk when reaching the
850 * until entity. This is used to disable a partially started pipeline due to a
851 * subdev start error.
852 */
853static int rkisp1_pipeline_sink_walk(struct media_entity *from,
854 struct media_entity *until,
855 int (*cb)(struct media_entity *from,
856 struct media_entity *curr))
857{
858 struct media_entity *entity = from;
859 struct media_pad *pad;
860 unsigned int i;
861 int ret;
862
863 while (1) {
864 pad = NULL;
865 /* Find remote source pad */
866 for (i = 0; i < entity->num_pads; i++) {
867 struct media_pad *spad = &entity->pads[i];
868
869 if (!(spad->flags & MEDIA_PAD_FL_SINK))
870 continue;
871 pad = media_entity_remote_pad(spad);
872 if (pad && is_media_entity_v4l2_subdev(pad->entity))
873 break;
874 }
875 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
876 break;
877
878 entity = pad->entity;
879 if (entity == until)
880 break;
881
882 ret = cb(from, entity);
883 if (ret)
884 return ret;
885 }
886
887 return 0;
888}
889
890static int rkisp1_pipeline_disable_cb(struct media_entity *from,
891 struct media_entity *curr)
892{
893 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(curr);
894
895 return v4l2_subdev_call(sd, video, s_stream, false);
896}
897
898static int rkisp1_pipeline_enable_cb(struct media_entity *from,
899 struct media_entity *curr)
900{
901 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(curr);
902
903 return v4l2_subdev_call(sd, video, s_stream, true);
904}
905
906static void rkisp1_stream_stop(struct rkisp1_capture *cap)
907{
908 int ret;
909
910 /* Stream should stop in interrupt. If it dosn't, stop it by force. */
911 cap->is_stopping = true;
912 ret = wait_event_timeout(cap->done,
913 !cap->is_streaming,
914 msecs_to_jiffies(1000));
915 if (!ret) {
916 cap->rkisp1->debug.stop_timeout[cap->id]++;
917 cap->ops->stop(cap);
918 cap->is_stopping = false;
919 cap->is_streaming = false;
920 }
921}
922
923static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue)
924{
925 struct rkisp1_capture *cap = queue->drv_priv;
926 struct rkisp1_vdev_node *node = &cap->vnode;
927 struct rkisp1_device *rkisp1 = cap->rkisp1;
928 int ret;
929
930 rkisp1_stream_stop(cap);
931 media_pipeline_stop(&node->vdev.entity);
932 ret = rkisp1_pipeline_sink_walk(&node->vdev.entity, NULL,
933 rkisp1_pipeline_disable_cb);
934 if (ret)
935 dev_err(rkisp1->dev,
936 "pipeline stream-off failed error:%d\n", ret);
937
938 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR);
939
8fd390b8 940 v4l2_pipeline_pm_put(&node->vdev.entity);
56e3b29f
HK		 941 ret = pm_runtime_put(rkisp1->dev);
942 if (ret)
943 dev_err(rkisp1->dev, "power down failed error:%d\n", ret);
944
945 rkisp1_dummy_buf_destroy(cap);
946}
947
948/*
949 * Most of registers inside rockchip ISP1 have shadow register since
950 * they must be not be changed during processing a frame.
951 * Usually, each sub-module updates its shadow register after
952 * processing the last pixel of a frame.
953 */
954static void rkisp1_stream_start(struct rkisp1_capture *cap)
955{
956 struct rkisp1_device *rkisp1 = cap->rkisp1;
957 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
958
959 cap->ops->set_data_path(cap);
960 cap->ops->config(cap);
961
962 /* Setup a buffer for the next frame */
963 rkisp1_handle_buffer(cap);
964 cap->ops->enable(cap);
965 /* It's safe to config ACTIVE and SHADOW regs for the
966 * first stream. While when the second is starting, do NOT
967 * force update because it also update the first one.
968 *
969 * The latter case would drop one more buf(that is 2) since
970 * there's not buf in shadow when the second FE received. This's
971 * also required because the second FE maybe corrupt especially
972 * when run at 120fps.
973 */
974 if (!other->is_streaming) {
975 /* force cfg update */
976 rkisp1_write(rkisp1,
977 RKISP1_CIF_MI_INIT_SOFT_UPD, RKISP1_CIF_MI_INIT);
978 rkisp1_handle_buffer(cap);
979 }
980 cap->is_streaming = true;
981}
982
983static int
984rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
985{
986 struct rkisp1_capture *cap = queue->drv_priv;
987 struct media_entity *entity = &cap->vnode.vdev.entity;
988 int ret;
989
990 ret = rkisp1_dummy_buf_create(cap);
991 if (ret)
992 goto err_ret_buffers;
993
994 ret = pm_runtime_get_sync(cap->rkisp1->dev);
995 if (ret) {
996 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret);
997 goto err_destroy_dummy;
998 }
8fd390b8 999 ret = v4l2_pipeline_pm_get(entity);
56e3b29f
HK		 1000 if (ret) {
1001 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret);
1002 goto err_pipe_pm_put;
1003 }
1004
1005 rkisp1_stream_start(cap);
1006
1007 /* start sub-devices */
1008 ret = rkisp1_pipeline_sink_walk(entity, NULL,
1009 rkisp1_pipeline_enable_cb);
1010 if (ret)
1011 goto err_stop_stream;
1012
1013 ret = media_pipeline_start(entity, &cap->rkisp1->pipe);
1014 if (ret) {
1015 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret);
1016 goto err_pipe_disable;
1017 }
1018
1019 return 0;
1020
1021err_pipe_disable:
1022 rkisp1_pipeline_sink_walk(entity, NULL, rkisp1_pipeline_disable_cb);
1023err_stop_stream:
1024 rkisp1_stream_stop(cap);
8fd390b8 1025 v4l2_pipeline_pm_put(entity);
56e3b29f
HK		 1026err_pipe_pm_put:
1027 pm_runtime_put(cap->rkisp1->dev);
1028err_destroy_dummy:
1029 rkisp1_dummy_buf_destroy(cap);
1030err_ret_buffers:
1031 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED);
1032
1033 return ret;
1034}
1035
1036static struct vb2_ops rkisp1_vb2_ops = {
1037 .queue_setup = rkisp1_vb2_queue_setup,
1038 .buf_queue = rkisp1_vb2_buf_queue,
1039 .buf_prepare = rkisp1_vb2_buf_prepare,
1040 .wait_prepare = vb2_ops_wait_prepare,
1041 .wait_finish = vb2_ops_wait_finish,
1042 .stop_streaming = rkisp1_vb2_stop_streaming,
1043 .start_streaming = rkisp1_vb2_start_streaming,
1044};
1045
1046/* ----------------------------------------------------------------------------
1047 * IOCTLs operations
1048 */
1049
1050static const struct v4l2_format_info *
1051rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm,
1052 enum rkisp1_stream_id id)
1053{
1054 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0];
1055 const struct v4l2_format_info *info;
1056 unsigned int i;
1057 u32 stride;
1058
1059 info = v4l2_format_info(pixm->pixelformat);
1060 pixm->num_planes = info->mem_planes;
1061 stride = info->bpp[0] * pixm->width;
1062 /* Self path supports custom stride but Main path doesn't */
1063 if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride)
1064 plane_y->bytesperline = stride;
1065 plane_y->sizeimage = plane_y->bytesperline * pixm->height;
1066
1067 /* normalize stride to pixels per line */
1068 stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]);
1069
1070 for (i = 1; i < info->comp_planes; i++) {
1071 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i];
1072
1073 /* bytesperline for other components derive from Y component */
1074 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) *
1075 info->bpp[i];
1076 plane->sizeimage = plane->bytesperline *
1077 DIV_ROUND_UP(pixm->height, info->vdiv);
1078 }
1079
1080 /*
1081 * If pixfmt is packed, then plane_fmt[0] should contain the total size
1082 * considering all components. plane_fmt[i] for i > 0 should be ignored
1083 * by userspace as mem_planes == 1, but we are keeping information there
1084 * for convenience.
1085 */
1086 if (info->mem_planes == 1)
1087 for (i = 1; i < info->comp_planes; i++)
1088 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage;
1089
1090 return info;
1091}
1092
1093static const struct rkisp1_capture_fmt_cfg *
1094rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt)
1095{
1096 unsigned int i;
1097
1098 for (i = 0; i < cap->config->fmt_size; i++) {
1099 if (cap->config->fmts[i].fourcc == pixelfmt)
1100 return &cap->config->fmts[i];
1101 }
1102 return NULL;
1103}
1104
1105static void rkisp1_try_fmt(const struct rkisp1_capture *cap,
1106 struct v4l2_pix_format_mplane *pixm,
1107 const struct rkisp1_capture_fmt_cfg **fmt_cfg,
1108 const struct v4l2_format_info **fmt_info)
1109{
1110 const struct rkisp1_capture_config *config = cap->config;
1111 struct rkisp1_capture *other_cap =
1112 &cap->rkisp1->capture_devs[cap->id ^ 1];
1113 const struct rkisp1_capture_fmt_cfg *fmt;
1114 const struct v4l2_format_info *info;
1115 const unsigned int max_widths[] = { RKISP1_RSZ_MP_SRC_MAX_WIDTH,
1116 RKISP1_RSZ_SP_SRC_MAX_WIDTH };
1117 const unsigned int max_heights[] = { RKISP1_RSZ_MP_SRC_MAX_HEIGHT,
1118 RKISP1_RSZ_SP_SRC_MAX_HEIGHT};
1119
1120 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat);
1121 if (!fmt) {
1122 fmt = config->fmts;
1123 pixm->pixelformat = fmt->fourcc;
1124 }
1125
1126 pixm->width = clamp_t(u32, pixm->width,
1127 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]);
1128 pixm->height = clamp_t(u32, pixm->height,
1129 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]);
1130
1131 pixm->field = V4L2_FIELD_NONE;
1132 pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
1133 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1134
1135 info = rkisp1_fill_pixfmt(pixm, cap->id);
1136
1137 /* can not change quantization when stream-on */
1138 if (other_cap->is_streaming)
1139 pixm->quantization = other_cap->pix.fmt.quantization;
1140 /* output full range by default, take effect in params */
1141 else if (!pixm->quantization ||
1142 pixm->quantization > V4L2_QUANTIZATION_LIM_RANGE)
1143 pixm->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1144
1145 if (fmt_cfg)
1146 *fmt_cfg = fmt;
1147 if (fmt_info)
1148 *fmt_info = info;
1149}
1150
1151static void rkisp1_set_fmt(struct rkisp1_capture *cap,
1152 struct v4l2_pix_format_mplane *pixm)
1153{
1154 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info);
1155 cap->pix.fmt = *pixm;
1156
1157 /* SP supports custom stride in number of pixels of the Y plane */
1158 if (cap->id == RKISP1_SELFPATH)
1159 cap->sp_y_stride = pixm->plane_fmt[0].bytesperline /
1160 cap->pix.info->bpp[0];
1161}
1162
1163static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh,
1164 struct v4l2_format *f)
1165{
1166 struct rkisp1_capture *cap = video_drvdata(file);
1167
1168 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL);
1169
1170 return 0;
1171}
1172
1173static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
1174 struct v4l2_fmtdesc *f)
1175{
1176 struct rkisp1_capture *cap = video_drvdata(file);
1177 const struct rkisp1_capture_fmt_cfg *fmt = NULL;
1178
1179 if (f->index >= cap->config->fmt_size)
1180 return -EINVAL;
1181
1182 fmt = &cap->config->fmts[f->index];
1183 f->pixelformat = fmt->fourcc;
1184
1185 return 0;
1186}
1187
1188static int rkisp1_s_fmt_vid_cap_mplane(struct file *file,
1189 void *priv, struct v4l2_format *f)
1190{
1191 struct rkisp1_capture *cap = video_drvdata(file);
1192 struct rkisp1_vdev_node *node =
1193 rkisp1_vdev_to_node(&cap->vnode.vdev);
1194
1195 if (vb2_is_busy(&node->buf_queue))
1196 return -EBUSY;
1197
1198 rkisp1_set_fmt(cap, &f->fmt.pix_mp);
1199
1200 return 0;
1201}
1202
1203static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh,
1204 struct v4l2_format *f)
1205{
1206 struct rkisp1_capture *cap = video_drvdata(file);
1207
1208 f->fmt.pix_mp = cap->pix.fmt;
1209
1210 return 0;
1211}
1212
1213static int
1214rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
1215{
1216 struct rkisp1_capture *cap_dev = video_drvdata(file);
1217 struct rkisp1_device *rkisp1 = cap_dev->rkisp1;
1218
1219 strscpy(cap->driver, rkisp1->dev->driver->name, sizeof(cap->driver));
1220 strscpy(cap->card, rkisp1->dev->driver->name, sizeof(cap->card));
1221 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info));
1222
1223 return 0;
1224}
1225
1226static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = {
1227 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1228 .vidioc_querybuf = vb2_ioctl_querybuf,
1229 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1230 .vidioc_qbuf = vb2_ioctl_qbuf,
1231 .vidioc_expbuf = vb2_ioctl_expbuf,
1232 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1233 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1234 .vidioc_streamon = vb2_ioctl_streamon,
1235 .vidioc_streamoff = vb2_ioctl_streamoff,
1236 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane,
1237 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane,
1238 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane,
1239 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane,
1240 .vidioc_querycap = rkisp1_querycap,
1241 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1242 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1243};
1244
1245static int rkisp1_capture_link_validate(struct media_link *link)
1246{
1247 struct video_device *vdev =
1248 media_entity_to_video_device(link->sink->entity);
1249 struct v4l2_subdev *sd =
1250 media_entity_to_v4l2_subdev(link->source->entity);
1251 struct rkisp1_capture *cap = video_get_drvdata(vdev);
1252 struct rkisp1_isp *isp = &cap->rkisp1->isp;
1253 struct v4l2_subdev_format sd_fmt;
1254 int ret;
1255
1256 if (cap->id == RKISP1_SELFPATH &&
1257 isp->src_fmt->mbus_code != MEDIA_BUS_FMT_YUYV8_2X8) {
1258 dev_err(cap->rkisp1->dev,
1259 "selfpath only supports MEDIA_BUS_FMT_YUYV8_2X8\n");
1260 return -EPIPE;
1261 }
1262
1263 if (cap->pix.cfg->fmt_type != isp->src_fmt->fmt_type) {
1264 dev_err(cap->rkisp1->dev,
1265 "format type mismatch in link '%s:%d->%s:%d'\n",
1266 link->source->entity->name, link->source->index,
1267 link->sink->entity->name, link->sink->index);
1268 return -EPIPE;
1269 }
1270
1271 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1272 sd_fmt.pad = link->source->index;
1273 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt);
1274 if (ret)
1275 return ret;
1276
1277 if (sd_fmt.format.height != cap->pix.fmt.height ||
1278 sd_fmt.format.width != cap->pix.fmt.width)
1279 return -EPIPE;
1280
1281 return 0;
1282}
1283
1284/* ----------------------------------------------------------------------------
1285 * core functions
1286 */
1287
1288static const struct media_entity_operations rkisp1_media_ops = {
1289 .link_validate = rkisp1_capture_link_validate,
1290};
1291
1292static const struct v4l2_file_operations rkisp1_fops = {
1293 .open = v4l2_fh_open,
1294 .release = vb2_fop_release,
1295 .unlocked_ioctl = video_ioctl2,
1296 .poll = vb2_fop_poll,
1297 .mmap = vb2_fop_mmap,
1298};
1299
1300static void rkisp1_unregister_capture(struct rkisp1_capture *cap)
1301{
1302 media_entity_cleanup(&cap->vnode.vdev.entity);
1303 video_unregister_device(&cap->vnode.vdev);
1304}
1305
1306void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1)
1307{
1308 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH];
1309 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH];
1310
1311 rkisp1_unregister_capture(mp);
1312 rkisp1_unregister_capture(sp);
1313}
1314
1315static int rkisp1_register_capture(struct rkisp1_capture *cap)
1316{
1317 const char * const dev_names[] = {RKISP1_MP_DEV_NAME,
1318 RKISP1_SP_DEV_NAME};
1319 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev;
1320 struct video_device *vdev = &cap->vnode.vdev;
1321 struct rkisp1_vdev_node *node;
1322 struct vb2_queue *q;
1323 int ret;
1324
1325 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name));
1326 node = rkisp1_vdev_to_node(vdev);
1327 mutex_init(&node->vlock);
1328
1329 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops;
1330 vdev->release = video_device_release_empty;
1331 vdev->fops = &rkisp1_fops;
1332 vdev->minor = -1;
1333 vdev->v4l2_dev = v4l2_dev;
1334 vdev->lock = &node->vlock;
1335 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1336 V4L2_CAP_STREAMING;
1337 vdev->entity.ops = &rkisp1_media_ops;
1338 video_set_drvdata(vdev, cap);
1339 vdev->vfl_dir = VFL_DIR_RX;
1340 node->pad.flags = MEDIA_PAD_FL_SINK;
1341
1342 q = &node->buf_queue;
1343 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
5f028c51 1344 q->io_modes = VB2_MMAP | VB2_DMABUF;
56e3b29f
HK		 1345 q->drv_priv = cap;
1346 q->ops = &rkisp1_vb2_ops;
1347 q->mem_ops = &vb2_dma_contig_memops;
1348 q->buf_struct_size = sizeof(struct rkisp1_buffer);
1349 q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED;
1350 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1351 q->lock = &node->vlock;
1352 q->dev = cap->rkisp1->dev;
1353 ret = vb2_queue_init(q);
1354 if (ret) {
1355 dev_err(cap->rkisp1->dev,
1356 "vb2 queue init failed (err=%d)\n", ret);
1357 return ret;
1358 }
1359
1360 vdev->queue = q;
1361
0e17c50f 1362 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
56e3b29f
HK		 1363 if (ret) {
1364 dev_err(cap->rkisp1->dev,
1365 "failed to register %s, ret=%d\n", vdev->name, ret);
1366 return ret;
1367 }
1368 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name,
1369 vdev->num);
1370
1371 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
1372 if (ret) {
1373 video_unregister_device(vdev);
1374 return ret;
1375 }
1376
1377 return 0;
1378}
1379
1380static void
1381rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id)
1382{
1383 struct rkisp1_capture *cap = &rkisp1->capture_devs[id];
1384 struct v4l2_pix_format_mplane pixm;
1385
1386 memset(cap, 0, sizeof(*cap));
1387 cap->id = id;
1388 cap->rkisp1 = rkisp1;
1389
1390 INIT_LIST_HEAD(&cap->buf.queue);
1391 init_waitqueue_head(&cap->done);
1392 spin_lock_init(&cap->buf.lock);
1393 if (cap->id == RKISP1_SELFPATH) {
1394 cap->ops = &rkisp1_capture_ops_sp;
1395 cap->config = &rkisp1_capture_config_sp;
1396 } else {
1397 cap->ops = &rkisp1_capture_ops_mp;
1398 cap->config = &rkisp1_capture_config_mp;
1399 }
1400
1401 cap->is_streaming = false;
1402
1403 memset(&pixm, 0, sizeof(pixm));
1404 pixm.pixelformat = V4L2_PIX_FMT_YUYV;
1405 pixm.width = RKISP1_DEFAULT_WIDTH;
1406 pixm.height = RKISP1_DEFAULT_HEIGHT;
1407 rkisp1_set_fmt(cap, &pixm);
1408}
1409
1410int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1)
1411{
1412 struct rkisp1_capture *cap;
1413 unsigned int i, j;
1414 int ret;
1415
1416 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) {
1417 rkisp1_capture_init(rkisp1, i);
1418 cap = &rkisp1->capture_devs[i];
1419 cap->rkisp1 = rkisp1;
1420 ret = rkisp1_register_capture(cap);
1421 if (ret)
1422 goto err_unreg_capture_devs;
1423 }
1424
1425 return 0;
1426
1427err_unreg_capture_devs:
1428 for (j = 0; j < i; j++) {
1429 cap = &rkisp1->capture_devs[j];
1430 rkisp1_unregister_capture(cap);
1431 }
1432
1433 return ret;
1434}
Linux 6.x block layer and io_uring tree(s)