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7807063b RMS |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver | |
4 | * | |
5 | * Copyright (C) 2019 Linaro Ltd | |
6 | * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. | |
7 | * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
fc120960 | 12 | #include <linux/debugfs.h> |
7807063b RMS |
13 | #include <linux/delay.h> |
14 | #include <linux/errno.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
7807063b | 17 | #include <linux/kernel.h> |
7807063b | 18 | #include <linux/module.h> |
9994e00d LP |
19 | #include <linux/mutex.h> |
20 | #include <linux/of.h> | |
f0e7cfbb | 21 | #include <linux/of_device.h> |
7807063b RMS |
22 | #include <linux/platform_device.h> |
23 | #include <linux/pm_runtime.h> | |
7807063b | 24 | #include <linux/regulator/consumer.h> |
9994e00d | 25 | #include <linux/reset.h> |
7807063b RMS |
26 | #include <linux/spinlock.h> |
27 | ||
74f81584 | 28 | #include <media/v4l2-common.h> |
7807063b RMS |
29 | #include <media/v4l2-device.h> |
30 | #include <media/v4l2-fwnode.h> | |
6e996653 | 31 | #include <media/v4l2-mc.h> |
7807063b RMS |
32 | #include <media/v4l2-subdev.h> |
33 | ||
2c2ae48d | 34 | #define CSIS_DRIVER_NAME "imx7-mipi-csis" |
7807063b | 35 | |
2c2ae48d LP |
36 | #define CSIS_PAD_SINK 0 |
37 | #define CSIS_PAD_SOURCE 1 | |
38 | #define CSIS_PADS_NUM 2 | |
7807063b | 39 | |
2c2ae48d LP |
40 | #define MIPI_CSIS_DEF_PIX_WIDTH 640 |
41 | #define MIPI_CSIS_DEF_PIX_HEIGHT 480 | |
7807063b RMS |
42 | |
43 | /* Register map definition */ | |
44 | ||
45 | /* CSIS common control */ | |
46 | #define MIPI_CSIS_CMN_CTRL 0x04 | |
47 | #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) | |
48 | #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) | |
49 | #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) | |
50 | #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) | |
51 | #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) | |
52 | ||
53 | #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 | |
54 | #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) | |
55 | ||
56 | /* CSIS clock control */ | |
57 | #define MIPI_CSIS_CLK_CTRL 0x08 | |
58 | #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) | |
59 | #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) | |
60 | #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) | |
61 | #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) | |
62 | #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) | |
63 | #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) | |
64 | ||
65 | /* CSIS Interrupt mask */ | |
7b437a24 LP |
66 | #define MIPI_CSIS_INT_MSK 0x10 |
67 | #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) | |
68 | #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) | |
69 | #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) | |
70 | #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) | |
71 | #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) | |
72 | #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) | |
73 | #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) | |
74 | #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) | |
75 | #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) | |
76 | #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) | |
77 | #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) | |
78 | #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) | |
79 | #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) | |
80 | #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) | |
7807063b RMS |
81 | |
82 | /* CSIS Interrupt source */ | |
7b437a24 LP |
83 | #define MIPI_CSIS_INT_SRC 0x14 |
84 | #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) | |
85 | #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) | |
86 | #define MIPI_CSIS_INT_SRC_EVEN BIT(30) | |
87 | #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) | |
88 | #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) | |
89 | #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) | |
90 | #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) | |
91 | #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) | |
92 | #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) | |
93 | #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) | |
94 | #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) | |
95 | #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) | |
96 | #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) | |
97 | #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) | |
98 | #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) | |
99 | #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) | |
100 | #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) | |
101 | #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff | |
7807063b RMS |
102 | |
103 | /* D-PHY status control */ | |
7b437a24 LP |
104 | #define MIPI_CSIS_DPHY_STATUS 0x20 |
105 | #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) | |
106 | #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) | |
107 | #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) | |
108 | #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) | |
7807063b RMS |
109 | |
110 | /* D-PHY common control */ | |
7b437a24 LP |
111 | #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 |
112 | #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) | |
113 | #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) | |
114 | #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) | |
115 | #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) | |
116 | #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) | |
117 | #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) | |
118 | #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) | |
119 | #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) | |
120 | #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) | |
7807063b RMS |
121 | |
122 | /* D-PHY Master and Slave Control register Low */ | |
e3851164 LP |
123 | #define MIPI_CSIS_DPHY_BCTRL_L 0x30 |
124 | #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) | |
125 | #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) | |
126 | #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) | |
127 | #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) | |
128 | #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) | |
129 | #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) | |
130 | #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) | |
131 | #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) | |
132 | #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) | |
133 | #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) | |
134 | #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) | |
135 | #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) | |
136 | #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) | |
137 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) | |
138 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) | |
139 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) | |
140 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) | |
141 | #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) | |
142 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) | |
143 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) | |
144 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) | |
145 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) | |
146 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) | |
147 | #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) | |
148 | #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) | |
149 | #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) | |
150 | #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) | |
151 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) | |
152 | #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) | |
153 | #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) | |
154 | #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) | |
155 | #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) | |
156 | #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) | |
157 | ||
7807063b | 158 | /* D-PHY Master and Slave Control register High */ |
e3851164 | 159 | #define MIPI_CSIS_DPHY_BCTRL_H 0x34 |
7807063b | 160 | /* D-PHY Slave Control register Low */ |
e3851164 | 161 | #define MIPI_CSIS_DPHY_SCTRL_L 0x38 |
7807063b | 162 | /* D-PHY Slave Control register High */ |
e3851164 | 163 | #define MIPI_CSIS_DPHY_SCTRL_H 0x3c |
7807063b RMS |
164 | |
165 | /* ISP Configuration register */ | |
7b437a24 | 166 | #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) |
7807063b RMS |
167 | #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) |
168 | #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) | |
ca403b37 LP |
169 | #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) |
170 | #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) | |
171 | #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ | |
7807063b | 172 | #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) |
3acb8889 | 173 | #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) |
2c2ae48d | 174 | #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) |
7807063b RMS |
175 | |
176 | /* ISP Image Resolution register */ | |
7b437a24 | 177 | #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) |
2c2ae48d LP |
178 | #define CSIS_MAX_PIX_WIDTH 0xffff |
179 | #define CSIS_MAX_PIX_HEIGHT 0xffff | |
7807063b RMS |
180 | |
181 | /* ISP SYNC register */ | |
7b437a24 LP |
182 | #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) |
183 | #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 | |
184 | #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 | |
185 | #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 | |
7807063b | 186 | |
1cb3ff13 LP |
187 | /* ISP shadow registers */ |
188 | #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) | |
189 | #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) | |
190 | #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) | |
191 | ||
4fe5bb0b LP |
192 | /* Debug control register */ |
193 | #define MIPI_CSIS_DBG_CTRL 0xc0 | |
7fe1de81 LP |
194 | #define MIPI_CSIS_DBG_INTR_MSK 0xc4 |
195 | #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) | |
196 | #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) | |
197 | #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) | |
198 | #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) | |
199 | #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) | |
200 | #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) | |
201 | #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) | |
202 | #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) | |
203 | #define MIPI_CSIS_DBG_INTR_SRC 0xc8 | |
204 | #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) | |
205 | #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) | |
206 | #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) | |
207 | #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) | |
208 | #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) | |
209 | #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) | |
210 | #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) | |
211 | #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) | |
4fe5bb0b | 212 | |
95a13790 LP |
213 | #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) |
214 | ||
7807063b | 215 | /* Non-image packet data buffers */ |
2c2ae48d LP |
216 | #define MIPI_CSIS_PKTDATA_ODD 0x2000 |
217 | #define MIPI_CSIS_PKTDATA_EVEN 0x3000 | |
218 | #define MIPI_CSIS_PKTDATA_SIZE SZ_4K | |
7807063b | 219 | |
2c2ae48d | 220 | #define DEFAULT_SCLK_CSIS_FREQ 166000000UL |
7807063b | 221 | |
3acb8889 LP |
222 | /* MIPI CSI-2 Data Types */ |
223 | #define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18 | |
224 | #define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19 | |
225 | #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a | |
226 | #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c | |
227 | #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d | |
228 | #define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e | |
229 | #define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f | |
230 | #define MIPI_CSI2_DATA_TYPE_RGB565 0x22 | |
231 | #define MIPI_CSI2_DATA_TYPE_RGB666 0x23 | |
232 | #define MIPI_CSI2_DATA_TYPE_RGB888 0x24 | |
233 | #define MIPI_CSI2_DATA_TYPE_RAW6 0x28 | |
234 | #define MIPI_CSI2_DATA_TYPE_RAW7 0x29 | |
235 | #define MIPI_CSI2_DATA_TYPE_RAW8 0x2a | |
236 | #define MIPI_CSI2_DATA_TYPE_RAW10 0x2b | |
237 | #define MIPI_CSI2_DATA_TYPE_RAW12 0x2c | |
238 | #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d | |
239 | #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) | |
240 | ||
7807063b RMS |
241 | enum { |
242 | ST_POWERED = 1, | |
243 | ST_STREAMING = 2, | |
244 | ST_SUSPENDED = 4, | |
245 | }; | |
246 | ||
247 | struct mipi_csis_event { | |
7fe1de81 | 248 | bool debug; |
7807063b RMS |
249 | u32 mask; |
250 | const char * const name; | |
251 | unsigned int counter; | |
252 | }; | |
253 | ||
254 | static const struct mipi_csis_event mipi_csis_events[] = { | |
255 | /* Errors */ | |
7fe1de81 LP |
256 | { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, |
257 | { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, | |
258 | { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, | |
259 | { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, | |
260 | { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, | |
261 | { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, | |
262 | { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, | |
263 | { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, | |
264 | { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, | |
265 | { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, | |
266 | { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, | |
267 | { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, | |
268 | { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, | |
269 | { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, | |
7807063b | 270 | /* Non-image data receive events */ |
7fe1de81 LP |
271 | { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, |
272 | { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, | |
273 | { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, | |
274 | { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, | |
7807063b | 275 | /* Frame start/end */ |
7fe1de81 LP |
276 | { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, |
277 | { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, | |
278 | { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, | |
279 | { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, | |
7807063b RMS |
280 | }; |
281 | ||
282 | #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) | |
283 | ||
6e1de006 LP |
284 | enum mipi_csis_clk { |
285 | MIPI_CSIS_CLK_PCLK, | |
286 | MIPI_CSIS_CLK_WRAP, | |
287 | MIPI_CSIS_CLK_PHY, | |
f0e7cfbb | 288 | MIPI_CSIS_CLK_AXI, |
6e1de006 LP |
289 | }; |
290 | ||
291 | static const char * const mipi_csis_clk_id[] = { | |
292 | "pclk", | |
293 | "wrap", | |
294 | "phy", | |
f0e7cfbb LP |
295 | "axi", |
296 | }; | |
297 | ||
298 | enum mipi_csis_version { | |
299 | MIPI_CSIS_V3_3, | |
300 | MIPI_CSIS_V3_6_3, | |
301 | }; | |
302 | ||
303 | struct mipi_csis_info { | |
304 | enum mipi_csis_version version; | |
305 | unsigned int num_clocks; | |
6e1de006 | 306 | }; |
7807063b | 307 | |
7807063b | 308 | struct csi_state { |
7807063b | 309 | struct device *dev; |
7807063b | 310 | void __iomem *regs; |
7807063b | 311 | struct clk_bulk_data *clks; |
0092d4a8 LP |
312 | struct reset_control *mrst; |
313 | struct regulator *mipi_phy_regulator; | |
f0e7cfbb | 314 | const struct mipi_csis_info *info; |
7807063b | 315 | |
0092d4a8 LP |
316 | struct v4l2_subdev sd; |
317 | struct media_pad pads[CSIS_PADS_NUM]; | |
318 | struct v4l2_async_notifier notifier; | |
319 | struct v4l2_subdev *src_sd; | |
320 | ||
321 | struct v4l2_fwnode_bus_mipi_csi2 bus; | |
7807063b RMS |
322 | u32 clk_frequency; |
323 | u32 hs_settle; | |
996f6f51 | 324 | u32 clk_settle; |
7807063b | 325 | |
0092d4a8 | 326 | struct mutex lock; /* Protect csis_fmt, format_mbus and state */ |
7807063b RMS |
327 | const struct csis_pix_format *csis_fmt; |
328 | struct v4l2_mbus_framefmt format_mbus; | |
0092d4a8 | 329 | u32 state; |
7807063b | 330 | |
0092d4a8 | 331 | spinlock_t slock; /* Protect events */ |
7807063b | 332 | struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; |
0092d4a8 | 333 | struct dentry *debugfs_root; |
385031b6 LP |
334 | struct { |
335 | bool enable; | |
336 | u32 hs_settle; | |
337 | u32 clk_settle; | |
338 | } debug; | |
7807063b RMS |
339 | }; |
340 | ||
b329650e LP |
341 | /* ----------------------------------------------------------------------------- |
342 | * Format helpers | |
343 | */ | |
344 | ||
7807063b | 345 | struct csis_pix_format { |
7807063b | 346 | u32 code; |
3acb8889 | 347 | u32 data_type; |
a0ec36a3 | 348 | u8 width; |
7807063b RMS |
349 | }; |
350 | ||
351 | static const struct csis_pix_format mipi_csis_formats[] = { | |
d9a7dd2f | 352 | /* YUV formats. */ |
7807063b | 353 | { |
aeceec5e | 354 | .code = MEDIA_BUS_FMT_UYVY8_1X16, |
3acb8889 | 355 | .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8, |
aeceec5e | 356 | .width = 16, |
d9a7dd2f LP |
357 | }, |
358 | /* RAW (Bayer and greyscale) formats. */ | |
359 | { | |
7807063b | 360 | .code = MEDIA_BUS_FMT_SBGGR8_1X8, |
3acb8889 | 361 | .data_type = MIPI_CSI2_DATA_TYPE_RAW8, |
a0ec36a3 | 362 | .width = 8, |
7807063b | 363 | }, { |
d9a7dd2f | 364 | .code = MEDIA_BUS_FMT_SGBRG8_1X8, |
3acb8889 | 365 | .data_type = MIPI_CSI2_DATA_TYPE_RAW8, |
a0ec36a3 | 366 | .width = 8, |
d9a7dd2f LP |
367 | }, { |
368 | .code = MEDIA_BUS_FMT_SGRBG8_1X8, | |
3acb8889 | 369 | .data_type = MIPI_CSI2_DATA_TYPE_RAW8, |
a0ec36a3 | 370 | .width = 8, |
d9a7dd2f LP |
371 | }, { |
372 | .code = MEDIA_BUS_FMT_SRGGB8_1X8, | |
3acb8889 | 373 | .data_type = MIPI_CSI2_DATA_TYPE_RAW8, |
a0ec36a3 | 374 | .width = 8, |
e1a7461b LP |
375 | }, { |
376 | .code = MEDIA_BUS_FMT_Y8_1X8, | |
3acb8889 | 377 | .data_type = MIPI_CSI2_DATA_TYPE_RAW8, |
a0ec36a3 | 378 | .width = 8, |
d9a7dd2f LP |
379 | }, { |
380 | .code = MEDIA_BUS_FMT_SBGGR10_1X10, | |
3acb8889 | 381 | .data_type = MIPI_CSI2_DATA_TYPE_RAW10, |
a0ec36a3 | 382 | .width = 10, |
d9a7dd2f LP |
383 | }, { |
384 | .code = MEDIA_BUS_FMT_SGBRG10_1X10, | |
3acb8889 | 385 | .data_type = MIPI_CSI2_DATA_TYPE_RAW10, |
a0ec36a3 | 386 | .width = 10, |
d9a7dd2f LP |
387 | }, { |
388 | .code = MEDIA_BUS_FMT_SGRBG10_1X10, | |
3acb8889 | 389 | .data_type = MIPI_CSI2_DATA_TYPE_RAW10, |
a0ec36a3 | 390 | .width = 10, |
d9a7dd2f LP |
391 | }, { |
392 | .code = MEDIA_BUS_FMT_SRGGB10_1X10, | |
3acb8889 | 393 | .data_type = MIPI_CSI2_DATA_TYPE_RAW10, |
a0ec36a3 | 394 | .width = 10, |
e1a7461b LP |
395 | }, { |
396 | .code = MEDIA_BUS_FMT_Y10_1X10, | |
3acb8889 | 397 | .data_type = MIPI_CSI2_DATA_TYPE_RAW10, |
a0ec36a3 | 398 | .width = 10, |
d9a7dd2f LP |
399 | }, { |
400 | .code = MEDIA_BUS_FMT_SBGGR12_1X12, | |
3acb8889 | 401 | .data_type = MIPI_CSI2_DATA_TYPE_RAW12, |
a0ec36a3 | 402 | .width = 12, |
d9a7dd2f LP |
403 | }, { |
404 | .code = MEDIA_BUS_FMT_SGBRG12_1X12, | |
3acb8889 | 405 | .data_type = MIPI_CSI2_DATA_TYPE_RAW12, |
a0ec36a3 | 406 | .width = 12, |
d9a7dd2f LP |
407 | }, { |
408 | .code = MEDIA_BUS_FMT_SGRBG12_1X12, | |
3acb8889 | 409 | .data_type = MIPI_CSI2_DATA_TYPE_RAW12, |
a0ec36a3 | 410 | .width = 12, |
d9a7dd2f LP |
411 | }, { |
412 | .code = MEDIA_BUS_FMT_SRGGB12_1X12, | |
3acb8889 | 413 | .data_type = MIPI_CSI2_DATA_TYPE_RAW12, |
a0ec36a3 | 414 | .width = 12, |
e1a7461b LP |
415 | }, { |
416 | .code = MEDIA_BUS_FMT_Y12_1X12, | |
3acb8889 | 417 | .data_type = MIPI_CSI2_DATA_TYPE_RAW12, |
a0ec36a3 | 418 | .width = 12, |
d9a7dd2f LP |
419 | }, { |
420 | .code = MEDIA_BUS_FMT_SBGGR14_1X14, | |
3acb8889 | 421 | .data_type = MIPI_CSI2_DATA_TYPE_RAW14, |
a0ec36a3 | 422 | .width = 14, |
d9a7dd2f LP |
423 | }, { |
424 | .code = MEDIA_BUS_FMT_SGBRG14_1X14, | |
3acb8889 | 425 | .data_type = MIPI_CSI2_DATA_TYPE_RAW14, |
a0ec36a3 | 426 | .width = 14, |
d9a7dd2f LP |
427 | }, { |
428 | .code = MEDIA_BUS_FMT_SGRBG14_1X14, | |
3acb8889 | 429 | .data_type = MIPI_CSI2_DATA_TYPE_RAW14, |
a0ec36a3 | 430 | .width = 14, |
d9a7dd2f LP |
431 | }, { |
432 | .code = MEDIA_BUS_FMT_SRGGB14_1X14, | |
3acb8889 | 433 | .data_type = MIPI_CSI2_DATA_TYPE_RAW14, |
a0ec36a3 | 434 | .width = 14, |
7807063b RMS |
435 | } |
436 | }; | |
437 | ||
b329650e | 438 | static const struct csis_pix_format *find_csis_format(u32 code) |
7807063b | 439 | { |
eed6a930 | 440 | unsigned int i; |
7807063b | 441 | |
b329650e LP |
442 | for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) |
443 | if (code == mipi_csis_formats[i].code) | |
444 | return &mipi_csis_formats[i]; | |
445 | return NULL; | |
7807063b RMS |
446 | } |
447 | ||
b329650e LP |
448 | /* ----------------------------------------------------------------------------- |
449 | * Hardware configuration | |
450 | */ | |
6e996653 | 451 | |
b329650e | 452 | static inline u32 mipi_csis_read(struct csi_state *state, u32 reg) |
7807063b | 453 | { |
b329650e | 454 | return readl(state->regs + reg); |
7807063b RMS |
455 | } |
456 | ||
b329650e | 457 | static inline void mipi_csis_write(struct csi_state *state, u32 reg, u32 val) |
7807063b | 458 | { |
b329650e | 459 | writel(val, state->regs + reg); |
7807063b RMS |
460 | } |
461 | ||
462 | static void mipi_csis_enable_interrupts(struct csi_state *state, bool on) | |
463 | { | |
7b437a24 | 464 | mipi_csis_write(state, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); |
7fe1de81 | 465 | mipi_csis_write(state, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); |
7807063b RMS |
466 | } |
467 | ||
468 | static void mipi_csis_sw_reset(struct csi_state *state) | |
469 | { | |
470 | u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); | |
471 | ||
472 | mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, | |
473 | val | MIPI_CSIS_CMN_CTRL_RESET); | |
474 | usleep_range(10, 20); | |
475 | } | |
476 | ||
7807063b RMS |
477 | static void mipi_csis_system_enable(struct csi_state *state, int on) |
478 | { | |
479 | u32 val, mask; | |
480 | ||
481 | val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); | |
482 | if (on) | |
483 | val |= MIPI_CSIS_CMN_CTRL_ENABLE; | |
484 | else | |
485 | val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; | |
486 | mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); | |
487 | ||
7b437a24 LP |
488 | val = mipi_csis_read(state, MIPI_CSIS_DPHY_CMN_CTRL); |
489 | val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; | |
7807063b RMS |
490 | if (on) { |
491 | mask = (1 << (state->bus.num_data_lanes + 1)) - 1; | |
7b437a24 | 492 | val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); |
7807063b | 493 | } |
7b437a24 | 494 | mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, val); |
7807063b RMS |
495 | } |
496 | ||
497 | /* Called with the state.lock mutex held */ | |
498 | static void __mipi_csis_set_format(struct csi_state *state) | |
499 | { | |
500 | struct v4l2_mbus_framefmt *mf = &state->format_mbus; | |
501 | u32 val; | |
502 | ||
503 | /* Color format */ | |
7b437a24 | 504 | val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0)); |
eeea9ac2 | 505 | val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK); |
3acb8889 | 506 | val |= MIPI_CSIS_ISPCFG_FMT(state->csis_fmt->data_type); |
7b437a24 | 507 | mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val); |
7807063b RMS |
508 | |
509 | /* Pixel resolution */ | |
510 | val = mf->width | (mf->height << 16); | |
7b437a24 | 511 | mipi_csis_write(state, MIPI_CSIS_ISP_RESOL_CH(0), val); |
7807063b RMS |
512 | } |
513 | ||
74f81584 LP |
514 | static int mipi_csis_calculate_params(struct csi_state *state) |
515 | { | |
516 | s64 link_freq; | |
517 | u32 lane_rate; | |
518 | ||
519 | /* Calculate the line rate from the pixel rate. */ | |
520 | link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler, | |
521 | state->csis_fmt->width, | |
522 | state->bus.num_data_lanes * 2); | |
523 | if (link_freq < 0) { | |
524 | dev_err(state->dev, "Unable to obtain link frequency: %d\n", | |
525 | (int)link_freq); | |
526 | return link_freq; | |
527 | } | |
528 | ||
529 | lane_rate = link_freq * 2; | |
530 | ||
531 | if (lane_rate < 80000000 || lane_rate > 1500000000) { | |
532 | dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate); | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
536 | /* | |
537 | * The HSSETTLE counter value is document in a table, but can also | |
996f6f51 LP |
538 | * easily be calculated. Hardcode the CLKSETTLE value to 0 for now |
539 | * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until | |
540 | * we figure out how to compute it correctly. | |
74f81584 LP |
541 | */ |
542 | state->hs_settle = (lane_rate - 5000000) / 45000000; | |
996f6f51 LP |
543 | state->clk_settle = 0; |
544 | ||
545 | dev_dbg(state->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", | |
546 | lane_rate, state->clk_settle, state->hs_settle); | |
74f81584 | 547 | |
385031b6 LP |
548 | if (state->debug.hs_settle < 0xff) { |
549 | dev_dbg(state->dev, "overriding Ths_settle with %u\n", | |
550 | state->debug.hs_settle); | |
551 | state->hs_settle = state->debug.hs_settle; | |
552 | } | |
553 | ||
554 | if (state->debug.clk_settle < 4) { | |
555 | dev_dbg(state->dev, "overriding Tclk_settle with %u\n", | |
556 | state->debug.clk_settle); | |
557 | state->clk_settle = state->debug.clk_settle; | |
558 | } | |
559 | ||
74f81584 LP |
560 | return 0; |
561 | } | |
562 | ||
7807063b RMS |
563 | static void mipi_csis_set_params(struct csi_state *state) |
564 | { | |
565 | int lanes = state->bus.num_data_lanes; | |
566 | u32 val; | |
567 | ||
568 | val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); | |
569 | val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; | |
570 | val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; | |
f0e7cfbb LP |
571 | if (state->info->version == MIPI_CSIS_V3_3) |
572 | val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; | |
7807063b RMS |
573 | mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); |
574 | ||
575 | __mipi_csis_set_format(state); | |
576 | ||
7b437a24 | 577 | mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, |
996f6f51 LP |
578 | MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle) | |
579 | MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(state->clk_settle)); | |
7807063b | 580 | |
7b437a24 LP |
581 | val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) |
582 | | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) | |
583 | | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); | |
584 | mipi_csis_write(state, MIPI_CSIS_ISP_SYNC_CH(0), val); | |
7807063b RMS |
585 | |
586 | val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL); | |
6e1de006 | 587 | val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; |
7807063b RMS |
588 | val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); |
589 | val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; | |
590 | mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val); | |
591 | ||
e3851164 LP |
592 | mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_L, |
593 | MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | | |
594 | MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | | |
595 | MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | | |
596 | MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | | |
597 | MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | | |
598 | MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | | |
599 | MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); | |
600 | mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_H, 0); | |
7807063b RMS |
601 | |
602 | /* Update the shadow register. */ | |
603 | val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); | |
604 | mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, | |
605 | val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | | |
606 | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); | |
607 | } | |
608 | ||
2b393f91 | 609 | static int mipi_csis_clk_enable(struct csi_state *state) |
7807063b | 610 | { |
f0e7cfbb | 611 | return clk_bulk_prepare_enable(state->info->num_clocks, state->clks); |
7807063b RMS |
612 | } |
613 | ||
614 | static void mipi_csis_clk_disable(struct csi_state *state) | |
615 | { | |
f0e7cfbb | 616 | clk_bulk_disable_unprepare(state->info->num_clocks, state->clks); |
7807063b RMS |
617 | } |
618 | ||
619 | static int mipi_csis_clk_get(struct csi_state *state) | |
620 | { | |
7807063b RMS |
621 | unsigned int i; |
622 | int ret; | |
623 | ||
f0e7cfbb | 624 | state->clks = devm_kcalloc(state->dev, state->info->num_clocks, |
62bd05a4 | 625 | sizeof(*state->clks), GFP_KERNEL); |
7807063b RMS |
626 | |
627 | if (!state->clks) | |
628 | return -ENOMEM; | |
629 | ||
f0e7cfbb | 630 | for (i = 0; i < state->info->num_clocks; i++) |
7807063b RMS |
631 | state->clks[i].id = mipi_csis_clk_id[i]; |
632 | ||
f0e7cfbb LP |
633 | ret = devm_clk_bulk_get(state->dev, state->info->num_clocks, |
634 | state->clks); | |
7807063b RMS |
635 | if (ret < 0) |
636 | return ret; | |
637 | ||
7807063b | 638 | /* Set clock rate */ |
6e1de006 LP |
639 | ret = clk_set_rate(state->clks[MIPI_CSIS_CLK_WRAP].clk, |
640 | state->clk_frequency); | |
7807063b | 641 | if (ret < 0) |
62bd05a4 LP |
642 | dev_err(state->dev, "set rate=%d failed: %d\n", |
643 | state->clk_frequency, ret); | |
7807063b RMS |
644 | |
645 | return ret; | |
646 | } | |
647 | ||
648 | static void mipi_csis_start_stream(struct csi_state *state) | |
649 | { | |
650 | mipi_csis_sw_reset(state); | |
651 | mipi_csis_set_params(state); | |
652 | mipi_csis_system_enable(state, true); | |
653 | mipi_csis_enable_interrupts(state, true); | |
654 | } | |
655 | ||
656 | static void mipi_csis_stop_stream(struct csi_state *state) | |
657 | { | |
658 | mipi_csis_enable_interrupts(state, false); | |
659 | mipi_csis_system_enable(state, false); | |
660 | } | |
661 | ||
b329650e LP |
662 | static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) |
663 | { | |
664 | struct csi_state *state = dev_id; | |
665 | unsigned long flags; | |
666 | unsigned int i; | |
667 | u32 status; | |
668 | u32 dbg_status; | |
669 | ||
670 | status = mipi_csis_read(state, MIPI_CSIS_INT_SRC); | |
671 | dbg_status = mipi_csis_read(state, MIPI_CSIS_DBG_INTR_SRC); | |
672 | ||
673 | spin_lock_irqsave(&state->slock, flags); | |
674 | ||
675 | /* Update the event/error counters */ | |
385031b6 | 676 | if ((status & MIPI_CSIS_INT_SRC_ERRORS) || state->debug.enable) { |
b329650e LP |
677 | for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { |
678 | struct mipi_csis_event *event = &state->events[i]; | |
679 | ||
680 | if ((!event->debug && (status & event->mask)) || | |
681 | (event->debug && (dbg_status & event->mask))) | |
682 | event->counter++; | |
683 | } | |
684 | } | |
685 | spin_unlock_irqrestore(&state->slock, flags); | |
686 | ||
687 | mipi_csis_write(state, MIPI_CSIS_INT_SRC, status); | |
688 | mipi_csis_write(state, MIPI_CSIS_DBG_INTR_SRC, dbg_status); | |
689 | ||
690 | return IRQ_HANDLED; | |
691 | } | |
692 | ||
acdff8e1 LP |
693 | /* ----------------------------------------------------------------------------- |
694 | * PHY regulator and reset | |
695 | */ | |
696 | ||
697 | static int mipi_csis_phy_enable(struct csi_state *state) | |
698 | { | |
f0e7cfbb LP |
699 | if (state->info->version != MIPI_CSIS_V3_3) |
700 | return 0; | |
701 | ||
acdff8e1 LP |
702 | return regulator_enable(state->mipi_phy_regulator); |
703 | } | |
704 | ||
705 | static int mipi_csis_phy_disable(struct csi_state *state) | |
706 | { | |
f0e7cfbb LP |
707 | if (state->info->version != MIPI_CSIS_V3_3) |
708 | return 0; | |
709 | ||
acdff8e1 LP |
710 | return regulator_disable(state->mipi_phy_regulator); |
711 | } | |
712 | ||
713 | static void mipi_csis_phy_reset(struct csi_state *state) | |
714 | { | |
f0e7cfbb LP |
715 | if (state->info->version != MIPI_CSIS_V3_3) |
716 | return; | |
717 | ||
acdff8e1 LP |
718 | reset_control_assert(state->mrst); |
719 | msleep(20); | |
720 | reset_control_deassert(state->mrst); | |
721 | } | |
722 | ||
723 | static int mipi_csis_phy_init(struct csi_state *state) | |
724 | { | |
f0e7cfbb LP |
725 | if (state->info->version != MIPI_CSIS_V3_3) |
726 | return 0; | |
727 | ||
acdff8e1 LP |
728 | /* Get MIPI PHY reset and regulator. */ |
729 | state->mrst = devm_reset_control_get_exclusive(state->dev, NULL); | |
730 | if (IS_ERR(state->mrst)) | |
731 | return PTR_ERR(state->mrst); | |
732 | ||
733 | state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy"); | |
734 | if (IS_ERR(state->mipi_phy_regulator)) | |
735 | return PTR_ERR(state->mipi_phy_regulator); | |
736 | ||
737 | return regulator_set_voltage(state->mipi_phy_regulator, 1000000, | |
738 | 1000000); | |
739 | } | |
740 | ||
b329650e LP |
741 | /* ----------------------------------------------------------------------------- |
742 | * Debug | |
743 | */ | |
744 | ||
7807063b RMS |
745 | static void mipi_csis_clear_counters(struct csi_state *state) |
746 | { | |
747 | unsigned long flags; | |
748 | unsigned int i; | |
749 | ||
750 | spin_lock_irqsave(&state->slock, flags); | |
751 | for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) | |
752 | state->events[i].counter = 0; | |
753 | spin_unlock_irqrestore(&state->slock, flags); | |
754 | } | |
755 | ||
756 | static void mipi_csis_log_counters(struct csi_state *state, bool non_errors) | |
757 | { | |
d2fcc9c2 | 758 | unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS |
7fe1de81 | 759 | : MIPI_CSIS_NUM_EVENTS - 8; |
7807063b | 760 | unsigned long flags; |
d2fcc9c2 | 761 | unsigned int i; |
7807063b RMS |
762 | |
763 | spin_lock_irqsave(&state->slock, flags); | |
764 | ||
d2fcc9c2 | 765 | for (i = 0; i < num_events; ++i) { |
385031b6 | 766 | if (state->events[i].counter > 0 || state->debug.enable) |
62bd05a4 LP |
767 | dev_info(state->dev, "%s events: %d\n", |
768 | state->events[i].name, | |
7807063b RMS |
769 | state->events[i].counter); |
770 | } | |
771 | spin_unlock_irqrestore(&state->slock, flags); | |
772 | } | |
773 | ||
b329650e LP |
774 | static int mipi_csis_dump_regs(struct csi_state *state) |
775 | { | |
776 | static const struct { | |
777 | u32 offset; | |
778 | const char * const name; | |
779 | } registers[] = { | |
780 | { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" }, | |
781 | { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" }, | |
782 | { MIPI_CSIS_INT_MSK, "INT_MSK" }, | |
783 | { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" }, | |
784 | { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" }, | |
785 | { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, | |
786 | { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, | |
787 | { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, | |
788 | { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, | |
789 | { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, | |
790 | { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, | |
791 | { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, | |
95a13790 | 792 | { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, |
b329650e LP |
793 | }; |
794 | ||
b329650e LP |
795 | unsigned int i; |
796 | u32 cfg; | |
797 | ||
62bd05a4 | 798 | dev_info(state->dev, "--- REGISTERS ---\n"); |
b329650e LP |
799 | |
800 | for (i = 0; i < ARRAY_SIZE(registers); i++) { | |
801 | cfg = mipi_csis_read(state, registers[i].offset); | |
62bd05a4 | 802 | dev_info(state->dev, "%14s: 0x%08x\n", registers[i].name, cfg); |
b329650e LP |
803 | } |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
808 | static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) | |
809 | { | |
810 | struct csi_state *state = m->private; | |
811 | ||
812 | return mipi_csis_dump_regs(state); | |
813 | } | |
814 | DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); | |
815 | ||
816 | static void mipi_csis_debugfs_init(struct csi_state *state) | |
817 | { | |
385031b6 LP |
818 | state->debug.hs_settle = UINT_MAX; |
819 | state->debug.clk_settle = UINT_MAX; | |
820 | ||
b329650e LP |
821 | state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL); |
822 | ||
823 | debugfs_create_bool("debug_enable", 0600, state->debugfs_root, | |
385031b6 | 824 | &state->debug.enable); |
b329650e LP |
825 | debugfs_create_file("dump_regs", 0600, state->debugfs_root, state, |
826 | &mipi_csis_dump_regs_fops); | |
385031b6 LP |
827 | debugfs_create_u32("tclk_settle", 0600, state->debugfs_root, |
828 | &state->debug.clk_settle); | |
829 | debugfs_create_u32("ths_settle", 0600, state->debugfs_root, | |
830 | &state->debug.hs_settle); | |
b329650e LP |
831 | } |
832 | ||
833 | static void mipi_csis_debugfs_exit(struct csi_state *state) | |
834 | { | |
835 | debugfs_remove_recursive(state->debugfs_root); | |
836 | } | |
837 | ||
838 | /* ----------------------------------------------------------------------------- | |
7807063b RMS |
839 | * V4L2 subdev operations |
840 | */ | |
b329650e LP |
841 | |
842 | static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev) | |
843 | { | |
b0db06bb | 844 | return container_of(sdev, struct csi_state, sd); |
b329650e LP |
845 | } |
846 | ||
b0db06bb | 847 | static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) |
7807063b | 848 | { |
b0db06bb | 849 | struct csi_state *state = mipi_sd_to_csis_state(sd); |
74f81584 | 850 | int ret; |
7807063b RMS |
851 | |
852 | if (enable) { | |
74f81584 LP |
853 | ret = mipi_csis_calculate_params(state); |
854 | if (ret < 0) | |
855 | return ret; | |
856 | ||
7807063b | 857 | mipi_csis_clear_counters(state); |
8f5586dc | 858 | |
62bd05a4 | 859 | ret = pm_runtime_resume_and_get(state->dev); |
75ecb9c8 | 860 | if (ret < 0) |
7807063b | 861 | return ret; |
75ecb9c8 | 862 | |
7807063b | 863 | ret = v4l2_subdev_call(state->src_sd, core, s_power, 1); |
421ba86a | 864 | if (ret < 0 && ret != -ENOIOCTLCMD) |
8f5586dc | 865 | goto done; |
7807063b RMS |
866 | } |
867 | ||
868 | mutex_lock(&state->lock); | |
8f5586dc | 869 | |
7807063b | 870 | if (enable) { |
f65ffcd8 | 871 | if (state->state & ST_SUSPENDED) { |
7807063b RMS |
872 | ret = -EBUSY; |
873 | goto unlock; | |
874 | } | |
875 | ||
876 | mipi_csis_start_stream(state); | |
877 | ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1); | |
878 | if (ret < 0) | |
879 | goto unlock; | |
880 | ||
881 | mipi_csis_log_counters(state, true); | |
882 | ||
f65ffcd8 | 883 | state->state |= ST_STREAMING; |
7807063b RMS |
884 | } else { |
885 | v4l2_subdev_call(state->src_sd, video, s_stream, 0); | |
770cbf89 | 886 | ret = v4l2_subdev_call(state->src_sd, core, s_power, 0); |
421ba86a LP |
887 | if (ret == -ENOIOCTLCMD) |
888 | ret = 0; | |
7807063b | 889 | mipi_csis_stop_stream(state); |
f65ffcd8 | 890 | state->state &= ~ST_STREAMING; |
385031b6 | 891 | if (state->debug.enable) |
7807063b RMS |
892 | mipi_csis_log_counters(state, true); |
893 | } | |
894 | ||
895 | unlock: | |
896 | mutex_unlock(&state->lock); | |
8f5586dc LP |
897 | |
898 | done: | |
899 | if (!enable || ret < 0) | |
62bd05a4 | 900 | pm_runtime_put(state->dev); |
7807063b RMS |
901 | |
902 | return ret; | |
903 | } | |
904 | ||
7807063b RMS |
905 | static struct v4l2_mbus_framefmt * |
906 | mipi_csis_get_format(struct csi_state *state, | |
0d346d2a | 907 | struct v4l2_subdev_state *sd_state, |
7807063b RMS |
908 | enum v4l2_subdev_format_whence which, |
909 | unsigned int pad) | |
910 | { | |
911 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
0d346d2a | 912 | return v4l2_subdev_get_try_format(&state->sd, sd_state, pad); |
7807063b RMS |
913 | |
914 | return &state->format_mbus; | |
915 | } | |
916 | ||
b0db06bb | 917 | static int mipi_csis_init_cfg(struct v4l2_subdev *sd, |
0d346d2a | 918 | struct v4l2_subdev_state *sd_state) |
45cde0aa | 919 | { |
b0db06bb | 920 | struct csi_state *state = mipi_sd_to_csis_state(sd); |
45cde0aa LP |
921 | struct v4l2_mbus_framefmt *fmt_sink; |
922 | struct v4l2_mbus_framefmt *fmt_source; | |
923 | enum v4l2_subdev_format_whence which; | |
45cde0aa | 924 | |
0d346d2a TV |
925 | which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; |
926 | fmt_sink = mipi_csis_get_format(state, sd_state, which, CSIS_PAD_SINK); | |
f89ab84a | 927 | |
aeceec5e | 928 | fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16; |
f89ab84a LP |
929 | fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH; |
930 | fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT; | |
931 | fmt_sink->field = V4L2_FIELD_NONE; | |
932 | ||
933 | fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M; | |
934 | fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace); | |
935 | fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace); | |
936 | fmt_sink->quantization = | |
937 | V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace, | |
938 | fmt_sink->ycbcr_enc); | |
45cde0aa LP |
939 | |
940 | /* | |
941 | * When called from mipi_csis_subdev_init() to initialize the active | |
942 | * configuration, cfg is NULL, which indicates there's no source pad | |
943 | * configuration to set. | |
944 | */ | |
0d346d2a | 945 | if (!sd_state) |
45cde0aa LP |
946 | return 0; |
947 | ||
0d346d2a TV |
948 | fmt_source = mipi_csis_get_format(state, sd_state, which, |
949 | CSIS_PAD_SOURCE); | |
45cde0aa LP |
950 | *fmt_source = *fmt_sink; |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
b0db06bb | 955 | static int mipi_csis_get_fmt(struct v4l2_subdev *sd, |
0d346d2a | 956 | struct v4l2_subdev_state *sd_state, |
7807063b RMS |
957 | struct v4l2_subdev_format *sdformat) |
958 | { | |
b0db06bb | 959 | struct csi_state *state = mipi_sd_to_csis_state(sd); |
7807063b RMS |
960 | struct v4l2_mbus_framefmt *fmt; |
961 | ||
0d346d2a TV |
962 | fmt = mipi_csis_get_format(state, sd_state, sdformat->which, |
963 | sdformat->pad); | |
2cb7c5c0 LP |
964 | |
965 | mutex_lock(&state->lock); | |
7807063b | 966 | sdformat->format = *fmt; |
7807063b RMS |
967 | mutex_unlock(&state->lock); |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
b0db06bb | 972 | static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, |
0d346d2a | 973 | struct v4l2_subdev_state *sd_state, |
4b7126a7 LP |
974 | struct v4l2_subdev_mbus_code_enum *code) |
975 | { | |
b0db06bb | 976 | struct csi_state *state = mipi_sd_to_csis_state(sd); |
4b7126a7 LP |
977 | |
978 | /* | |
979 | * The CSIS can't transcode in any way, the source format is identical | |
980 | * to the sink format. | |
981 | */ | |
982 | if (code->pad == CSIS_PAD_SOURCE) { | |
983 | struct v4l2_mbus_framefmt *fmt; | |
984 | ||
985 | if (code->index > 0) | |
986 | return -EINVAL; | |
987 | ||
0d346d2a TV |
988 | fmt = mipi_csis_get_format(state, sd_state, code->which, |
989 | code->pad); | |
4b7126a7 LP |
990 | code->code = fmt->code; |
991 | return 0; | |
992 | } | |
993 | ||
994 | if (code->pad != CSIS_PAD_SINK) | |
995 | return -EINVAL; | |
996 | ||
997 | if (code->index >= ARRAY_SIZE(mipi_csis_formats)) | |
998 | return -EINVAL; | |
999 | ||
1000 | code->code = mipi_csis_formats[code->index].code; | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
b0db06bb | 1005 | static int mipi_csis_set_fmt(struct v4l2_subdev *sd, |
0d346d2a | 1006 | struct v4l2_subdev_state *sd_state, |
7807063b RMS |
1007 | struct v4l2_subdev_format *sdformat) |
1008 | { | |
b0db06bb | 1009 | struct csi_state *state = mipi_sd_to_csis_state(sd); |
d321dd23 | 1010 | struct csis_pix_format const *csis_fmt; |
7807063b | 1011 | struct v4l2_mbus_framefmt *fmt; |
b06bde9a | 1012 | unsigned int align; |
7807063b | 1013 | |
d321dd23 LP |
1014 | /* |
1015 | * The CSIS can't transcode in any way, the source format can't be | |
1016 | * modified. | |
1017 | */ | |
1018 | if (sdformat->pad == CSIS_PAD_SOURCE) | |
0d346d2a | 1019 | return mipi_csis_get_fmt(sd, sd_state, sdformat); |
d321dd23 LP |
1020 | |
1021 | if (sdformat->pad != CSIS_PAD_SINK) | |
1022 | return -EINVAL; | |
7807063b | 1023 | |
b06bde9a | 1024 | /* |
2cb7c5c0 LP |
1025 | * Validate the media bus code and clamp and align the size. |
1026 | * | |
b06bde9a LP |
1027 | * The total number of bits per line must be a multiple of 8. We thus |
1028 | * need to align the width for formats that are not multiples of 8 | |
1029 | * bits. | |
1030 | */ | |
2cb7c5c0 LP |
1031 | csis_fmt = find_csis_format(sdformat->format.code); |
1032 | if (!csis_fmt) | |
1033 | csis_fmt = &mipi_csis_formats[0]; | |
1034 | ||
b06bde9a LP |
1035 | switch (csis_fmt->width % 8) { |
1036 | case 0: | |
dd419105 | 1037 | align = 0; |
b06bde9a LP |
1038 | break; |
1039 | case 4: | |
dd419105 | 1040 | align = 1; |
b06bde9a LP |
1041 | break; |
1042 | case 2: | |
1043 | case 6: | |
dd419105 | 1044 | align = 2; |
b06bde9a | 1045 | break; |
43c3f12d TR |
1046 | default: |
1047 | /* 1, 3, 5, 7 */ | |
dd419105 | 1048 | align = 3; |
b06bde9a LP |
1049 | break; |
1050 | } | |
1051 | ||
2cb7c5c0 LP |
1052 | v4l_bound_align_image(&sdformat->format.width, 1, |
1053 | CSIS_MAX_PIX_WIDTH, align, | |
1054 | &sdformat->format.height, 1, | |
1055 | CSIS_MAX_PIX_HEIGHT, 0, 0); | |
1056 | ||
0d346d2a TV |
1057 | fmt = mipi_csis_get_format(state, sd_state, sdformat->which, |
1058 | sdformat->pad); | |
2cb7c5c0 LP |
1059 | |
1060 | mutex_lock(&state->lock); | |
1061 | ||
1062 | fmt->code = csis_fmt->code; | |
1063 | fmt->width = sdformat->format.width; | |
1064 | fmt->height = sdformat->format.height; | |
d321dd23 | 1065 | |
7807063b RMS |
1066 | sdformat->format = *fmt; |
1067 | ||
d321dd23 | 1068 | /* Propagate the format from sink to source. */ |
0d346d2a | 1069 | fmt = mipi_csis_get_format(state, sd_state, sdformat->which, |
d321dd23 LP |
1070 | CSIS_PAD_SOURCE); |
1071 | *fmt = sdformat->format; | |
1072 | ||
1073 | /* Store the CSIS format descriptor for active formats. */ | |
1074 | if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) | |
1075 | state->csis_fmt = csis_fmt; | |
1076 | ||
7807063b RMS |
1077 | mutex_unlock(&state->lock); |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
b0db06bb | 1082 | static int mipi_csis_log_status(struct v4l2_subdev *sd) |
7807063b | 1083 | { |
b0db06bb | 1084 | struct csi_state *state = mipi_sd_to_csis_state(sd); |
7807063b RMS |
1085 | |
1086 | mutex_lock(&state->lock); | |
1087 | mipi_csis_log_counters(state, true); | |
385031b6 | 1088 | if (state->debug.enable && (state->state & ST_POWERED)) |
7807063b RMS |
1089 | mipi_csis_dump_regs(state); |
1090 | mutex_unlock(&state->lock); | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
7807063b RMS |
1095 | static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { |
1096 | .log_status = mipi_csis_log_status, | |
1097 | }; | |
1098 | ||
7807063b RMS |
1099 | static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { |
1100 | .s_stream = mipi_csis_s_stream, | |
1101 | }; | |
1102 | ||
1103 | static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { | |
1104 | .init_cfg = mipi_csis_init_cfg, | |
4b7126a7 | 1105 | .enum_mbus_code = mipi_csis_enum_mbus_code, |
7807063b RMS |
1106 | .get_fmt = mipi_csis_get_fmt, |
1107 | .set_fmt = mipi_csis_set_fmt, | |
1108 | }; | |
1109 | ||
1110 | static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { | |
1111 | .core = &mipi_csis_core_ops, | |
1112 | .video = &mipi_csis_video_ops, | |
1113 | .pad = &mipi_csis_pad_ops, | |
1114 | }; | |
1115 | ||
b329650e LP |
1116 | /* ----------------------------------------------------------------------------- |
1117 | * Media entity operations | |
1118 | */ | |
7807063b | 1119 | |
b329650e LP |
1120 | static int mipi_csis_link_setup(struct media_entity *entity, |
1121 | const struct media_pad *local_pad, | |
1122 | const struct media_pad *remote_pad, u32 flags) | |
1123 | { | |
b0db06bb LP |
1124 | struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); |
1125 | struct csi_state *state = mipi_sd_to_csis_state(sd); | |
b329650e | 1126 | struct v4l2_subdev *remote_sd; |
7807063b | 1127 | |
b329650e LP |
1128 | dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name, |
1129 | local_pad->entity->name); | |
7807063b | 1130 | |
b329650e LP |
1131 | /* We only care about the link to the source. */ |
1132 | if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) | |
1133 | return 0; | |
7807063b | 1134 | |
b329650e | 1135 | remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); |
7807063b | 1136 | |
b329650e LP |
1137 | if (flags & MEDIA_LNK_FL_ENABLED) { |
1138 | if (state->src_sd) | |
1139 | return -EBUSY; | |
1140 | ||
1141 | state->src_sd = remote_sd; | |
1142 | } else { | |
1143 | state->src_sd = NULL; | |
1144 | } | |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | static const struct media_entity_operations mipi_csis_entity_ops = { | |
1150 | .link_setup = mipi_csis_link_setup, | |
1151 | .link_validate = v4l2_subdev_link_validate, | |
1152 | .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, | |
1153 | }; | |
1154 | ||
1155 | /* ----------------------------------------------------------------------------- | |
1156 | * Async subdev notifier | |
1157 | */ | |
1158 | ||
1159 | static struct csi_state * | |
1160 | mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) | |
1161 | { | |
1162 | return container_of(n, struct csi_state, notifier); | |
1163 | } | |
1164 | ||
1165 | static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, | |
6e996653 SL |
1166 | struct v4l2_subdev *sd, |
1167 | struct v4l2_async_subdev *asd) | |
1168 | { | |
1169 | struct csi_state *state = mipi_notifier_to_csis_state(notifier); | |
b0db06bb | 1170 | struct media_pad *sink = &state->sd.entity.pads[CSIS_PAD_SINK]; |
6e996653 | 1171 | |
dbedd2f4 | 1172 | return v4l2_create_fwnode_links_to_pad(sd, sink, 0); |
6e996653 SL |
1173 | } |
1174 | ||
1175 | static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { | |
1176 | .bound = mipi_csis_notify_bound, | |
1177 | }; | |
1178 | ||
0e63a5e4 SL |
1179 | static int mipi_csis_async_register(struct csi_state *state) |
1180 | { | |
1181 | struct v4l2_fwnode_endpoint vep = { | |
1182 | .bus_type = V4L2_MBUS_CSI2_DPHY, | |
1183 | }; | |
c1cf3d89 | 1184 | struct v4l2_async_subdev *asd; |
0e63a5e4 | 1185 | struct fwnode_handle *ep; |
88fc8138 | 1186 | unsigned int i; |
0e63a5e4 SL |
1187 | int ret; |
1188 | ||
3c8c1539 | 1189 | v4l2_async_nf_init(&state->notifier); |
0e63a5e4 SL |
1190 | |
1191 | ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0, | |
1192 | FWNODE_GRAPH_ENDPOINT_NEXT); | |
1193 | if (!ep) | |
1194 | return -ENOTCONN; | |
1195 | ||
1196 | ret = v4l2_fwnode_endpoint_parse(ep, &vep); | |
1197 | if (ret) | |
1198 | goto err_parse; | |
1199 | ||
88fc8138 LP |
1200 | for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { |
1201 | if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { | |
1202 | dev_err(state->dev, | |
1203 | "data lanes reordering is not supported"); | |
80daed70 | 1204 | ret = -EINVAL; |
88fc8138 LP |
1205 | goto err_parse; |
1206 | } | |
1207 | } | |
1208 | ||
0e63a5e4 SL |
1209 | state->bus = vep.bus.mipi_csi2; |
1210 | ||
1211 | dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes); | |
1212 | dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags); | |
1213 | ||
3c8c1539 SA |
1214 | asd = v4l2_async_nf_add_fwnode_remote(&state->notifier, ep, |
1215 | struct v4l2_async_subdev); | |
c1cf3d89 EG |
1216 | if (IS_ERR(asd)) { |
1217 | ret = PTR_ERR(asd); | |
0e63a5e4 SL |
1218 | goto err_parse; |
1219 | } | |
1220 | ||
0e63a5e4 SL |
1221 | fwnode_handle_put(ep); |
1222 | ||
6e996653 SL |
1223 | state->notifier.ops = &mipi_csis_notify_ops; |
1224 | ||
3c8c1539 | 1225 | ret = v4l2_async_subdev_nf_register(&state->sd, &state->notifier); |
2a4558c6 SL |
1226 | if (ret) |
1227 | return ret; | |
1228 | ||
b0db06bb | 1229 | return v4l2_async_register_subdev(&state->sd); |
0e63a5e4 SL |
1230 | |
1231 | err_parse: | |
1232 | fwnode_handle_put(ep); | |
7807063b RMS |
1233 | |
1234 | return ret; | |
1235 | } | |
1236 | ||
b329650e LP |
1237 | /* ----------------------------------------------------------------------------- |
1238 | * Suspend/resume | |
1239 | */ | |
1240 | ||
1241 | static int mipi_csis_pm_suspend(struct device *dev, bool runtime) | |
7807063b | 1242 | { |
b0db06bb LP |
1243 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
1244 | struct csi_state *state = mipi_sd_to_csis_state(sd); | |
b329650e | 1245 | int ret = 0; |
7807063b | 1246 | |
b329650e | 1247 | mutex_lock(&state->lock); |
f65ffcd8 | 1248 | if (state->state & ST_POWERED) { |
b329650e | 1249 | mipi_csis_stop_stream(state); |
acdff8e1 | 1250 | ret = mipi_csis_phy_disable(state); |
b329650e LP |
1251 | if (ret) |
1252 | goto unlock; | |
1253 | mipi_csis_clk_disable(state); | |
f65ffcd8 | 1254 | state->state &= ~ST_POWERED; |
b329650e | 1255 | if (!runtime) |
f65ffcd8 | 1256 | state->state |= ST_SUSPENDED; |
b329650e LP |
1257 | } |
1258 | ||
1259 | unlock: | |
1260 | mutex_unlock(&state->lock); | |
1261 | ||
1262 | return ret ? -EAGAIN : 0; | |
7807063b | 1263 | } |
7807063b | 1264 | |
b329650e | 1265 | static int mipi_csis_pm_resume(struct device *dev, bool runtime) |
7807063b | 1266 | { |
b0db06bb LP |
1267 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
1268 | struct csi_state *state = mipi_sd_to_csis_state(sd); | |
b329650e | 1269 | int ret = 0; |
7807063b | 1270 | |
b329650e | 1271 | mutex_lock(&state->lock); |
f65ffcd8 | 1272 | if (!runtime && !(state->state & ST_SUSPENDED)) |
b329650e LP |
1273 | goto unlock; |
1274 | ||
f65ffcd8 | 1275 | if (!(state->state & ST_POWERED)) { |
acdff8e1 | 1276 | ret = mipi_csis_phy_enable(state); |
b329650e LP |
1277 | if (ret) |
1278 | goto unlock; | |
1279 | ||
f65ffcd8 | 1280 | state->state |= ST_POWERED; |
b329650e LP |
1281 | mipi_csis_clk_enable(state); |
1282 | } | |
f65ffcd8 | 1283 | if (state->state & ST_STREAMING) |
b329650e LP |
1284 | mipi_csis_start_stream(state); |
1285 | ||
f65ffcd8 | 1286 | state->state &= ~ST_SUSPENDED; |
b329650e LP |
1287 | |
1288 | unlock: | |
1289 | mutex_unlock(&state->lock); | |
1290 | ||
1291 | return ret ? -EAGAIN : 0; | |
7807063b RMS |
1292 | } |
1293 | ||
b329650e | 1294 | static int __maybe_unused mipi_csis_suspend(struct device *dev) |
7807063b | 1295 | { |
b329650e LP |
1296 | return mipi_csis_pm_suspend(dev, false); |
1297 | } | |
1298 | ||
1299 | static int __maybe_unused mipi_csis_resume(struct device *dev) | |
1300 | { | |
1301 | return mipi_csis_pm_resume(dev, false); | |
1302 | } | |
1303 | ||
1304 | static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev) | |
1305 | { | |
1306 | return mipi_csis_pm_suspend(dev, true); | |
1307 | } | |
1308 | ||
1309 | static int __maybe_unused mipi_csis_runtime_resume(struct device *dev) | |
1310 | { | |
1311 | return mipi_csis_pm_resume(dev, true); | |
1312 | } | |
1313 | ||
1314 | static const struct dev_pm_ops mipi_csis_pm_ops = { | |
1315 | SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, | |
1316 | NULL) | |
1317 | SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume) | |
1318 | }; | |
1319 | ||
1320 | /* ----------------------------------------------------------------------------- | |
1321 | * Probe/remove & platform driver | |
1322 | */ | |
1323 | ||
96703073 | 1324 | static int mipi_csis_subdev_init(struct csi_state *state) |
b329650e | 1325 | { |
96703073 | 1326 | struct v4l2_subdev *sd = &state->sd; |
b329650e | 1327 | |
96703073 | 1328 | v4l2_subdev_init(sd, &mipi_csis_subdev_ops); |
b0db06bb | 1329 | sd->owner = THIS_MODULE; |
5be7f8c9 LP |
1330 | snprintf(sd->name, sizeof(sd->name), "csis-%s", |
1331 | dev_name(state->dev)); | |
b329650e | 1332 | |
b0db06bb LP |
1333 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
1334 | sd->ctrl_handler = NULL; | |
b329650e | 1335 | |
b0db06bb LP |
1336 | sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; |
1337 | sd->entity.ops = &mipi_csis_entity_ops; | |
b329650e | 1338 | |
96703073 | 1339 | sd->dev = state->dev; |
b329650e LP |
1340 | |
1341 | state->csis_fmt = &mipi_csis_formats[0]; | |
b0db06bb | 1342 | mipi_csis_init_cfg(sd, NULL); |
b329650e LP |
1343 | |
1344 | state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK | |
1345 | | MEDIA_PAD_FL_MUST_CONNECT; | |
1346 | state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE | |
1347 | | MEDIA_PAD_FL_MUST_CONNECT; | |
b0db06bb | 1348 | return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, |
b329650e LP |
1349 | state->pads); |
1350 | } | |
1351 | ||
deb1c972 | 1352 | static int mipi_csis_parse_dt(struct csi_state *state) |
b329650e | 1353 | { |
deb1c972 | 1354 | struct device_node *node = state->dev->of_node; |
b329650e LP |
1355 | |
1356 | if (of_property_read_u32(node, "clock-frequency", | |
1357 | &state->clk_frequency)) | |
1358 | state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; | |
1359 | ||
b329650e | 1360 | return 0; |
7807063b RMS |
1361 | } |
1362 | ||
7807063b RMS |
1363 | static int mipi_csis_probe(struct platform_device *pdev) |
1364 | { | |
1365 | struct device *dev = &pdev->dev; | |
7807063b | 1366 | struct csi_state *state; |
e71bcbe6 | 1367 | int irq; |
7acc1f91 | 1368 | int ret; |
7807063b RMS |
1369 | |
1370 | state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); | |
1371 | if (!state) | |
1372 | return -ENOMEM; | |
1373 | ||
7479454c | 1374 | mutex_init(&state->lock); |
7807063b RMS |
1375 | spin_lock_init(&state->slock); |
1376 | ||
7807063b | 1377 | state->dev = dev; |
f0e7cfbb | 1378 | state->info = of_device_get_match_data(dev); |
7807063b | 1379 | |
7479454c LP |
1380 | memcpy(state->events, mipi_csis_events, sizeof(state->events)); |
1381 | ||
1382 | /* Parse DT properties. */ | |
deb1c972 | 1383 | ret = mipi_csis_parse_dt(state); |
7807063b RMS |
1384 | if (ret < 0) { |
1385 | dev_err(dev, "Failed to parse device tree: %d\n", ret); | |
1386 | return ret; | |
1387 | } | |
1388 | ||
7479454c | 1389 | /* Acquire resources. */ |
80a501a4 | 1390 | state->regs = devm_platform_ioremap_resource(pdev, 0); |
7807063b RMS |
1391 | if (IS_ERR(state->regs)) |
1392 | return PTR_ERR(state->regs); | |
1393 | ||
e71bcbe6 LP |
1394 | irq = platform_get_irq(pdev, 0); |
1395 | if (irq < 0) | |
1396 | return irq; | |
7807063b | 1397 | |
7479454c LP |
1398 | ret = mipi_csis_phy_init(state); |
1399 | if (ret < 0) | |
1400 | return ret; | |
1401 | ||
7807063b RMS |
1402 | ret = mipi_csis_clk_get(state); |
1403 | if (ret < 0) | |
1404 | return ret; | |
1405 | ||
7479454c LP |
1406 | /* Reset PHY and enable the clocks. */ |
1407 | mipi_csis_phy_reset(state); | |
1408 | ||
2b393f91 FE |
1409 | ret = mipi_csis_clk_enable(state); |
1410 | if (ret < 0) { | |
1411 | dev_err(state->dev, "failed to enable clocks: %d\n", ret); | |
1412 | return ret; | |
1413 | } | |
7807063b | 1414 | |
7479454c | 1415 | /* Now that the hardware is initialized, request the interrupt. */ |
e71bcbe6 LP |
1416 | ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, |
1417 | dev_name(dev), state); | |
7807063b RMS |
1418 | if (ret) { |
1419 | dev_err(dev, "Interrupt request failed\n"); | |
1420 | goto disable_clock; | |
1421 | } | |
1422 | ||
7479454c | 1423 | /* Initialize and register the subdev. */ |
96703073 | 1424 | ret = mipi_csis_subdev_init(state); |
7807063b RMS |
1425 | if (ret < 0) |
1426 | goto disable_clock; | |
1427 | ||
7479454c LP |
1428 | platform_set_drvdata(pdev, &state->sd); |
1429 | ||
0e63a5e4 SL |
1430 | ret = mipi_csis_async_register(state); |
1431 | if (ret < 0) { | |
62bd05a4 | 1432 | dev_err(dev, "async register failed: %d\n", ret); |
0e63a5e4 SL |
1433 | goto cleanup; |
1434 | } | |
1435 | ||
7479454c | 1436 | /* Initialize debugfs. */ |
7807063b | 1437 | mipi_csis_debugfs_init(state); |
7479454c LP |
1438 | |
1439 | /* Enable runtime PM. */ | |
7807063b RMS |
1440 | pm_runtime_enable(dev); |
1441 | if (!pm_runtime_enabled(dev)) { | |
1442 | ret = mipi_csis_pm_resume(dev, true); | |
1443 | if (ret < 0) | |
1444 | goto unregister_all; | |
1445 | } | |
1446 | ||
62bd05a4 | 1447 | dev_info(dev, "lanes: %d, freq: %u\n", |
74f81584 | 1448 | state->bus.num_data_lanes, state->clk_frequency); |
7807063b RMS |
1449 | |
1450 | return 0; | |
1451 | ||
1452 | unregister_all: | |
1453 | mipi_csis_debugfs_exit(state); | |
0e63a5e4 | 1454 | cleanup: |
b0db06bb | 1455 | media_entity_cleanup(&state->sd.entity); |
3c8c1539 SA |
1456 | v4l2_async_nf_unregister(&state->notifier); |
1457 | v4l2_async_nf_cleanup(&state->notifier); | |
b0db06bb | 1458 | v4l2_async_unregister_subdev(&state->sd); |
7807063b RMS |
1459 | disable_clock: |
1460 | mipi_csis_clk_disable(state); | |
1461 | mutex_destroy(&state->lock); | |
1462 | ||
1463 | return ret; | |
1464 | } | |
1465 | ||
7807063b RMS |
1466 | static int mipi_csis_remove(struct platform_device *pdev) |
1467 | { | |
b0db06bb LP |
1468 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); |
1469 | struct csi_state *state = mipi_sd_to_csis_state(sd); | |
7807063b RMS |
1470 | |
1471 | mipi_csis_debugfs_exit(state); | |
3c8c1539 SA |
1472 | v4l2_async_nf_unregister(&state->notifier); |
1473 | v4l2_async_nf_cleanup(&state->notifier); | |
b0db06bb | 1474 | v4l2_async_unregister_subdev(&state->sd); |
7807063b RMS |
1475 | |
1476 | pm_runtime_disable(&pdev->dev); | |
1477 | mipi_csis_pm_suspend(&pdev->dev, true); | |
1478 | mipi_csis_clk_disable(state); | |
b0db06bb | 1479 | media_entity_cleanup(&state->sd.entity); |
7807063b RMS |
1480 | mutex_destroy(&state->lock); |
1481 | pm_runtime_set_suspended(&pdev->dev); | |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
7807063b | 1486 | static const struct of_device_id mipi_csis_of_match[] = { |
f0e7cfbb LP |
1487 | { |
1488 | .compatible = "fsl,imx7-mipi-csi2", | |
1489 | .data = &(const struct mipi_csis_info){ | |
1490 | .version = MIPI_CSIS_V3_3, | |
1491 | .num_clocks = 3, | |
1492 | }, | |
1493 | }, { | |
1494 | .compatible = "fsl,imx8mm-mipi-csi2", | |
1495 | .data = &(const struct mipi_csis_info){ | |
1496 | .version = MIPI_CSIS_V3_6_3, | |
1497 | .num_clocks = 4, | |
1498 | }, | |
1499 | }, | |
7807063b RMS |
1500 | { /* sentinel */ }, |
1501 | }; | |
1502 | MODULE_DEVICE_TABLE(of, mipi_csis_of_match); | |
1503 | ||
1504 | static struct platform_driver mipi_csis_driver = { | |
1505 | .probe = mipi_csis_probe, | |
1506 | .remove = mipi_csis_remove, | |
1507 | .driver = { | |
1508 | .of_match_table = mipi_csis_of_match, | |
1509 | .name = CSIS_DRIVER_NAME, | |
1510 | .pm = &mipi_csis_pm_ops, | |
1511 | }, | |
1512 | }; | |
1513 | ||
1514 | module_platform_driver(mipi_csis_driver); | |
1515 | ||
f0e7cfbb | 1516 | MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); |
7807063b RMS |
1517 | MODULE_LICENSE("GPL v2"); |
1518 | MODULE_ALIAS("platform:imx7-mipi-csi2"); |