[linux-2.6-block.git] / drivers / staging / media / atomisp / pci / atomisp2 / css2400 / css_2401_csi2p_system / host / isys_irq_private.h

/*
 * Support for Intel Camera Imaging ISP subsystem.
 * Copyright (c) 2015, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef __ISYS_IRQ_PRIVATE_H__
#define __ISYS_IRQ_PRIVATE_H__

#include "isys_irq_global.h"
#include "isys_irq_local.h"

#if defined(USE_INPUT_SYSTEM_VERSION_2401)

/* -------------------------------------------------------+
 |             Native command interface (NCI)             |
 + -------------------------------------------------------*/

/**
* @brief Get the isys irq status.
* Refer to "isys_irq.h" for details.
*/
STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_get(
	const isys_irq_ID_t	isys_irqc_id,
	isys_irqc_state_t *state)
{
	state->edge     = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_EDGE_REG_IDX);
	state->mask     = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX);
	state->status   = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_STATUS_REG_IDX);
	state->enable   = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX);
	state->level_no = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_LEVEL_NO_REG_IDX);
	/*
	** Invalid to read/load from write-only register 'clear'
	** state->clear = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX);
	*/
}

/**
* @brief Dump the isys irq status.
* Refer to "isys_irq.h" for details.
*/
STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_dump(
	const isys_irq_ID_t	isys_irqc_id,
	const isys_irqc_state_t *state)
{
	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
		"isys irq controller id %d"
		"\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x"
		"\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
		isys_irqc_id,
		state->status, state->edge, state->mask, state->enable, state->level_no);
}

/* end of NCI */

/* -------------------------------------------------------+
 |              Device level interface (DLI)              |
 + -------------------------------------------------------*/

/* Support functions */
STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_reg_store(
	const isys_irq_ID_t	isys_irqc_id,
	const unsigned int	reg_idx,
	const hrt_data	value)
{
	unsigned int reg_addr;

	assert(isys_irqc_id < N_ISYS_IRQ_ID);
	assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);

	reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
		"isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);

	ia_css_device_store_uint32(reg_addr, value);
}

STORAGE_CLASS_ISYS2401_IRQ_C hrt_data isys_irqc_reg_load(
	const isys_irq_ID_t	isys_irqc_id,
	const unsigned int	reg_idx)
{
	unsigned int reg_addr;
	hrt_data value;

	assert(isys_irqc_id < N_ISYS_IRQ_ID);
	assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);

	reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
	value = ia_css_device_load_uint32(reg_addr);
	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
		"isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);

	return value;
}

/* end of DLI */

#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */

#endif	/* __ISYS_IRQ_PRIVATE_H__ */
Commit	Line	Data
a49d2536 AC	1	/*
	2	* Support for Intel Camera Imaging ISP subsystem.
	3	* Copyright (c) 2015, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#ifndef __ISYS_IRQ_PRIVATE_H__
	16	#define __ISYS_IRQ_PRIVATE_H__
	17
	18	#include "isys_irq_global.h"
	19	#include "isys_irq_local.h"
	20
	21	#if defined(USE_INPUT_SYSTEM_VERSION_2401)
	22
	23	/* -------------------------------------------------------+
	24	\| Native command interface (NCI) \|
	25	+ -------------------------------------------------------*/
	26
	27	/**
	28	* @brief Get the isys irq status.
	29	* Refer to "isys_irq.h" for details.
	30	*/
	31	STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_get(
	32	const isys_irq_ID_t isys_irqc_id,
	33	isys_irqc_state_t *state)
	34	{
	35	state->edge = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_EDGE_REG_IDX);
	36	state->mask = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX);
	37	state->status = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_STATUS_REG_IDX);
	38	state->enable = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX);
	39	state->level_no = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_LEVEL_NO_REG_IDX);
	40	/*
	41	** Invalid to read/load from write-only register 'clear'
	42	** state->clear = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX);
	43	*/
	44	}
	45
	46	/**
	47	* @brief Dump the isys irq status.
	48	* Refer to "isys_irq.h" for details.
	49	*/
	50	STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_dump(
	51	const isys_irq_ID_t isys_irqc_id,
	52	const isys_irqc_state_t *state)
	53	{
	54	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
	55	"isys irq controller id %d"
	56	"\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x"
	57	"\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
	58	isys_irqc_id,
	59	state->status, state->edge, state->mask, state->enable, state->level_no);
	60	}
	61
d929fb4e	62	/* end of NCI */
a49d2536 AC	63
	64	/* -------------------------------------------------------+
	65	\| Device level interface (DLI) \|
	66	+ -------------------------------------------------------*/
	67
	68	/* Support functions */
	69	STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_reg_store(
	70	const isys_irq_ID_t isys_irqc_id,
	71	const unsigned int reg_idx,
	72	const hrt_data value)
	73	{
	74	unsigned int reg_addr;
	75
	76	assert(isys_irqc_id < N_ISYS_IRQ_ID);
	77	assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
	78
	79	reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
	80	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
	81	"isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);
	82
	83	ia_css_device_store_uint32(reg_addr, value);
	84	}
	85
	86	STORAGE_CLASS_ISYS2401_IRQ_C hrt_data isys_irqc_reg_load(
	87	const isys_irq_ID_t isys_irqc_id,
	88	const unsigned int reg_idx)
	89	{
	90	unsigned int reg_addr;
	91	hrt_data value;
	92
	93	assert(isys_irqc_id < N_ISYS_IRQ_ID);
	94	assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
	95
	96	reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
	97	value = ia_css_device_load_uint32(reg_addr);
	98	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
	99	"isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);
	100
	101	return value;
	102	}
	103
d929fb4e	104	/* end of DLI */
a49d2536 AC	105
	106	#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */
	107
	108	#endif /* __ISYS_IRQ_PRIVATE_H__ */