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a49d2536 AC |
1 | /* |
2 | * Support for the Omnivision OV8858 camera sensor. | |
3 | * | |
4 | * Copyright (c) 2014 Intel Corporation. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License version | |
8 | * 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
18 | * 02110-1301, USA. | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __OV8858_H__ | |
23 | #define __OV8858_H__ | |
25016567 | 24 | #include "../include/linux/atomisp_platform.h" |
a49d2536 AC |
25 | #include <media/v4l2-ctrls.h> |
26 | ||
27 | #define I2C_MSG_LENGTH 0x2 | |
28 | ||
29 | /* | |
30 | * This should be added into include/linux/videodev2.h | |
31 | * NOTE: This is most likely not used anywhere. | |
32 | */ | |
33 | #define V4L2_IDENT_OV8858 V4L2_IDENT_UNKNOWN | |
34 | ||
35 | /* | |
36 | * Indexes for VCM driver lists | |
37 | */ | |
38 | #define OV8858_ID_DEFAULT 0 | |
39 | #define OV8858_SUNNY 1 | |
40 | ||
41 | #define OV8858_OTP_START_ADDR 0x7010 | |
42 | #define OV8858_OTP_END_ADDR 0x7186 | |
43 | ||
44 | /* | |
45 | * ov8858 System control registers | |
46 | */ | |
47 | ||
48 | #define OV8858_OTP_LOAD_CTRL 0x3D81 | |
49 | #define OV8858_OTP_MODE_CTRL 0x3D84 | |
50 | #define OV8858_OTP_START_ADDR_REG 0x3D88 | |
51 | #define OV8858_OTP_END_ADDR_REG 0x3D8A | |
52 | #define OV8858_OTP_ISP_CTRL2 0x5002 | |
53 | ||
54 | #define OV8858_OTP_MODE_MANUAL BIT(6) | |
55 | #define OV8858_OTP_MODE_PROGRAM_DISABLE BIT(7) | |
56 | #define OV8858_OTP_LOAD_ENABLE BIT(0) | |
57 | #define OV8858_OTP_DPC_ENABLE BIT(3) | |
58 | ||
59 | #define OV8858_PLL1_PREDIV0 0x030A | |
60 | #define OV8858_PLL1_PREDIV 0x0300 | |
61 | #define OV8858_PLL1_MULTIPLIER 0x0301 | |
62 | #define OV8858_PLL1_SYS_PRE_DIV 0x0305 | |
63 | #define OV8858_PLL1_SYS_DIVIDER 0x0306 | |
64 | ||
65 | #define OV8858_PLL1_PREDIV0_MASK BIT(0) | |
66 | #define OV8858_PLL1_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) | |
67 | #define OV8858_PLL1_MULTIPLIER_MASK 0x01FF | |
68 | #define OV8858_PLL1_SYS_PRE_DIV_MASK (BIT(0) | BIT(1)) | |
69 | #define OV8858_PLL1_SYS_DIVIDER_MASK BIT(0) | |
70 | ||
71 | #define OV8858_PLL2_PREDIV0 0x0312 | |
72 | #define OV8858_PLL2_PREDIV 0x030B | |
73 | #define OV8858_PLL2_MULTIPLIER 0x030C | |
74 | #define OV8858_PLL2_DAC_DIVIDER 0x0312 | |
75 | #define OV8858_PLL2_SYS_PRE_DIV 0x030F | |
76 | #define OV8858_PLL2_SYS_DIVIDER 0x030E | |
77 | ||
78 | #define OV8858_PLL2_PREDIV0_MASK BIT(4) | |
79 | #define OV8858_PLL2_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) | |
80 | #define OV8858_PLL2_MULTIPLIER_MASK 0x01FF | |
81 | #define OV8858_PLL2_DAC_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) | |
82 | #define OV8858_PLL2_SYS_PRE_DIV_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) | |
83 | #define OV8858_PLL2_SYS_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2)) | |
84 | ||
85 | #define OV8858_PLL_SCLKSEL1 0x3032 | |
86 | #define OV8858_PLL_SCLKSEL2 0x3033 | |
87 | #define OV8858_SRB_HOST_INPUT_DIS 0x3106 | |
88 | ||
89 | #define OV8858_PLL_SCLKSEL1_MASK BIT(7) | |
90 | #define OV8858_PLL_SCLKSEL2_MASK BIT(1) | |
91 | ||
92 | #define OV8858_SYS_PRE_DIV_OFFSET 2 | |
93 | #define OV8858_SYS_PRE_DIV_MASK (BIT(2) | BIT(3)) | |
94 | #define OV8858_SCLK_PDIV_OFFSET 4 | |
95 | #define OV8858_SCLK_PDIV_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7)) | |
96 | ||
97 | #define OV8858_TIMING_HTS 0x380C | |
98 | #define OV8858_TIMING_VTS 0x380E | |
99 | ||
100 | #define OV8858_HORIZONTAL_START_H 0x3800 | |
101 | #define OV8858_VERTICAL_START_H 0x3802 | |
102 | #define OV8858_HORIZONTAL_END_H 0x3804 | |
103 | #define OV8858_VERTICAL_END_H 0x3806 | |
104 | #define OV8858_HORIZONTAL_OUTPUT_SIZE_H 0x3808 | |
105 | #define OV8858_VERTICAL_OUTPUT_SIZE_H 0x380A | |
106 | ||
107 | #define OV8858_GROUP_ACCESS 0x3208 | |
108 | #define OV8858_GROUP_ZERO 0x00 | |
109 | #define OV8858_GROUP_ACCESS_HOLD_START 0x00 | |
110 | #define OV8858_GROUP_ACCESS_HOLD_END 0x10 | |
111 | #define OV8858_GROUP_ACCESS_DELAY_LAUNCH 0xA0 | |
112 | #define OV8858_GROUP_ACCESS_QUICK_LAUNCH 0xE0 | |
113 | ||
114 | #define OV_SUBDEV_PREFIX "ov" | |
115 | #define OV_ID_DEFAULT 0x0000 | |
116 | #define OV8858_NAME "ov8858" | |
117 | #define OV8858_CHIP_ID 0x8858 | |
118 | ||
119 | #define OV8858_LONG_EXPO 0x3500 | |
120 | #define OV8858_LONG_GAIN 0x3508 | |
121 | #define OV8858_LONG_DIGI_GAIN 0x350A | |
122 | #define OV8858_SHORT_GAIN 0x350C | |
123 | #define OV8858_SHORT_DIGI_GAIN 0x350E | |
124 | ||
125 | #define OV8858_FORMAT1 0x3820 | |
126 | #define OV8858_FORMAT2 0x3821 | |
127 | ||
128 | #define OV8858_FLIP_ENABLE 0x06 | |
129 | ||
130 | #define OV8858_MWB_RED_GAIN_H 0x5032 | |
131 | #define OV8858_MWB_GREEN_GAIN_H 0x5034 | |
132 | #define OV8858_MWB_BLUE_GAIN_H 0x5036 | |
133 | #define OV8858_MWB_GAIN_MAX 0x0FFF | |
134 | ||
135 | #define OV8858_CHIP_ID_HIGH 0x300B | |
136 | #define OV8858_CHIP_ID_LOW 0x300C | |
137 | #define OV8858_STREAM_MODE 0x0100 | |
138 | ||
139 | #define OV8858_FOCAL_LENGTH_NUM 294 /* 2.94mm */ | |
140 | #define OV8858_FOCAL_LENGTH_DEM 100 | |
141 | #define OV8858_F_NUMBER_DEFAULT_NUM 24 /* 2.4 */ | |
142 | #define OV8858_F_NUMBER_DEM 10 | |
143 | ||
144 | #define OV8858_H_INC_ODD 0x3814 | |
145 | #define OV8858_H_INC_EVEN 0x3815 | |
146 | #define OV8858_V_INC_ODD 0x382A | |
147 | #define OV8858_V_INC_EVEN 0x382B | |
148 | ||
149 | #define OV8858_READ_MODE_BINNING_ON 0x0400 /* ToDo: Check this */ | |
150 | #define OV8858_READ_MODE_BINNING_OFF 0x00 /* ToDo: Check this */ | |
151 | #define OV8858_BIN_FACTOR_MAX 2 | |
152 | #define OV8858_INTEGRATION_TIME_MARGIN 14 | |
153 | ||
154 | #define OV8858_MAX_VTS_VALUE 0xFFFF | |
155 | #define OV8858_MAX_EXPOSURE_VALUE \ | |
156 | (OV8858_MAX_VTS_VALUE - OV8858_INTEGRATION_TIME_MARGIN) | |
157 | #define OV8858_MAX_GAIN_VALUE 0x07FF | |
158 | ||
159 | #define OV8858_MAX_FOCUS_POS 1023 | |
160 | ||
161 | #define OV8858_TEST_PATTERN_REG 0x5E00 | |
162 | ||
163 | struct ov8858_vcm { | |
164 | int (*power_up)(struct v4l2_subdev *sd); | |
165 | int (*power_down)(struct v4l2_subdev *sd); | |
166 | int (*init)(struct v4l2_subdev *sd); | |
167 | int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); | |
168 | int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); | |
169 | int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); | |
170 | int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); | |
171 | int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); | |
172 | int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); | |
173 | int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); | |
174 | }; | |
175 | ||
176 | /* | |
177 | * Defines for register writes and register array processing | |
178 | * */ | |
179 | #define OV8858_BYTE_MAX 32 | |
180 | #define OV8858_SHORT_MAX 16 | |
181 | #define OV8858_TOK_MASK 0xFFF0 | |
182 | ||
183 | #define MAX_FPS_OPTIONS_SUPPORTED 3 | |
184 | ||
185 | #define OV8858_DEPTH_COMP_CONST 2200 | |
186 | #define OV8858_DEPTH_VTS_CONST 2573 | |
187 | ||
188 | enum ov8858_tok_type { | |
189 | OV8858_8BIT = 0x0001, | |
190 | OV8858_16BIT = 0x0002, | |
191 | OV8858_TOK_TERM = 0xF000, /* terminating token for reg list */ | |
192 | OV8858_TOK_DELAY = 0xFE00 /* delay token for reg list */ | |
193 | }; | |
194 | ||
195 | /* | |
196 | * If register address or register width is not 32 bit width, | |
197 | * user needs to convert it manually | |
198 | */ | |
199 | struct s_register_setting { | |
200 | u32 reg; | |
201 | u32 val; | |
202 | }; | |
203 | ||
204 | /** | |
205 | * struct ov8858_reg - MI sensor register format | |
206 | * @type: type of the register | |
207 | * @reg: 16-bit offset to register | |
208 | * @val: 8/16/32-bit register value | |
209 | * | |
210 | * Define a structure for sensor register initialization values | |
211 | */ | |
212 | struct ov8858_reg { | |
213 | enum ov8858_tok_type type; | |
214 | u16 sreg; | |
215 | u32 val; /* @set value for read/mod/write, @mask */ | |
216 | }; | |
217 | ||
218 | struct ov8858_fps_setting { | |
219 | int fps; | |
220 | unsigned short pixels_per_line; | |
221 | unsigned short lines_per_frame; | |
222 | const struct ov8858_reg *regs; /* regs that the fps setting needs */ | |
223 | }; | |
224 | ||
225 | struct ov8858_resolution { | |
226 | u8 *desc; | |
227 | const struct ov8858_reg *regs; | |
228 | int res; | |
229 | int width; | |
230 | int height; | |
231 | bool used; | |
232 | u8 bin_factor_x; | |
233 | u8 bin_factor_y; | |
234 | unsigned short skip_frames; | |
235 | const struct ov8858_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; | |
236 | }; | |
237 | ||
238 | /* | |
239 | * ov8858 device structure | |
240 | * */ | |
241 | struct ov8858_device { | |
242 | struct v4l2_subdev sd; | |
243 | struct media_pad pad; | |
244 | struct v4l2_mbus_framefmt format; | |
245 | ||
246 | struct camera_sensor_platform_data *platform_data; | |
247 | struct mutex input_lock; /* serialize sensor's ioctl */ | |
248 | int fmt_idx; | |
249 | int streaming; | |
250 | int vt_pix_clk_freq_mhz; | |
251 | int fps_index; | |
252 | u16 sensor_id; /* Sensor id from registers */ | |
253 | u16 i2c_id; /* Sensor id from i2c_device_id */ | |
254 | int exposure; | |
255 | int gain; | |
256 | u16 digital_gain; | |
257 | u16 pixels_per_line; | |
258 | u16 lines_per_frame; | |
259 | u8 fps; | |
260 | u8 *otp_data; | |
261 | /* Prevent the framerate from being lowered in low light scenes. */ | |
262 | int limit_exposure_flag; | |
263 | bool hflip; | |
264 | bool vflip; | |
265 | ||
266 | const struct ov8858_reg *regs; | |
267 | struct ov8858_vcm *vcm_driver; | |
268 | const struct ov8858_resolution *curr_res_table; | |
8033120f | 269 | unsigned long entries_curr_table; |
a49d2536 AC |
270 | |
271 | struct v4l2_ctrl_handler ctrl_handler; | |
272 | struct v4l2_ctrl *run_mode; | |
273 | }; | |
274 | ||
275 | #define to_ov8858_sensor(x) container_of(x, struct ov8858_device, sd) | |
276 | ||
277 | #define OV8858_MAX_WRITE_BUF_SIZE 32 | |
278 | struct ov8858_write_buffer { | |
279 | u16 addr; | |
280 | u8 data[OV8858_MAX_WRITE_BUF_SIZE]; | |
281 | }; | |
282 | ||
283 | struct ov8858_write_ctrl { | |
284 | int index; | |
285 | struct ov8858_write_buffer buffer; | |
286 | }; | |
287 | ||
288 | static const struct ov8858_reg ov8858_soft_standby[] = { | |
289 | {OV8858_8BIT, 0x0100, 0x00}, | |
290 | {OV8858_TOK_TERM, 0, 0} | |
291 | }; | |
292 | ||
293 | static const struct ov8858_reg ov8858_streaming[] = { | |
294 | {OV8858_8BIT, 0x0100, 0x01}, | |
295 | {OV8858_TOK_TERM, 0, 0} | |
296 | }; | |
297 | ||
298 | static const struct ov8858_reg ov8858_param_hold[] = { | |
299 | {OV8858_8BIT, OV8858_GROUP_ACCESS, | |
300 | OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_START}, | |
301 | {OV8858_TOK_TERM, 0, 0} | |
302 | }; | |
303 | ||
304 | static const struct ov8858_reg ov8858_param_update[] = { | |
305 | {OV8858_8BIT, OV8858_GROUP_ACCESS, | |
306 | OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_END}, | |
307 | {OV8858_8BIT, OV8858_GROUP_ACCESS, | |
308 | OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_DELAY_LAUNCH}, | |
309 | {OV8858_TOK_TERM, 0, 0} | |
310 | }; | |
311 | ||
312 | extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); | |
313 | extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); | |
314 | extern int dw9718_vcm_init(struct v4l2_subdev *sd); | |
315 | extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); | |
316 | extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); | |
317 | extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); | |
318 | extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); | |
319 | extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); | |
320 | extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); | |
321 | extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); | |
322 | ||
323 | extern int vcm_power_up(struct v4l2_subdev *sd); | |
324 | extern int vcm_power_down(struct v4l2_subdev *sd); | |
325 | ||
326 | static struct ov8858_vcm ov8858_vcms[] = { | |
327 | [OV8858_SUNNY] = { | |
328 | .power_up = dw9718_vcm_power_up, | |
329 | .power_down = dw9718_vcm_power_down, | |
330 | .init = dw9718_vcm_init, | |
331 | .t_focus_vcm = dw9718_t_focus_vcm, | |
332 | .t_focus_abs = dw9718_t_focus_abs, | |
333 | .t_focus_rel = dw9718_t_focus_rel, | |
334 | .q_focus_status = dw9718_q_focus_status, | |
335 | .q_focus_abs = dw9718_q_focus_abs, | |
336 | .t_vcm_slew = dw9718_t_vcm_slew, | |
337 | .t_vcm_timing = dw9718_t_vcm_timing, | |
338 | }, | |
339 | [OV8858_ID_DEFAULT] = { | |
340 | .power_up = NULL, | |
341 | .power_down = NULL, | |
342 | }, | |
343 | }; | |
344 | ||
345 | ||
346 | #define OV8858_RES_WIDTH_MAX 3280 | |
347 | #define OV8858_RES_HEIGHT_MAX 2464 | |
348 | ||
349 | static struct ov8858_reg ov8858_BasicSettings[] = { | |
350 | {OV8858_8BIT, 0x0103, 0x01}, /* software_reset */ | |
351 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
352 | /* PLL settings */ | |
353 | {OV8858_8BIT, 0x0300, 0x05}, /* pll1_pre_div = /4 */ | |
354 | {OV8858_8BIT, 0x0302, 0xAF}, /* pll1_multiplier = 175 */ | |
355 | {OV8858_8BIT, 0x0303, 0x00}, /* pll1_divm = /(1 + 0) */ | |
356 | {OV8858_8BIT, 0x0304, 0x03}, /* pll1_div_mipi = /8 */ | |
357 | {OV8858_8BIT, 0x030B, 0x02}, /* pll2_pre_div = /2 */ | |
358 | {OV8858_8BIT, 0x030D, 0x4E}, /* pll2_r_divp = 78 */ | |
359 | {OV8858_8BIT, 0x030E, 0x00}, /* pll2_r_divs = /1 */ | |
360 | {OV8858_8BIT, 0x030F, 0x04}, /* pll2_r_divsp = /(1 + 4) */ | |
361 | /* pll2_pre_div0 = /1, pll2_r_divdac = /(1 + 1) */ | |
362 | {OV8858_8BIT, 0x0312, 0x01}, | |
363 | {OV8858_8BIT, 0x031E, 0x0C}, /* pll1_no_lat = 1, mipi_bitsel_man = 0 */ | |
364 | ||
365 | /* PAD OEN2, VSYNC out enable=0x80, disable=0x00 */ | |
366 | {OV8858_8BIT, 0x3002, 0x80}, | |
367 | /* PAD OUT2, VSYNC pulse direction low-to-high = 1 */ | |
368 | {OV8858_8BIT, 0x3007, 0x01}, | |
369 | /* PAD SEL2, VSYNC out value = 0 */ | |
370 | {OV8858_8BIT, 0x300D, 0x00}, | |
371 | /* PAD OUT2, VSYNC out select = 0 */ | |
372 | {OV8858_8BIT, 0x3010, 0x00}, | |
373 | ||
374 | /* Npump clock div = /2, Ppump clock div = /4 */ | |
375 | {OV8858_8BIT, 0x3015, 0x01}, | |
376 | /* | |
377 | * mipi_lane_mode = 1+3, mipi_lvds_sel = 1 = MIPI enable, | |
378 | * r_phy_pd_mipi_man = 0, lane_dis_option = 0 | |
379 | */ | |
380 | {OV8858_8BIT, 0x3018, 0x72}, | |
381 | /* Clock switch output = normal, pclk_div = /1 */ | |
382 | {OV8858_8BIT, 0x3020, 0x93}, | |
383 | /* | |
384 | * lvds_mode_o = 0, clock lane disable when pd_mipi = 0, | |
385 | * pd_mipi enable when rst_sync = 1 | |
386 | */ | |
387 | {OV8858_8BIT, 0x3022, 0x01}, | |
388 | {OV8858_8BIT, 0x3031, 0x0A}, /* mipi_bit_sel = 10 */ | |
389 | {OV8858_8BIT, 0x3034, 0x00}, /* Unknown */ | |
390 | /* sclk_div = /1, sclk_pre_div = /1, chip debug = 1 */ | |
391 | {OV8858_8BIT, 0x3106, 0x01}, | |
392 | ||
393 | {OV8858_8BIT, 0x3305, 0xF1}, /* Unknown */ | |
394 | {OV8858_8BIT, 0x3307, 0x04}, /* Unknown */ | |
395 | {OV8858_8BIT, 0x3308, 0x00}, /* Unknown */ | |
396 | {OV8858_8BIT, 0x3309, 0x28}, /* Unknown */ | |
397 | {OV8858_8BIT, 0x330A, 0x00}, /* Unknown */ | |
398 | {OV8858_8BIT, 0x330B, 0x20}, /* Unknown */ | |
399 | {OV8858_8BIT, 0x330C, 0x00}, /* Unknown */ | |
400 | {OV8858_8BIT, 0x330D, 0x00}, /* Unknown */ | |
401 | {OV8858_8BIT, 0x330E, 0x00}, /* Unknown */ | |
402 | {OV8858_8BIT, 0x330F, 0x40}, /* Unknown */ | |
403 | ||
404 | {OV8858_8BIT, 0x3500, 0x00}, /* long exposure = 0x9A20 */ | |
405 | {OV8858_8BIT, 0x3501, 0x9A}, /* long exposure = 0x9A20 */ | |
406 | {OV8858_8BIT, 0x3502, 0x20}, /* long exposure = 0x9A20 */ | |
407 | /* | |
408 | * Digital fraction gain delay option = Delay 1 frame, | |
409 | * Gain change delay option = Delay 1 frame, | |
410 | * Gain delay option = Delay 1 frame, | |
411 | * Gain manual as sensor gain = Input gain as real gain format, | |
412 | * Exposure delay option (must be 0 = Delay 1 frame, | |
413 | * Exposure change delay option (must be 0) = Delay 1 frame | |
414 | */ | |
415 | {OV8858_8BIT, 0x3503, 0x00}, | |
416 | {OV8858_8BIT, 0x3505, 0x80}, /* gain conversation option */ | |
417 | /* | |
418 | * [10:7] are integer gain, [6:0] are fraction gain. For example: | |
419 | * 0x80 is 1x gain, 0x100 is 2x gain, 0x1C0 is 3.5x gain | |
420 | */ | |
421 | {OV8858_8BIT, 0x3508, 0x02}, /* long gain = 0x0200 */ | |
422 | {OV8858_8BIT, 0x3509, 0x00}, /* long gain = 0x0200 */ | |
423 | {OV8858_8BIT, 0x350C, 0x00}, /* short gain = 0x0080 */ | |
424 | {OV8858_8BIT, 0x350D, 0x80}, /* short gain = 0x0080 */ | |
425 | {OV8858_8BIT, 0x3510, 0x00}, /* short exposure = 0x000200 */ | |
426 | {OV8858_8BIT, 0x3511, 0x02}, /* short exposure = 0x000200 */ | |
427 | {OV8858_8BIT, 0x3512, 0x00}, /* short exposure = 0x000200 */ | |
428 | ||
429 | {OV8858_8BIT, 0x3600, 0x00}, /* Unknown */ | |
430 | {OV8858_8BIT, 0x3601, 0x00}, /* Unknown */ | |
431 | {OV8858_8BIT, 0x3602, 0x00}, /* Unknown */ | |
432 | {OV8858_8BIT, 0x3603, 0x00}, /* Unknown */ | |
433 | {OV8858_8BIT, 0x3604, 0x22}, /* Unknown */ | |
434 | {OV8858_8BIT, 0x3605, 0x30}, /* Unknown */ | |
435 | {OV8858_8BIT, 0x3606, 0x00}, /* Unknown */ | |
436 | {OV8858_8BIT, 0x3607, 0x20}, /* Unknown */ | |
437 | {OV8858_8BIT, 0x3608, 0x11}, /* Unknown */ | |
438 | {OV8858_8BIT, 0x3609, 0x28}, /* Unknown */ | |
439 | {OV8858_8BIT, 0x360A, 0x00}, /* Unknown */ | |
440 | {OV8858_8BIT, 0x360B, 0x06}, /* Unknown */ | |
441 | {OV8858_8BIT, 0x360C, 0xDC}, /* Unknown */ | |
442 | {OV8858_8BIT, 0x360D, 0x40}, /* Unknown */ | |
443 | {OV8858_8BIT, 0x360E, 0x0C}, /* Unknown */ | |
444 | {OV8858_8BIT, 0x360F, 0x20}, /* Unknown */ | |
445 | {OV8858_8BIT, 0x3610, 0x07}, /* Unknown */ | |
446 | {OV8858_8BIT, 0x3611, 0x20}, /* Unknown */ | |
447 | {OV8858_8BIT, 0x3612, 0x88}, /* Unknown */ | |
448 | {OV8858_8BIT, 0x3613, 0x80}, /* Unknown */ | |
449 | {OV8858_8BIT, 0x3614, 0x58}, /* Unknown */ | |
450 | {OV8858_8BIT, 0x3615, 0x00}, /* Unknown */ | |
451 | {OV8858_8BIT, 0x3616, 0x4A}, /* Unknown */ | |
452 | {OV8858_8BIT, 0x3617, 0x90}, /* Unknown */ | |
453 | {OV8858_8BIT, 0x3618, 0x56}, /* Unknown */ | |
454 | {OV8858_8BIT, 0x3619, 0x70}, /* Unknown */ | |
455 | {OV8858_8BIT, 0x361A, 0x99}, /* Unknown */ | |
456 | {OV8858_8BIT, 0x361B, 0x00}, /* Unknown */ | |
457 | {OV8858_8BIT, 0x361C, 0x07}, /* Unknown */ | |
458 | {OV8858_8BIT, 0x361D, 0x00}, /* Unknown */ | |
459 | {OV8858_8BIT, 0x361E, 0x00}, /* Unknown */ | |
460 | {OV8858_8BIT, 0x361F, 0x00}, /* Unknown */ | |
461 | {OV8858_8BIT, 0x3633, 0x0C}, /* Unknown */ | |
462 | {OV8858_8BIT, 0x3634, 0x0C}, /* Unknown */ | |
463 | {OV8858_8BIT, 0x3635, 0x0C}, /* Unknown */ | |
464 | {OV8858_8BIT, 0x3636, 0x0C}, /* Unknown */ | |
465 | {OV8858_8BIT, 0x3638, 0xFF}, /* Unknown */ | |
466 | {OV8858_8BIT, 0x3645, 0x13}, /* Unknown */ | |
467 | {OV8858_8BIT, 0x3646, 0x83}, /* Unknown */ | |
468 | {OV8858_8BIT, 0x364A, 0x07}, /* Unknown */ | |
469 | ||
470 | {OV8858_8BIT, 0x3700, 0x30}, /* Unknown */ | |
471 | {OV8858_8BIT, 0x3701, 0x18}, /* Unknown */ | |
472 | {OV8858_8BIT, 0x3702, 0x50}, /* Unknown */ | |
473 | {OV8858_8BIT, 0x3703, 0x32}, /* Unknown */ | |
474 | {OV8858_8BIT, 0x3704, 0x28}, /* Unknown */ | |
475 | {OV8858_8BIT, 0x3705, 0x00}, /* Unknown */ | |
476 | {OV8858_8BIT, 0x3706, 0x6A}, /* Unknown */ | |
477 | {OV8858_8BIT, 0x3707, 0x08}, /* Unknown */ | |
478 | {OV8858_8BIT, 0x3708, 0x48}, /* Unknown */ | |
479 | {OV8858_8BIT, 0x3709, 0x66}, /* Unknown */ | |
480 | {OV8858_8BIT, 0x370A, 0x01}, /* Unknown */ | |
481 | {OV8858_8BIT, 0x370B, 0x6A}, /* Unknown */ | |
482 | {OV8858_8BIT, 0x370C, 0x07}, /* Unknown */ | |
483 | {OV8858_8BIT, 0x3712, 0x44}, /* Unknown */ | |
484 | {OV8858_8BIT, 0x3714, 0x24}, /* Unknown */ | |
485 | {OV8858_8BIT, 0x3718, 0x14}, /* Unknown */ | |
486 | {OV8858_8BIT, 0x3719, 0x31}, /* Unknown */ | |
487 | {OV8858_8BIT, 0x371E, 0x31}, /* Unknown */ | |
488 | {OV8858_8BIT, 0x371F, 0x7F}, /* Unknown */ | |
489 | {OV8858_8BIT, 0x3720, 0x0A}, /* Unknown */ | |
490 | {OV8858_8BIT, 0x3721, 0x0A}, /* Unknown */ | |
491 | {OV8858_8BIT, 0x3724, 0x0C}, /* Unknown */ | |
492 | {OV8858_8BIT, 0x3725, 0x02}, /* Unknown */ | |
493 | {OV8858_8BIT, 0x3726, 0x0C}, /* Unknown */ | |
494 | {OV8858_8BIT, 0x3728, 0x0A}, /* Unknown */ | |
495 | {OV8858_8BIT, 0x3729, 0x03}, /* Unknown */ | |
496 | {OV8858_8BIT, 0x372A, 0x06}, /* Unknown */ | |
497 | {OV8858_8BIT, 0x372B, 0xA6}, /* Unknown */ | |
498 | {OV8858_8BIT, 0x372C, 0xA6}, /* Unknown */ | |
499 | {OV8858_8BIT, 0x372D, 0xA6}, /* Unknown */ | |
500 | {OV8858_8BIT, 0x372E, 0x0C}, /* Unknown */ | |
501 | {OV8858_8BIT, 0x372F, 0x20}, /* Unknown */ | |
502 | {OV8858_8BIT, 0x3730, 0x02}, /* Unknown */ | |
503 | {OV8858_8BIT, 0x3731, 0x0C}, /* Unknown */ | |
504 | {OV8858_8BIT, 0x3732, 0x28}, /* Unknown */ | |
505 | {OV8858_8BIT, 0x3733, 0x10}, /* Unknown */ | |
506 | {OV8858_8BIT, 0x3734, 0x40}, /* Unknown */ | |
507 | {OV8858_8BIT, 0x3736, 0x30}, /* Unknown */ | |
508 | {OV8858_8BIT, 0x373A, 0x0A}, /* Unknown */ | |
509 | {OV8858_8BIT, 0x373B, 0x0B}, /* Unknown */ | |
510 | {OV8858_8BIT, 0x373C, 0x14}, /* Unknown */ | |
511 | {OV8858_8BIT, 0x373E, 0x06}, /* Unknown */ | |
512 | {OV8858_8BIT, 0x3755, 0x10}, /* Unknown */ | |
513 | {OV8858_8BIT, 0x3758, 0x00}, /* Unknown */ | |
514 | {OV8858_8BIT, 0x3759, 0x4C}, /* Unknown */ | |
515 | {OV8858_8BIT, 0x375A, 0x0C}, /* Unknown */ | |
516 | {OV8858_8BIT, 0x375B, 0x26}, /* Unknown */ | |
517 | {OV8858_8BIT, 0x375C, 0x20}, /* Unknown */ | |
518 | {OV8858_8BIT, 0x375D, 0x04}, /* Unknown */ | |
519 | {OV8858_8BIT, 0x375E, 0x00}, /* Unknown */ | |
520 | {OV8858_8BIT, 0x375F, 0x28}, /* Unknown */ | |
521 | {OV8858_8BIT, 0x3760, 0x00}, /* Unknown */ | |
522 | {OV8858_8BIT, 0x3761, 0x00}, /* Unknown */ | |
523 | {OV8858_8BIT, 0x3762, 0x00}, /* Unknown */ | |
524 | {OV8858_8BIT, 0x3763, 0x00}, /* Unknown */ | |
525 | {OV8858_8BIT, 0x3766, 0xFF}, /* Unknown */ | |
526 | {OV8858_8BIT, 0x3768, 0x22}, /* Unknown */ | |
527 | {OV8858_8BIT, 0x3769, 0x44}, /* Unknown */ | |
528 | {OV8858_8BIT, 0x376A, 0x44}, /* Unknown */ | |
529 | {OV8858_8BIT, 0x376B, 0x00}, /* Unknown */ | |
530 | {OV8858_8BIT, 0x376F, 0x01}, /* Unknown */ | |
531 | {OV8858_8BIT, 0x3772, 0x46}, /* Unknown */ | |
532 | {OV8858_8BIT, 0x3773, 0x04}, /* Unknown */ | |
533 | {OV8858_8BIT, 0x3774, 0x2C}, /* Unknown */ | |
534 | {OV8858_8BIT, 0x3775, 0x13}, /* Unknown */ | |
535 | {OV8858_8BIT, 0x3776, 0x08}, /* Unknown */ | |
536 | {OV8858_8BIT, 0x3777, 0x00}, /* Unknown */ | |
537 | {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ | |
538 | {OV8858_8BIT, 0x37A0, 0x88}, /* Unknown */ | |
539 | {OV8858_8BIT, 0x37A1, 0x7A}, /* Unknown */ | |
540 | {OV8858_8BIT, 0x37A2, 0x7A}, /* Unknown */ | |
541 | {OV8858_8BIT, 0x37A3, 0x00}, /* Unknown */ | |
542 | {OV8858_8BIT, 0x37A4, 0x00}, /* Unknown */ | |
543 | {OV8858_8BIT, 0x37A5, 0x00}, /* Unknown */ | |
544 | {OV8858_8BIT, 0x37A6, 0x00}, /* Unknown */ | |
545 | {OV8858_8BIT, 0x37A7, 0x88}, /* Unknown */ | |
546 | {OV8858_8BIT, 0x37A8, 0x98}, /* Unknown */ | |
547 | {OV8858_8BIT, 0x37A9, 0x98}, /* Unknown */ | |
548 | {OV8858_8BIT, 0x37AA, 0x88}, /* Unknown */ | |
549 | {OV8858_8BIT, 0x37AB, 0x5C}, /* Unknown */ | |
550 | {OV8858_8BIT, 0x37AC, 0x5C}, /* Unknown */ | |
551 | {OV8858_8BIT, 0x37AD, 0x55}, /* Unknown */ | |
552 | {OV8858_8BIT, 0x37AE, 0x19}, /* Unknown */ | |
553 | {OV8858_8BIT, 0x37AF, 0x19}, /* Unknown */ | |
554 | {OV8858_8BIT, 0x37B0, 0x00}, /* Unknown */ | |
555 | {OV8858_8BIT, 0x37B1, 0x00}, /* Unknown */ | |
556 | {OV8858_8BIT, 0x37B2, 0x00}, /* Unknown */ | |
557 | {OV8858_8BIT, 0x37B3, 0x84}, /* Unknown */ | |
558 | {OV8858_8BIT, 0x37B4, 0x84}, /* Unknown */ | |
559 | {OV8858_8BIT, 0x37B5, 0x66}, /* Unknown */ | |
560 | {OV8858_8BIT, 0x37B6, 0x00}, /* Unknown */ | |
561 | {OV8858_8BIT, 0x37B7, 0x00}, /* Unknown */ | |
562 | {OV8858_8BIT, 0x37B8, 0x00}, /* Unknown */ | |
563 | {OV8858_8BIT, 0x37B9, 0xFF}, /* Unknown */ | |
564 | ||
565 | {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ | |
566 | {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ | |
567 | {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ | |
568 | {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ | |
569 | {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ | |
570 | {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ | |
571 | {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ | |
572 | {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ | |
573 | {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high */ | |
574 | {OV8858_8BIT, 0x3809, 0xC0}, /* h_output_size low */ | |
575 | {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ | |
576 | {OV8858_8BIT, 0x380B, 0x90}, /* v_output_size low */ | |
577 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
578 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
579 | {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ | |
580 | {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ | |
581 | {OV8858_8BIT, 0x3810, 0x00}, /* h_win offset high */ | |
582 | {OV8858_8BIT, 0x3811, 0x04}, /* h_win offset low */ | |
583 | {OV8858_8BIT, 0x3812, 0x00}, /* v_win offset high */ | |
584 | {OV8858_8BIT, 0x3813, 0x02}, /* v_win offset low */ | |
585 | {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ | |
586 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
587 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
588 | {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ | |
589 | {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ | |
590 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
591 | ||
592 | {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ | |
593 | {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ | |
594 | {OV8858_8BIT, 0x3837, 0x18}, /* Unknown */ | |
595 | {OV8858_8BIT, 0x3841, 0xFF}, /* AUTO_SIZE_CTRL */ | |
596 | {OV8858_8BIT, 0x3846, 0x48}, /* Unknown */ | |
597 | ||
598 | {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ | |
599 | {OV8858_8BIT, 0x3D8C, 0x73}, /* OTP_SETTING_STT_ADDRESS */ | |
600 | {OV8858_8BIT, 0x3D8D, 0xDE}, /* OTP_SETTING_STT_ADDRESS */ | |
601 | {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ | |
602 | {OV8858_8BIT, 0x3F0A, 0x80}, /* PSRAM control register */ | |
603 | ||
604 | {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ | |
605 | {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ | |
606 | {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ | |
607 | {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ | |
608 | {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ | |
609 | {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ | |
610 | {OV8858_8BIT, 0x400A, 0x01}, | |
611 | {OV8858_8BIT, 0x4011, 0x20}, /* BLC CTRL11 = 0x20 */ | |
612 | {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ | |
613 | {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ | |
614 | {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ | |
615 | {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ | |
616 | {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ | |
617 | {OV8858_8BIT, 0x4022, 0x0C}, /* Anchor left end = 0x0C60 */ | |
618 | {OV8858_8BIT, 0x4023, 0x60}, /* Anchor left end = 0x0C60 */ | |
619 | {OV8858_8BIT, 0x4024, 0x0F}, /* Anchor right start = 0x0F36 */ | |
620 | {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0F36 */ | |
621 | {OV8858_8BIT, 0x4026, 0x0F}, /* Anchor right end = 0x0F37 */ | |
622 | {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0F37 */ | |
623 | {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ | |
624 | {OV8858_8BIT, 0x4029, 0x04}, /* Top zero line number = 4 */ | |
625 | {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ | |
626 | {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ | |
627 | {OV8858_8BIT, 0x402C, 0x00}, /* Bottom zero start line = 0 */ | |
628 | {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ | |
629 | {OV8858_8BIT, 0x402E, 0x04}, /* Bottom black line start = 4 */ | |
630 | {OV8858_8BIT, 0x402F, 0x08}, /* Bottom black line number = 8 */ | |
631 | ||
632 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
633 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
634 | {OV8858_8BIT, 0x4300, 0xFF}, /* clip_max[11:4] = 0xFFF */ | |
635 | {OV8858_8BIT, 0x4301, 0x00}, /* clip_min[11:4] = 0 */ | |
636 | {OV8858_8BIT, 0x4302, 0x0F}, /* clip_min/max[3:0] */ | |
637 | {OV8858_8BIT, 0x4307, 0x01}, /* Unknown */ | |
638 | {OV8858_8BIT, 0x4316, 0x00}, /* CTRL16 = default */ | |
639 | {OV8858_8BIT, 0x4503, 0x18}, /* Unknown */ | |
640 | {OV8858_8BIT, 0x4500, 0x38}, /* Unknown */ | |
641 | {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ | |
642 | {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ | |
643 | /* wkup_dly = Mark1 wakeup delay/2^10 = 0x25 */ | |
644 | {OV8858_8BIT, 0x4808, 0x25}, | |
645 | {OV8858_8BIT, 0x4816, 0x52}, /* Embedded data type*/ | |
646 | {OV8858_8BIT, 0x481F, 0x32}, /* clk_prepare_min = 0x32 */ | |
647 | {OV8858_8BIT, 0x4825, 0x3A}, /* lpx_p_min = 0x3A */ | |
648 | {OV8858_8BIT, 0x4826, 0x40}, /* hs_prepare_min = 0x40 */ | |
649 | {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ | |
650 | {OV8858_8BIT, 0x4850, 0x10}, /* LANE SEL01 */ | |
651 | {OV8858_8BIT, 0x4851, 0x32}, /* LANE SEL02 */ | |
652 | ||
653 | {OV8858_8BIT, 0x4B00, 0x2A}, /* Unknown */ | |
654 | {OV8858_8BIT, 0x4B0D, 0x00}, /* Unknown */ | |
655 | {OV8858_8BIT, 0x4D00, 0x04}, /* TPM_CTRL_REG */ | |
656 | {OV8858_8BIT, 0x4D01, 0x18}, /* TPM_CTRL_REG */ | |
657 | {OV8858_8BIT, 0x4D02, 0xC3}, /* TPM_CTRL_REG */ | |
658 | {OV8858_8BIT, 0x4D03, 0xFF}, /* TPM_CTRL_REG */ | |
659 | {OV8858_8BIT, 0x4D04, 0xFF}, /* TPM_CTRL_REG */ | |
660 | {OV8858_8BIT, 0x4D05, 0xFF}, /* TPM_CTRL_REG */ | |
661 | ||
662 | /* | |
663 | * Lens correction (LENC) function enable = 0 | |
664 | * Slave sensor AWB Gain function enable = 1 | |
665 | * Slave sensor AWB Statistics function enable = 1 | |
666 | * Master sensor AWB Gain function enable = 1 | |
667 | * Master sensor AWB Statistics function enable = 1 | |
668 | * Black DPC function enable = 1 | |
669 | * White DPC function enable =1 | |
670 | */ | |
671 | {OV8858_8BIT, 0x5000, 0x7E}, | |
672 | {OV8858_8BIT, 0x5001, 0x01}, /* BLC function enable = 1 */ | |
673 | /* | |
674 | * Horizontal scale function enable = 0 | |
675 | * WBMATCH bypass mode = Select slave sensor's gain | |
676 | * WBMATCH function enable = 0 | |
677 | * Master MWB gain support RGBC = 0 | |
678 | * OTP_DPC function enable = 1 | |
679 | * Manual mode of VarioPixel function enable = 0 | |
680 | * Manual enable of VarioPixel function enable = 0 | |
681 | * Use VSYNC to latch ISP modules's function enable signals = 0 | |
682 | */ | |
683 | {OV8858_8BIT, 0x5002, 0x08}, | |
684 | /* | |
685 | * Bypass all ISP modules after BLC module = 0 | |
686 | * DPC_DBC buffer control enable = 1 | |
687 | * WBMATCH VSYNC selection = Select master sensor's VSYNC fall | |
688 | * Select master AWB gain to embed line = AWB gain before manual mode | |
689 | * Enable BLC's input flip_i signal = 0 | |
690 | */ | |
691 | {OV8858_8BIT, 0x5003, 0x20}, | |
692 | {OV8858_8BIT, 0x5041, 0x1D}, /* ISP CTRL41 - embedded data=on */ | |
693 | {OV8858_8BIT, 0x5046, 0x12}, /* ISP CTRL46 = default */ | |
694 | /* | |
695 | * Tail enable = 1 | |
696 | * Saturate cross cluster enable = 1 | |
697 | * Remove cross cluster enable = 1 | |
698 | * Enable to remove connected defect pixels in same channel = 1 | |
699 | * Enable to remove connected defect pixels in different channel = 1 | |
700 | * Smooth enable, use average G for recovery = 1 | |
701 | * Black/white sensor mode enable = 0 | |
702 | * Manual mode enable = 0 | |
703 | */ | |
704 | {OV8858_8BIT, 0x5780, 0xFC}, | |
705 | {OV8858_8BIT, 0x5784, 0x0C}, /* DPC CTRL04 */ | |
706 | {OV8858_8BIT, 0x5787, 0x40}, /* DPC CTRL07 */ | |
707 | {OV8858_8BIT, 0x5788, 0x08}, /* DPC CTRL08 */ | |
708 | {OV8858_8BIT, 0x578A, 0x02}, /* DPC CTRL0A */ | |
709 | {OV8858_8BIT, 0x578B, 0x01}, /* DPC CTRL0B */ | |
710 | {OV8858_8BIT, 0x578C, 0x01}, /* DPC CTRL0C */ | |
711 | {OV8858_8BIT, 0x578E, 0x02}, /* DPC CTRL0E */ | |
712 | {OV8858_8BIT, 0x578F, 0x01}, /* DPC CTRL0F */ | |
713 | {OV8858_8BIT, 0x5790, 0x01}, /* DPC CTRL10 */ | |
714 | {OV8858_8BIT, 0x5901, 0x00}, /* VAP CTRL01 = default */ | |
715 | /* WINC CTRL08 = embedded data in 1st line*/ | |
716 | {OV8858_8BIT, 0x5A08, 0x00}, | |
717 | {OV8858_8BIT, 0x5B00, 0x02}, /* OTP CTRL00 */ | |
718 | {OV8858_8BIT, 0x5B01, 0x10}, /* OTP CTRL01 */ | |
719 | {OV8858_8BIT, 0x5B02, 0x03}, /* OTP CTRL02 */ | |
720 | {OV8858_8BIT, 0x5B03, 0xCF}, /* OTP CTRL03 */ | |
721 | {OV8858_8BIT, 0x5B05, 0x6C}, /* OTP CTRL05 = default */ | |
722 | {OV8858_8BIT, 0x5E00, 0x00}, /* PRE CTRL00 = default */ | |
723 | {OV8858_8BIT, 0x5E01, 0x41}, /* PRE_CTRL01 = default */ | |
724 | ||
725 | {OV8858_TOK_TERM, 0, 0} | |
726 | }; | |
727 | ||
728 | /*****************************STILL********************************/ | |
729 | ||
730 | static const struct ov8858_reg ov8858_8M[] = { | |
731 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
732 | {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ | |
733 | {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ | |
734 | {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ | |
735 | {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ | |
736 | {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ | |
737 | {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ | |
738 | {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low 3283 */ | |
739 | {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ | |
740 | {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ | |
741 | {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 2464 */ | |
742 | {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ | |
743 | {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ | |
744 | {OV8858_8BIT, 0x380B, 0xa0}, /* v_output_size low */ | |
745 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
746 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
747 | {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ | |
748 | {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ | |
749 | {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ | |
750 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
751 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
752 | {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ | |
753 | {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ | |
754 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
755 | {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ | |
756 | {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ | |
757 | {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ | |
758 | {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ | |
759 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
760 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
761 | {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ | |
762 | {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ | |
763 | {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ | |
764 | {OV8858_TOK_TERM, 0, 0} | |
765 | }; | |
766 | ||
767 | static const struct ov8858_reg ov8858_3276x1848[] = { | |
768 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
769 | {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ | |
770 | {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ | |
771 | {OV8858_8BIT, 0x3801, 0x10}, /* h_crop_start low 0c->10*/ | |
772 | {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ | |
773 | {OV8858_8BIT, 0x3803, 0x42}, /* v_crop_start low 3e->42*/ | |
774 | {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ | |
775 | {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ | |
776 | {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ | |
777 | {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ | |
778 | {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3276 x 1848 */ | |
779 | {OV8858_8BIT, 0x3809, 0xCC}, /* h_output_size low d0->cc*/ | |
780 | {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ | |
781 | {OV8858_8BIT, 0x380B, 0x38}, /* v_output_size low 3c->38*/ | |
782 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
783 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
784 | {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ | |
785 | {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ | |
786 | {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ | |
787 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
788 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
789 | {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ | |
790 | {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ | |
791 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
792 | {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ | |
793 | {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ | |
794 | {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ | |
795 | {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ | |
796 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
797 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
798 | {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ | |
799 | {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ | |
800 | {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ | |
801 | {OV8858_TOK_TERM, 0, 0} | |
802 | }; | |
803 | ||
804 | static const struct ov8858_reg ov8858_6M[] = { | |
805 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
806 | {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ | |
807 | {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ | |
808 | {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ | |
809 | {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ | |
810 | {OV8858_8BIT, 0x3803, 0x3E}, /* v_crop_start low */ | |
811 | {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ | |
812 | {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ | |
813 | {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ | |
814 | {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ | |
815 | {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 1852 */ | |
816 | {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ | |
817 | {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ | |
818 | {OV8858_8BIT, 0x380B, 0x3C}, /* v_output_size low */ | |
819 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
820 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
821 | {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ | |
822 | {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ | |
823 | {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ | |
824 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
825 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
826 | {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ | |
827 | {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ | |
828 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
829 | {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ | |
830 | {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ | |
831 | {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ | |
832 | {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ | |
833 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
834 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
835 | {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ | |
836 | {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ | |
837 | {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ | |
838 | {OV8858_TOK_TERM, 0, 0} | |
839 | }; | |
840 | ||
841 | static const struct ov8858_reg ov8858_1080P_60[] = { | |
842 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
843 | {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ | |
844 | {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ | |
845 | {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ | |
846 | {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ | |
847 | {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ | |
848 | {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ | |
849 | {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ | |
850 | {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ | |
851 | {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ | |
852 | {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ | |
853 | {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ | |
854 | {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ | |
855 | {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ | |
856 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
857 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
858 | {OV8858_8BIT, 0x380E, 0x04}, /* vertical timing size high */ | |
859 | {OV8858_8BIT, 0x380F, 0xEC}, /* vertical timing size low */ | |
860 | {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ | |
861 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
862 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
863 | {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ | |
864 | {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ | |
865 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
866 | {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ | |
867 | {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ | |
868 | {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ | |
869 | {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ | |
870 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
871 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
872 | {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ | |
873 | {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ | |
874 | {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ | |
875 | {OV8858_TOK_TERM, 0, 0} | |
876 | }; | |
877 | ||
878 | static const struct ov8858_reg ov8858_1080P_30[] = { | |
879 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
880 | {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ | |
881 | {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ | |
882 | {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ | |
883 | {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ | |
884 | {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ | |
885 | {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ | |
886 | {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ | |
887 | {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ | |
888 | {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ | |
889 | {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ | |
890 | {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ | |
891 | {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ | |
892 | {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ | |
893 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
894 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
895 | {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ | |
896 | {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ | |
897 | {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ | |
898 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
899 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
900 | {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ | |
901 | {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ | |
902 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
903 | {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ | |
904 | {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ | |
905 | {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ | |
906 | {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ | |
907 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
908 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
909 | {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ | |
910 | {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ | |
911 | {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ | |
912 | {OV8858_TOK_TERM, 0, 0} | |
913 | }; | |
914 | ||
915 | static const struct ov8858_reg ov8858_1640x1232[] = { | |
916 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
917 | {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ | |
918 | {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ | |
919 | {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ | |
920 | {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ | |
921 | {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ | |
922 | {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ | |
923 | {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ | |
924 | {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ | |
925 | {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ | |
926 | {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1232 */ | |
927 | {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ | |
928 | {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ | |
929 | {OV8858_8BIT, 0x380B, 0xD0}, /* v_output_size low */ | |
930 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
931 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
932 | {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ | |
933 | {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ | |
934 | {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ | |
935 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
936 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
937 | {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ | |
938 | {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ | |
939 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
940 | {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ | |
941 | {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ | |
942 | {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ | |
943 | {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ | |
944 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
945 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
946 | {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ | |
947 | {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ | |
948 | {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ | |
949 | {OV8858_TOK_TERM, 0, 0} | |
950 | }; | |
951 | ||
952 | static const struct ov8858_reg ov8858_1640x1096[] = { | |
953 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
954 | {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ | |
955 | {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ | |
956 | {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ | |
957 | {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ | |
958 | {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ | |
959 | {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ | |
960 | {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ | |
961 | {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ | |
962 | {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ | |
963 | {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1096 */ | |
964 | {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ | |
965 | {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ | |
966 | {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ | |
967 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
968 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
969 | {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ | |
970 | {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ | |
971 | {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ | |
972 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
973 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
974 | {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ | |
975 | {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ | |
976 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
977 | {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ | |
978 | {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ | |
979 | {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ | |
980 | {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ | |
981 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
982 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
983 | {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ | |
984 | {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ | |
985 | {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ | |
986 | {OV8858_TOK_TERM, 0, 0} | |
987 | }; | |
988 | ||
989 | ||
990 | static const struct ov8858_reg ov8858_1640x926[] = { | |
991 | {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ | |
992 | {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ | |
993 | {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ | |
994 | {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ | |
995 | {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ | |
996 | {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ | |
997 | {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ | |
998 | {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ | |
999 | {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ | |
1000 | {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ | |
1001 | {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 926 */ | |
1002 | {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ | |
1003 | {OV8858_8BIT, 0x380A, 0x03}, /* v_output_size high */ | |
1004 | {OV8858_8BIT, 0x380B, 0x9E}, /* v_output_size low */ | |
1005 | {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ | |
1006 | {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ | |
1007 | {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ | |
1008 | {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ | |
1009 | {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ | |
1010 | {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ | |
1011 | {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ | |
1012 | {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ | |
1013 | {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ | |
1014 | {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ | |
1015 | {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ | |
1016 | {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ | |
1017 | {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ | |
1018 | {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ | |
1019 | {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ | |
1020 | {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ | |
1021 | {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ | |
1022 | {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ | |
1023 | {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ | |
1024 | {OV8858_TOK_TERM, 0, 0} | |
1025 | }; | |
1026 | ||
1027 | static struct ov8858_resolution ov8858_res_preview[] = { | |
1028 | { | |
1029 | .desc = "ov8858_1640x926_PREVIEW", | |
1030 | .width = 1640, | |
1031 | .height = 926, | |
1032 | .used = 0, | |
1033 | .regs = ov8858_1640x926, | |
1034 | .bin_factor_x = 0, | |
1035 | .bin_factor_y = 0, | |
1036 | .skip_frames = 0, | |
1037 | .fps_options = { | |
1038 | { | |
1039 | .fps = 30, | |
1040 | .pixels_per_line = 3880, | |
1041 | .lines_per_frame = 2573, | |
1042 | }, | |
1043 | { | |
1044 | } | |
1045 | }, | |
1046 | }, | |
1047 | { | |
1048 | .desc = "ov8858_1640x1232_PREVIEW", | |
1049 | .width = 1640, | |
1050 | .height = 1232, | |
1051 | .used = 0, | |
1052 | .regs = ov8858_1640x1232, | |
1053 | .bin_factor_x = 0, | |
1054 | .bin_factor_y = 0, | |
1055 | .skip_frames = 0, | |
1056 | .fps_options = { | |
1057 | { | |
1058 | .fps = 30, | |
1059 | .pixels_per_line = 3880, | |
1060 | .lines_per_frame = 2573, | |
1061 | }, | |
1062 | { | |
1063 | } | |
1064 | }, | |
1065 | }, | |
1066 | { | |
1067 | .desc = "ov8858_1936x1096_PREVIEW", | |
1068 | .width = 1936, | |
1069 | .height = 1096, | |
1070 | .used = 0, | |
1071 | .regs = ov8858_1080P_30, | |
1072 | .bin_factor_x = 0, | |
1073 | .bin_factor_y = 0, | |
1074 | .skip_frames = 0, | |
1075 | .fps_options = { | |
1076 | { | |
1077 | .fps = 30, | |
1078 | .pixels_per_line = 3880, | |
1079 | .lines_per_frame = 2573, | |
1080 | }, | |
1081 | { | |
1082 | } | |
1083 | }, | |
1084 | }, | |
1085 | { | |
1086 | .desc = "ov8858_3276x1848_PREVIEW", | |
1087 | .width = 3276, | |
1088 | .height = 1848, | |
1089 | .used = 0, | |
1090 | .regs = ov8858_3276x1848, | |
1091 | .bin_factor_x = 0, | |
1092 | .bin_factor_y = 0, | |
1093 | .skip_frames = 0, | |
1094 | .fps_options = { | |
1095 | { | |
1096 | .fps = 30, | |
1097 | .pixels_per_line = 3880, | |
1098 | .lines_per_frame = 2573, | |
1099 | }, | |
1100 | { | |
1101 | } | |
1102 | }, | |
1103 | }, | |
1104 | { | |
1105 | .desc = "ov8858_8M_PREVIEW", | |
1106 | .width = 3280, | |
1107 | .height = 2464, | |
1108 | .used = 0, | |
1109 | .regs = ov8858_8M, | |
1110 | .bin_factor_x = 0, | |
1111 | .bin_factor_y = 0, | |
1112 | .skip_frames = 0, | |
1113 | .fps_options = { | |
1114 | { | |
1115 | .fps = 30, | |
1116 | .pixels_per_line = 3880, | |
1117 | .lines_per_frame = 2573, | |
1118 | }, | |
1119 | { | |
1120 | } | |
1121 | }, | |
1122 | }, | |
1123 | }; | |
1124 | ||
1125 | static struct ov8858_resolution ov8858_res_still[] = { | |
1126 | { | |
1127 | .desc = "ov8858_1640x1232_STILL", | |
1128 | .width = 1640, | |
1129 | .height = 1232, | |
1130 | .used = 0, | |
1131 | .regs = ov8858_1640x1232, | |
1132 | .bin_factor_x = 0, | |
1133 | .bin_factor_y = 0, | |
1134 | .skip_frames = 0, | |
1135 | .fps_options = { | |
1136 | { | |
1137 | .fps = 30, | |
1138 | .pixels_per_line = 3880, | |
1139 | .lines_per_frame = 2573, | |
1140 | }, | |
1141 | { | |
1142 | } | |
1143 | }, | |
1144 | }, | |
1145 | { | |
1146 | .desc = "ov8858_1640x926_STILL", | |
1147 | .width = 1640, | |
1148 | .height = 926, | |
1149 | .used = 0, | |
1150 | .regs = ov8858_1640x926, | |
1151 | .bin_factor_x = 0, | |
1152 | .bin_factor_y = 0, | |
1153 | .skip_frames = 1, | |
1154 | .fps_options = { | |
1155 | { | |
1156 | .fps = 30, | |
1157 | .pixels_per_line = 3880, | |
1158 | .lines_per_frame = 2573, | |
1159 | }, | |
1160 | { | |
1161 | } | |
1162 | }, | |
1163 | }, | |
1164 | { | |
1165 | .desc = "ov8858_3276X1848_STILL", | |
1166 | .width = 3276, | |
1167 | .height = 1848, | |
1168 | .used = 0, | |
1169 | .regs = ov8858_3276x1848, | |
1170 | .bin_factor_x = 0, | |
1171 | .bin_factor_y = 0, | |
1172 | .skip_frames = 1, | |
1173 | .fps_options = { | |
1174 | { | |
1175 | .fps = 30, | |
1176 | .pixels_per_line = 3880, | |
1177 | .lines_per_frame = 2573, | |
1178 | }, | |
1179 | { | |
1180 | } | |
1181 | }, | |
1182 | }, | |
1183 | { | |
1184 | .desc = "ov8858_8M_STILL", | |
1185 | .width = 3280, | |
1186 | .height = 2464, | |
1187 | .used = 0, | |
1188 | .regs = ov8858_8M, | |
1189 | .bin_factor_x = 0, | |
1190 | .bin_factor_y = 0, | |
1191 | .skip_frames = 1, | |
1192 | .fps_options = { | |
1193 | { | |
1194 | /* Pixel clock: 149.76MHZ */ | |
1195 | .fps = 10, | |
1196 | .pixels_per_line = 3880, | |
1197 | .lines_per_frame = 3859, | |
1198 | }, | |
1199 | { | |
1200 | } | |
1201 | }, | |
1202 | }, | |
1203 | }; | |
1204 | ||
1205 | static struct ov8858_resolution ov8858_res_video[] = { | |
1206 | { | |
1207 | .desc = "ov8858_1640x926_VIDEO", | |
1208 | .width = 1640, | |
1209 | .height = 926, | |
1210 | .used = 0, | |
1211 | .regs = ov8858_1640x926, | |
1212 | .bin_factor_x = 0, | |
1213 | .bin_factor_y = 0, | |
1214 | .skip_frames = 1, | |
1215 | .fps_options = { | |
1216 | { | |
1217 | .fps = 30, | |
1218 | .pixels_per_line = 3880, | |
1219 | .lines_per_frame = 2573, | |
1220 | }, | |
1221 | { | |
1222 | } | |
1223 | }, | |
1224 | }, | |
1225 | { | |
1226 | .desc = "ov8858_1640x1232_VIDEO", | |
1227 | .width = 1640, | |
1228 | .height = 1232, | |
1229 | .used = 0, | |
1230 | .regs = ov8858_1640x1232, | |
1231 | .bin_factor_x = 0, | |
1232 | .bin_factor_y = 0, | |
1233 | .skip_frames = 1, | |
1234 | .fps_options = { | |
1235 | { | |
1236 | .fps = 30, | |
1237 | .pixels_per_line = 3880, | |
1238 | .lines_per_frame = 2573, | |
1239 | }, | |
1240 | { | |
1241 | } | |
1242 | }, | |
1243 | }, | |
1244 | { | |
1245 | .desc = "ov8858_1640x1096_VIDEO", | |
1246 | .width = 1640, | |
1247 | .height = 1096, | |
1248 | .used = 0, | |
1249 | .regs = ov8858_1640x1096, | |
1250 | .bin_factor_x = 0, | |
1251 | .bin_factor_y = 0, | |
1252 | .skip_frames = 1, | |
1253 | .fps_options = { | |
1254 | { | |
1255 | .fps = 30, | |
1256 | .pixels_per_line = 3880, | |
1257 | .lines_per_frame = 2573, | |
1258 | }, | |
1259 | { | |
1260 | } | |
1261 | }, | |
1262 | }, | |
1263 | { | |
1264 | .desc = "ov8858_1080P_30_VIDEO", | |
1265 | .width = 1936, | |
1266 | .height = 1096, | |
1267 | .used = 0, | |
1268 | .regs = ov8858_1080P_30, | |
1269 | .bin_factor_x = 0, | |
1270 | .bin_factor_y = 0, | |
1271 | .skip_frames = 1, | |
1272 | .fps_options = { | |
1273 | { | |
1274 | .fps = 30, | |
1275 | .pixels_per_line = 3880, | |
1276 | .lines_per_frame = 2573, | |
1277 | }, | |
1278 | { | |
1279 | } | |
1280 | }, | |
1281 | }, | |
1282 | }; | |
1283 | ||
1284 | #endif /* __OV8858_H__ */ |