Commit | Line | Data |
---|---|---|
b8d181e4 PZ |
1 | /* |
2 | * i.MX IPUv3 DP Overlay Planes | |
3 | * | |
4 | * Copyright (C) 2013 Philipp Zabel, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <drm/drmP.h> | |
17 | #include <drm/drm_fb_cma_helper.h> | |
18 | #include <drm/drm_gem_cma_helper.h> | |
19 | ||
39b9004d | 20 | #include "video/imx-ipu-v3.h" |
b8d181e4 PZ |
21 | #include "ipuv3-plane.h" |
22 | ||
23 | #define to_ipu_plane(x) container_of(x, struct ipu_plane, base) | |
24 | ||
25 | static const uint32_t ipu_plane_formats[] = { | |
26 | DRM_FORMAT_XRGB1555, | |
27 | DRM_FORMAT_XBGR1555, | |
28 | DRM_FORMAT_ARGB8888, | |
29 | DRM_FORMAT_XRGB8888, | |
30 | DRM_FORMAT_ABGR8888, | |
31 | DRM_FORMAT_XBGR8888, | |
32 | DRM_FORMAT_YUYV, | |
33 | DRM_FORMAT_YVYU, | |
34 | DRM_FORMAT_YUV420, | |
35 | DRM_FORMAT_YVU420, | |
36 | }; | |
37 | ||
38 | int ipu_plane_irq(struct ipu_plane *ipu_plane) | |
39 | { | |
40 | return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch, | |
41 | IPU_IRQ_EOF); | |
42 | } | |
43 | ||
44 | static int calc_vref(struct drm_display_mode *mode) | |
45 | { | |
46 | unsigned long htotal, vtotal; | |
47 | ||
48 | htotal = mode->htotal; | |
49 | vtotal = mode->vtotal; | |
50 | ||
51 | if (!htotal || !vtotal) | |
52 | return 60; | |
53 | ||
54 | return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal); | |
55 | } | |
56 | ||
57 | static inline int calc_bandwidth(int width, int height, unsigned int vref) | |
58 | { | |
59 | return width * height * vref; | |
60 | } | |
61 | ||
62 | int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb, | |
63 | int x, int y) | |
64 | { | |
b8d181e4 | 65 | struct drm_gem_cma_object *cma_obj; |
ee2e072e | 66 | unsigned long eba; |
356f9524 | 67 | int active; |
b8d181e4 PZ |
68 | |
69 | cma_obj = drm_fb_cma_get_gem_obj(fb, 0); | |
70 | if (!cma_obj) { | |
38821e64 | 71 | DRM_DEBUG_KMS("entry is null.\n"); |
b8d181e4 PZ |
72 | return -EFAULT; |
73 | } | |
74 | ||
18589738 FE |
75 | dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d", |
76 | &cma_obj->paddr, x, y); | |
b8d181e4 | 77 | |
bc2b067a LS |
78 | eba = cma_obj->paddr + fb->offsets[0] + |
79 | fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x; | |
356f9524 PZ |
80 | |
81 | if (ipu_plane->enabled) { | |
82 | active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); | |
83 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba); | |
84 | ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active); | |
85 | } else { | |
86 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba); | |
87 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba); | |
88 | } | |
b8d181e4 | 89 | |
32f71106 LS |
90 | /* cache offsets for subsequent pageflips */ |
91 | ipu_plane->x = x; | |
92 | ipu_plane->y = y; | |
93 | ||
b8d181e4 PZ |
94 | return 0; |
95 | } | |
96 | ||
97 | int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc, | |
98 | struct drm_display_mode *mode, | |
99 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
100 | unsigned int crtc_w, unsigned int crtc_h, | |
101 | uint32_t src_x, uint32_t src_y, | |
102 | uint32_t src_w, uint32_t src_h) | |
103 | { | |
b8d181e4 PZ |
104 | struct device *dev = ipu_plane->base.dev->dev; |
105 | int ret; | |
106 | ||
107 | /* no scaling */ | |
108 | if (src_w != crtc_w || src_h != crtc_h) | |
109 | return -EINVAL; | |
110 | ||
111 | /* clip to crtc bounds */ | |
112 | if (crtc_x < 0) { | |
113 | if (-crtc_x > crtc_w) | |
114 | return -EINVAL; | |
115 | src_x += -crtc_x; | |
116 | src_w -= -crtc_x; | |
117 | crtc_w -= -crtc_x; | |
118 | crtc_x = 0; | |
119 | } | |
120 | if (crtc_y < 0) { | |
121 | if (-crtc_y > crtc_h) | |
122 | return -EINVAL; | |
123 | src_y += -crtc_y; | |
124 | src_h -= -crtc_y; | |
125 | crtc_h -= -crtc_y; | |
126 | crtc_y = 0; | |
127 | } | |
128 | if (crtc_x + crtc_w > mode->hdisplay) { | |
129 | if (crtc_x > mode->hdisplay) | |
130 | return -EINVAL; | |
131 | crtc_w = mode->hdisplay - crtc_x; | |
132 | src_w = crtc_w; | |
133 | } | |
134 | if (crtc_y + crtc_h > mode->vdisplay) { | |
135 | if (crtc_y > mode->vdisplay) | |
136 | return -EINVAL; | |
137 | crtc_h = mode->vdisplay - crtc_y; | |
138 | src_h = crtc_h; | |
139 | } | |
140 | /* full plane minimum width is 13 pixels */ | |
141 | if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG)) | |
142 | return -EINVAL; | |
143 | if (crtc_h < 2) | |
144 | return -EINVAL; | |
145 | ||
146 | switch (ipu_plane->dp_flow) { | |
147 | case IPU_DP_FLOW_SYNC_BG: | |
148 | ret = ipu_dp_setup_channel(ipu_plane->dp, | |
149 | IPUV3_COLORSPACE_RGB, | |
150 | IPUV3_COLORSPACE_RGB); | |
151 | if (ret) { | |
152 | dev_err(dev, | |
153 | "initializing display processor failed with %d\n", | |
154 | ret); | |
155 | return ret; | |
156 | } | |
e6245fc7 | 157 | ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); |
b8d181e4 PZ |
158 | break; |
159 | case IPU_DP_FLOW_SYNC_FG: | |
160 | ipu_dp_setup_channel(ipu_plane->dp, | |
161 | ipu_drm_fourcc_to_colorspace(fb->pixel_format), | |
162 | IPUV3_COLORSPACE_UNKNOWN); | |
163 | ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y); | |
e6245fc7 PZ |
164 | /* Enable local alpha on partial plane */ |
165 | switch (fb->pixel_format) { | |
166 | case DRM_FORMAT_ARGB8888: | |
167 | case DRM_FORMAT_ABGR8888: | |
168 | ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false); | |
169 | break; | |
170 | default: | |
171 | break; | |
172 | } | |
b8d181e4 PZ |
173 | } |
174 | ||
175 | ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w); | |
176 | if (ret) { | |
177 | dev_err(dev, "initializing dmfc channel failed with %d\n", ret); | |
178 | return ret; | |
179 | } | |
180 | ||
181 | ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc, | |
182 | calc_bandwidth(crtc_w, crtc_h, | |
183 | calc_vref(mode)), 64); | |
184 | if (ret) { | |
185 | dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret); | |
186 | return ret; | |
187 | } | |
188 | ||
2eb671c4 SL |
189 | ipu_cpmem_zero(ipu_plane->ipu_ch); |
190 | ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h); | |
191 | ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format); | |
b8d181e4 PZ |
192 | if (ret < 0) { |
193 | dev_err(dev, "unsupported pixel format 0x%08x\n", | |
194 | fb->pixel_format); | |
195 | return ret; | |
196 | } | |
197 | ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); | |
356f9524 | 198 | ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); |
7cd9bebe | 199 | ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]); |
b8d181e4 PZ |
200 | |
201 | ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y); | |
202 | if (ret < 0) | |
203 | return ret; | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | void ipu_plane_put_resources(struct ipu_plane *ipu_plane) | |
209 | { | |
210 | if (!IS_ERR_OR_NULL(ipu_plane->dp)) | |
211 | ipu_dp_put(ipu_plane->dp); | |
212 | if (!IS_ERR_OR_NULL(ipu_plane->dmfc)) | |
213 | ipu_dmfc_put(ipu_plane->dmfc); | |
214 | if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch)) | |
215 | ipu_idmac_put(ipu_plane->ipu_ch); | |
216 | } | |
217 | ||
218 | int ipu_plane_get_resources(struct ipu_plane *ipu_plane) | |
219 | { | |
220 | int ret; | |
221 | ||
222 | ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma); | |
223 | if (IS_ERR(ipu_plane->ipu_ch)) { | |
224 | ret = PTR_ERR(ipu_plane->ipu_ch); | |
225 | DRM_ERROR("failed to get idmac channel: %d\n", ret); | |
226 | return ret; | |
227 | } | |
228 | ||
229 | ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma); | |
230 | if (IS_ERR(ipu_plane->dmfc)) { | |
231 | ret = PTR_ERR(ipu_plane->dmfc); | |
232 | DRM_ERROR("failed to get dmfc: ret %d\n", ret); | |
233 | goto err_out; | |
234 | } | |
235 | ||
236 | if (ipu_plane->dp_flow >= 0) { | |
237 | ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow); | |
238 | if (IS_ERR(ipu_plane->dp)) { | |
239 | ret = PTR_ERR(ipu_plane->dp); | |
240 | DRM_ERROR("failed to get dp flow: %d\n", ret); | |
241 | goto err_out; | |
242 | } | |
243 | } | |
244 | ||
245 | return 0; | |
246 | err_out: | |
247 | ipu_plane_put_resources(ipu_plane); | |
248 | ||
249 | return ret; | |
250 | } | |
251 | ||
252 | void ipu_plane_enable(struct ipu_plane *ipu_plane) | |
253 | { | |
285bbb01 PZ |
254 | if (ipu_plane->dp) |
255 | ipu_dp_enable(ipu_plane->ipu); | |
b8d181e4 PZ |
256 | ipu_dmfc_enable_channel(ipu_plane->dmfc); |
257 | ipu_idmac_enable_channel(ipu_plane->ipu_ch); | |
258 | if (ipu_plane->dp) | |
259 | ipu_dp_enable_channel(ipu_plane->dp); | |
260 | ||
261 | ipu_plane->enabled = true; | |
262 | } | |
263 | ||
264 | void ipu_plane_disable(struct ipu_plane *ipu_plane) | |
265 | { | |
266 | ipu_plane->enabled = false; | |
267 | ||
268 | ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50); | |
269 | ||
270 | if (ipu_plane->dp) | |
271 | ipu_dp_disable_channel(ipu_plane->dp); | |
272 | ipu_idmac_disable_channel(ipu_plane->ipu_ch); | |
273 | ipu_dmfc_disable_channel(ipu_plane->dmfc); | |
285bbb01 PZ |
274 | if (ipu_plane->dp) |
275 | ipu_dp_disable(ipu_plane->ipu); | |
b8d181e4 PZ |
276 | } |
277 | ||
b8d181e4 PZ |
278 | /* |
279 | * drm_plane API | |
280 | */ | |
281 | ||
282 | static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
283 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
284 | unsigned int crtc_w, unsigned int crtc_h, | |
285 | uint32_t src_x, uint32_t src_y, | |
286 | uint32_t src_w, uint32_t src_h) | |
287 | { | |
288 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); | |
289 | int ret = 0; | |
290 | ||
291 | DRM_DEBUG_KMS("plane - %p\n", plane); | |
292 | ||
293 | if (!ipu_plane->enabled) | |
294 | ret = ipu_plane_get_resources(ipu_plane); | |
295 | if (ret < 0) | |
296 | return ret; | |
297 | ||
298 | ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb, | |
299 | crtc_x, crtc_y, crtc_w, crtc_h, | |
300 | src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16); | |
301 | if (ret < 0) { | |
302 | ipu_plane_put_resources(ipu_plane); | |
303 | return ret; | |
304 | } | |
305 | ||
306 | if (crtc != plane->crtc) | |
307 | dev_info(plane->dev->dev, "crtc change: %p -> %p\n", | |
308 | plane->crtc, crtc); | |
309 | plane->crtc = crtc; | |
310 | ||
b46355f0 SG |
311 | if (!ipu_plane->enabled) |
312 | ipu_plane_enable(ipu_plane); | |
b8d181e4 PZ |
313 | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int ipu_disable_plane(struct drm_plane *plane) | |
318 | { | |
319 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); | |
320 | ||
321 | DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); | |
322 | ||
b46355f0 SG |
323 | if (ipu_plane->enabled) |
324 | ipu_plane_disable(ipu_plane); | |
b8d181e4 PZ |
325 | |
326 | ipu_plane_put_resources(ipu_plane); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | static void ipu_plane_destroy(struct drm_plane *plane) | |
332 | { | |
333 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); | |
334 | ||
335 | DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); | |
336 | ||
337 | ipu_disable_plane(plane); | |
338 | drm_plane_cleanup(plane); | |
339 | kfree(ipu_plane); | |
340 | } | |
341 | ||
342 | static struct drm_plane_funcs ipu_plane_funcs = { | |
343 | .update_plane = ipu_update_plane, | |
344 | .disable_plane = ipu_disable_plane, | |
345 | .destroy = ipu_plane_destroy, | |
346 | }; | |
347 | ||
348 | struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, | |
349 | int dma, int dp, unsigned int possible_crtcs, | |
350 | bool priv) | |
351 | { | |
352 | struct ipu_plane *ipu_plane; | |
353 | int ret; | |
354 | ||
355 | DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n", | |
356 | dma, dp, possible_crtcs); | |
357 | ||
358 | ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL); | |
359 | if (!ipu_plane) { | |
360 | DRM_ERROR("failed to allocate plane\n"); | |
361 | return ERR_PTR(-ENOMEM); | |
362 | } | |
363 | ||
364 | ipu_plane->ipu = ipu; | |
365 | ipu_plane->dma = dma; | |
366 | ipu_plane->dp_flow = dp; | |
367 | ||
368 | ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs, | |
369 | &ipu_plane_funcs, ipu_plane_formats, | |
370 | ARRAY_SIZE(ipu_plane_formats), | |
371 | priv); | |
372 | if (ret) { | |
373 | DRM_ERROR("failed to initialize plane\n"); | |
374 | kfree(ipu_plane); | |
375 | return ERR_PTR(ret); | |
376 | } | |
377 | ||
378 | return ipu_plane; | |
379 | } |