[linux-2.6-block.git] / drivers / staging / imx-drm / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/component.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include <video/imx-ipu-v3.h>
#include "imx-drm.h"
#include "ipuv3-plane.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;

	/* plane[0] is the full plane, plane[1] is the partial plane */
	struct ipu_plane	*plane[2];

	struct ipu_dc		*dc;
	struct ipu_di		*di;
	int			enabled;
	struct drm_pending_vblank_event *page_flip_event;
	struct drm_framebuffer	*newfb;
	int			irq;
	u32			interface_pix_fmt;
	unsigned long		di_clkflags;
	int			di_hsync_pin;
	int			di_vsync_pin;
};

#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)

static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
{
	if (ipu_crtc->enabled)
		return;

	ipu_di_enable(ipu_crtc->di);
	ipu_dc_enable_channel(ipu_crtc->dc);
	ipu_plane_enable(ipu_crtc->plane[0]);

	ipu_crtc->enabled = 1;
}

static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
{
	if (!ipu_crtc->enabled)
		return;

	ipu_plane_disable(ipu_crtc->plane[0]);
	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_di_disable(ipu_crtc->di);

	ipu_crtc->enabled = 0;
}

static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);

	switch (mode) {
	case DRM_MODE_DPMS_ON:
		ipu_fb_enable(ipu_crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
		ipu_fb_disable(ipu_crtc);
		break;
	}
}

static int ipu_page_flip(struct drm_crtc *crtc,
		struct drm_framebuffer *fb,
		struct drm_pending_vblank_event *event,
		uint32_t page_flip_flags)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	int ret;

	if (ipu_crtc->newfb)
		return -EBUSY;

	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	if (ret) {
		dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
		list_del(&event->base.link);

		return ret;
	}

	ipu_crtc->newfb = fb;
	ipu_crtc->page_flip_event = event;
	crtc->primary->fb = fb;

	return 0;
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_crtc_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = ipu_page_flip,
};

static int ipu_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *orig_mode,
			       struct drm_display_mode *mode,
			       int x, int y,
			       struct drm_framebuffer *old_fb)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	int ret;
	struct ipu_di_signal_cfg sig_cfg = {};
	u32 out_pixel_fmt;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	out_pixel_fmt = ipu_crtc->interface_pix_fmt;

	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		sig_cfg.interlaced = 1;
	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
		sig_cfg.Hsync_pol = 1;
	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
		sig_cfg.Vsync_pol = 1;

	sig_cfg.enable_pol = 1;
	sig_cfg.clk_pol = 1;
	sig_cfg.width = mode->hdisplay;
	sig_cfg.height = mode->vdisplay;
	sig_cfg.pixel_fmt = out_pixel_fmt;
	sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
	sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
	sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;

	sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
	sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
	sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
	sig_cfg.pixelclock = mode->clock * 1000;
	sig_cfg.clkflags = ipu_crtc->di_clkflags;

	sig_cfg.v_to_h_sync = 0;

	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;

	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
			out_pixel_fmt, mode->hdisplay);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing display controller failed with %d\n",
				ret);
		return ret;
	}

	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing panel failed with %d\n", ret);
		return ret;
	}

	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode, crtc->primary->fb,
				  0, 0, mode->hdisplay, mode->vdisplay,
				  x, y, mode->hdisplay, mode->vdisplay);
}

static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
{
	unsigned long flags;
	struct drm_device *drm = ipu_crtc->base.dev;

	spin_lock_irqsave(&drm->event_lock, flags);
	if (ipu_crtc->page_flip_event)
		drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
	ipu_crtc->page_flip_event = NULL;
	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
	spin_unlock_irqrestore(&drm->event_lock, flags);
}

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	if (ipu_crtc->newfb) {
		ipu_crtc->newfb = NULL;
		ipu_plane_set_base(ipu_crtc->plane[0], ipu_crtc->base.primary->fb,
				ipu_crtc->plane[0]->x, ipu_crtc->plane[0]->y);
		ipu_crtc_handle_pageflip(ipu_crtc);
	}

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void ipu_crtc_prepare(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_disable(ipu_crtc);
}

static void ipu_crtc_commit(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_enable(ipu_crtc);
}

static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.dpms = ipu_crtc_dpms,
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set = ipu_crtc_mode_set,
	.prepare = ipu_crtc_prepare,
	.commit = ipu_crtc_commit,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->page_flip_event = NULL;
	ipu_crtc->newfb = NULL;
}

static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
		u32 pixfmt, int hsync_pin, int vsync_pin)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->interface_pix_fmt = pixfmt;
	ipu_crtc->di_hsync_pin = hsync_pin;
	ipu_crtc->di_vsync_pin = vsync_pin;

	switch (encoder_type) {
	case DRM_MODE_ENCODER_DAC:
	case DRM_MODE_ENCODER_TVDAC:
	case DRM_MODE_ENCODER_LVDS:
		ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC |
			IPU_DI_CLKMODE_EXT;
		break;
	case DRM_MODE_ENCODER_TMDS:
	case DRM_MODE_ENCODER_NONE:
		ipu_crtc->di_clkflags = 0;
		break;
	}

	return 0;
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
		ipu_dc_put(ipu_crtc->dc);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int dp = -EINVAL;
	int ret;
	int id;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
			&ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	if (pdata->dp >= 0)
		dp = IPU_DP_FLOW_SYNC_BG;
	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
					    pdata->dma[0], dp, BIT(id), true);
	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
			ret);
		goto err_remove_crtc;
	}

	/* If this crtc is using the DP, add an overlay plane */
	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
		ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
						    pdata->dma[1],
						    IPU_DP_FLOW_SYNC_FG,
						    BIT(id), false);
		if (IS_ERR(ipu_crtc->plane[1]))
			ipu_crtc->plane[1] = NULL;
	}

	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_plane_res;
	}

	return 0;

err_put_plane_res:
	ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static struct device_node *ipu_drm_get_port_by_id(struct device_node *parent,
						  int port_id)
{
	struct device_node *port;
	int id, ret;

	port = of_get_child_by_name(parent, "port");
	while (port) {
		ret = of_property_read_u32(port, "reg", &id);
		if (!ret && id == port_id)
			return port;

		do {
			port = of_get_next_child(parent, port);
			if (!port)
				return NULL;
		} while (of_node_cmp(port->name, "port"));
	}

	return NULL;
}

static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
	struct ipu_client_platformdata *pdata = dev->platform_data;
	struct drm_device *drm = data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = dev;

	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
	if (ret)
		return ret;

	dev_set_drvdata(dev, ipu_crtc);

	return 0;
}

static void ipu_drm_unbind(struct device *dev, struct device *master,
	void *data)
{
	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_plane_put_resources(ipu_crtc->plane[0]);
	ipu_put_resources(ipu_crtc);
}

static const struct component_ops ipu_crtc_ops = {
	.bind = ipu_drm_bind,
	.unbind = ipu_drm_unbind,
};

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ipu_client_platformdata *pdata = dev->platform_data;
	int ret;

	if (!dev->platform_data)
		return -EINVAL;

	if (!dev->of_node) {
		/* Associate crtc device with the corresponding DI port node */
		dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node,
						      pdata->di + 2);
		if (!dev->of_node) {
			dev_err(dev, "missing port@%d node in %s\n",
				pdata->di + 2, dev->parent->of_node->full_name);
			return -ENODEV;
		}
	}

	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	return component_add(dev, &ipu_crtc_ops);
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &ipu_crtc_ops);
	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ipuv3-crtc");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	18	* MA 02110-1301, USA.
	19	*/
17b5001b	20	#include <linux/component.h>
f326f799 SH	21	#include <linux/module.h>
	22	#include <linux/export.h>
	23	#include <linux/device.h>
	24	#include <linux/platform_device.h>
	25	#include <drm/drmP.h>
f326f799 SH	26	#include <drm/drm_crtc_helper.h>
	27	#include <linux/fb.h>
	28	#include <linux/clk.h>
b8d181e4	29	#include <linux/errno.h>
f326f799 SH	30	#include <drm/drm_gem_cma_helper.h>
	31	#include <drm/drm_fb_cma_helper.h>
	32
39b9004d	33	#include <video/imx-ipu-v3.h>
f326f799	34	#include "imx-drm.h"
b8d181e4	35	#include "ipuv3-plane.h"
f326f799 SH	36
	37	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	38
f326f799	39	struct ipu_crtc {
f326f799 SH	40	struct device *dev;
	41	struct drm_crtc base;
	42	struct imx_drm_crtc *imx_crtc;
b8d181e4 PZ	43
	44	/* plane[0] is the full plane, plane[1] is the partial plane */
	45	struct ipu_plane *plane[2];
	46
f326f799	47	struct ipu_dc *dc;
f326f799 SH	48	struct ipu_di *di;
f326f799 SH	49	int enabled;
f326f799 SH	50	struct drm_pending_vblank_event *page_flip_event;
	51	struct drm_framebuffer *newfb;
	52	int irq;
	53	u32 interface_pix_fmt;
	54	unsigned long di_clkflags;
2ea42608 PZ	55	int di_hsync_pin;
2ea42608 PZ	56	int di_vsync_pin;
f326f799 SH	57	};
	58
	59	#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
	60
f326f799 SH	61	static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
	62	{
	63	if (ipu_crtc->enabled)
	64	return;
	65
	66	ipu_di_enable(ipu_crtc->di);
f326f799	67	ipu_dc_enable_channel(ipu_crtc->dc);
b8d181e4	68	ipu_plane_enable(ipu_crtc->plane[0]);
f326f799 SH	69
	70	ipu_crtc->enabled = 1;
	71	}
	72
	73	static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
	74	{
	75	if (!ipu_crtc->enabled)
	76	return;
	77
b8d181e4	78	ipu_plane_disable(ipu_crtc->plane[0]);
f326f799	79	ipu_dc_disable_channel(ipu_crtc->dc);
f326f799 SH	80	ipu_di_disable(ipu_crtc->di);
	81
	82	ipu_crtc->enabled = 0;
	83	}
	84
	85	static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
	86	{
	87	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	88
a8e4e232	89	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
f326f799 SH	90
	91	switch (mode) {
	92	case DRM_MODE_DPMS_ON:
	93	ipu_fb_enable(ipu_crtc);
	94	break;
	95	case DRM_MODE_DPMS_STANDBY:
	96	case DRM_MODE_DPMS_SUSPEND:
	97	case DRM_MODE_DPMS_OFF:
	98	ipu_fb_disable(ipu_crtc);
	99	break;
	100	}
	101	}
	102
	103	static int ipu_page_flip(struct drm_crtc *crtc,
	104	struct drm_framebuffer *fb,
ed8d1975 KP	105	struct drm_pending_vblank_event *event,
ed8d1975 KP	106	uint32_t page_flip_flags)
f326f799 SH	107	{
	108	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	109	int ret;
	110
	111	if (ipu_crtc->newfb)
	112	return -EBUSY;
	113
	114	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	115	if (ret) {
	116	dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
	117	list_del(&event->base.link);
	118
	119	return ret;
	120	}
	121
	122	ipu_crtc->newfb = fb;
	123	ipu_crtc->page_flip_event = event;
f4510a27	124	crtc->primary->fb = fb;
f326f799 SH	125
	126	return 0;
	127	}
	128
	129	static const struct drm_crtc_funcs ipu_crtc_funcs = {
	130	.set_config = drm_crtc_helper_set_config,
	131	.destroy = drm_crtc_cleanup,
	132	.page_flip = ipu_page_flip,
	133	};
	134
f326f799 SH	135	static int ipu_crtc_mode_set(struct drm_crtc *crtc,
	136	struct drm_display_mode *orig_mode,
	137	struct drm_display_mode *mode,
	138	int x, int y,
	139	struct drm_framebuffer *old_fb)
	140	{
	141	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
f326f799 SH	142	int ret;
	143	struct ipu_di_signal_cfg sig_cfg = {};
	144	u32 out_pixel_fmt;
f326f799 SH	145
	146	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
	147	mode->hdisplay);
	148	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
	149	mode->vdisplay);
	150
f326f799 SH	151	out_pixel_fmt = ipu_crtc->interface_pix_fmt;
	152
	153	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
	154	sig_cfg.interlaced = 1;
	155	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
	156	sig_cfg.Hsync_pol = 1;
	157	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
	158	sig_cfg.Vsync_pol = 1;
	159
	160	sig_cfg.enable_pol = 1;
f0ac9beb	161	sig_cfg.clk_pol = 1;
f326f799 SH	162	sig_cfg.width = mode->hdisplay;
	163	sig_cfg.height = mode->vdisplay;
	164	sig_cfg.pixel_fmt = out_pixel_fmt;
	165	sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
	166	sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
	167	sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;
	168
	169	sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
	170	sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
	171	sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
	172	sig_cfg.pixelclock = mode->clock * 1000;
	173	sig_cfg.clkflags = ipu_crtc->di_clkflags;
	174
	175	sig_cfg.v_to_h_sync = 0;
	176
2ea42608 PZ	177	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	178	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
	179
f326f799 SH	180	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
	181	out_pixel_fmt, mode->hdisplay);
	182	if (ret) {
	183	dev_err(ipu_crtc->dev,
	184	"initializing display controller failed with %d\n",
	185	ret);
	186	return ret;
	187	}
	188
	189	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	190	if (ret) {
	191	dev_err(ipu_crtc->dev,
	192	"initializing panel failed with %d\n", ret);
	193	return ret;
	194	}
	195
f4510a27	196	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode, crtc->primary->fb,
b8d181e4 PZ	197	0, 0, mode->hdisplay, mode->vdisplay,
b8d181e4 PZ	198	x, y, mode->hdisplay, mode->vdisplay);
f326f799 SH	199	}
	200
	201	static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
	202	{
f326f799 SH	203	unsigned long flags;
	204	struct drm_device *drm = ipu_crtc->base.dev;
	205
	206	spin_lock_irqsave(&drm->event_lock, flags);
0eca56f9 RC	207	if (ipu_crtc->page_flip_event)
0eca56f9 RC	208	drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
f326f799	209	ipu_crtc->page_flip_event = NULL;
f326f799	210	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
f326f799 SH	211	spin_unlock_irqrestore(&drm->event_lock, flags);
	212	}
	213
	214	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	215	{
	216	struct ipu_crtc *ipu_crtc = dev_id;
	217
	218	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	219
	220	if (ipu_crtc->newfb) {
f326f799	221	ipu_crtc->newfb = NULL;
f4510a27	222	ipu_plane_set_base(ipu_crtc->plane[0], ipu_crtc->base.primary->fb,
32f71106	223	ipu_crtc->plane[0]->x, ipu_crtc->plane[0]->y);
f326f799 SH	224	ipu_crtc_handle_pageflip(ipu_crtc);
	225	}
	226
	227	return IRQ_HANDLED;
	228	}
	229
	230	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	231	const struct drm_display_mode *mode,
	232	struct drm_display_mode *adjusted_mode)
	233	{
	234	return true;
	235	}
	236
	237	static void ipu_crtc_prepare(struct drm_crtc *crtc)
	238	{
	239	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	240
	241	ipu_fb_disable(ipu_crtc);
	242	}
	243
	244	static void ipu_crtc_commit(struct drm_crtc *crtc)
	245	{
	246	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	247
	248	ipu_fb_enable(ipu_crtc);
	249	}
	250
f326f799 SH	251	static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	252	.dpms = ipu_crtc_dpms,
	253	.mode_fixup = ipu_crtc_mode_fixup,
	254	.mode_set = ipu_crtc_mode_set,
	255	.prepare = ipu_crtc_prepare,
	256	.commit = ipu_crtc_commit,
f326f799 SH	257	};
	258
	259	static int ipu_enable_vblank(struct drm_crtc *crtc)
	260	{
f326f799 SH	261	return 0;
	262	}
	263
	264	static void ipu_disable_vblank(struct drm_crtc *crtc)
	265	{
	266	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	267
6ee4d7fe SH	268	ipu_crtc->page_flip_event = NULL;
6ee4d7fe SH	269	ipu_crtc->newfb = NULL;
f326f799 SH	270	}
	271
	272	static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
2ea42608	273	u32 pixfmt, int hsync_pin, int vsync_pin)
f326f799 SH	274	{
	275	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	276
	277	ipu_crtc->interface_pix_fmt = pixfmt;
2ea42608 PZ	278	ipu_crtc->di_hsync_pin = hsync_pin;
2ea42608 PZ	279	ipu_crtc->di_vsync_pin = vsync_pin;
f326f799 SH	280
f326f799 SH	281	switch (encoder_type) {
b60b5bcb PZ	282	case DRM_MODE_ENCODER_DAC:
b60b5bcb PZ	283	case DRM_MODE_ENCODER_TVDAC:
f326f799 SH	284	case DRM_MODE_ENCODER_LVDS:
	285	ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC \|
	286	IPU_DI_CLKMODE_EXT;
	287	break;
f2d66aad	288	case DRM_MODE_ENCODER_TMDS:
f326f799 SH	289	case DRM_MODE_ENCODER_NONE:
	290	ipu_crtc->di_clkflags = 0;
	291	break;
	292	}
	293
	294	return 0;
	295	}
	296
	297	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	298	.enable_vblank = ipu_enable_vblank,
	299	.disable_vblank = ipu_disable_vblank,
	300	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	301	.crtc_funcs = &ipu_crtc_funcs,
	302	.crtc_helper_funcs = &ipu_helper_funcs,
	303	};
	304
	305	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	306	{
b8d181e4 PZ	307	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
b8d181e4 PZ	308	ipu_dc_put(ipu_crtc->dc);
f326f799 SH	309	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	310	ipu_di_put(ipu_crtc->di);
	311	}
	312
	313	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	314	struct ipu_client_platformdata *pdata)
	315	{
	316	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	317	int ret;
	318
f326f799 SH	319	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	320	if (IS_ERR(ipu_crtc->dc)) {
	321	ret = PTR_ERR(ipu_crtc->dc);
	322	goto err_out;
	323	}
	324
f326f799 SH	325	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	326	if (IS_ERR(ipu_crtc->di)) {
	327	ret = PTR_ERR(ipu_crtc->di);
	328	goto err_out;
	329	}
	330
f326f799 SH	331	return 0;
	332	err_out:
	333	ipu_put_resources(ipu_crtc);
	334
	335	return ret;
	336	}
	337
	338	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
32266b45	339	struct ipu_client_platformdata pdata, struct drm_device drm)
f326f799	340	{
47b1be5c	341	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
b8d181e4	342	int dp = -EINVAL;
f326f799	343	int ret;
b8d181e4	344	int id;
f326f799 SH	345
	346	ret = ipu_get_resources(ipu_crtc, pdata);
	347	if (ret) {
	348	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	349	ret);
	350	return ret;
	351	}
	352
655b43cc PZ	353	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
655b43cc PZ	354	&ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
f326f799 SH	355	if (ret) {
	356	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	357	goto err_put_resources;
	358	}
	359
b8d181e4 PZ	360	if (pdata->dp >= 0)
	361	dp = IPU_DP_FLOW_SYNC_BG;
	362	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
	363	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
	364	pdata->dma[0], dp, BIT(id), true);
	365	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
	366	if (ret) {
	367	dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
	368	ret);
	369	goto err_remove_crtc;
	370	}
	371
	372	/* If this crtc is using the DP, add an overlay plane */
	373	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
	374	ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
	375	pdata->dma[1],
	376	IPU_DP_FLOW_SYNC_FG,
	377	BIT(id), false);
	378	if (IS_ERR(ipu_crtc->plane[1]))
	379	ipu_crtc->plane[1] = NULL;
	380	}
	381
	382	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
47b1be5c PZ	383	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	384	"imx_drm", ipu_crtc);
	385	if (ret < 0) {
	386	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
b8d181e4	387	goto err_put_plane_res;
47b1be5c PZ	388	}
47b1be5c PZ	389
f326f799 SH	390	return 0;
f326f799 SH	391
b8d181e4 PZ	392	err_put_plane_res:
	393	ipu_plane_put_resources(ipu_crtc->plane[0]);
	394	err_remove_crtc:
	395	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
f326f799 SH	396	err_put_resources:
	397	ipu_put_resources(ipu_crtc);
	398
	399	return ret;
	400	}
	401
655b43cc PZ	402	static struct device_node ipu_drm_get_port_by_id(struct device_node parent,
	403	int port_id)
	404	{
	405	struct device_node *port;
	406	int id, ret;
	407
	408	port = of_get_child_by_name(parent, "port");
	409	while (port) {
	410	ret = of_property_read_u32(port, "reg", &id);
	411	if (!ret && id == port_id)
	412	return port;
	413
	414	do {
	415	port = of_get_next_child(parent, port);
	416	if (!port)
	417	return NULL;
	418	} while (of_node_cmp(port->name, "port"));
	419	}
	420
	421	return NULL;
	422	}
	423
17b5001b	424	static int ipu_drm_bind(struct device dev, struct device master, void *data)
f326f799	425	{
17b5001b	426	struct ipu_client_platformdata *pdata = dev->platform_data;
32266b45	427	struct drm_device *drm = data;
f326f799 SH	428	struct ipu_crtc *ipu_crtc;
	429	int ret;
	430
17b5001b	431	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
f326f799 SH	432	if (!ipu_crtc)
	433	return -ENOMEM;
	434
17b5001b	435	ipu_crtc->dev = dev;
f326f799	436
32266b45	437	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
9a8f3f44 LW	438	if (ret)
9a8f3f44 LW	439	return ret;
f326f799	440
17b5001b	441	dev_set_drvdata(dev, ipu_crtc);
f326f799 SH	442
	443	return 0;
	444	}
	445
17b5001b RK	446	static void ipu_drm_unbind(struct device dev, struct device master,
17b5001b RK	447	void *data)
f326f799	448	{
17b5001b	449	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
f326f799 SH	450
	451	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	452
b8d181e4	453	ipu_plane_put_resources(ipu_crtc->plane[0]);
f326f799	454	ipu_put_resources(ipu_crtc);
17b5001b RK	455	}
	456
	457	static const struct component_ops ipu_crtc_ops = {
	458	.bind = ipu_drm_bind,
	459	.unbind = ipu_drm_unbind,
	460	};
f326f799	461
17b5001b RK	462	static int ipu_drm_probe(struct platform_device *pdev)
17b5001b RK	463	{
655b43cc PZ	464	struct device *dev = &pdev->dev;
655b43cc PZ	465	struct ipu_client_platformdata *pdata = dev->platform_data;
17b5001b RK	466	int ret;
17b5001b RK	467
655b43cc	468	if (!dev->platform_data)
17b5001b RK	469	return -EINVAL;
17b5001b RK	470
655b43cc PZ	471	if (!dev->of_node) {
	472	/* Associate crtc device with the corresponding DI port node */
	473	dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node,
	474	pdata->di + 2);
	475	if (!dev->of_node) {
	476	dev_err(dev, "missing port@%d node in %s\n",
	477	pdata->di + 2, dev->parent->of_node->full_name);
	478	return -ENODEV;
	479	}
	480	}
	481
	482	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
17b5001b RK	483	if (ret)
	484	return ret;
	485
655b43cc	486	return component_add(dev, &ipu_crtc_ops);
17b5001b RK	487	}
	488
	489	static int ipu_drm_remove(struct platform_device *pdev)
	490	{
	491	component_del(&pdev->dev, &ipu_crtc_ops);
f326f799 SH	492	return 0;
	493	}
	494
	495	static struct platform_driver ipu_drm_driver = {
	496	.driver = {
	497	.name = "imx-ipuv3-crtc",
	498	},
	499	.probe = ipu_drm_probe,
99c28f10	500	.remove = ipu_drm_remove,
f326f799 SH	501	};
	502	module_platform_driver(ipu_drm_driver);
	503
	504	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	505	MODULE_DESCRIPTION(DRIVER_DESC);
	506	MODULE_LICENSE("GPL");
ce9c1cef	507	MODULE_ALIAS("platform:imx-ipuv3-crtc");