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imx-drm: imx-drm-core: provide common connector and encoder cleanup functions
[linux-2.6-block.git] / drivers / staging / imx-drm / imx-tve.c
CommitLineData
fcbc51e5
PZ		 1/*
2 * i.MX drm driver - Television Encoder (TVEv2)
3 *
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/clk-provider.h>
17b5001b 23#include <linux/component.h>
fcbc51e5 24#include <linux/module.h>
687b81d0 25#include <linux/i2c.h>
fcbc51e5
PZ		 26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28#include <linux/spinlock.h>
29#include <linux/videodev2.h>
30#include <drm/drmP.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/drm_crtc_helper.h>
33
34#include "imx-drm.h"
35
36#define TVE_COM_CONF_REG 0x00
37#define TVE_TVDAC0_CONT_REG 0x28
38#define TVE_TVDAC1_CONT_REG 0x2c
39#define TVE_TVDAC2_CONT_REG 0x30
40#define TVE_CD_CONT_REG 0x34
41#define TVE_INT_CONT_REG 0x64
42#define TVE_STAT_REG 0x68
43#define TVE_TST_MODE_REG 0x6c
44#define TVE_MV_CONT_REG 0xdc
45
46/* TVE_COM_CONF_REG */
47#define TVE_SYNC_CH_2_EN BIT(22)
48#define TVE_SYNC_CH_1_EN BIT(21)
49#define TVE_SYNC_CH_0_EN BIT(20)
50#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
51#define TVE_TV_OUT_DISABLE (0x0 << 12)
52#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
53#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
54#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
55#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
56#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
57#define TVE_TV_OUT_YPBPR (0x6 << 12)
58#define TVE_TV_OUT_RGB (0x7 << 12)
59#define TVE_TV_STAND_MASK (0xf << 8)
60#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
61#define TVE_P2I_CONV_EN BIT(7)
62#define TVE_INP_VIDEO_FORM BIT(6)
63#define TVE_INP_YCBCR_422 (0x0 << 6)
64#define TVE_INP_YCBCR_444 (0x1 << 6)
65#define TVE_DATA_SOURCE_MASK (0x3 << 4)
66#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
67#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
68#define TVE_DATA_SOURCE_EXT (0x2 << 4)
69#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
70#define TVE_IPU_CLK_EN_OFS 3
71#define TVE_IPU_CLK_EN BIT(3)
72#define TVE_DAC_SAMP_RATE_OFS 1
73#define TVE_DAC_SAMP_RATE_WIDTH 2
74#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
75#define TVE_DAC_FULL_RATE (0x0 << 1)
76#define TVE_DAC_DIV2_RATE (0x1 << 1)
77#define TVE_DAC_DIV4_RATE (0x2 << 1)
78#define TVE_EN BIT(0)
79
80/* TVE_TVDACx_CONT_REG */
81#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
82
83/* TVE_CD_CONT_REG */
84#define TVE_CD_CH_2_SM_EN BIT(22)
85#define TVE_CD_CH_1_SM_EN BIT(21)
86#define TVE_CD_CH_0_SM_EN BIT(20)
87#define TVE_CD_CH_2_LM_EN BIT(18)
88#define TVE_CD_CH_1_LM_EN BIT(17)
89#define TVE_CD_CH_0_LM_EN BIT(16)
90#define TVE_CD_CH_2_REF_LVL BIT(10)
91#define TVE_CD_CH_1_REF_LVL BIT(9)
92#define TVE_CD_CH_0_REF_LVL BIT(8)
93#define TVE_CD_EN BIT(0)
94
95/* TVE_INT_CONT_REG */
96#define TVE_FRAME_END_IEN BIT(13)
97#define TVE_CD_MON_END_IEN BIT(2)
98#define TVE_CD_SM_IEN BIT(1)
99#define TVE_CD_LM_IEN BIT(0)
100
101/* TVE_TST_MODE_REG */
102#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
103
104#define con_to_tve(x) container_of(x, struct imx_tve, connector)
105#define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
106
107enum {
108 TVE_MODE_TVOUT,
109 TVE_MODE_VGA,
110};
111
112struct imx_tve {
113 struct drm_connector connector;
114 struct imx_drm_connector *imx_drm_connector;
115 struct drm_encoder encoder;
116 struct imx_drm_encoder *imx_drm_encoder;
117 struct device *dev;
fcbc51e5
PZ		 118 spinlock_t lock; /* register lock */
119 bool enabled;
120 int mode;
121
122 struct regmap *regmap;
123 struct regulator *dac_reg;
124 struct i2c_adapter *ddc;
125 struct clk *clk;
126 struct clk *di_sel_clk;
127 struct clk_hw clk_hw_di;
128 struct clk *di_clk;
129 int vsync_pin;
130 int hsync_pin;
131};
132
133static void tve_lock(void *__tve)
5d78bf80 134__acquires(&tve->lock)
fcbc51e5
PZ		 135{
136 struct imx_tve *tve = __tve;
137 spin_lock(&tve->lock);
138}
139
140static void tve_unlock(void *__tve)
5d78bf80 141__releases(&tve->lock)
fcbc51e5
PZ		 142{
143 struct imx_tve *tve = __tve;
144 spin_unlock(&tve->lock);
145}
146
147static void tve_enable(struct imx_tve *tve)
148{
fcbc51e5
PZ		 149 int ret;
150
fcbc51e5 151 if (!tve->enabled) {
89bc5be7 152 tve->enabled = true;
fcbc51e5
PZ		 153 clk_prepare_enable(tve->clk);
154 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
155 TVE_IPU_CLK_EN | TVE_EN,
156 TVE_IPU_CLK_EN | TVE_EN);
157 }
158
159 /* clear interrupt status register */
160 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
161
162 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
163 if (tve->mode == TVE_MODE_VGA)
164 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
165 else
166 regmap_write(tve->regmap, TVE_INT_CONT_REG,
89911e58
AW		 167 TVE_CD_SM_IEN |
168 TVE_CD_LM_IEN |
169 TVE_CD_MON_END_IEN);
fcbc51e5
PZ		 170}
171
172static void tve_disable(struct imx_tve *tve)
173{
fcbc51e5
PZ		 174 int ret;
175
fcbc51e5 176 if (tve->enabled) {
89bc5be7 177 tve->enabled = false;
fcbc51e5
PZ		 178 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
179 TVE_IPU_CLK_EN | TVE_EN, 0);
180 clk_disable_unprepare(tve->clk);
181 }
fcbc51e5
PZ		 182}
183
184static int tve_setup_tvout(struct imx_tve *tve)
185{
186 return -ENOTSUPP;
187}
188
189static int tve_setup_vga(struct imx_tve *tve)
190{
191 unsigned int mask;
192 unsigned int val;
193 int ret;
194
195 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
196 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
197 TVE_TVDAC_GAIN_MASK, 0x0a);
198 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
199 TVE_TVDAC_GAIN_MASK, 0x0a);
200 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
201 TVE_TVDAC_GAIN_MASK, 0x0a);
202
203 /* set configuration register */
204 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
205 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
206 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
207 val |= TVE_TV_STAND_HD_1080P30 | 0;
208 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
209 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
210 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
211 if (ret < 0) {
212 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
213 return ret;
214 }
215
216 /* set test mode (as documented) */
217 ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
218 TVE_TVDAC_TEST_MODE_MASK, 1);
219
220 return 0;
221}
222
223static enum drm_connector_status imx_tve_connector_detect(
224 struct drm_connector *connector, bool force)
225{
226 return connector_status_connected;
227}
228
229static void imx_tve_connector_destroy(struct drm_connector *connector)
230{
231 /* do not free here */
232}
233
234static int imx_tve_connector_get_modes(struct drm_connector *connector)
235{
236 struct imx_tve *tve = con_to_tve(connector);
237 struct edid *edid;
238 int ret = 0;
239
240 if (!tve->ddc)
241 return 0;
242
243 edid = drm_get_edid(connector, tve->ddc);
244 if (edid) {
245 drm_mode_connector_update_edid_property(connector, edid);
246 ret = drm_add_edid_modes(connector, edid);
247 kfree(edid);
248 }
249
250 return ret;
251}
252
253static int imx_tve_connector_mode_valid(struct drm_connector *connector,
254 struct drm_display_mode *mode)
255{
256 struct imx_tve *tve = con_to_tve(connector);
257 unsigned long rate;
baa68c4b
RK		 258 int ret;
259
260 ret = imx_drm_connector_mode_valid(connector, mode);
261 if (ret != MODE_OK)
262 return ret;
fcbc51e5
PZ		 263
264 /* pixel clock with 2x oversampling */
265 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
266 if (rate == mode->clock)
267 return MODE_OK;
268
269 /* pixel clock without oversampling */
270 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
271 if (rate == mode->clock)
272 return MODE_OK;
273
274 dev_warn(tve->dev, "ignoring mode %dx%d\n",
275 mode->hdisplay, mode->vdisplay);
276
277 return MODE_BAD;
278}
279
280static struct drm_encoder *imx_tve_connector_best_encoder(
281 struct drm_connector *connector)
282{
283 struct imx_tve *tve = con_to_tve(connector);
284
285 return &tve->encoder;
286}
287
288static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
289{
290 struct imx_tve *tve = enc_to_tve(encoder);
291 int ret;
292
293 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
294 TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
295 if (ret < 0)
296 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
297}
298
299static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
300 const struct drm_display_mode *mode,
301 struct drm_display_mode *adjusted_mode)
302{
303 return true;
304}
305
306static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
307{
308 struct imx_tve *tve = enc_to_tve(encoder);
309
310 tve_disable(tve);
311
312 switch (tve->mode) {
313 case TVE_MODE_VGA:
f2d66aad 314 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
fcbc51e5
PZ		 315 tve->hsync_pin, tve->vsync_pin);
316 break;
317 case TVE_MODE_TVOUT:
f2d66aad 318 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
fcbc51e5
PZ		 319 break;
320 }
321}
322
323static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
324 struct drm_display_mode *mode,
325 struct drm_display_mode *adjusted_mode)
326{
327 struct imx_tve *tve = enc_to_tve(encoder);
328 unsigned long rounded_rate;
329 unsigned long rate;
330 int div = 1;
331 int ret;
332
333 /*
334 * FIXME
335 * we should try 4k * mode->clock first,
336 * and enable 4x oversampling for lower resolutions
337 */
338 rate = 2000UL * mode->clock;
339 clk_set_rate(tve->clk, rate);
340 rounded_rate = clk_get_rate(tve->clk);
341 if (rounded_rate >= rate)
342 div = 2;
343 clk_set_rate(tve->di_clk, rounded_rate / div);
344
345 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
346 if (ret < 0) {
347 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
348 ret);
349 }
350
351 if (tve->mode == TVE_MODE_VGA)
352 tve_setup_vga(tve);
353 else
354 tve_setup_tvout(tve);
355}
356
357static void imx_tve_encoder_commit(struct drm_encoder *encoder)
358{
359 struct imx_tve *tve = enc_to_tve(encoder);
360
361 tve_enable(tve);
362}
363
364static void imx_tve_encoder_disable(struct drm_encoder *encoder)
365{
366 struct imx_tve *tve = enc_to_tve(encoder);
367
368 tve_disable(tve);
369}
370
371static void imx_tve_encoder_destroy(struct drm_encoder *encoder)
372{
373 /* do not free here */
374}
375
376static struct drm_connector_funcs imx_tve_connector_funcs = {
377 .dpms = drm_helper_connector_dpms,
378 .fill_modes = drm_helper_probe_single_connector_modes,
379 .detect = imx_tve_connector_detect,
380 .destroy = imx_tve_connector_destroy,
381};
382
383static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
384 .get_modes = imx_tve_connector_get_modes,
385 .best_encoder = imx_tve_connector_best_encoder,
386 .mode_valid = imx_tve_connector_mode_valid,
387};
388
389static struct drm_encoder_funcs imx_tve_encoder_funcs = {
390 .destroy = imx_tve_encoder_destroy,
391};
392
393static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
394 .dpms = imx_tve_encoder_dpms,
395 .mode_fixup = imx_tve_encoder_mode_fixup,
396 .prepare = imx_tve_encoder_prepare,
397 .mode_set = imx_tve_encoder_mode_set,
398 .commit = imx_tve_encoder_commit,
399 .disable = imx_tve_encoder_disable,
400};
401
402static irqreturn_t imx_tve_irq_handler(int irq, void *data)
403{
404 struct imx_tve *tve = data;
405 unsigned int val;
406
407 regmap_read(tve->regmap, TVE_STAT_REG, &val);
408
409 /* clear interrupt status register */
410 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
411
412 return IRQ_HANDLED;
413}
414
415static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
416 unsigned long parent_rate)
417{
418 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
419 unsigned int val;
420 int ret;
421
422 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
423 if (ret < 0)
424 return 0;
425
426 switch (val & TVE_DAC_SAMP_RATE_MASK) {
427 case TVE_DAC_DIV4_RATE:
428 return parent_rate / 4;
429 case TVE_DAC_DIV2_RATE:
430 return parent_rate / 2;
431 case TVE_DAC_FULL_RATE:
432 default:
433 return parent_rate;
434 }
435
436 return 0;
437}
438
439static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
440 unsigned long *prate)
441{
442 unsigned long div;
443
444 div = *prate / rate;
445 if (div >= 4)
446 return *prate / 4;
447 else if (div >= 2)
448 return *prate / 2;
449 else
450 return *prate;
451}
452
453static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
454 unsigned long parent_rate)
455{
456 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
457 unsigned long div;
458 u32 val;
459 int ret;
460
461 div = parent_rate / rate;
462 if (div >= 4)
463 val = TVE_DAC_DIV4_RATE;
464 else if (div >= 2)
465 val = TVE_DAC_DIV2_RATE;
466 else
467 val = TVE_DAC_FULL_RATE;
468
89911e58
AW		 469 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
470 TVE_DAC_SAMP_RATE_MASK, val);
471
fcbc51e5
PZ		 472 if (ret < 0) {
473 dev_err(tve->dev, "failed to set divider: %d\n", ret);
474 return ret;
475 }
476
477 return 0;
478}
479
480static struct clk_ops clk_tve_di_ops = {
481 .round_rate = clk_tve_di_round_rate,
482 .set_rate = clk_tve_di_set_rate,
483 .recalc_rate = clk_tve_di_recalc_rate,
484};
485
486static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
487{
488 const char *tve_di_parent[1];
489 struct clk_init_data init = {
490 .name = "tve_di",
491 .ops = &clk_tve_di_ops,
492 .num_parents = 1,
493 .flags = 0,
494 };
495
496 tve_di_parent[0] = __clk_get_name(tve->clk);
497 init.parent_names = (const char **)&tve_di_parent;
498
499 tve->clk_hw_di.init = &init;
500 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
501 if (IS_ERR(tve->di_clk)) {
502 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
503 PTR_ERR(tve->di_clk));
504 return PTR_ERR(tve->di_clk);
505 }
506
507 return 0;
508}
509
510static int imx_tve_register(struct imx_tve *tve)
511{
f2d66aad 512 int encoder_type;
fcbc51e5
PZ		 513 int ret;
514
f2d66aad
RK		 515 encoder_type = tve->mode == TVE_MODE_VGA ?
516 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
517
fcbc51e5
PZ		 518 tve->connector.funcs = &imx_tve_connector_funcs;
519 tve->encoder.funcs = &imx_tve_encoder_funcs;
520
f2d66aad 521 tve->encoder.encoder_type = encoder_type;
fcbc51e5
PZ		 522 tve->connector.connector_type = DRM_MODE_CONNECTOR_VGA;
523
524 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
525 ret = imx_drm_add_encoder(&tve->encoder, &tve->imx_drm_encoder,
526 THIS_MODULE);
527 if (ret) {
528 dev_err(tve->dev, "adding encoder failed with %d\n", ret);
529 return ret;
530 }
531
532 drm_connector_helper_add(&tve->connector,
533 &imx_tve_connector_helper_funcs);
534
535 ret = imx_drm_add_connector(&tve->connector,
536 &tve->imx_drm_connector, THIS_MODULE);
537 if (ret) {
538 imx_drm_remove_encoder(tve->imx_drm_encoder);
539 dev_err(tve->dev, "adding connector failed with %d\n", ret);
540 return ret;
541 }
542
543 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
544
545 return 0;
546}
547
548static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
549{
550 return (reg % 4 == 0) && (reg <= 0xdc);
551}
552
553static struct regmap_config tve_regmap_config = {
554 .reg_bits = 32,
555 .val_bits = 32,
556 .reg_stride = 4,
557
558 .readable_reg = imx_tve_readable_reg,
559
560 .lock = tve_lock,
561 .unlock = tve_unlock,
562
563 .max_register = 0xdc,
564};
565
566static const char *imx_tve_modes[] = {
567 [TVE_MODE_TVOUT] = "tvout",
568 [TVE_MODE_VGA] = "vga",
569};
570
7fc6cb28 571static const int of_get_tve_mode(struct device_node *np)
fcbc51e5
PZ		 572{
573 const char *bm;
574 int ret, i;
575
576 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
577 if (ret < 0)
578 return ret;
579
580 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
581 if (!strcasecmp(bm, imx_tve_modes[i]))
582 return i;
583
584 return -EINVAL;
585}
586
17b5001b 587static int imx_tve_bind(struct device *dev, struct device *master, void *data)
fcbc51e5 588{
17b5001b
RK		 589 struct platform_device *pdev = to_platform_device(dev);
590 struct device_node *np = dev->of_node;
fcbc51e5
PZ		 591 struct device_node *ddc_node;
592 struct imx_tve *tve;
593 struct resource *res;
594 void __iomem *base;
595 unsigned int val;
596 int irq;
597 int ret;
598
17b5001b 599 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
fcbc51e5
PZ		 600 if (!tve)
601 return -ENOMEM;
602
17b5001b 603 tve->dev = dev;
fcbc51e5 604 spin_lock_init(&tve->lock);
fcbc51e5
PZ		 605
606 ddc_node = of_parse_phandle(np, "ddc", 0);
607 if (ddc_node) {
608 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
609 of_node_put(ddc_node);
610 }
611
612 tve->mode = of_get_tve_mode(np);
613 if (tve->mode != TVE_MODE_VGA) {
17b5001b 614 dev_err(dev, "only VGA mode supported, currently\n");
fcbc51e5
PZ		 615 return -EINVAL;
616 }
617
618 if (tve->mode == TVE_MODE_VGA) {
89911e58
AW		 619 ret = of_property_read_u32(np, "fsl,hsync-pin",
620 &tve->hsync_pin);
621
fcbc51e5 622 if (ret < 0) {
17b5001b 623 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 624 return ret;
625 }
626
89911e58
AW		 627 ret |= of_property_read_u32(np, "fsl,vsync-pin",
628 &tve->vsync_pin);
629
fcbc51e5 630 if (ret < 0) {
17b5001b 631 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 632 return ret;
633 }
634 }
635
636 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17b5001b 637 base = devm_ioremap_resource(dev, res);
9b43b56f
LN		 638 if (IS_ERR(base))
639 return PTR_ERR(base);
fcbc51e5
PZ		 640
641 tve_regmap_config.lock_arg = tve;
17b5001b 642 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
fcbc51e5
PZ		 643 &tve_regmap_config);
644 if (IS_ERR(tve->regmap)) {
17b5001b 645 dev_err(dev, "failed to init regmap: %ld\n",
fcbc51e5
PZ		 646 PTR_ERR(tve->regmap));
647 return PTR_ERR(tve->regmap);
648 }
649
650 irq = platform_get_irq(pdev, 0);
651 if (irq < 0) {
17b5001b 652 dev_err(dev, "failed to get irq\n");
fcbc51e5
PZ		 653 return irq;
654 }
655
17b5001b 656 ret = devm_request_threaded_irq(dev, irq, NULL,
fcbc51e5
PZ		 657 imx_tve_irq_handler, IRQF_ONESHOT,
658 "imx-tve", tve);
659 if (ret < 0) {
17b5001b 660 dev_err(dev, "failed to request irq: %d\n", ret);
fcbc51e5
PZ		 661 return ret;
662 }
663
17b5001b 664 tve->dac_reg = devm_regulator_get(dev, "dac");
fcbc51e5
PZ		 665 if (!IS_ERR(tve->dac_reg)) {
666 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
c7b0cf3e
FE		 667 ret = regulator_enable(tve->dac_reg);
668 if (ret)
669 return ret;
fcbc51e5
PZ		 670 }
671
17b5001b 672 tve->clk = devm_clk_get(dev, "tve");
fcbc51e5 673 if (IS_ERR(tve->clk)) {
17b5001b 674 dev_err(dev, "failed to get high speed tve clock: %ld\n",
fcbc51e5
PZ		 675 PTR_ERR(tve->clk));
676 return PTR_ERR(tve->clk);
677 }
678
679 /* this is the IPU DI clock input selector, can be parented to tve_di */
17b5001b 680 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
fcbc51e5 681 if (IS_ERR(tve->di_sel_clk)) {
17b5001b 682 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
fcbc51e5
PZ		 683 PTR_ERR(tve->di_sel_clk));
684 return PTR_ERR(tve->di_sel_clk);
685 }
686
687 ret = tve_clk_init(tve, base);
688 if (ret < 0)
689 return ret;
690
691 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
692 if (ret < 0) {
17b5001b 693 dev_err(dev, "failed to read configuration register: %d\n", ret);
fcbc51e5
PZ		 694 return ret;
695 }
696 if (val != 0x00100000) {
17b5001b 697 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
fcbc51e5 698 return -ENODEV;
a22526e4 699 }
fcbc51e5
PZ		 700
701 /* disable cable detection for VGA mode */
702 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
703
704 ret = imx_tve_register(tve);
705 if (ret)
706 return ret;
707
708 ret = imx_drm_encoder_add_possible_crtcs(tve->imx_drm_encoder, np);
709
17b5001b 710 dev_set_drvdata(dev, tve);
fcbc51e5
PZ		 711
712 return 0;
713}
714
17b5001b
RK		 715static void imx_tve_unbind(struct device *dev, struct device *master,
716 void *data)
fcbc51e5 717{
17b5001b 718 struct imx_tve *tve = dev_get_drvdata(dev);
fcbc51e5
PZ		 719 struct drm_connector *connector = &tve->connector;
720 struct drm_encoder *encoder = &tve->encoder;
721
722 drm_mode_connector_detach_encoder(connector, encoder);
723
724 imx_drm_remove_connector(tve->imx_drm_connector);
725 imx_drm_remove_encoder(tve->imx_drm_encoder);
726
727 if (!IS_ERR(tve->dac_reg))
728 regulator_disable(tve->dac_reg);
17b5001b 729}
fcbc51e5 730
17b5001b
RK		 731static const struct component_ops imx_tve_ops = {
732 .bind = imx_tve_bind,
733 .unbind = imx_tve_unbind,
734};
735
736static int imx_tve_probe(struct platform_device *pdev)
737{
738 return component_add(&pdev->dev, &imx_tve_ops);
739}
740
741static int imx_tve_remove(struct platform_device *pdev)
742{
743 component_del(&pdev->dev, &imx_tve_ops);
fcbc51e5
PZ		 744 return 0;
745}
746
747static const struct of_device_id imx_tve_dt_ids[] = {
748 { .compatible = "fsl,imx53-tve", },
749 { /* sentinel */ }
750};
751
752static struct platform_driver imx_tve_driver = {
753 .probe = imx_tve_probe,
754 .remove = imx_tve_remove,
755 .driver = {
756 .of_match_table = imx_tve_dt_ids,
757 .name = "imx-tve",
758 .owner = THIS_MODULE,
759 },
760};
761
762module_platform_driver(imx_tve_driver);
763
764MODULE_DESCRIPTION("i.MX Television Encoder driver");
765MODULE_AUTHOR("Philipp Zabel, Pengutronix");
766MODULE_LICENSE("GPL");
52db752c 767MODULE_ALIAS("platform:imx-tve");
Linux 6.x block layer and io_uring tree(s)