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gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging
[linux-2.6-block.git] / drivers / staging / imx-drm / imx-tve.c
CommitLineData
fcbc51e5
PZ		 1/*
2 * i.MX drm driver - Television Encoder (TVEv2)
3 *
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/clk-provider.h>
17b5001b 23#include <linux/component.h>
fcbc51e5 24#include <linux/module.h>
687b81d0 25#include <linux/i2c.h>
fcbc51e5
PZ		 26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28#include <linux/spinlock.h>
29#include <linux/videodev2.h>
30#include <drm/drmP.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/drm_crtc_helper.h>
39b9004d 33#include <video/imx-ipu-v3.h>
fcbc51e5
PZ		 34
35#include "imx-drm.h"
36
37#define TVE_COM_CONF_REG 0x00
38#define TVE_TVDAC0_CONT_REG 0x28
39#define TVE_TVDAC1_CONT_REG 0x2c
40#define TVE_TVDAC2_CONT_REG 0x30
41#define TVE_CD_CONT_REG 0x34
42#define TVE_INT_CONT_REG 0x64
43#define TVE_STAT_REG 0x68
44#define TVE_TST_MODE_REG 0x6c
45#define TVE_MV_CONT_REG 0xdc
46
47/* TVE_COM_CONF_REG */
48#define TVE_SYNC_CH_2_EN BIT(22)
49#define TVE_SYNC_CH_1_EN BIT(21)
50#define TVE_SYNC_CH_0_EN BIT(20)
51#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
52#define TVE_TV_OUT_DISABLE (0x0 << 12)
53#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
54#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
55#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
56#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
57#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
58#define TVE_TV_OUT_YPBPR (0x6 << 12)
59#define TVE_TV_OUT_RGB (0x7 << 12)
60#define TVE_TV_STAND_MASK (0xf << 8)
61#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
62#define TVE_P2I_CONV_EN BIT(7)
63#define TVE_INP_VIDEO_FORM BIT(6)
64#define TVE_INP_YCBCR_422 (0x0 << 6)
65#define TVE_INP_YCBCR_444 (0x1 << 6)
66#define TVE_DATA_SOURCE_MASK (0x3 << 4)
67#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
68#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
69#define TVE_DATA_SOURCE_EXT (0x2 << 4)
70#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
71#define TVE_IPU_CLK_EN_OFS 3
72#define TVE_IPU_CLK_EN BIT(3)
73#define TVE_DAC_SAMP_RATE_OFS 1
74#define TVE_DAC_SAMP_RATE_WIDTH 2
75#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
76#define TVE_DAC_FULL_RATE (0x0 << 1)
77#define TVE_DAC_DIV2_RATE (0x1 << 1)
78#define TVE_DAC_DIV4_RATE (0x2 << 1)
79#define TVE_EN BIT(0)
80
81/* TVE_TVDACx_CONT_REG */
82#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
83
84/* TVE_CD_CONT_REG */
85#define TVE_CD_CH_2_SM_EN BIT(22)
86#define TVE_CD_CH_1_SM_EN BIT(21)
87#define TVE_CD_CH_0_SM_EN BIT(20)
88#define TVE_CD_CH_2_LM_EN BIT(18)
89#define TVE_CD_CH_1_LM_EN BIT(17)
90#define TVE_CD_CH_0_LM_EN BIT(16)
91#define TVE_CD_CH_2_REF_LVL BIT(10)
92#define TVE_CD_CH_1_REF_LVL BIT(9)
93#define TVE_CD_CH_0_REF_LVL BIT(8)
94#define TVE_CD_EN BIT(0)
95
96/* TVE_INT_CONT_REG */
97#define TVE_FRAME_END_IEN BIT(13)
98#define TVE_CD_MON_END_IEN BIT(2)
99#define TVE_CD_SM_IEN BIT(1)
100#define TVE_CD_LM_IEN BIT(0)
101
102/* TVE_TST_MODE_REG */
103#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
104
105#define con_to_tve(x) container_of(x, struct imx_tve, connector)
106#define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
107
108enum {
109 TVE_MODE_TVOUT,
110 TVE_MODE_VGA,
111};
112
113struct imx_tve {
114 struct drm_connector connector;
fcbc51e5 115 struct drm_encoder encoder;
fcbc51e5 116 struct device *dev;
fcbc51e5
PZ		 117 spinlock_t lock; /* register lock */
118 bool enabled;
119 int mode;
120
121 struct regmap *regmap;
122 struct regulator *dac_reg;
123 struct i2c_adapter *ddc;
124 struct clk *clk;
125 struct clk *di_sel_clk;
126 struct clk_hw clk_hw_di;
127 struct clk *di_clk;
128 int vsync_pin;
129 int hsync_pin;
130};
131
132static void tve_lock(void *__tve)
5d78bf80 133__acquires(&tve->lock)
fcbc51e5
PZ		 134{
135 struct imx_tve *tve = __tve;
136 spin_lock(&tve->lock);
137}
138
139static void tve_unlock(void *__tve)
5d78bf80 140__releases(&tve->lock)
fcbc51e5
PZ		 141{
142 struct imx_tve *tve = __tve;
143 spin_unlock(&tve->lock);
144}
145
146static void tve_enable(struct imx_tve *tve)
147{
fcbc51e5
PZ		 148 int ret;
149
fcbc51e5 150 if (!tve->enabled) {
89bc5be7 151 tve->enabled = true;
fcbc51e5
PZ		 152 clk_prepare_enable(tve->clk);
153 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
154 TVE_IPU_CLK_EN | TVE_EN,
155 TVE_IPU_CLK_EN | TVE_EN);
156 }
157
158 /* clear interrupt status register */
159 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
160
161 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
162 if (tve->mode == TVE_MODE_VGA)
163 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
164 else
165 regmap_write(tve->regmap, TVE_INT_CONT_REG,
89911e58
AW		 166 TVE_CD_SM_IEN |
167 TVE_CD_LM_IEN |
168 TVE_CD_MON_END_IEN);
fcbc51e5
PZ		 169}
170
171static void tve_disable(struct imx_tve *tve)
172{
fcbc51e5
PZ		 173 int ret;
174
fcbc51e5 175 if (tve->enabled) {
89bc5be7 176 tve->enabled = false;
fcbc51e5
PZ		 177 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
178 TVE_IPU_CLK_EN | TVE_EN, 0);
179 clk_disable_unprepare(tve->clk);
180 }
fcbc51e5
PZ		 181}
182
183static int tve_setup_tvout(struct imx_tve *tve)
184{
185 return -ENOTSUPP;
186}
187
188static int tve_setup_vga(struct imx_tve *tve)
189{
190 unsigned int mask;
191 unsigned int val;
192 int ret;
193
194 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
195 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
196 TVE_TVDAC_GAIN_MASK, 0x0a);
197 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
198 TVE_TVDAC_GAIN_MASK, 0x0a);
199 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
200 TVE_TVDAC_GAIN_MASK, 0x0a);
201
202 /* set configuration register */
203 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
204 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
205 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
206 val |= TVE_TV_STAND_HD_1080P30 | 0;
207 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
208 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
209 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
210 if (ret < 0) {
211 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
212 return ret;
213 }
214
215 /* set test mode (as documented) */
216 ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
217 TVE_TVDAC_TEST_MODE_MASK, 1);
218
219 return 0;
220}
221
222static enum drm_connector_status imx_tve_connector_detect(
223 struct drm_connector *connector, bool force)
224{
225 return connector_status_connected;
226}
227
fcbc51e5
PZ		 228static int imx_tve_connector_get_modes(struct drm_connector *connector)
229{
230 struct imx_tve *tve = con_to_tve(connector);
231 struct edid *edid;
232 int ret = 0;
233
234 if (!tve->ddc)
235 return 0;
236
237 edid = drm_get_edid(connector, tve->ddc);
238 if (edid) {
239 drm_mode_connector_update_edid_property(connector, edid);
240 ret = drm_add_edid_modes(connector, edid);
241 kfree(edid);
242 }
243
244 return ret;
245}
246
247static int imx_tve_connector_mode_valid(struct drm_connector *connector,
248 struct drm_display_mode *mode)
249{
250 struct imx_tve *tve = con_to_tve(connector);
251 unsigned long rate;
baa68c4b
RK		 252 int ret;
253
254 ret = imx_drm_connector_mode_valid(connector, mode);
255 if (ret != MODE_OK)
256 return ret;
fcbc51e5
PZ		 257
258 /* pixel clock with 2x oversampling */
259 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
260 if (rate == mode->clock)
261 return MODE_OK;
262
263 /* pixel clock without oversampling */
264 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
265 if (rate == mode->clock)
266 return MODE_OK;
267
268 dev_warn(tve->dev, "ignoring mode %dx%d\n",
269 mode->hdisplay, mode->vdisplay);
270
271 return MODE_BAD;
272}
273
274static struct drm_encoder *imx_tve_connector_best_encoder(
275 struct drm_connector *connector)
276{
277 struct imx_tve *tve = con_to_tve(connector);
278
279 return &tve->encoder;
280}
281
282static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
283{
284 struct imx_tve *tve = enc_to_tve(encoder);
285 int ret;
286
287 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
288 TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
289 if (ret < 0)
290 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
291}
292
293static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
294 const struct drm_display_mode *mode,
295 struct drm_display_mode *adjusted_mode)
296{
297 return true;
298}
299
300static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
301{
302 struct imx_tve *tve = enc_to_tve(encoder);
303
304 tve_disable(tve);
305
306 switch (tve->mode) {
307 case TVE_MODE_VGA:
f2d66aad 308 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
fcbc51e5
PZ		 309 tve->hsync_pin, tve->vsync_pin);
310 break;
311 case TVE_MODE_TVOUT:
f2d66aad 312 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
fcbc51e5
PZ		 313 break;
314 }
315}
316
317static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
318 struct drm_display_mode *mode,
319 struct drm_display_mode *adjusted_mode)
320{
321 struct imx_tve *tve = enc_to_tve(encoder);
322 unsigned long rounded_rate;
323 unsigned long rate;
324 int div = 1;
325 int ret;
326
327 /*
328 * FIXME
329 * we should try 4k * mode->clock first,
330 * and enable 4x oversampling for lower resolutions
331 */
332 rate = 2000UL * mode->clock;
333 clk_set_rate(tve->clk, rate);
334 rounded_rate = clk_get_rate(tve->clk);
335 if (rounded_rate >= rate)
336 div = 2;
337 clk_set_rate(tve->di_clk, rounded_rate / div);
338
339 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
340 if (ret < 0) {
341 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
342 ret);
343 }
344
345 if (tve->mode == TVE_MODE_VGA)
346 tve_setup_vga(tve);
347 else
348 tve_setup_tvout(tve);
349}
350
351static void imx_tve_encoder_commit(struct drm_encoder *encoder)
352{
353 struct imx_tve *tve = enc_to_tve(encoder);
354
355 tve_enable(tve);
356}
357
358static void imx_tve_encoder_disable(struct drm_encoder *encoder)
359{
360 struct imx_tve *tve = enc_to_tve(encoder);
361
362 tve_disable(tve);
363}
364
fcbc51e5
PZ		 365static struct drm_connector_funcs imx_tve_connector_funcs = {
366 .dpms = drm_helper_connector_dpms,
367 .fill_modes = drm_helper_probe_single_connector_modes,
368 .detect = imx_tve_connector_detect,
1b3f7675 369 .destroy = imx_drm_connector_destroy,
fcbc51e5
PZ		 370};
371
372static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
373 .get_modes = imx_tve_connector_get_modes,
374 .best_encoder = imx_tve_connector_best_encoder,
375 .mode_valid = imx_tve_connector_mode_valid,
376};
377
378static struct drm_encoder_funcs imx_tve_encoder_funcs = {
1b3f7675 379 .destroy = imx_drm_encoder_destroy,
fcbc51e5
PZ		 380};
381
382static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
383 .dpms = imx_tve_encoder_dpms,
384 .mode_fixup = imx_tve_encoder_mode_fixup,
385 .prepare = imx_tve_encoder_prepare,
386 .mode_set = imx_tve_encoder_mode_set,
387 .commit = imx_tve_encoder_commit,
388 .disable = imx_tve_encoder_disable,
389};
390
391static irqreturn_t imx_tve_irq_handler(int irq, void *data)
392{
393 struct imx_tve *tve = data;
394 unsigned int val;
395
396 regmap_read(tve->regmap, TVE_STAT_REG, &val);
397
398 /* clear interrupt status register */
399 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
400
401 return IRQ_HANDLED;
402}
403
404static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
405 unsigned long parent_rate)
406{
407 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
408 unsigned int val;
409 int ret;
410
411 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
412 if (ret < 0)
413 return 0;
414
415 switch (val & TVE_DAC_SAMP_RATE_MASK) {
416 case TVE_DAC_DIV4_RATE:
417 return parent_rate / 4;
418 case TVE_DAC_DIV2_RATE:
419 return parent_rate / 2;
420 case TVE_DAC_FULL_RATE:
421 default:
422 return parent_rate;
423 }
424
425 return 0;
426}
427
428static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
429 unsigned long *prate)
430{
431 unsigned long div;
432
433 div = *prate / rate;
434 if (div >= 4)
435 return *prate / 4;
436 else if (div >= 2)
437 return *prate / 2;
438 else
439 return *prate;
440}
441
442static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
443 unsigned long parent_rate)
444{
445 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
446 unsigned long div;
447 u32 val;
448 int ret;
449
450 div = parent_rate / rate;
451 if (div >= 4)
452 val = TVE_DAC_DIV4_RATE;
453 else if (div >= 2)
454 val = TVE_DAC_DIV2_RATE;
455 else
456 val = TVE_DAC_FULL_RATE;
457
89911e58
AW		 458 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
459 TVE_DAC_SAMP_RATE_MASK, val);
460
fcbc51e5
PZ		 461 if (ret < 0) {
462 dev_err(tve->dev, "failed to set divider: %d\n", ret);
463 return ret;
464 }
465
466 return 0;
467}
468
469static struct clk_ops clk_tve_di_ops = {
470 .round_rate = clk_tve_di_round_rate,
471 .set_rate = clk_tve_di_set_rate,
472 .recalc_rate = clk_tve_di_recalc_rate,
473};
474
475static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
476{
477 const char *tve_di_parent[1];
478 struct clk_init_data init = {
479 .name = "tve_di",
480 .ops = &clk_tve_di_ops,
481 .num_parents = 1,
482 .flags = 0,
483 };
484
485 tve_di_parent[0] = __clk_get_name(tve->clk);
486 init.parent_names = (const char **)&tve_di_parent;
487
488 tve->clk_hw_di.init = &init;
489 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
490 if (IS_ERR(tve->di_clk)) {
491 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
492 PTR_ERR(tve->di_clk));
493 return PTR_ERR(tve->di_clk);
494 }
495
496 return 0;
497}
498
1b3f7675 499static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
fcbc51e5 500{
f2d66aad 501 int encoder_type;
fcbc51e5
PZ		 502 int ret;
503
f2d66aad
RK		 504 encoder_type = tve->mode == TVE_MODE_VGA ?
505 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
506
1b3f7675
RK		 507 ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
508 tve->dev->of_node);
509 if (ret)
510 return ret;
fcbc51e5
PZ		 511
512 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
1b3f7675
RK		 513 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
514 encoder_type);
fcbc51e5
PZ		 515
516 drm_connector_helper_add(&tve->connector,
517 &imx_tve_connector_helper_funcs);
1b3f7675
RK		 518 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
519 DRM_MODE_CONNECTOR_VGA);
fcbc51e5
PZ		 520
521 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
522
523 return 0;
524}
525
526static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
527{
528 return (reg % 4 == 0) && (reg <= 0xdc);
529}
530
531static struct regmap_config tve_regmap_config = {
532 .reg_bits = 32,
533 .val_bits = 32,
534 .reg_stride = 4,
535
536 .readable_reg = imx_tve_readable_reg,
537
538 .lock = tve_lock,
539 .unlock = tve_unlock,
540
541 .max_register = 0xdc,
542};
543
544static const char *imx_tve_modes[] = {
545 [TVE_MODE_TVOUT] = "tvout",
546 [TVE_MODE_VGA] = "vga",
547};
548
7fc6cb28 549static const int of_get_tve_mode(struct device_node *np)
fcbc51e5
PZ		 550{
551 const char *bm;
552 int ret, i;
553
554 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
555 if (ret < 0)
556 return ret;
557
558 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
559 if (!strcasecmp(bm, imx_tve_modes[i]))
560 return i;
561
562 return -EINVAL;
563}
564
17b5001b 565static int imx_tve_bind(struct device *dev, struct device *master, void *data)
fcbc51e5 566{
17b5001b 567 struct platform_device *pdev = to_platform_device(dev);
1b3f7675 568 struct drm_device *drm = data;
17b5001b 569 struct device_node *np = dev->of_node;
fcbc51e5
PZ		 570 struct device_node *ddc_node;
571 struct imx_tve *tve;
572 struct resource *res;
573 void __iomem *base;
574 unsigned int val;
575 int irq;
576 int ret;
577
17b5001b 578 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
fcbc51e5
PZ		 579 if (!tve)
580 return -ENOMEM;
581
17b5001b 582 tve->dev = dev;
fcbc51e5 583 spin_lock_init(&tve->lock);
fcbc51e5 584
62e3879a 585 ddc_node = of_parse_phandle(np, "i2c-ddc-bus", 0);
fcbc51e5
PZ		 586 if (ddc_node) {
587 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
588 of_node_put(ddc_node);
589 }
590
591 tve->mode = of_get_tve_mode(np);
592 if (tve->mode != TVE_MODE_VGA) {
17b5001b 593 dev_err(dev, "only VGA mode supported, currently\n");
fcbc51e5
PZ		 594 return -EINVAL;
595 }
596
597 if (tve->mode == TVE_MODE_VGA) {
89911e58
AW		 598 ret = of_property_read_u32(np, "fsl,hsync-pin",
599 &tve->hsync_pin);
600
fcbc51e5 601 if (ret < 0) {
17b5001b 602 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 603 return ret;
604 }
605
89911e58
AW		 606 ret |= of_property_read_u32(np, "fsl,vsync-pin",
607 &tve->vsync_pin);
608
fcbc51e5 609 if (ret < 0) {
17b5001b 610 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 611 return ret;
612 }
613 }
614
615 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17b5001b 616 base = devm_ioremap_resource(dev, res);
9b43b56f
LN		 617 if (IS_ERR(base))
618 return PTR_ERR(base);
fcbc51e5
PZ		 619
620 tve_regmap_config.lock_arg = tve;
17b5001b 621 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
fcbc51e5
PZ		 622 &tve_regmap_config);
623 if (IS_ERR(tve->regmap)) {
17b5001b 624 dev_err(dev, "failed to init regmap: %ld\n",
fcbc51e5
PZ		 625 PTR_ERR(tve->regmap));
626 return PTR_ERR(tve->regmap);
627 }
628
629 irq = platform_get_irq(pdev, 0);
630 if (irq < 0) {
17b5001b 631 dev_err(dev, "failed to get irq\n");
fcbc51e5
PZ		 632 return irq;
633 }
634
17b5001b 635 ret = devm_request_threaded_irq(dev, irq, NULL,
fcbc51e5
PZ		 636 imx_tve_irq_handler, IRQF_ONESHOT,
637 "imx-tve", tve);
638 if (ret < 0) {
17b5001b 639 dev_err(dev, "failed to request irq: %d\n", ret);
fcbc51e5
PZ		 640 return ret;
641 }
642
17b5001b 643 tve->dac_reg = devm_regulator_get(dev, "dac");
fcbc51e5
PZ		 644 if (!IS_ERR(tve->dac_reg)) {
645 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
c7b0cf3e
FE		 646 ret = regulator_enable(tve->dac_reg);
647 if (ret)
648 return ret;
fcbc51e5
PZ		 649 }
650
17b5001b 651 tve->clk = devm_clk_get(dev, "tve");
fcbc51e5 652 if (IS_ERR(tve->clk)) {
17b5001b 653 dev_err(dev, "failed to get high speed tve clock: %ld\n",
fcbc51e5
PZ		 654 PTR_ERR(tve->clk));
655 return PTR_ERR(tve->clk);
656 }
657
658 /* this is the IPU DI clock input selector, can be parented to tve_di */
17b5001b 659 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
fcbc51e5 660 if (IS_ERR(tve->di_sel_clk)) {
17b5001b 661 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
fcbc51e5
PZ		 662 PTR_ERR(tve->di_sel_clk));
663 return PTR_ERR(tve->di_sel_clk);
664 }
665
666 ret = tve_clk_init(tve, base);
667 if (ret < 0)
668 return ret;
669
670 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
671 if (ret < 0) {
17b5001b 672 dev_err(dev, "failed to read configuration register: %d\n", ret);
fcbc51e5
PZ		 673 return ret;
674 }
675 if (val != 0x00100000) {
17b5001b 676 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
fcbc51e5 677 return -ENODEV;
a22526e4 678 }
fcbc51e5
PZ		 679
680 /* disable cable detection for VGA mode */
681 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
682
1b3f7675 683 ret = imx_tve_register(drm, tve);
fcbc51e5
PZ		 684 if (ret)
685 return ret;
686
17b5001b 687 dev_set_drvdata(dev, tve);
fcbc51e5
PZ		 688
689 return 0;
690}
691
17b5001b
RK		 692static void imx_tve_unbind(struct device *dev, struct device *master,
693 void *data)
fcbc51e5 694{
17b5001b 695 struct imx_tve *tve = dev_get_drvdata(dev);
fcbc51e5 696
1b3f7675
RK		 697 tve->connector.funcs->destroy(&tve->connector);
698 tve->encoder.funcs->destroy(&tve->encoder);
fcbc51e5
PZ		 699
700 if (!IS_ERR(tve->dac_reg))
701 regulator_disable(tve->dac_reg);
17b5001b 702}
fcbc51e5 703
17b5001b
RK		 704static const struct component_ops imx_tve_ops = {
705 .bind = imx_tve_bind,
706 .unbind = imx_tve_unbind,
707};
708
709static int imx_tve_probe(struct platform_device *pdev)
710{
711 return component_add(&pdev->dev, &imx_tve_ops);
712}
713
714static int imx_tve_remove(struct platform_device *pdev)
715{
716 component_del(&pdev->dev, &imx_tve_ops);
fcbc51e5
PZ		 717 return 0;
718}
719
720static const struct of_device_id imx_tve_dt_ids[] = {
721 { .compatible = "fsl,imx53-tve", },
722 { /* sentinel */ }
723};
724
725static struct platform_driver imx_tve_driver = {
726 .probe = imx_tve_probe,
727 .remove = imx_tve_remove,
728 .driver = {
729 .of_match_table = imx_tve_dt_ids,
730 .name = "imx-tve",
731 .owner = THIS_MODULE,
732 },
733};
734
735module_platform_driver(imx_tve_driver);
736
737MODULE_DESCRIPTION("i.MX Television Encoder driver");
738MODULE_AUTHOR("Philipp Zabel, Pengutronix");
739MODULE_LICENSE("GPL");
52db752c 740MODULE_ALIAS("platform:imx-tve");
Linux 6.x block layer and io_uring tree(s)