Commit | Line | Data |
---|---|---|
565e7dc8 HJ |
1 | /* |
2 | * | |
3 | * Copyright (c) 2009, Microsoft Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * | |
18 | * Authors: | |
19 | * Haiyang Zhang <haiyangz@microsoft.com> | |
20 | * Hank Janssen <hjanssen@microsoft.com> | |
21 | * | |
22 | */ | |
6658be6a GKH |
23 | #ifndef __HV_API_H |
24 | #define __HV_API_H | |
565e7dc8 | 25 | |
e3fe0bb6 S |
26 | struct hv_guid { |
27 | unsigned char data[16]; | |
28 | }; | |
29 | ||
30 | ||
65452d1f GKH |
31 | |
32 | /* Status codes for hypervisor operations. */ | |
33 | ||
34 | /* | |
35 | * HV_STATUS_SUCCESS | |
36 | * The specified hypercall succeeded | |
37 | */ | |
38 | #define HV_STATUS_SUCCESS ((u16)0x0000) | |
39 | ||
40 | /* | |
41 | * HV_STATUS_INVALID_HYPERCALL_CODE | |
42 | * The hypervisor does not support the operation because the specified | |
43 | * hypercall code is not supported. | |
44 | */ | |
45 | #define HV_STATUS_INVALID_HYPERCALL_CODE ((u16)0x0002) | |
46 | ||
47 | /* | |
48 | * HV_STATUS_INVALID_HYPERCALL_INPUT | |
49 | * The hypervisor does not support the operation because the encoding for the | |
50 | * hypercall input register is not supported. | |
51 | */ | |
52 | #define HV_STATUS_INVALID_HYPERCALL_INPUT ((u16)0x0003) | |
53 | ||
54 | /* | |
55 | * HV_STATUS_INVALID_ALIGNMENT | |
25985edc | 56 | * The hypervisor could not perform the operation because a parameter has an |
65452d1f GKH |
57 | * invalid alignment. |
58 | */ | |
59 | #define HV_STATUS_INVALID_ALIGNMENT ((u16)0x0004) | |
60 | ||
61 | /* | |
62 | * HV_STATUS_INVALID_PARAMETER | |
25985edc | 63 | * The hypervisor could not perform the operation because an invalid parameter |
65452d1f GKH |
64 | * was specified. |
65 | */ | |
66 | #define HV_STATUS_INVALID_PARAMETER ((u16)0x0005) | |
67 | ||
68 | /* | |
69 | * HV_STATUS_ACCESS_DENIED | |
70 | * Access to the specified object was denied. | |
71 | */ | |
72 | #define HV_STATUS_ACCESS_DENIED ((u16)0x0006) | |
73 | ||
74 | /* | |
75 | * HV_STATUS_INVALID_PARTITION_STATE | |
76 | * The hypervisor could not perform the operation because the partition is | |
77 | * entering or in an invalid state. | |
78 | */ | |
79 | #define HV_STATUS_INVALID_PARTITION_STATE ((u16)0x0007) | |
80 | ||
81 | /* | |
82 | * HV_STATUS_OPERATION_DENIED | |
83 | * The operation is not allowed in the current state. | |
84 | */ | |
85 | #define HV_STATUS_OPERATION_DENIED ((u16)0x0008) | |
86 | ||
87 | /* | |
88 | * HV_STATUS_UNKNOWN_PROPERTY | |
89 | * The hypervisor does not recognize the specified partition property. | |
90 | */ | |
91 | #define HV_STATUS_UNKNOWN_PROPERTY ((u16)0x0009) | |
92 | ||
93 | /* | |
94 | * HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE | |
95 | * The specified value of a partition property is out of range or violates an | |
96 | * invariant. | |
97 | */ | |
98 | #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE ((u16)0x000A) | |
99 | ||
100 | /* | |
101 | * HV_STATUS_INSUFFICIENT_MEMORY | |
102 | * There is not enough memory in the hypervisor pool to complete the operation. | |
103 | */ | |
104 | #define HV_STATUS_INSUFFICIENT_MEMORY ((u16)0x000B) | |
105 | ||
106 | /* | |
107 | * HV_STATUS_PARTITION_TOO_DEEP | |
108 | * The maximum partition depth has been exceeded for the partition hierarchy. | |
109 | */ | |
110 | #define HV_STATUS_PARTITION_TOO_DEEP ((u16)0x000C) | |
111 | ||
112 | /* | |
113 | * HV_STATUS_INVALID_PARTITION_ID | |
114 | * A partition with the specified partition Id does not exist. | |
115 | */ | |
116 | #define HV_STATUS_INVALID_PARTITION_ID ((u16)0x000D) | |
117 | ||
118 | /* | |
119 | * HV_STATUS_INVALID_VP_INDEX | |
120 | * The hypervisor could not perform the operation because the specified VP | |
121 | * index is invalid. | |
122 | */ | |
123 | #define HV_STATUS_INVALID_VP_INDEX ((u16)0x000E) | |
124 | ||
125 | /* | |
126 | * HV_STATUS_NOT_FOUND | |
127 | * The iteration is complete; no addition items in the iteration could be | |
128 | * found. | |
129 | */ | |
130 | #define HV_STATUS_NOT_FOUND ((u16)0x0010) | |
131 | ||
132 | /* | |
133 | * HV_STATUS_INVALID_PORT_ID | |
134 | * The hypervisor could not perform the operation because the specified port | |
135 | * identifier is invalid. | |
136 | */ | |
137 | #define HV_STATUS_INVALID_PORT_ID ((u16)0x0011) | |
138 | ||
139 | /* | |
140 | * HV_STATUS_INVALID_CONNECTION_ID | |
141 | * The hypervisor could not perform the operation because the specified | |
142 | * connection identifier is invalid. | |
143 | */ | |
144 | #define HV_STATUS_INVALID_CONNECTION_ID ((u16)0x0012) | |
145 | ||
146 | /* | |
147 | * HV_STATUS_INSUFFICIENT_BUFFERS | |
148 | * You did not supply enough message buffers to send a message. | |
149 | */ | |
150 | #define HV_STATUS_INSUFFICIENT_BUFFERS ((u16)0x0013) | |
151 | ||
152 | /* | |
153 | * HV_STATUS_NOT_ACKNOWLEDGED | |
154 | * The previous virtual interrupt has not been acknowledged. | |
155 | */ | |
156 | #define HV_STATUS_NOT_ACKNOWLEDGED ((u16)0x0014) | |
157 | ||
158 | /* | |
159 | * HV_STATUS_INVALID_VP_STATE | |
160 | * A virtual processor is not in the correct state for the performance of the | |
161 | * indicated operation. | |
162 | */ | |
163 | #define HV_STATUS_INVALID_VP_STATE ((u16)0x0015) | |
164 | ||
165 | /* | |
166 | * HV_STATUS_ACKNOWLEDGED | |
167 | * The previous virtual interrupt has already been acknowledged. | |
168 | */ | |
169 | #define HV_STATUS_ACKNOWLEDGED ((u16)0x0016) | |
170 | ||
171 | /* | |
172 | * HV_STATUS_INVALID_SAVE_RESTORE_STATE | |
173 | * The indicated partition is not in a valid state for saving or restoring. | |
174 | */ | |
175 | #define HV_STATUS_INVALID_SAVE_RESTORE_STATE ((u16)0x0017) | |
176 | ||
177 | /* | |
178 | * HV_STATUS_INVALID_SYNIC_STATE | |
179 | * The hypervisor could not complete the operation because a required feature | |
180 | * of the synthetic interrupt controller (SynIC) was disabled. | |
181 | */ | |
182 | #define HV_STATUS_INVALID_SYNIC_STATE ((u16)0x0018) | |
183 | ||
184 | /* | |
185 | * HV_STATUS_OBJECT_IN_USE | |
186 | * The hypervisor could not perform the operation because the object or value | |
187 | * was either already in use or being used for a purpose that would not permit | |
188 | * completing the operation. | |
189 | */ | |
190 | #define HV_STATUS_OBJECT_IN_USE ((u16)0x0019) | |
191 | ||
192 | /* | |
193 | * HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO | |
194 | * The proximity domain information is invalid. | |
195 | */ | |
196 | #define HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO ((u16)0x001A) | |
197 | ||
198 | /* | |
199 | * HV_STATUS_NO_DATA | |
200 | * An attempt to retrieve debugging data failed because none was available. | |
201 | */ | |
202 | #define HV_STATUS_NO_DATA ((u16)0x001B) | |
203 | ||
204 | /* | |
205 | * HV_STATUS_INACTIVE | |
206 | * The physical connection being used for debuggging has not recorded any | |
207 | * receive activity since the last operation. | |
208 | */ | |
209 | #define HV_STATUS_INACTIVE ((u16)0x001C) | |
210 | ||
211 | /* | |
212 | * HV_STATUS_NO_RESOURCES | |
213 | * There are not enough resources to complete the operation. | |
214 | */ | |
215 | #define HV_STATUS_NO_RESOURCES ((u16)0x001D) | |
216 | ||
217 | /* | |
218 | * HV_STATUS_FEATURE_UNAVAILABLE | |
219 | * A hypervisor feature is not available to the user. | |
220 | */ | |
221 | #define HV_STATUS_FEATURE_UNAVAILABLE ((u16)0x001E) | |
222 | ||
223 | /* | |
224 | * HV_STATUS_UNSUCCESSFUL | |
225 | * {Operation Failed} The requested operation was unsuccessful. | |
226 | */ | |
227 | #define HV_STATUS_UNSUCCESSFUL ((u16)0x1001) | |
228 | ||
229 | /* | |
230 | * HV_STATUS_INSUFFICIENT_BUFFER | |
231 | * The specified buffer was too small to contain all of the requested data. | |
232 | */ | |
233 | #define HV_STATUS_INSUFFICIENT_BUFFER ((u16)0x1002) | |
234 | ||
235 | /* | |
236 | * HV_STATUS_GPA_NOT_PRESENT | |
237 | * The guest physical address is not currently associated with a system | |
238 | * physical address. | |
239 | */ | |
240 | #define HV_STATUS_GPA_NOT_PRESENT ((u16)0x1003) | |
241 | ||
242 | /* | |
243 | * HV_STATUS_GUEST_PAGE_FAULT | |
244 | * The operation would have resulted in a page fault in the guest. | |
245 | */ | |
246 | #define HV_STATUS_GUEST_PAGE_FAULT ((u16)0x1004) | |
247 | ||
248 | /* | |
249 | * HV_STATUS_RUNDOWN_DISABLED | |
250 | * The operation cannot proceed as the rundown object was marked disabled. | |
251 | */ | |
252 | #define HV_STATUS_RUNDOWN_DISABLED ((u16)0x1005) | |
253 | ||
254 | /* | |
255 | * HV_STATUS_KEY_ALREADY_EXISTS | |
256 | * The entry cannot be added as another entry with the same key already exists. | |
257 | */ | |
258 | #define HV_STATUS_KEY_ALREADY_EXISTS ((u16)0x1006) | |
259 | ||
260 | /* | |
261 | * HV_STATUS_GPA_INTERCEPT | |
262 | * The operation resulted an intercept on a region of guest physical memory. | |
263 | */ | |
264 | #define HV_STATUS_GPA_INTERCEPT ((u16)0x1007) | |
265 | ||
266 | /* | |
267 | * HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT | |
268 | * The operation would have resulted in a general protection fault in the | |
269 | * guest. | |
270 | */ | |
271 | #define HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT ((u16)0x1008) | |
272 | ||
273 | /* | |
274 | * HV_STATUS_GUEST_STACK_FAULT | |
275 | * The operation would have resulted in a stack fault in the guest. | |
276 | */ | |
277 | #define HV_STATUS_GUEST_STACK_FAULT ((u16)0x1009) | |
278 | ||
279 | /* | |
280 | * HV_STATUS_GUEST_INVALID_OPCODE_FAULT | |
281 | * The operation would have resulted in an invalid opcode fault in the guest. | |
282 | */ | |
283 | #define HV_STATUS_GUEST_INVALID_OPCODE_FAULT ((u16)0x100A) | |
284 | ||
285 | /* | |
286 | * HV_STATUS_FINALIZE_INCOMPLETE | |
287 | * The partition is not completely finalized. | |
288 | */ | |
289 | #define HV_STATUS_FINALIZE_INCOMPLETE ((u16)0x100B) | |
290 | ||
291 | /* | |
292 | * HV_STATUS_GUEST_MACHINE_CHECK_ABORT | |
293 | * The operation would have resulted in an machine check abort in the guest. | |
294 | */ | |
295 | #define HV_STATUS_GUEST_MACHINE_CHECK_ABORT ((u16)0x100C) | |
296 | ||
297 | /* | |
298 | * HV_STATUS_ILLEGAL_OVERLAY_ACCESS | |
299 | * An illegal access was attempted to an overlay page. | |
300 | */ | |
301 | #define HV_STATUS_ILLEGAL_OVERLAY_ACCESS ((u16)0x100D) | |
302 | ||
303 | /* | |
304 | * HV_STATUS_INSUFFICIENT_SYSTEM_VA | |
305 | * There is not enough system VA space available to satisfy the request, | |
306 | */ | |
307 | #define HV_STATUS_INSUFFICIENT_SYSTEM_VA ((u16)0x100E) | |
308 | ||
309 | /* | |
310 | * HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED | |
311 | * The passed virtual address was not mapped in the hypervisor address space. | |
312 | */ | |
313 | #define HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED ((u16)0x100F) | |
314 | ||
315 | /* | |
316 | * HV_STATUS_NOT_IMPLEMENTED | |
317 | * The requested operation is not implemented in this version of the | |
318 | * hypervisor. | |
319 | */ | |
320 | #define HV_STATUS_NOT_IMPLEMENTED ((u16)0x1010) | |
321 | ||
322 | /* | |
323 | * HV_STATUS_VMX_INSTRUCTION_FAILED | |
bbc9a991 | 324 | * The requested VMX instruction failed to complete successfully. |
65452d1f GKH |
325 | */ |
326 | #define HV_STATUS_VMX_INSTRUCTION_FAILED ((u16)0x1011) | |
327 | ||
328 | /* | |
329 | * HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS | |
bbc9a991 | 330 | * The requested VMX instruction failed to complete successfully indicating |
65452d1f GKH |
331 | * status. |
332 | */ | |
333 | #define HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS ((u16)0x1012) | |
334 | ||
335 | /* | |
336 | * HV_STATUS_MSR_ACCESS_FAILED | |
337 | * The requested access to the model specific register failed. | |
338 | */ | |
339 | #define HV_STATUS_MSR_ACCESS_FAILED ((u16)0x1013) | |
340 | ||
341 | /* | |
342 | * HV_STATUS_CR_ACCESS_FAILED | |
343 | * The requested access to the control register failed. | |
344 | */ | |
345 | #define HV_STATUS_CR_ACCESS_FAILED ((u16)0x1014) | |
346 | ||
347 | /* | |
348 | * HV_STATUS_TIMEOUT | |
349 | * The specified timeout expired before the operation completed. | |
350 | */ | |
351 | #define HV_STATUS_TIMEOUT ((u16)0x1016) | |
352 | ||
353 | /* | |
354 | * HV_STATUS_MSR_INTERCEPT | |
355 | * The requested access to the model specific register generated an intercept. | |
356 | */ | |
357 | #define HV_STATUS_MSR_INTERCEPT ((u16)0x1017) | |
358 | ||
359 | /* | |
360 | * HV_STATUS_CPUID_INTERCEPT | |
361 | * The CPUID instruction generated an intercept. | |
362 | */ | |
363 | #define HV_STATUS_CPUID_INTERCEPT ((u16)0x1018) | |
364 | ||
365 | /* | |
366 | * HV_STATUS_REPEAT_INSTRUCTION | |
367 | * The current instruction should be repeated and the instruction pointer not | |
368 | * advanced. | |
369 | */ | |
370 | #define HV_STATUS_REPEAT_INSTRUCTION ((u16)0x1019) | |
371 | ||
372 | /* | |
373 | * HV_STATUS_PAGE_PROTECTION_VIOLATION | |
374 | * The current instruction should be repeated and the instruction pointer not | |
375 | * advanced. | |
376 | */ | |
377 | #define HV_STATUS_PAGE_PROTECTION_VIOLATION ((u16)0x101A) | |
378 | ||
379 | /* | |
380 | * HV_STATUS_PAGE_TABLE_INVALID | |
381 | * The current instruction should be repeated and the instruction pointer not | |
382 | * advanced. | |
383 | */ | |
384 | #define HV_STATUS_PAGE_TABLE_INVALID ((u16)0x101B) | |
385 | ||
386 | /* | |
387 | * HV_STATUS_PAGE_NOT_PRESENT | |
388 | * The current instruction should be repeated and the instruction pointer not | |
389 | * advanced. | |
390 | */ | |
391 | #define HV_STATUS_PAGE_NOT_PRESENT ((u16)0x101C) | |
392 | ||
393 | /* | |
394 | * HV_STATUS_IO_INTERCEPT | |
395 | * The requested access to the I/O port generated an intercept. | |
396 | */ | |
397 | #define HV_STATUS_IO_INTERCEPT ((u16)0x101D) | |
398 | ||
399 | /* | |
400 | * HV_STATUS_NOTHING_TO_DO | |
401 | * There is nothing to do. | |
402 | */ | |
403 | #define HV_STATUS_NOTHING_TO_DO ((u16)0x101E) | |
404 | ||
405 | /* | |
406 | * HV_STATUS_THREAD_TERMINATING | |
407 | * The requested thread is terminating. | |
408 | */ | |
409 | #define HV_STATUS_THREAD_TERMINATING ((u16)0x101F) | |
410 | ||
411 | /* | |
412 | * HV_STATUS_SECTION_ALREADY_CONSTRUCTED | |
413 | * The specified section was already constructed. | |
414 | */ | |
415 | #define HV_STATUS_SECTION_ALREADY_CONSTRUCTED ((u16)0x1020) | |
416 | ||
417 | /* HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED | |
418 | * The specified section was not already constructed. | |
419 | */ | |
420 | #define HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED ((u16)0x1021) | |
421 | ||
422 | /* | |
423 | * HV_STATUS_PAGE_ALREADY_COMMITTED | |
424 | * The specified virtual address was already backed by physical memory. | |
425 | */ | |
426 | #define HV_STATUS_PAGE_ALREADY_COMMITTED ((u16)0x1022) | |
427 | ||
428 | /* | |
429 | * HV_STATUS_PAGE_NOT_ALREADY_COMMITTED | |
430 | * The specified virtual address was not already backed by physical memory. | |
431 | */ | |
432 | #define HV_STATUS_PAGE_NOT_ALREADY_COMMITTED ((u16)0x1023) | |
433 | ||
434 | /* | |
435 | * HV_STATUS_COMMITTED_PAGES_REMAIN | |
436 | * Committed pages remain in the section. | |
437 | */ | |
438 | #define HV_STATUS_COMMITTED_PAGES_REMAIN ((u16)0x1024) | |
439 | ||
440 | /* | |
441 | * HV_STATUS_NO_REMAINING_COMMITTED_PAGES | |
442 | * No additional committed pages beyond the specified page exist in the | |
443 | * section. | |
444 | */ | |
445 | #define HV_STATUS_NO_REMAINING_COMMITTED_PAGES ((u16)0x1025) | |
446 | ||
447 | /* | |
448 | * HV_STATUS_INSUFFICIENT_COMPARTMENT_VA | |
449 | * The VA space of the compartment is exhausted. | |
450 | */ | |
451 | #define HV_STATUS_INSUFFICIENT_COMPARTMENT_VA ((u16)0x1026) | |
452 | ||
453 | /* | |
454 | * HV_STATUS_DEREF_SPA_LIST_FULL | |
455 | * The SPA dereference list is full, and there are additional entries to be | |
456 | * added to it. | |
457 | */ | |
458 | #define HV_STATUS_DEREF_SPA_LIST_FULL ((u16)0x1027) | |
459 | ||
460 | /* | |
461 | * HV_STATUS_GPA_OUT_OF_RANGE | |
462 | * The supplied GPA is out of range. | |
463 | */ | |
464 | #define HV_STATUS_GPA_OUT_OF_RANGE ((u16)0x1027) | |
465 | ||
466 | /* | |
467 | * HV_STATUS_NONVOLATILE_XMM_STALE | |
468 | * The XMM register that was being accessed is stale. | |
469 | */ | |
470 | #define HV_STATUS_NONVOLATILE_XMM_STALE ((u16)0x1028) | |
471 | ||
472 | /* HV_STATUS_UNSUPPORTED_PROCESSOR | |
473 | * The hypervisor does not support the processors in this system. | |
474 | */ | |
475 | #define HV_STATUS_UNSUPPORTED_PROCESSOR ((u16)0x1029) | |
476 | ||
477 | /* | |
478 | * HV_STATUS_INSUFFICIENT_CROM_SPACE | |
479 | * Insufficient space existed for copying over the CROM contents. | |
480 | */ | |
481 | #define HV_STATUS_INSUFFICIENT_CROM_SPACE ((u16)0x2000) | |
482 | ||
483 | /* | |
484 | * HV_STATUS_BAD_CROM_FORMAT | |
485 | * The contents of the CROM failed validation attempts. | |
486 | */ | |
487 | #define HV_STATUS_BAD_CROM_FORMAT ((u16)0x2001) | |
488 | ||
489 | /* | |
490 | * HV_STATUS_UNSUPPORTED_CROM_FORMAT | |
491 | * The contents of the CROM contain contents the parser doesn't support. | |
492 | */ | |
493 | #define HV_STATUS_UNSUPPORTED_CROM_FORMAT ((u16)0x2002) | |
494 | ||
495 | /* | |
496 | * HV_STATUS_UNSUPPORTED_CONTROLLER | |
497 | * The register format of the OHCI controller specified for debugging is not | |
498 | * supported. | |
499 | */ | |
500 | #define HV_STATUS_UNSUPPORTED_CONTROLLER ((u16)0x2003) | |
501 | ||
502 | /* | |
503 | * HV_STATUS_CROM_TOO_LARGE | |
504 | * The CROM contents were to large to copy over. | |
505 | */ | |
506 | #define HV_STATUS_CROM_TOO_LARGE ((u16)0x2004) | |
507 | ||
508 | /* | |
509 | * HV_STATUS_CONTROLLER_IN_USE | |
510 | * The OHCI controller specified for debugging cannot be used as it is already | |
511 | * in use. | |
512 | */ | |
513 | #define HV_STATUS_CONTROLLER_IN_USE ((u16)0x2005) | |
514 | ||
515 | ||
6658be6a GKH |
516 | /* |
517 | * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent | |
f6feebe0 | 518 | * is set by CPUID(HVCPUID_VERSION_FEATURES). |
6658be6a GKH |
519 | */ |
520 | enum hv_cpuid_function { | |
f6feebe0 HZ |
521 | HVCPUID_VERSION_FEATURES = 0x00000001, |
522 | HVCPUID_VENDOR_MAXFUNCTION = 0x40000000, | |
523 | HVCPUID_INTERFACE = 0x40000001, | |
6658be6a GKH |
524 | |
525 | /* | |
526 | * The remaining functions depend on the value of | |
f6feebe0 | 527 | * HVCPUID_INTERFACE |
6658be6a | 528 | */ |
f6feebe0 HZ |
529 | HVCPUID_VERSION = 0x40000002, |
530 | HVCPUID_FEATURES = 0x40000003, | |
531 | HVCPUID_ENLIGHTENMENT_INFO = 0x40000004, | |
532 | HVCPUID_IMPLEMENTATION_LIMITS = 0x40000005, | |
6658be6a | 533 | }; |
454f18a9 BP |
534 | |
535 | /* Define the virtual APIC registers */ | |
c786a84e GKH |
536 | #define HV_X64_MSR_EOI (0x40000070) |
537 | #define HV_X64_MSR_ICR (0x40000071) | |
538 | #define HV_X64_MSR_TPR (0x40000072) | |
539 | #define HV_X64_MSR_APIC_ASSIST_PAGE (0x40000073) | |
454f18a9 BP |
540 | |
541 | /* Define version of the synthetic interrupt controller. */ | |
c786a84e | 542 | #define HV_SYNIC_VERSION (1) |
454f18a9 BP |
543 | |
544 | /* Define synthetic interrupt controller model specific registers. */ | |
c786a84e GKH |
545 | #define HV_X64_MSR_SCONTROL (0x40000080) |
546 | #define HV_X64_MSR_SVERSION (0x40000081) | |
547 | #define HV_X64_MSR_SIEFP (0x40000082) | |
548 | #define HV_X64_MSR_SIMP (0x40000083) | |
549 | #define HV_X64_MSR_EOM (0x40000084) | |
550 | #define HV_X64_MSR_SINT0 (0x40000090) | |
551 | #define HV_X64_MSR_SINT1 (0x40000091) | |
552 | #define HV_X64_MSR_SINT2 (0x40000092) | |
553 | #define HV_X64_MSR_SINT3 (0x40000093) | |
554 | #define HV_X64_MSR_SINT4 (0x40000094) | |
555 | #define HV_X64_MSR_SINT5 (0x40000095) | |
556 | #define HV_X64_MSR_SINT6 (0x40000096) | |
557 | #define HV_X64_MSR_SINT7 (0x40000097) | |
558 | #define HV_X64_MSR_SINT8 (0x40000098) | |
559 | #define HV_X64_MSR_SINT9 (0x40000099) | |
560 | #define HV_X64_MSR_SINT10 (0x4000009A) | |
561 | #define HV_X64_MSR_SINT11 (0x4000009B) | |
562 | #define HV_X64_MSR_SINT12 (0x4000009C) | |
563 | #define HV_X64_MSR_SINT13 (0x4000009D) | |
564 | #define HV_X64_MSR_SINT14 (0x4000009E) | |
565 | #define HV_X64_MSR_SINT15 (0x4000009F) | |
454f18a9 BP |
566 | |
567 | /* Define the expected SynIC version. */ | |
c786a84e | 568 | #define HV_SYNIC_VERSION_1 (0x1) |
454f18a9 BP |
569 | |
570 | /* Define synthetic interrupt controller message constants. */ | |
c786a84e GKH |
571 | #define HV_MESSAGE_SIZE (256) |
572 | #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) | |
573 | #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) | |
574 | #define HV_ANY_VP (0xFFFFFFFF) | |
454f18a9 BP |
575 | |
576 | /* Define synthetic interrupt controller flag constants. */ | |
c786a84e GKH |
577 | #define HV_EVENT_FLAGS_COUNT (256 * 8) |
578 | #define HV_EVENT_FLAGS_BYTE_COUNT (256) | |
579 | #define HV_EVENT_FLAGS_DWORD_COUNT (256 / sizeof(u32)) | |
454f18a9 BP |
580 | |
581 | /* Define hypervisor message types. */ | |
eacb1b4d | 582 | enum hv_message_type { |
f6feebe0 | 583 | HVMSG_NONE = 0x00000000, |
c786a84e GKH |
584 | |
585 | /* Memory access messages. */ | |
f6feebe0 HZ |
586 | HVMSG_UNMAPPED_GPA = 0x80000000, |
587 | HVMSG_GPA_INTERCEPT = 0x80000001, | |
c786a84e GKH |
588 | |
589 | /* Timer notification messages. */ | |
f6feebe0 | 590 | HVMSG_TIMER_EXPIRED = 0x80000010, |
c786a84e GKH |
591 | |
592 | /* Error messages. */ | |
f6feebe0 HZ |
593 | HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, |
594 | HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, | |
595 | HVMSG_UNSUPPORTED_FEATURE = 0x80000022, | |
c786a84e GKH |
596 | |
597 | /* Trace buffer complete messages. */ | |
f6feebe0 | 598 | HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, |
c786a84e GKH |
599 | |
600 | /* Platform-specific processor intercept messages. */ | |
f6feebe0 HZ |
601 | HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, |
602 | HVMSG_X64_MSR_INTERCEPT = 0x80010001, | |
603 | HVMSG_X64_CPUID_INTERCEPT = 0x80010002, | |
604 | HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, | |
605 | HVMSG_X64_APIC_EOI = 0x80010004, | |
606 | HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 | |
eacb1b4d | 607 | }; |
565e7dc8 | 608 | |
454f18a9 | 609 | /* Define the number of synthetic interrupt sources. */ |
c786a84e GKH |
610 | #define HV_SYNIC_SINT_COUNT (16) |
611 | #define HV_SYNIC_STIMER_COUNT (4) | |
454f18a9 | 612 | |
454f18a9 | 613 | /* Define invalid partition identifier. */ |
eacb1b4d | 614 | #define HV_PARTITION_ID_INVALID ((u64)0x0) |
454f18a9 BP |
615 | |
616 | /* Define connection identifier type. */ | |
eacb1b4d | 617 | union hv_connection_id { |
f6feebe0 | 618 | u32 asu32; |
c786a84e | 619 | struct { |
f6feebe0 HZ |
620 | u32 id:24; |
621 | u32 reserved:8; | |
c786a84e | 622 | } u; |
eacb1b4d | 623 | }; |
565e7dc8 | 624 | |
454f18a9 | 625 | /* Define port identifier type. */ |
eacb1b4d | 626 | union hv_port_id { |
f6feebe0 | 627 | u32 asu32; |
c786a84e | 628 | struct { |
f6feebe0 HZ |
629 | u32 id:24; |
630 | u32 reserved:8; | |
c786a84e | 631 | } u ; |
eacb1b4d | 632 | }; |
565e7dc8 | 633 | |
454f18a9 | 634 | /* Define port type. */ |
eacb1b4d | 635 | enum hv_port_type { |
f6feebe0 HZ |
636 | HVPORT_MSG = 1, |
637 | HVPORT_EVENT = 2, | |
638 | HVPORT_MONITOR = 3 | |
eacb1b4d | 639 | }; |
565e7dc8 | 640 | |
454f18a9 | 641 | /* Define port information structure. */ |
eacb1b4d | 642 | struct hv_port_info { |
f6feebe0 HZ |
643 | enum hv_port_type port_type; |
644 | u32 padding; | |
c786a84e GKH |
645 | union { |
646 | struct { | |
f6feebe0 HZ |
647 | u32 target_sint; |
648 | u32 target_vp; | |
649 | u64 rsvdz; | |
650 | } message_port_info; | |
c786a84e | 651 | struct { |
f6feebe0 HZ |
652 | u32 target_sint; |
653 | u32 target_vp; | |
654 | u16 base_flag_bumber; | |
655 | u16 flag_count; | |
656 | u32 rsvdz; | |
657 | } event_port_info; | |
c786a84e | 658 | struct { |
f6feebe0 HZ |
659 | u64 monitor_address; |
660 | u64 rsvdz; | |
661 | } monitor_port_info; | |
c786a84e | 662 | }; |
eacb1b4d | 663 | }; |
565e7dc8 | 664 | |
eacb1b4d | 665 | struct hv_connection_info { |
f6feebe0 HZ |
666 | enum hv_port_type port_type; |
667 | u32 padding; | |
c786a84e GKH |
668 | union { |
669 | struct { | |
f6feebe0 HZ |
670 | u64 rsvdz; |
671 | } message_connection_info; | |
c786a84e | 672 | struct { |
f6feebe0 HZ |
673 | u64 rsvdz; |
674 | } event_connection_info; | |
c786a84e | 675 | struct { |
f6feebe0 HZ |
676 | u64 monitor_address; |
677 | } monitor_connection_info; | |
c786a84e | 678 | }; |
eacb1b4d | 679 | }; |
565e7dc8 | 680 | |
454f18a9 | 681 | /* Define synthetic interrupt controller message flags. */ |
eacb1b4d | 682 | union hv_message_flags { |
f6feebe0 | 683 | u8 asu8; |
c786a84e | 684 | struct { |
f6feebe0 HZ |
685 | u8 msg_pending:1; |
686 | u8 reserved:7; | |
c786a84e | 687 | }; |
eacb1b4d | 688 | }; |
565e7dc8 | 689 | |
454f18a9 | 690 | /* Define synthetic interrupt controller message header. */ |
eacb1b4d | 691 | struct hv_message_header { |
f6feebe0 HZ |
692 | enum hv_message_type message_type; |
693 | u8 payload_size; | |
694 | union hv_message_flags message_flags; | |
695 | u8 reserved[2]; | |
c786a84e | 696 | union { |
f6feebe0 HZ |
697 | u64 sender; |
698 | union hv_port_id port; | |
c786a84e | 699 | }; |
eacb1b4d | 700 | }; |
565e7dc8 | 701 | |
454f18a9 | 702 | /* Define timer message payload structure. */ |
eacb1b4d | 703 | struct hv_timer_message_payload { |
f6feebe0 HZ |
704 | u32 timer_index; |
705 | u32 reserved; | |
706 | u64 expiration_time; /* When the timer expired */ | |
707 | u64 delivery_time; /* When the message was delivered */ | |
eacb1b4d | 708 | }; |
565e7dc8 | 709 | |
454f18a9 | 710 | /* Define synthetic interrupt controller message format. */ |
eacb1b4d | 711 | struct hv_message { |
f6feebe0 | 712 | struct hv_message_header header; |
c786a84e | 713 | union { |
f6feebe0 | 714 | u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; |
c786a84e | 715 | } u ; |
eacb1b4d | 716 | }; |
565e7dc8 | 717 | |
454f18a9 | 718 | /* Define the number of message buffers associated with each port. */ |
c786a84e | 719 | #define HV_PORT_MESSAGE_BUFFER_COUNT (16) |
454f18a9 BP |
720 | |
721 | /* Define the synthetic interrupt message page layout. */ | |
eacb1b4d | 722 | struct hv_message_page { |
f6feebe0 | 723 | struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; |
eacb1b4d | 724 | }; |
565e7dc8 | 725 | |
454f18a9 | 726 | /* Define the synthetic interrupt controller event flags format. */ |
eacb1b4d | 727 | union hv_synic_event_flags { |
f6feebe0 HZ |
728 | u8 flags8[HV_EVENT_FLAGS_BYTE_COUNT]; |
729 | u32 flags32[HV_EVENT_FLAGS_DWORD_COUNT]; | |
eacb1b4d | 730 | }; |
565e7dc8 | 731 | |
454f18a9 | 732 | /* Define the synthetic interrupt flags page layout. */ |
eacb1b4d | 733 | struct hv_synic_event_flags_page { |
f6feebe0 | 734 | union hv_synic_event_flags sintevent_flags[HV_SYNIC_SINT_COUNT]; |
eacb1b4d | 735 | }; |
565e7dc8 | 736 | |
454f18a9 | 737 | /* Define SynIC control register. */ |
eacb1b4d | 738 | union hv_synic_scontrol { |
f6feebe0 | 739 | u64 as_uint64; |
c786a84e | 740 | struct { |
f6feebe0 HZ |
741 | u64 enable:1; |
742 | u64 reserved:63; | |
c786a84e | 743 | }; |
eacb1b4d | 744 | }; |
565e7dc8 | 745 | |
454f18a9 | 746 | /* Define synthetic interrupt source. */ |
eacb1b4d | 747 | union hv_synic_sint { |
f6feebe0 | 748 | u64 as_uint64; |
c786a84e | 749 | struct { |
f6feebe0 HZ |
750 | u64 vector:8; |
751 | u64 reserved1:8; | |
752 | u64 masked:1; | |
753 | u64 auto_eoi:1; | |
754 | u64 reserved2:46; | |
c786a84e | 755 | }; |
eacb1b4d | 756 | }; |
565e7dc8 | 757 | |
454f18a9 | 758 | /* Define the format of the SIMP register */ |
eacb1b4d | 759 | union hv_synic_simp { |
f6feebe0 | 760 | u64 as_uint64; |
c786a84e | 761 | struct { |
f6feebe0 HZ |
762 | u64 simp_enabled:1; |
763 | u64 preserved:11; | |
764 | u64 base_simp_gpa:52; | |
c786a84e | 765 | }; |
eacb1b4d | 766 | }; |
454f18a9 BP |
767 | |
768 | /* Define the format of the SIEFP register */ | |
eacb1b4d | 769 | union hv_synic_siefp { |
f6feebe0 | 770 | u64 as_uint64; |
c786a84e | 771 | struct { |
f6feebe0 HZ |
772 | u64 siefp_enabled:1; |
773 | u64 preserved:11; | |
774 | u64 base_siefp_gpa:52; | |
c786a84e | 775 | }; |
eacb1b4d | 776 | }; |
565e7dc8 | 777 | |
454f18a9 | 778 | /* Definitions for the monitored notification facility */ |
eacb1b4d | 779 | union hv_monitor_trigger_group { |
f6feebe0 | 780 | u64 as_uint64; |
c786a84e | 781 | struct { |
f6feebe0 HZ |
782 | u32 pending; |
783 | u32 armed; | |
c786a84e | 784 | }; |
eacb1b4d | 785 | }; |
565e7dc8 | 786 | |
eacb1b4d | 787 | struct hv_monitor_parameter { |
f6feebe0 HZ |
788 | union hv_connection_id connectionid; |
789 | u16 flagnumber; | |
790 | u16 rsvdz; | |
eacb1b4d | 791 | }; |
565e7dc8 | 792 | |
eacb1b4d | 793 | union hv_monitor_trigger_state { |
f6feebe0 | 794 | u32 asu32; |
565e7dc8 | 795 | |
c786a84e | 796 | struct { |
f6feebe0 HZ |
797 | u32 group_enable:4; |
798 | u32 rsvdz:28; | |
c786a84e | 799 | }; |
eacb1b4d | 800 | }; |
565e7dc8 | 801 | |
eacb1b4d | 802 | /* struct hv_monitor_page Layout */ |
454f18a9 BP |
803 | /* ------------------------------------------------------ */ |
804 | /* | 0 | TriggerState (4 bytes) | Rsvd1 (4 bytes) | */ | |
805 | /* | 8 | TriggerGroup[0] | */ | |
806 | /* | 10 | TriggerGroup[1] | */ | |
807 | /* | 18 | TriggerGroup[2] | */ | |
808 | /* | 20 | TriggerGroup[3] | */ | |
809 | /* | 28 | Rsvd2[0] | */ | |
810 | /* | 30 | Rsvd2[1] | */ | |
811 | /* | 38 | Rsvd2[2] | */ | |
812 | /* | 40 | NextCheckTime[0][0] | NextCheckTime[0][1] | */ | |
813 | /* | ... | */ | |
814 | /* | 240 | Latency[0][0..3] | */ | |
815 | /* | 340 | Rsvz3[0] | */ | |
816 | /* | 440 | Parameter[0][0] | */ | |
817 | /* | 448 | Parameter[0][1] | */ | |
818 | /* | ... | */ | |
819 | /* | 840 | Rsvd4[0] | */ | |
820 | /* ------------------------------------------------------ */ | |
eacb1b4d | 821 | struct hv_monitor_page { |
f6feebe0 HZ |
822 | union hv_monitor_trigger_state trigger_state; |
823 | u32 rsvdz1; | |
565e7dc8 | 824 | |
f6feebe0 HZ |
825 | union hv_monitor_trigger_group trigger_group[4]; |
826 | u64 rsvdz2[3]; | |
565e7dc8 | 827 | |
f6feebe0 | 828 | s32 next_checktime[4][32]; |
565e7dc8 | 829 | |
f6feebe0 HZ |
830 | u16 latency[4][32]; |
831 | u64 rsvdz3[32]; | |
565e7dc8 | 832 | |
f6feebe0 | 833 | struct hv_monitor_parameter parameter[4][32]; |
565e7dc8 | 834 | |
f6feebe0 | 835 | u8 rsvdz4[1984]; |
eacb1b4d | 836 | }; |
c786a84e | 837 | |
6658be6a GKH |
838 | /* Declare the various hypercall operations. */ |
839 | enum hv_call_code { | |
f6feebe0 HZ |
840 | HVCALL_POST_MESSAGE = 0x005c, |
841 | HVCALL_SIGNAL_EVENT = 0x005d, | |
6658be6a GKH |
842 | }; |
843 | ||
d44890c8 | 844 | /* Definition of the hv_post_message hypercall input structure. */ |
6658be6a | 845 | struct hv_input_post_message { |
f6feebe0 HZ |
846 | union hv_connection_id connectionid; |
847 | u32 reserved; | |
848 | enum hv_message_type message_type; | |
849 | u32 payload_size; | |
850 | u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; | |
6658be6a GKH |
851 | }; |
852 | ||
d44890c8 | 853 | /* Definition of the hv_signal_event hypercall input structure. */ |
6658be6a | 854 | struct hv_input_signal_event { |
f6feebe0 HZ |
855 | union hv_connection_id connectionid; |
856 | u16 flag_number; | |
857 | u16 rsvdz; | |
6658be6a GKH |
858 | }; |
859 | ||
860 | /* | |
861 | * Versioning definitions used for guests reporting themselves to the | |
862 | * hypervisor, and visa versa. | |
863 | */ | |
864 | ||
865 | /* Version info reported by guest OS's */ | |
866 | enum hv_guest_os_vendor { | |
f6feebe0 | 867 | HVGUESTOS_VENDOR_MICROSOFT = 0x0001 |
6658be6a GKH |
868 | }; |
869 | ||
870 | enum hv_guest_os_microsoft_ids { | |
f6feebe0 HZ |
871 | HVGUESTOS_MICROSOFT_UNDEFINED = 0x00, |
872 | HVGUESTOS_MICROSOFT_MSDOS = 0x01, | |
873 | HVGUESTOS_MICROSOFT_WINDOWS3X = 0x02, | |
874 | HVGUESTOS_MICROSOFT_WINDOWS9X = 0x03, | |
875 | HVGUESTOS_MICROSOFT_WINDOWSNT = 0x04, | |
876 | HVGUESTOS_MICROSOFT_WINDOWSCE = 0x05 | |
6658be6a GKH |
877 | }; |
878 | ||
879 | /* | |
880 | * Declare the MSR used to identify the guest OS. | |
881 | */ | |
882 | #define HV_X64_MSR_GUEST_OS_ID 0x40000000 | |
883 | ||
884 | union hv_x64_msr_guest_os_id_contents { | |
f6feebe0 | 885 | u64 as_uint64; |
6658be6a | 886 | struct { |
f6feebe0 HZ |
887 | u64 build_number:16; |
888 | u64 service_version:8; /* Service Pack, etc. */ | |
889 | u64 minor_version:8; | |
890 | u64 major_version:8; | |
891 | u64 os_id:8; /* enum hv_guest_os_microsoft_ids (if Vendor=MS) */ | |
892 | u64 vendor_id:16; /* enum hv_guest_os_vendor */ | |
6658be6a GKH |
893 | }; |
894 | }; | |
895 | ||
896 | /* | |
897 | * Declare the MSR used to setup pages used to communicate with the hypervisor. | |
898 | */ | |
899 | #define HV_X64_MSR_HYPERCALL 0x40000001 | |
900 | ||
901 | union hv_x64_msr_hypercall_contents { | |
f6feebe0 | 902 | u64 as_uint64; |
6658be6a | 903 | struct { |
f6feebe0 HZ |
904 | u64 enable:1; |
905 | u64 reserved:11; | |
906 | u64 guest_physical_address:52; | |
6658be6a GKH |
907 | }; |
908 | }; | |
909 | ||
c786a84e | 910 | #endif |