Commit | Line | Data |
---|---|---|
783de57c | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2fc51f76 TP |
2 | /* |
3 | * FB driver for the ILI9325 LCD Controller | |
4 | * | |
5 | * Copyright (C) 2013 Noralf Tronnes | |
6 | * | |
7 | * Based on ili9325.c by Jeroen Domburg | |
2fc51f76 TP |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
c440eee1 | 13 | #include <linux/gpio/consumer.h> |
2fc51f76 TP |
14 | #include <linux/delay.h> |
15 | ||
16 | #include "fbtft.h" | |
17 | ||
18 | #define DRVNAME "fb_ili9325" | |
19 | #define WIDTH 240 | |
20 | #define HEIGHT 320 | |
21 | #define BPP 16 | |
22 | #define FPS 20 | |
23 | #define DEFAULT_GAMMA "0F 00 7 2 0 0 6 5 4 1\n" \ | |
24 | "04 16 2 7 6 3 2 1 7 7" | |
25 | ||
1c41494a | 26 | static unsigned int bt = 6; /* VGL=Vci*4 , VGH=Vci*4 */ |
c444ebc8 | 27 | module_param(bt, uint, 0000); |
2fc51f76 TP |
28 | MODULE_PARM_DESC(bt, "Sets the factor used in the step-up circuits"); |
29 | ||
1c41494a | 30 | static unsigned int vc = 0x03; /* Vci1=Vci*0.80 */ |
c444ebc8 | 31 | module_param(vc, uint, 0000); |
b1e9c8b7 | 32 | MODULE_PARM_DESC(vc, "Sets the ratio factor of Vci to generate the reference voltages Vci1"); |
2fc51f76 | 33 | |
1c41494a | 34 | static unsigned int vrh = 0x0d; /* VREG1OUT=Vci*1.85 */ |
c444ebc8 | 35 | module_param(vrh, uint, 0000); |
b1e9c8b7 | 36 | MODULE_PARM_DESC(vrh, "Set the amplifying rate (1.6 ~ 1.9) of Vci applied to output the VREG1OUT"); |
2fc51f76 | 37 | |
1c41494a | 38 | static unsigned int vdv = 0x12; /* VCOMH amplitude=VREG1OUT*0.98 */ |
c444ebc8 | 39 | module_param(vdv, uint, 0000); |
b1e9c8b7 | 40 | MODULE_PARM_DESC(vdv, "Select the factor of VREG1OUT to set the amplitude of Vcom"); |
2fc51f76 | 41 | |
1c41494a | 42 | static unsigned int vcm = 0x0a; /* VCOMH=VREG1OUT*0.735 */ |
c444ebc8 | 43 | module_param(vcm, uint, 0000); |
2fc51f76 TP |
44 | MODULE_PARM_DESC(vcm, "Set the internal VcomH voltage"); |
45 | ||
2fc51f76 | 46 | /* |
3a334ea5 ERR |
47 | * Verify that this configuration is within the Voltage limits |
48 | * | |
49 | * Display module configuration: Vcc = IOVcc = Vci = 3.3V | |
50 | * | |
51 | * Voltages | |
52 | * ---------- | |
53 | * Vci = 3.3 | |
54 | * Vci1 = Vci * 0.80 = 2.64 | |
55 | * DDVDH = Vci1 * 2 = 5.28 | |
56 | * VCL = -Vci1 = -2.64 | |
57 | * VREG1OUT = Vci * 1.85 = 4.88 | |
58 | * VCOMH = VREG1OUT * 0.735 = 3.59 | |
59 | * VCOM amplitude = VREG1OUT * 0.98 = 4.79 | |
60 | * VGH = Vci * 4 = 13.2 | |
61 | * VGL = -Vci * 4 = -13.2 | |
62 | * | |
63 | * Limits | |
64 | * -------- | |
65 | * Power supplies | |
66 | * 1.65 < IOVcc < 3.30 => 1.65 < 3.3 < 3.30 | |
67 | * 2.40 < Vcc < 3.30 => 2.40 < 3.3 < 3.30 | |
68 | * 2.50 < Vci < 3.30 => 2.50 < 3.3 < 3.30 | |
69 | * | |
70 | * Source/VCOM power supply voltage | |
71 | * 4.50 < DDVDH < 6.0 => 4.50 < 5.28 < 6.0 | |
72 | * -3.0 < VCL < -2.0 => -3.0 < -2.64 < -2.0 | |
73 | * VCI - VCL < 6.0 => 5.94 < 6.0 | |
74 | * | |
75 | * Gate driver output voltage | |
76 | * 10 < VGH < 20 => 10 < 13.2 < 20 | |
77 | * -15 < VGL < -5 => -15 < -13.2 < -5 | |
78 | * VGH - VGL < 32 => 26.4 < 32 | |
79 | * | |
80 | * VCOM driver output voltage | |
81 | * VCOMH - VCOML < 6.0 => 4.79 < 6.0 | |
82 | */ | |
2fc51f76 TP |
83 | |
84 | static int init_display(struct fbtft_par *par) | |
85 | { | |
2fc51f76 TP |
86 | par->fbtftops.reset(par); |
87 | ||
92e3e884 | 88 | if (par->gpio.cs) |
c440eee1 | 89 | gpiod_set_value(par->gpio.cs, 0); /* Activate chip */ |
2fc51f76 | 90 | |
153fe946 GU |
91 | bt &= 0x07; |
92 | vc &= 0x07; | |
93 | vrh &= 0x0f; | |
94 | vdv &= 0x1f; | |
95 | vcm &= 0x3f; | |
2fc51f76 TP |
96 | |
97 | /* Initialization sequence from ILI9325 Application Notes */ | |
98 | ||
99 | /* ----------- Start Initial Sequence ----------- */ | |
100 | write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ | |
101 | write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ | |
102 | write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ | |
103 | write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ | |
104 | write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ | |
105 | write_reg(par, 0x0004, 0x0000); /* Resize register */ | |
106 | write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ | |
107 | write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ | |
108 | write_reg(par, 0x000A, 0x0000); /* FMARK function */ | |
109 | write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ | |
110 | write_reg(par, 0x000D, 0x0000); /* Frame marker Position */ | |
111 | write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */ | |
112 | ||
113 | /* ----------- Power On sequence ----------- */ | |
114 | write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ | |
115 | write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ | |
116 | write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */ | |
117 | write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */ | |
118 | mdelay(200); /* Dis-charge capacitor power voltage */ | |
119 | write_reg(par, 0x0010, /* SAP, BT[3:0], AP, DSTB, SLP, STB */ | |
12eed2f2 | 120 | BIT(12) | (bt << 8) | BIT(7) | BIT(4)); |
2fc51f76 TP |
121 | write_reg(par, 0x0011, 0x220 | vc); /* DC1[2:0], DC0[2:0], VC[2:0] */ |
122 | mdelay(50); /* Delay 50ms */ | |
123 | write_reg(par, 0x0012, vrh); /* Internal reference voltage= Vci; */ | |
124 | mdelay(50); /* Delay 50ms */ | |
125 | write_reg(par, 0x0013, vdv << 8); /* Set VDV[4:0] for VCOM amplitude */ | |
126 | write_reg(par, 0x0029, vcm); /* Set VCM[5:0] for VCOMH */ | |
127 | write_reg(par, 0x002B, 0x000C); /* Set Frame Rate */ | |
128 | mdelay(50); /* Delay 50ms */ | |
129 | write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */ | |
130 | write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */ | |
131 | ||
132 | /*------------------ Set GRAM area --------------- */ | |
133 | write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */ | |
134 | write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */ | |
135 | write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */ | |
136 | write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */ | |
137 | write_reg(par, 0x0060, 0xA700); /* Gate Scan Line */ | |
138 | write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */ | |
139 | write_reg(par, 0x006A, 0x0000); /* set scrolling line */ | |
140 | ||
141 | /*-------------- Partial Display Control --------- */ | |
142 | write_reg(par, 0x0080, 0x0000); | |
143 | write_reg(par, 0x0081, 0x0000); | |
144 | write_reg(par, 0x0082, 0x0000); | |
145 | write_reg(par, 0x0083, 0x0000); | |
146 | write_reg(par, 0x0084, 0x0000); | |
147 | write_reg(par, 0x0085, 0x0000); | |
148 | ||
149 | /*-------------- Panel Control ------------------- */ | |
150 | write_reg(par, 0x0090, 0x0010); | |
151 | write_reg(par, 0x0092, 0x0600); | |
152 | write_reg(par, 0x0007, 0x0133); /* 262K color and display ON */ | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) | |
158 | { | |
2fc51f76 TP |
159 | switch (par->info->var.rotate) { |
160 | /* R20h = Horizontal GRAM Start Address */ | |
161 | /* R21h = Vertical GRAM Start Address */ | |
162 | case 0: | |
163 | write_reg(par, 0x0020, xs); | |
164 | write_reg(par, 0x0021, ys); | |
165 | break; | |
166 | case 180: | |
167 | write_reg(par, 0x0020, WIDTH - 1 - xs); | |
168 | write_reg(par, 0x0021, HEIGHT - 1 - ys); | |
169 | break; | |
170 | case 270: | |
171 | write_reg(par, 0x0020, WIDTH - 1 - ys); | |
172 | write_reg(par, 0x0021, xs); | |
173 | break; | |
174 | case 90: | |
175 | write_reg(par, 0x0020, ys); | |
176 | write_reg(par, 0x0021, HEIGHT - 1 - xs); | |
177 | break; | |
178 | } | |
179 | write_reg(par, 0x0022); /* Write Data to GRAM */ | |
180 | } | |
181 | ||
182 | static int set_var(struct fbtft_par *par) | |
183 | { | |
2fc51f76 TP |
184 | switch (par->info->var.rotate) { |
185 | /* AM: GRAM update direction */ | |
186 | case 0: | |
187 | write_reg(par, 0x03, 0x0030 | (par->bgr << 12)); | |
188 | break; | |
189 | case 180: | |
190 | write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); | |
191 | break; | |
192 | case 270: | |
193 | write_reg(par, 0x03, 0x0028 | (par->bgr << 12)); | |
194 | break; | |
195 | case 90: | |
196 | write_reg(par, 0x03, 0x0018 | (par->bgr << 12)); | |
197 | break; | |
198 | } | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
203 | /* | |
3a334ea5 ERR |
204 | * Gamma string format: |
205 | * VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5 | |
206 | * VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5 | |
207 | */ | |
0b1533c6 | 208 | #define CURVE(num, idx) curves[(num) * par->gamma.num_values + (idx)] |
22eb36b8 | 209 | static int set_gamma(struct fbtft_par *par, u32 *curves) |
2fc51f76 TP |
210 | { |
211 | unsigned long mask[] = { | |
153fe946 GU |
212 | 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, |
213 | 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
214 | }; | |
2fc51f76 TP |
215 | int i, j; |
216 | ||
2fc51f76 TP |
217 | /* apply mask */ |
218 | for (i = 0; i < 2; i++) | |
219 | for (j = 0; j < 10; j++) | |
94c0a544 | 220 | CURVE(i, j) &= mask[i * par->gamma.num_values + j]; |
2fc51f76 TP |
221 | |
222 | write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4)); | |
223 | write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6)); | |
224 | write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8)); | |
225 | write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2)); | |
226 | write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0)); | |
227 | ||
228 | write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4)); | |
229 | write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6)); | |
230 | write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8)); | |
231 | write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2)); | |
232 | write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0)); | |
233 | ||
234 | return 0; | |
235 | } | |
b4ac6b28 | 236 | |
2fc51f76 TP |
237 | #undef CURVE |
238 | ||
2fc51f76 TP |
239 | static struct fbtft_display display = { |
240 | .regwidth = 16, | |
241 | .width = WIDTH, | |
242 | .height = HEIGHT, | |
243 | .bpp = BPP, | |
244 | .fps = FPS, | |
245 | .gamma_num = 2, | |
246 | .gamma_len = 10, | |
247 | .gamma = DEFAULT_GAMMA, | |
248 | .fbtftops = { | |
249 | .init_display = init_display, | |
250 | .set_addr_win = set_addr_win, | |
251 | .set_var = set_var, | |
252 | .set_gamma = set_gamma, | |
253 | }, | |
254 | }; | |
1014c2ce | 255 | |
2fc51f76 TP |
256 | FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9325", &display); |
257 | ||
258 | MODULE_ALIAS("spi:" DRVNAME); | |
259 | MODULE_ALIAS("platform:" DRVNAME); | |
260 | MODULE_ALIAS("spi:ili9325"); | |
261 | MODULE_ALIAS("platform:ili9325"); | |
262 | ||
263 | MODULE_DESCRIPTION("FB driver for the ILI9325 LCD Controller"); | |
264 | MODULE_AUTHOR("Noralf Tronnes"); | |
265 | MODULE_LICENSE("GPL"); |