[linux-2.6-block.git] / drivers / staging / et131x / et1310_phy.h

/*
 * Agere Systems Inc.
 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
 *
 * Copyright © 2005 Agere Systems Inc.
 * All rights reserved.
 *   http://www.agere.com
 *
 *------------------------------------------------------------------------------
 *
 * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
 *                PHY.
 *
 *------------------------------------------------------------------------------
 *
 * SOFTWARE LICENSE
 *
 * This software is provided subject to the following terms and conditions,
 * which you should read carefully before using the software.  Using this
 * software indicates your acceptance of these terms and conditions.  If you do
 * not agree with these terms and conditions, do not use the software.
 *
 * Copyright © 2005 Agere Systems Inc.
 * All rights reserved.
 *
 * Redistribution and use in source or binary forms, with or without
 * modifications, are permitted provided that the following conditions are met:
 *
 * . Redistributions of source code must retain the above copyright notice, this
 *    list of conditions and the following Disclaimer as comments in the code as
 *    well as in the documentation and/or other materials provided with the
 *    distribution.
 *
 * . Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following Disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * . Neither the name of Agere Systems Inc. nor the names of the contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * Disclaimer
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGE.
 *
 */

#ifndef _ET1310_PHY_H_
#define _ET1310_PHY_H_

#include "et1310_address_map.h"

/* MI Register Addresses */
#define MI_CONTROL_REG                      0
#define MI_STATUS_REG                       1
#define MI_PHY_IDENTIFIER_1_REG             2
#define MI_PHY_IDENTIFIER_2_REG             3
#define MI_AUTONEG_ADVERTISEMENT_REG        4
#define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
#define MI_AUTONEG_EXPANSION_REG            6
#define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG   7
#define MI_LINK_PARTNER_NEXT_PAGE_REG       8
#define MI_1000BASET_CONTROL_REG            9
#define MI_1000BASET_STATUS_REG             10
#define MI_RESERVED11_REG                   11
#define MI_RESERVED12_REG                   12
#define MI_RESERVED13_REG                   13
#define MI_RESERVED14_REG                   14
#define MI_EXTENDED_STATUS_REG              15

/* VMI Register Addresses */
#define VMI_RESERVED16_REG                  16
#define VMI_RESERVED17_REG                  17
#define VMI_RESERVED18_REG                  18
#define VMI_LOOPBACK_CONTROL_REG            19
#define VMI_RESERVED20_REG                  20
#define VMI_MI_CONTROL_REG                  21
#define VMI_PHY_CONFIGURATION_REG           22
#define VMI_PHY_CONTROL_REG                 23
#define VMI_INTERRUPT_MASK_REG              24
#define VMI_INTERRUPT_STATUS_REG            25
#define VMI_PHY_STATUS_REG                  26
#define VMI_LED_CONTROL_1_REG               27
#define VMI_LED_CONTROL_2_REG               28
#define VMI_RESERVED29_REG                  29
#define VMI_RESERVED30_REG                  30
#define VMI_RESERVED31_REG                  31

/* PHY Register Mapping(MI) Management Interface Regs */
struct mi_regs {
	u8 bmcr;	/* Basic mode control reg(Reg 0x00) */
	u8 bmsr;	/* Basic mode status reg(Reg 0x01) */
	u8 idr1;	/* Phy identifier reg 1(Reg 0x02) */
	u8 idr2;	/* Phy identifier reg 2(Reg 0x03) */
	u8 anar;	/* Auto-Negotiation advertisement(Reg 0x04) */
	u8 anlpar;	/* Auto-Negotiation link Partner Ability(Reg 0x05) */
	u8 aner;	/* Auto-Negotiation expansion reg(Reg 0x06) */
	u8 annptr;	/* Auto-Negotiation next page transmit reg(Reg 0x07) */
	u8 lpnpr;	/* link partner next page reg(Reg 0x08) */
	u8 gcr;		/* Gigabit basic mode control reg(Reg 0x09) */
	u8 gsr;		/* Gigabit basic mode status reg(Reg 0x0A) */
	u8 mi_res1[4];	/* Future use by MI working group(Reg 0x0B - 0x0E) */
	u8 esr;		/* Extended status reg(Reg 0x0F) */
	u8 mi_res2[3];	/* Future use by MI working group(Reg 0x10 - 0x12) */
	u8 loop_ctl;	/* Loopback Control Reg(Reg 0x13) */
	u8 mi_res3;	/* Future use by MI working group(Reg 0x14) */
	u8 mcr;		/* MI Control Reg(Reg 0x15) */
	u8 pcr;		/* Configuration Reg(Reg 0x16) */
	u8 phy_ctl;	/* PHY Control Reg(Reg 0x17) */
	u8 imr;		/* Interrupt Mask Reg(Reg 0x18) */
	u8 isr;		/* Interrupt Status Reg(Reg 0x19) */
	u8 psr;		/* PHY Status Reg(Reg 0x1A) */
	u8 lcr1;		/* LED Control 1 Reg(Reg 0x1B) */
	u8 lcr2;		/* LED Control 2 Reg(Reg 0x1C) */
	u8 mi_res4[3];	/* Future use by MI working group(Reg 0x1D - 0x1F) */
};

/* MI Register 0: Basic mode control register */
typedef union _MI_BMCR_t {
	u16 value;
	struct {
#ifdef _BIT_FIELDS_HTOL
		u16 reset:1;		/* bit 15 */
		u16 loopback:1;		/* bit 14 */
		u16 speed_sel:1;		/* bit 13 */
		u16 enable_autoneg:1;	/* bit 12 */
		u16 power_down:1;		/* bit 11 */
		u16 isolate:1;		/* bit 10 */
		u16 restart_autoneg:1;	/* bit 9 */
		u16 duplex_mode:1;		/* bit 8 */
		u16 col_test:1;		/* bit 7 */
		u16 speed_1000_sel:1;	/* bit 6 */
		u16 res1:6;		/* bits 0-5 */
#else
		u16 res1:6;		/* bits 0-5 */
		u16 speed_1000_sel:1;	/* bit 6 */
		u16 col_test:1;		/* bit 7 */
		u16 duplex_mode:1;		/* bit 8 */
		u16 restart_autoneg:1;	/* bit 9 */
		u16 isolate:1;		/* bit 10 */
		u16 power_down:1;		/* bit 11 */
		u16 enable_autoneg:1;	/* bit 12 */
		u16 speed_sel:1;		/* bit 13 */
		u16 loopback:1;		/* bit 14 */
		u16 reset:1;		/* bit 15 */
#endif
	} bits;
} MI_BMCR_t, *PMI_BMCR_t;

/* MI Register 1:  Basic mode status register */
typedef union _MI_BMSR_t {
	u16 value;
	struct {
#ifdef _BIT_FIELDS_HTOL
		u16 link_100T4:1;		/* bit 15 */
		u16 link_100fdx:1;		/* bit 14 */
		u16 link_100hdx:1;		/* bit 13 */
		u16 link_10fdx:1;		/* bit 12 */
		u16 link_10hdx:1;		/* bit 11 */
		u16 link_100T2fdx:1;	/* bit 10 */
		u16 link_100T2hdx:1;	/* bit 9 */
		u16 extend_status:1;	/* bit 8 */
		u16 res1:1;		/* bit 7 */
		u16 preamble_supress:1;	/* bit 6 */
		u16 auto_neg_complete:1;	/* bit 5 */
		u16 remote_fault:1;	/* bit 4 */
		u16 auto_neg_able:1;	/* bit 3 */
		u16 link_status:1;		/* bit 2 */
		u16 jabber_detect:1;	/* bit 1 */
		u16 ext_cap:1;		/* bit 0 */
#else
		u16 ext_cap:1;		/* bit 0 */
		u16 jabber_detect:1;	/* bit 1 */
		u16 link_status:1;		/* bit 2 */
		u16 auto_neg_able:1;	/* bit 3 */
		u16 remote_fault:1;	/* bit 4 */
		u16 auto_neg_complete:1;	/* bit 5 */
		u16 preamble_supress:1;	/* bit 6 */
		u16 res1:1;		/* bit 7 */
		u16 extend_status:1;	/* bit 8 */
		u16 link_100T2hdx:1;	/* bit 9 */
		u16 link_100T2fdx:1;	/* bit 10 */
		u16 link_10hdx:1;		/* bit 11 */
		u16 link_10fdx:1;		/* bit 12 */
		u16 link_100hdx:1;		/* bit 13 */
		u16 link_100fdx:1;		/* bit 14 */
		u16 link_100T4:1;		/* bit 15 */
#endif
	} bits;
} MI_BMSR_t, *PMI_BMSR_t;

/* MI Register 4: Auto-negotiation advertisement register */
typedef union _MI_ANAR_t {
	u16 value;
	struct {
#ifdef _BIT_FIELDS_HTOL
		u16 np_indication:1;	/* bit 15 */
		u16 res2:1;		/* bit 14 */
		u16 remote_fault:1;	/* bit 13 */
		u16 res1:1;		/* bit 12 */
		u16 cap_asmpause:1;	/* bit 11 */
		u16 cap_pause:1;		/* bit 10 */
		u16 cap_100T4:1;		/* bit 9 */
		u16 cap_100fdx:1;		/* bit 8 */
		u16 cap_100hdx:1;		/* bit 7 */
		u16 cap_10fdx:1;		/* bit 6 */
		u16 cap_10hdx:1;		/* bit 5 */
		u16 selector:5;		/* bits 0-4 */
#else
		u16 selector:5;		/* bits 0-4 */
		u16 cap_10hdx:1;		/* bit 5 */
		u16 cap_10fdx:1;		/* bit 6 */
		u16 cap_100hdx:1;		/* bit 7 */
		u16 cap_100fdx:1;		/* bit 8 */
		u16 cap_100T4:1;		/* bit 9 */
		u16 cap_pause:1;		/* bit 10 */
		u16 cap_asmpause:1;	/* bit 11 */
		u16 res1:1;		/* bit 12 */
		u16 remote_fault:1;	/* bit 13 */
		u16 res2:1;		/* bit 14 */
		u16 np_indication:1;	/* bit 15 */
#endif
	} bits;
} MI_ANAR_t, *PMI_ANAR_t;

/* MI Register 5: Auto-negotiation link partner advertisement register
 *	15:	np_indication
 *	14:	acknowledge
 *	13:	remote_fault
 *	12:	res1:1;		
 *	11:	cap_asmpause
 *	10:	cap_pause
 *	9:	cap_100T4
 *	8:	cap_100fdx
 *	7:	cap_100hdx
 *	6:	cap_10fdx
 *	5:	cap_10hdx
 *	4-0:	selector
 */

/* MI Register 6: Auto-negotiation expansion register
 *	15-5:	reserved
 *	4:	pdf
 *	3:	lp_np_able
 *	2:	np_able
 *	1:	page_rx
 *	0:	lp_an_able
 */

/* MI Register 7: Auto-negotiation next page transmit reg(0x07) 
 *	15:	np
 *	14:	reserved
 *	13:	msg_page
 *	12:	ack2
 *	11:	toggle
 *	10-0	msg
 */

/* MI Register 8: Link Partner Next Page Reg(0x08) 
 *	15:	np
 *	14:	ack
 *	13:	msg_page
 *	12:	ack2
 *	11:	toggle
 *	10-0:	msg
 */

/* MI Register 9: 1000BaseT Control Reg(0x09)
 *	15-13:	test_mode
 *	12:	ms_config_en
 *	11:	ms_value
 *	10:	port_type
 *	9:	link_1000fdx
 *	8:	link_1000hdx
 *	7-0:	reserved
 */

/* MI Register 10: 1000BaseT Status Reg(0x0A)
 *	15:	ms_config_fault
 *	14:	ms_resolve
 *	13:	local_rx_status
 *	12:	remote_rx_status
 *	11:	link_1000fdx
 *	10:	link_1000hdx
 *	9-8:	reserved
 *	7-0:	idle_err_cnt
 */

/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */

/* MI Register 15: Extended status Reg(0x0F)
 *	15:	link_1000Xfdx
 *	14:	link_1000Xhdx
 *	13:	link_1000fdx
 *	12:	link_1000hdx
 *	11-0:	reserved
 */

/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */

/* MI Register 19: Loopback Control Reg(0x13)
 *	15:	mii_en
 *	14:	pcs_en
 *	13:	pmd_en
 *	12:	all_digital_en
 *	11:	replica_en
 *	10:	line_driver_en
 *	9-0:	reserved
 */

/* MI Register 20: Reserved Reg(0x14) */

/* MI Register 21: Management Interface Control Reg(0x15)
 *	15-11:	reserved
 *	10-4:	mi_error_count
 *	3:	reserved
 *	2:	ignore_10g_fr
 *	1:	reserved
 *	0:	preamble_supress_en
 */

/* MI Register 22: PHY Configuration Reg(0x16)
 *	15:	crs_tx_en
 *	14:	reserved
 *	13-12:	tx_fifo_depth
 *	11-10:	speed_downshift
 *	9:	pbi_detect
 *	8:	tbi_rate
 *	7:	alternate_np
 *	6:	group_mdio_en
 *	5:	tx_clock_en
 *	4:	sys_clock_en
 *	3:	reserved
 *	2-0:	mac_if_mode
 */

/* MI Register 23: PHY CONTROL Reg(0x17)
 *	15:	reserved
 *	14:	tdr_en
 *	13:	reserved
 *	12-11:	downshift_attempts
 *	10-6:	reserved
 *	5:	jabber_10baseT
 *	4:	sqe_10baseT
 *	3:	tp_loopback_10baseT
 *	2:	preamble_gen_en
 *	1:	reserved
 *	0:	force_int
 */

/* MI Register 24: Interrupt Mask Reg(0x18)
 *	15-10:	reserved
 *	9:	mdio_sync_lost
 *	8:	autoneg_status
 *	7:	hi_bit_err
 *	6:	np_rx
 *	5:	err_counter_full
 *	4:	fifo_over_underflow
 *	3:	rx_status
 *	2:	link_status
 *	1:	automatic_speed
 *	0:	int_en
 */


/* MI Register 25: Interrupt Status Reg(0x19)
 *	15-10:	reserved
 *	9:	mdio_sync_lost
 *	8:	autoneg_status
 *	7:	hi_bit_err
 *	6:	np_rx
 *	5:	err_counter_full
 *	4:	fifo_over_underflow
 *	3:	rx_status
 *	2:	link_status
 *	1:	automatic_speed
 *	0:	int_en
 */

/* MI Register 26: PHY Status Reg(0x1A)
 *	15:	reserved
 *	14-13:	autoneg_fault
 *	12:	autoneg_status
 *	11:	mdi_x_status
 *	10:	polarity_status
 *	9-8:	speed_status
 *	7:	duplex_status
 *	6:	link_status
 *	5:	tx_status
 *	4:	rx_status
 *	3:	collision_status
 *	2:	autoneg_en
 *	1:	pause_en
 *	0:	asymmetric_dir
 */

/* MI Register 27: LED Control Reg 1(0x1B)
 *	15-14:	reserved
 *	13-12:	led_dup_indicate
 *	11-10:	led_10baseT
 *	9-8:	led_collision
 *	7-4:	reserved
 *	3-2:	pulse_dur
 *	1:	pulse_stretch1
 *	0:	pulse_stretch0
 */

/* MI Register 28: LED Control Reg 2(0x1C)
 *	15-12:	led_link
 *	11-8:	led_tx_rx
 *	7-4:	led_100BaseTX
 *	3-0:	led_1000BaseT
 */

/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */


/* Prototypes for ET1310_phy.c */
/* Defines for PHY access routines */

/* Define bit operation flags */
#define TRUEPHY_BIT_CLEAR               0
#define TRUEPHY_BIT_SET                 1
#define TRUEPHY_BIT_READ                2

/* Define read/write operation flags */
#ifndef TRUEPHY_READ
#define TRUEPHY_READ                    0
#define TRUEPHY_WRITE                   1
#define TRUEPHY_MASK                    2
#endif

/* Define speeds */
#define TRUEPHY_SPEED_10MBPS            0
#define TRUEPHY_SPEED_100MBPS           1
#define TRUEPHY_SPEED_1000MBPS          2

/* Define duplex modes */
#define TRUEPHY_DUPLEX_HALF             0
#define TRUEPHY_DUPLEX_FULL             1

/* Define master/slave configuration values */
#define TRUEPHY_CFG_SLAVE               0
#define TRUEPHY_CFG_MASTER              1

/* Define MDI/MDI-X settings */
#define TRUEPHY_MDI                     0
#define TRUEPHY_MDIX                    1
#define TRUEPHY_AUTO_MDI_MDIX           2

/* Define 10Base-T link polarities */
#define TRUEPHY_POLARITY_NORMAL         0
#define TRUEPHY_POLARITY_INVERTED       1

/* Define auto-negotiation results */
#define TRUEPHY_ANEG_NOT_COMPLETE       0
#define TRUEPHY_ANEG_COMPLETE           1
#define TRUEPHY_ANEG_DISABLED           2

/* Define duplex advertisement flags */
#define TRUEPHY_ADV_DUPLEX_NONE         0x00
#define TRUEPHY_ADV_DUPLEX_FULL         0x01
#define TRUEPHY_ADV_DUPLEX_HALF         0x02
#define TRUEPHY_ADV_DUPLEX_BOTH     \
    (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)

#define PHY_CONTROL                0x00	/* #define TRU_MI_CONTROL_REGISTER                 0 */
#define PHY_STATUS                 0x01	/* #define TRU_MI_STATUS_REGISTER                  1 */
#define PHY_ID_1                   0x02	/* #define TRU_MI_PHY_IDENTIFIER_1_REGISTER        2 */
#define PHY_ID_2                   0x03	/* #define TRU_MI_PHY_IDENTIFIER_2_REGISTER        3 */
#define PHY_AUTO_ADVERTISEMENT     0x04	/* #define TRU_MI_ADVERTISEMENT_REGISTER           4 */
#define PHY_AUTO_LINK_PARTNER      0x05	/* #define TRU_MI_LINK_PARTNER_ABILITY_REGISTER    5 */
#define PHY_AUTO_EXPANSION         0x06	/* #define TRU_MI_EXPANSION_REGISTER               6 */
#define PHY_AUTO_NEXT_PAGE_TX      0x07	/* #define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER      7 */
#define PHY_LINK_PARTNER_NEXT_PAGE 0x08	/* #define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER  8 */
#define PHY_1000_CONTROL           0x09	/* #define TRU_MI_1000BASET_CONTROL_REGISTER       9 */
#define PHY_1000_STATUS            0x0A	/* #define TRU_MI_1000BASET_STATUS_REGISTER        10 */

#define PHY_EXTENDED_STATUS        0x0F	/* #define TRU_MI_EXTENDED_STATUS_REGISTER         15 */

/* some defines for modem registers that seem to be 'reserved' */
#define PHY_INDEX_REG              0x10
#define PHY_DATA_REG               0x11

#define PHY_MPHY_CONTROL_REG       0x12	/* #define TRU_VMI_MPHY_CONTROL_REGISTER           18 */

#define PHY_LOOPBACK_CONTROL       0x13	/* #define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER     19 */
					/* #define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER     20 */
#define PHY_REGISTER_MGMT_CONTROL  0x15	/* #define TRU_VMI_MI_SEQ_CONTROL_REGISTER         21 */
#define PHY_CONFIG                 0x16	/* #define TRU_VMI_CONFIGURATION_REGISTER          22 */
#define PHY_PHY_CONTROL            0x17	/* #define TRU_VMI_PHY_CONTROL_REGISTER            23 */
#define PHY_INTERRUPT_MASK         0x18	/* #define TRU_VMI_INTERRUPT_MASK_REGISTER         24 */
#define PHY_INTERRUPT_STATUS       0x19	/* #define TRU_VMI_INTERRUPT_STATUS_REGISTER       25 */
#define PHY_PHY_STATUS             0x1A	/* #define TRU_VMI_PHY_STATUS_REGISTER             26 */
#define PHY_LED_1                  0x1B	/* #define TRU_VMI_LED_CONTROL_1_REGISTER          27 */
#define PHY_LED_2                  0x1C	/* #define TRU_VMI_LED_CONTROL_2_REGISTER          28 */
					/* #define TRU_VMI_LINK_CONTROL_REGISTER           29 */
					/* #define TRU_VMI_TIMING_CONTROL_REGISTER */

#endif /* _ET1310_PHY_H_ */
Commit	Line	Data
cfb739b4 GKH	1	/*
	2	* Agere Systems Inc.
	3	* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
	4	*
64f93036	5	* Copyright © 2005 Agere Systems Inc.
cfb739b4 GKH	6	* All rights reserved.
	7	* http://www.agere.com
	8	*
	9	*------------------------------------------------------------------------------
	10	*
	11	* et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
	12	* PHY.
	13	*
	14	*------------------------------------------------------------------------------
	15	*
	16	* SOFTWARE LICENSE
	17	*
	18	* This software is provided subject to the following terms and conditions,
	19	* which you should read carefully before using the software. Using this
	20	* software indicates your acceptance of these terms and conditions. If you do
	21	* not agree with these terms and conditions, do not use the software.
	22	*
64f93036	23	* Copyright © 2005 Agere Systems Inc.
cfb739b4 GKH	24	* All rights reserved.
	25	*
	26	* Redistribution and use in source or binary forms, with or without
	27	* modifications, are permitted provided that the following conditions are met:
	28	*
	29	* . Redistributions of source code must retain the above copyright notice, this
	30	* list of conditions and the following Disclaimer as comments in the code as
	31	* well as in the documentation and/or other materials provided with the
	32	* distribution.
	33	*
	34	* . Redistributions in binary form must reproduce the above copyright notice,
	35	* this list of conditions and the following Disclaimer in the documentation
	36	* and/or other materials provided with the distribution.
	37	*
	38	* . Neither the name of Agere Systems Inc. nor the names of the contributors
	39	* may be used to endorse or promote products derived from this software
	40	* without specific prior written permission.
	41	*
	42	* Disclaimer
	43	*
64f93036	44	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
cfb739b4 GKH	45	* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
	46	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
	47	* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
	48	* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
	49	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	50	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	51	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	52	* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
	53	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
	54	* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
	55	* DAMAGE.
	56	*
	57	*/
	58
	59	#ifndef _ET1310_PHY_H_
	60	#define _ET1310_PHY_H_
	61
	62	#include "et1310_address_map.h"
	63
cfb739b4 GKH	64	/* MI Register Addresses */
	65	#define MI_CONTROL_REG 0
	66	#define MI_STATUS_REG 1
	67	#define MI_PHY_IDENTIFIER_1_REG 2
	68	#define MI_PHY_IDENTIFIER_2_REG 3
	69	#define MI_AUTONEG_ADVERTISEMENT_REG 4
	70	#define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
	71	#define MI_AUTONEG_EXPANSION_REG 6
	72	#define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG 7
	73	#define MI_LINK_PARTNER_NEXT_PAGE_REG 8
	74	#define MI_1000BASET_CONTROL_REG 9
	75	#define MI_1000BASET_STATUS_REG 10
	76	#define MI_RESERVED11_REG 11
	77	#define MI_RESERVED12_REG 12
	78	#define MI_RESERVED13_REG 13
	79	#define MI_RESERVED14_REG 14
	80	#define MI_EXTENDED_STATUS_REG 15
	81
	82	/* VMI Register Addresses */
	83	#define VMI_RESERVED16_REG 16
	84	#define VMI_RESERVED17_REG 17
	85	#define VMI_RESERVED18_REG 18
	86	#define VMI_LOOPBACK_CONTROL_REG 19
	87	#define VMI_RESERVED20_REG 20
	88	#define VMI_MI_CONTROL_REG 21
	89	#define VMI_PHY_CONFIGURATION_REG 22
	90	#define VMI_PHY_CONTROL_REG 23
	91	#define VMI_INTERRUPT_MASK_REG 24
	92	#define VMI_INTERRUPT_STATUS_REG 25
	93	#define VMI_PHY_STATUS_REG 26
	94	#define VMI_LED_CONTROL_1_REG 27
	95	#define VMI_LED_CONTROL_2_REG 28
	96	#define VMI_RESERVED29_REG 29
	97	#define VMI_RESERVED30_REG 30
	98	#define VMI_RESERVED31_REG 31
	99
	100	/* PHY Register Mapping(MI) Management Interface Regs */
404dc5f3	101	struct mi_regs {
64f93036 AC	102	u8 bmcr; /* Basic mode control reg(Reg 0x00) */
	103	u8 bmsr; /* Basic mode status reg(Reg 0x01) */
	104	u8 idr1; /* Phy identifier reg 1(Reg 0x02) */
	105	u8 idr2; /* Phy identifier reg 2(Reg 0x03) */
	106	u8 anar; /* Auto-Negotiation advertisement(Reg 0x04) */
	107	u8 anlpar; /* Auto-Negotiation link Partner Ability(Reg 0x05) */
	108	u8 aner; /* Auto-Negotiation expansion reg(Reg 0x06) */
	109	u8 annptr; /* Auto-Negotiation next page transmit reg(Reg 0x07) */
	110	u8 lpnpr; /* link partner next page reg(Reg 0x08) */
	111	u8 gcr; /* Gigabit basic mode control reg(Reg 0x09) */
	112	u8 gsr; /* Gigabit basic mode status reg(Reg 0x0A) */
	113	u8 mi_res1[4]; /* Future use by MI working group(Reg 0x0B - 0x0E) */
	114	u8 esr; /* Extended status reg(Reg 0x0F) */
	115	u8 mi_res2[3]; /* Future use by MI working group(Reg 0x10 - 0x12) */
	116	u8 loop_ctl; /* Loopback Control Reg(Reg 0x13) */
	117	u8 mi_res3; /* Future use by MI working group(Reg 0x14) */
	118	u8 mcr; /* MI Control Reg(Reg 0x15) */
	119	u8 pcr; /* Configuration Reg(Reg 0x16) */
	120	u8 phy_ctl; /* PHY Control Reg(Reg 0x17) */
	121	u8 imr; /* Interrupt Mask Reg(Reg 0x18) */
	122	u8 isr; /* Interrupt Status Reg(Reg 0x19) */
	123	u8 psr; /* PHY Status Reg(Reg 0x1A) */
	124	u8 lcr1; /* LED Control 1 Reg(Reg 0x1B) */
	125	u8 lcr2; /* LED Control 2 Reg(Reg 0x1C) */
	126	u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */
404dc5f3	127	};
cfb739b4 GKH	128
	129	/* MI Register 0: Basic mode control register */
	130	typedef union _MI_BMCR_t {
	131	u16 value;
	132	struct {
	133	#ifdef _BIT_FIELDS_HTOL
64f93036 AC	134	u16 reset:1; /* bit 15 */
	135	u16 loopback:1; /* bit 14 */
	136	u16 speed_sel:1; /* bit 13 */
	137	u16 enable_autoneg:1; /* bit 12 */
	138	u16 power_down:1; /* bit 11 */
	139	u16 isolate:1; /* bit 10 */
	140	u16 restart_autoneg:1; /* bit 9 */
	141	u16 duplex_mode:1; /* bit 8 */
	142	u16 col_test:1; /* bit 7 */
	143	u16 speed_1000_sel:1; /* bit 6 */
	144	u16 res1:6; /* bits 0-5 */
cfb739b4	145	#else
64f93036 AC	146	u16 res1:6; /* bits 0-5 */
	147	u16 speed_1000_sel:1; /* bit 6 */
	148	u16 col_test:1; /* bit 7 */
	149	u16 duplex_mode:1; /* bit 8 */
	150	u16 restart_autoneg:1; /* bit 9 */
	151	u16 isolate:1; /* bit 10 */
	152	u16 power_down:1; /* bit 11 */
	153	u16 enable_autoneg:1; /* bit 12 */
	154	u16 speed_sel:1; /* bit 13 */
	155	u16 loopback:1; /* bit 14 */
	156	u16 reset:1; /* bit 15 */
cfb739b4 GKH	157	#endif
	158	} bits;
	159	} MI_BMCR_t, *PMI_BMCR_t;
	160
	161	/* MI Register 1: Basic mode status register */
	162	typedef union _MI_BMSR_t {
	163	u16 value;
	164	struct {
	165	#ifdef _BIT_FIELDS_HTOL
64f93036 AC	166	u16 link_100T4:1; /* bit 15 */
	167	u16 link_100fdx:1; /* bit 14 */
	168	u16 link_100hdx:1; /* bit 13 */
	169	u16 link_10fdx:1; /* bit 12 */
	170	u16 link_10hdx:1; /* bit 11 */
	171	u16 link_100T2fdx:1; /* bit 10 */
	172	u16 link_100T2hdx:1; /* bit 9 */
	173	u16 extend_status:1; /* bit 8 */
	174	u16 res1:1; /* bit 7 */
	175	u16 preamble_supress:1; /* bit 6 */
	176	u16 auto_neg_complete:1; /* bit 5 */
	177	u16 remote_fault:1; /* bit 4 */
	178	u16 auto_neg_able:1; /* bit 3 */
	179	u16 link_status:1; /* bit 2 */
	180	u16 jabber_detect:1; /* bit 1 */
	181	u16 ext_cap:1; /* bit 0 */
cfb739b4	182	#else
64f93036 AC	183	u16 ext_cap:1; /* bit 0 */
	184	u16 jabber_detect:1; /* bit 1 */
	185	u16 link_status:1; /* bit 2 */
	186	u16 auto_neg_able:1; /* bit 3 */
	187	u16 remote_fault:1; /* bit 4 */
	188	u16 auto_neg_complete:1; /* bit 5 */
	189	u16 preamble_supress:1; /* bit 6 */
	190	u16 res1:1; /* bit 7 */
	191	u16 extend_status:1; /* bit 8 */
	192	u16 link_100T2hdx:1; /* bit 9 */
	193	u16 link_100T2fdx:1; /* bit 10 */
	194	u16 link_10hdx:1; /* bit 11 */
	195	u16 link_10fdx:1; /* bit 12 */
	196	u16 link_100hdx:1; /* bit 13 */
	197	u16 link_100fdx:1; /* bit 14 */
	198	u16 link_100T4:1; /* bit 15 */
cfb739b4 GKH	199	#endif
	200	} bits;
	201	} MI_BMSR_t, *PMI_BMSR_t;
	202
cfb739b4 GKH	203	/* MI Register 4: Auto-negotiation advertisement register */
	204	typedef union _MI_ANAR_t {
	205	u16 value;
	206	struct {
	207	#ifdef _BIT_FIELDS_HTOL
64f93036 AC	208	u16 np_indication:1; /* bit 15 */
	209	u16 res2:1; /* bit 14 */
	210	u16 remote_fault:1; /* bit 13 */
	211	u16 res1:1; /* bit 12 */
	212	u16 cap_asmpause:1; /* bit 11 */
	213	u16 cap_pause:1; /* bit 10 */
	214	u16 cap_100T4:1; /* bit 9 */
	215	u16 cap_100fdx:1; /* bit 8 */
	216	u16 cap_100hdx:1; /* bit 7 */
	217	u16 cap_10fdx:1; /* bit 6 */
	218	u16 cap_10hdx:1; /* bit 5 */
	219	u16 selector:5; /* bits 0-4 */
cfb739b4	220	#else
64f93036 AC	221	u16 selector:5; /* bits 0-4 */
	222	u16 cap_10hdx:1; /* bit 5 */
	223	u16 cap_10fdx:1; /* bit 6 */
	224	u16 cap_100hdx:1; /* bit 7 */
	225	u16 cap_100fdx:1; /* bit 8 */
	226	u16 cap_100T4:1; /* bit 9 */
	227	u16 cap_pause:1; /* bit 10 */
	228	u16 cap_asmpause:1; /* bit 11 */
	229	u16 res1:1; /* bit 12 */
	230	u16 remote_fault:1; /* bit 13 */
	231	u16 res2:1; /* bit 14 */
	232	u16 np_indication:1; /* bit 15 */
cfb739b4 GKH	233	#endif
	234	} bits;
	235	} MI_ANAR_t, *PMI_ANAR_t;
	236
404dc5f3 AC	237	/* MI Register 5: Auto-negotiation link partner advertisement register
	238	* 15: np_indication
	239	* 14: acknowledge
	240	* 13: remote_fault
	241	* 12: res1:1;
	242	* 11: cap_asmpause
	243	* 10: cap_pause
	244	* 9: cap_100T4
	245	* 8: cap_100fdx
	246	* 7: cap_100hdx
	247	* 6: cap_10fdx
	248	* 5: cap_10hdx
	249	* 4-0: selector
	250	*/
cfb739b4	251
404dc5f3 AC	252	/* MI Register 6: Auto-negotiation expansion register
	253	* 15-5: reserved
	254	* 4: pdf
	255	* 3: lp_np_able
	256	* 2: np_able
	257	* 1: page_rx
	258	* 0: lp_an_able
	259	*/
cfb739b4	260
404dc5f3 AC	261	/* MI Register 7: Auto-negotiation next page transmit reg(0x07)
	262	* 15: np
	263	* 14: reserved
	264	* 13: msg_page
	265	* 12: ack2
	266	* 11: toggle
	267	* 10-0 msg
	268	*/
cfb739b4	269
404dc5f3 AC	270	/* MI Register 8: Link Partner Next Page Reg(0x08)
	271	* 15: np
	272	* 14: ack
	273	* 13: msg_page
	274	* 12: ack2
	275	* 11: toggle
	276	* 10-0: msg
	277	*/
cfb739b4	278
404dc5f3 AC	279	/* MI Register 9: 1000BaseT Control Reg(0x09)
	280	* 15-13: test_mode
	281	* 12: ms_config_en
	282	* 11: ms_value
	283	* 10: port_type
	284	* 9: link_1000fdx
	285	* 8: link_1000hdx
	286	* 7-0: reserved
	287	*/
cfb739b4	288
404dc5f3 AC	289	/* MI Register 10: 1000BaseT Status Reg(0x0A)
	290	* 15: ms_config_fault
	291	* 14: ms_resolve
	292	* 13: local_rx_status
	293	* 12: remote_rx_status
	294	* 11: link_1000fdx
	295	* 10: link_1000hdx
	296	* 9-8: reserved
	297	* 7-0: idle_err_cnt
	298	*/
cfb739b4 GKH	299
cfb739b4 GKH	300	/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
cfb739b4	301
404dc5f3 AC	302	/* MI Register 15: Extended status Reg(0x0F)
	303	* 15: link_1000Xfdx
	304	* 14: link_1000Xhdx
	305	* 13: link_1000fdx
	306	* 12: link_1000hdx
	307	* 11-0: reserved
	308	*/
cfb739b4 GKH	309
	310	/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
	311
404dc5f3 AC	312	/* MI Register 19: Loopback Control Reg(0x13)
	313	* 15: mii_en
	314	* 14: pcs_en
	315	* 13: pmd_en
	316	* 12: all_digital_en
	317	* 11: replica_en
	318	* 10: line_driver_en
	319	* 9-0: reserved
	320	*/
cfb739b4 GKH	321
	322	/* MI Register 20: Reserved Reg(0x14) */
	323
404dc5f3 AC	324	/* MI Register 21: Management Interface Control Reg(0x15)
	325	* 15-11: reserved
	326	* 10-4: mi_error_count
	327	* 3: reserved
	328	* 2: ignore_10g_fr
	329	* 1: reserved
	330	* 0: preamble_supress_en
	331	*/
cfb739b4	332
404dc5f3 AC	333	/* MI Register 22: PHY Configuration Reg(0x16)
	334	* 15: crs_tx_en
	335	* 14: reserved
	336	* 13-12: tx_fifo_depth
	337	* 11-10: speed_downshift
	338	* 9: pbi_detect
	339	* 8: tbi_rate
	340	* 7: alternate_np
	341	* 6: group_mdio_en
	342	* 5: tx_clock_en
	343	* 4: sys_clock_en
	344	* 3: reserved
	345	* 2-0: mac_if_mode
	346	*/
cfb739b4	347
404dc5f3 AC	348	/* MI Register 23: PHY CONTROL Reg(0x17)
	349	* 15: reserved
	350	* 14: tdr_en
	351	* 13: reserved
	352	* 12-11: downshift_attempts
	353	* 10-6: reserved
	354	* 5: jabber_10baseT
	355	* 4: sqe_10baseT
	356	* 3: tp_loopback_10baseT
	357	* 2: preamble_gen_en
	358	* 1: reserved
	359	* 0: force_int
	360	*/
cfb739b4	361
404dc5f3 AC	362	/* MI Register 24: Interrupt Mask Reg(0x18)
	363	* 15-10: reserved
	364	* 9: mdio_sync_lost
	365	* 8: autoneg_status
	366	* 7: hi_bit_err
	367	* 6: np_rx
	368	* 5: err_counter_full
	369	* 4: fifo_over_underflow
	370	* 3: rx_status
	371	* 2: link_status
	372	* 1: automatic_speed
	373	* 0: int_en
	374	*/
cfb739b4	375
cfb739b4	376
404dc5f3 AC	377	/* MI Register 25: Interrupt Status Reg(0x19)
	378	* 15-10: reserved
	379	* 9: mdio_sync_lost
	380	* 8: autoneg_status
	381	* 7: hi_bit_err
	382	* 6: np_rx
	383	* 5: err_counter_full
	384	* 4: fifo_over_underflow
	385	* 3: rx_status
	386	* 2: link_status
	387	* 1: automatic_speed
	388	* 0: int_en
	389	*/
cfb739b4	390
404dc5f3 AC	391	/* MI Register 26: PHY Status Reg(0x1A)
	392	* 15: reserved
	393	* 14-13: autoneg_fault
	394	* 12: autoneg_status
	395	* 11: mdi_x_status
	396	* 10: polarity_status
	397	* 9-8: speed_status
	398	* 7: duplex_status
	399	* 6: link_status
	400	* 5: tx_status
	401	* 4: rx_status
	402	* 3: collision_status
	403	* 2: autoneg_en
	404	* 1: pause_en
	405	* 0: asymmetric_dir
	406	*/
cfb739b4	407
404dc5f3 AC	408	/* MI Register 27: LED Control Reg 1(0x1B)
	409	* 15-14: reserved
	410	* 13-12: led_dup_indicate
	411	* 11-10: led_10baseT
	412	* 9-8: led_collision
	413	* 7-4: reserved
	414	* 3-2: pulse_dur
	415	* 1: pulse_stretch1
	416	* 0: pulse_stretch0
	417	*/
	418
	419	/* MI Register 28: LED Control Reg 2(0x1C)
	420	* 15-12: led_link
	421	* 11-8: led_tx_rx
	422	* 7-4: led_100BaseTX
	423	* 3-0: led_1000BaseT
	424	*/
cfb739b4 GKH	425
	426	/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
	427
cfb739b4	428
cfb739b4	429	/* Prototypes for ET1310_phy.c */
cfb739b4 GKH	430	/* Defines for PHY access routines */
cfb739b4 GKH	431
64f93036	432	/* Define bit operation flags */
cfb739b4 GKH	433	#define TRUEPHY_BIT_CLEAR 0
	434	#define TRUEPHY_BIT_SET 1
	435	#define TRUEPHY_BIT_READ 2
	436
64f93036	437	/* Define read/write operation flags */
cfb739b4 GKH	438	#ifndef TRUEPHY_READ
	439	#define TRUEPHY_READ 0
	440	#define TRUEPHY_WRITE 1
	441	#define TRUEPHY_MASK 2
	442	#endif
	443
64f93036	444	/* Define speeds */
cfb739b4 GKH	445	#define TRUEPHY_SPEED_10MBPS 0
	446	#define TRUEPHY_SPEED_100MBPS 1
	447	#define TRUEPHY_SPEED_1000MBPS 2
	448
64f93036	449	/* Define duplex modes */
cfb739b4 GKH	450	#define TRUEPHY_DUPLEX_HALF 0
	451	#define TRUEPHY_DUPLEX_FULL 1
	452
64f93036	453	/* Define master/slave configuration values */
cfb739b4 GKH	454	#define TRUEPHY_CFG_SLAVE 0
	455	#define TRUEPHY_CFG_MASTER 1
	456
64f93036	457	/* Define MDI/MDI-X settings */
cfb739b4 GKH	458	#define TRUEPHY_MDI 0
	459	#define TRUEPHY_MDIX 1
	460	#define TRUEPHY_AUTO_MDI_MDIX 2
	461
64f93036	462	/* Define 10Base-T link polarities */
cfb739b4 GKH	463	#define TRUEPHY_POLARITY_NORMAL 0
	464	#define TRUEPHY_POLARITY_INVERTED 1
	465
64f93036	466	/* Define auto-negotiation results */
cfb739b4 GKH	467	#define TRUEPHY_ANEG_NOT_COMPLETE 0
	468	#define TRUEPHY_ANEG_COMPLETE 1
	469	#define TRUEPHY_ANEG_DISABLED 2
	470
25985edc	471	/* Define duplex advertisement flags */
cfb739b4 GKH	472	#define TRUEPHY_ADV_DUPLEX_NONE 0x00
	473	#define TRUEPHY_ADV_DUPLEX_FULL 0x01
	474	#define TRUEPHY_ADV_DUPLEX_HALF 0x02
	475	#define TRUEPHY_ADV_DUPLEX_BOTH \
	476	(TRUEPHY_ADV_DUPLEX_FULL \| TRUEPHY_ADV_DUPLEX_HALF)
	477
64f93036 AC	478	#define PHY_CONTROL 0x00 /* #define TRU_MI_CONTROL_REGISTER 0 */
	479	#define PHY_STATUS 0x01 /* #define TRU_MI_STATUS_REGISTER 1 */
	480	#define PHY_ID_1 0x02 /* #define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2 */
	481	#define PHY_ID_2 0x03 /* #define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3 */
	482	#define PHY_AUTO_ADVERTISEMENT 0x04 /* #define TRU_MI_ADVERTISEMENT_REGISTER 4 */
	483	#define PHY_AUTO_LINK_PARTNER 0x05 /* #define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5 */
	484	#define PHY_AUTO_EXPANSION 0x06 /* #define TRU_MI_EXPANSION_REGISTER 6 */
	485	#define PHY_AUTO_NEXT_PAGE_TX 0x07 /* #define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7 */
	486	#define PHY_LINK_PARTNER_NEXT_PAGE 0x08 /* #define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8 */
	487	#define PHY_1000_CONTROL 0x09 /* #define TRU_MI_1000BASET_CONTROL_REGISTER 9 */
	488	#define PHY_1000_STATUS 0x0A /* #define TRU_MI_1000BASET_STATUS_REGISTER 10 */
	489
	490	#define PHY_EXTENDED_STATUS 0x0F /* #define TRU_MI_EXTENDED_STATUS_REGISTER 15 */
	491
	492	/* some defines for modem registers that seem to be 'reserved' */
cfb739b4 GKH	493	#define PHY_INDEX_REG 0x10
	494	#define PHY_DATA_REG 0x11
	495
64f93036 AC	496	#define PHY_MPHY_CONTROL_REG 0x12 /* #define TRU_VMI_MPHY_CONTROL_REGISTER 18 */
	497
	498	#define PHY_LOOPBACK_CONTROL 0x13 /* #define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19 */
	499	/* #define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20 */
	500	#define PHY_REGISTER_MGMT_CONTROL 0x15 /* #define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21 */
	501	#define PHY_CONFIG 0x16 /* #define TRU_VMI_CONFIGURATION_REGISTER 22 */
	502	#define PHY_PHY_CONTROL 0x17 /* #define TRU_VMI_PHY_CONTROL_REGISTER 23 */
	503	#define PHY_INTERRUPT_MASK 0x18 /* #define TRU_VMI_INTERRUPT_MASK_REGISTER 24 */
	504	#define PHY_INTERRUPT_STATUS 0x19 /* #define TRU_VMI_INTERRUPT_STATUS_REGISTER 25 */
	505	#define PHY_PHY_STATUS 0x1A /* #define TRU_VMI_PHY_STATUS_REGISTER 26 */
	506	#define PHY_LED_1 0x1B /* #define TRU_VMI_LED_CONTROL_1_REGISTER 27 */
	507	#define PHY_LED_2 0x1C /* #define TRU_VMI_LED_CONTROL_2_REGISTER 28 */
	508	/* #define TRU_VMI_LINK_CONTROL_REGISTER 29 */
	509	/* #define TRU_VMI_TIMING_CONTROL_REGISTER */
cfb739b4	510
cfb739b4	511	#endif /* _ET1310_PHY_H_ */