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PM / AVS: rockchip-io: add io selectors and supplies for rk3399
[linux-2.6-block.git] / drivers / staging / emxx_udc / emxx_udc.c
CommitLineData
33aa8d45
MD		 1/*
2 * drivers/usb/gadget/emxx_udc.c
3 * EMXX FCD (Function Controller Driver) for USB.
4 *
5 * Copyright (C) 2010 Renesas Electronics Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
33aa8d45
MD		 15 */
16
17#include <linux/kernel.h>
0af61e66 18#include <linux/init.h>
33aa8d45
MD		 19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/interrupt.h>
27#include <linux/proc_fs.h>
28#include <linux/clk.h>
29#include <linux/ctype.h>
30#include <linux/string.h>
31#include <linux/dma-mapping.h>
32#include <linux/workqueue.h>
a790ebc1 33#include <linux/device.h>
33aa8d45
MD		 34
35#include <linux/usb/ch9.h>
36#include <linux/usb/gadget.h>
37
38#include <linux/irq.h>
39#include <linux/gpio.h>
40
41#include "emxx_udc.h"
42
33aa8d45
MD		 43#define DMA_ADDR_INVALID (~(dma_addr_t)0)
44
45static const char driver_name[] = "emxx_udc";
33aa8d45
MD		 46
47/*===========================================================================*/
48/* Prototype */
49static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
50static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
51/*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/
52static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
53static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
54static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
55
56static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
57static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
58
59/*===========================================================================*/
60/* Macro */
61#define _nbu2ss_zero_len_pkt(udc, epnum) \
62 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
63
33aa8d45
MD		 64/*===========================================================================*/
65/* Global */
66struct nbu2ss_udc udc_controller;
67
33aa8d45
MD		 68/*-------------------------------------------------------------------------*/
69/* Read */
70static inline u32 _nbu2ss_readl(void *address)
71{
ce1e3eb7 72 return __raw_readl(address);
33aa8d45
MD		 73}
74
75/*-------------------------------------------------------------------------*/
76/* Write */
77static inline void _nbu2ss_writel(void *address, u32 udata)
78{
ce1e3eb7 79 __raw_writel(udata, address);
33aa8d45
MD		 80}
81
82/*-------------------------------------------------------------------------*/
83/* Set Bit */
84static inline void _nbu2ss_bitset(void *address, u32 udata)
85{
86 u32 reg_dt = __raw_readl(address) | (udata);
7f39ae05 87
ce1e3eb7 88 __raw_writel(reg_dt, address);
33aa8d45
MD		 89}
90
91/*-------------------------------------------------------------------------*/
92/* Clear Bit */
93static inline void _nbu2ss_bitclr(void *address, u32 udata)
94{
95 u32 reg_dt = __raw_readl(address) & ~(udata);
7f39ae05 96
ce1e3eb7 97 __raw_writel(reg_dt, address);
33aa8d45
MD		 98}
99
100#ifdef UDC_DEBUG_DUMP
101/*-------------------------------------------------------------------------*/
102static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
103{
104 int i;
105 u32 reg_data;
106
107 pr_info("=== %s()\n", __func__);
108
706eb8cf 109 if (!udc) {
88689279 110 pr_err("%s udc == NULL\n", __func__);
33aa8d45
MD		 111 return;
112 }
113
114 spin_unlock(&udc->lock);
115
fb71d24b 116 dev_dbg(&udc->dev, "\n-USB REG-\n");
33aa8d45
MD		 117 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
118 reg_data = _nbu2ss_readl(
119 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i));
fb71d24b 120 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
33aa8d45
MD		 121
122 reg_data = _nbu2ss_readl(
123 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
fb71d24b 124 dev_dbg(&udc->dev, " %08x", (int)reg_data);
33aa8d45
MD		 125
126 reg_data = _nbu2ss_readl(
127 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
fb71d24b 128 dev_dbg(&udc->dev, " %08x", (int)reg_data);
33aa8d45
MD		 129
130 reg_data = _nbu2ss_readl(
131 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
fb71d24b 132 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
33aa8d45
MD		 133
134 }
135
136 spin_lock(&udc->lock);
137}
138#endif /* UDC_DEBUG_DUMP */
139
140/*-------------------------------------------------------------------------*/
141/* Endpoint 0 Callback (Complete) */
142static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
143{
144 u8 recipient;
145 u16 selector;
146 u32 test_mode;
147 struct usb_ctrlrequest *p_ctrl;
148 struct nbu2ss_udc *udc;
149
706eb8cf 150 if ((!_ep) || (!_req))
33aa8d45
MD		 151 return;
152
153 udc = (struct nbu2ss_udc *)_req->context;
154 p_ctrl = &udc->ctrl;
155 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
156
157 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
158 /*-------------------------------------------------*/
159 /* SET_FEATURE */
160 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
161 selector = p_ctrl->wValue;
162 if ((recipient == USB_RECIP_DEVICE) &&
163 (selector == USB_DEVICE_TEST_MODE)) {
164 test_mode = (u32)(p_ctrl->wIndex >> 8);
165 _nbu2ss_set_test_mode(udc, test_mode);
166 }
167 }
168 }
169}
170
171/*-------------------------------------------------------------------------*/
172/* Initialization usb_request */
173static void _nbu2ss_create_ep0_packet(
174 struct nbu2ss_udc *udc,
175 void *p_buf,
176 unsigned length
177)
178{
179 udc->ep0_req.req.buf = p_buf;
180 udc->ep0_req.req.length = length;
181 udc->ep0_req.req.dma = 0;
182 udc->ep0_req.req.zero = TRUE;
183 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
184 udc->ep0_req.req.status = -EINPROGRESS;
185 udc->ep0_req.req.context = udc;
186 udc->ep0_req.req.actual = 0;
187}
188
189/*-------------------------------------------------------------------------*/
190/* Acquisition of the first address of RAM(FIFO) */
191static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
192{
193 u32 num, buf_type;
194 u32 data, last_ram_adr, use_ram_size;
195
f6ef6c09 196 struct ep_regs *p_ep_regs;
33aa8d45
MD		 197
198 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
199 use_ram_size = 0;
200
201 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
202 p_ep_regs = &udc->p_regs->EP_REGS[num];
203 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
204 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPn_BUF_TYPE;
205 if (buf_type == 0) {
206 /* Single Buffer */
207 use_ram_size += (data & EPn_MPKT) / sizeof(u32);
208 } else {
209 /* Double Buffer */
210 use_ram_size += ((data & EPn_MPKT) / sizeof(u32)) * 2;
211 }
212
213 if ((data >> 16) > last_ram_adr)
ba57f5fa 214 last_ram_adr = data >> 16;
33aa8d45
MD		 215 }
216
217 return last_ram_adr + use_ram_size;
218}
219
220/*-------------------------------------------------------------------------*/
221/* Construction of Endpoint */
222static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
223{
224 u32 num;
225 u32 data;
226 u32 begin_adrs;
227
228 if (ep->epnum == 0)
229 return -EINVAL;
230
231 num = ep->epnum - 1;
232
233 /*-------------------------------------------------------------*/
234 /* RAM Transfer Address */
235 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
236 data = (begin_adrs << 16) | ep->ep.maxpacket;
237 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
238
239 /*-------------------------------------------------------------*/
240 /* Interrupt Enable */
241 data = 1 << (ep->epnum + 8);
242 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
243
244 /*-------------------------------------------------------------*/
245 /* Endpoint Type(Mode) */
246 /* Bulk, Interrupt, ISO */
247 switch (ep->ep_type) {
248 case USB_ENDPOINT_XFER_BULK:
249 data = EPn_BULK;
250 break;
251
252 case USB_ENDPOINT_XFER_INT:
253 data = EPn_BUF_SINGLE | EPn_INTERRUPT;
254 break;
255
256 case USB_ENDPOINT_XFER_ISOC:
257 data = EPn_ISO;
258 break;
259
260 default:
261 data = 0;
262 break;
263 }
264
265 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
266 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum|ep->direct));
267
268 if (ep->direct == USB_DIR_OUT) {
269 /*---------------------------------------------------------*/
270 /* OUT */
271 data = EPn_EN | EPn_BCLR | EPn_DIR0;
272 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
273
274 data = (EPn_ONAK | EPn_OSTL_EN | EPn_OSTL);
275 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
276
277 data = (EPn_OUT_EN | EPn_OUT_END_EN);
278 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
279 } else {
280 /*---------------------------------------------------------*/
281 /* IN */
282 data = (EPn_EN | EPn_BCLR | EPn_AUTO);
283 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
284
285 data = (EPn_ISTL);
286 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
287
288 data = (EPn_IN_EN | EPn_IN_END_EN);
289 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
290 }
291
292 return 0;
293}
294
295/*-------------------------------------------------------------------------*/
296/* Release of Endpoint */
297static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
298{
299 u32 num;
300 u32 data;
301
302 if ((ep->epnum == 0) || (udc->vbus_active == 0))
303 return -EINVAL;
304
305 num = ep->epnum - 1;
306
307 /*-------------------------------------------------------------*/
308 /* RAM Transfer Address */
309 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
310
311 /*-------------------------------------------------------------*/
312 /* Interrupt Disable */
313 data = 1 << (ep->epnum + 8);
314 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
315
316 if (ep->direct == USB_DIR_OUT) {
317 /*---------------------------------------------------------*/
318 /* OUT */
319 data = EPn_ONAK | EPn_BCLR;
320 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
321
322 data = EPn_EN | EPn_DIR0;
323 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
324
325 data = EPn_OUT_EN | EPn_OUT_END_EN;
326 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
327 } else {
328 /*---------------------------------------------------------*/
329 /* IN */
330 data = EPn_BCLR;
331 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
332
333 data = EPn_EN | EPn_AUTO;
334 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
335
336 data = EPn_IN_EN | EPn_IN_END_EN;
337 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
338 }
339
340 return 0;
341}
342
343/*-------------------------------------------------------------------------*/
344/* DMA setting (without Endpoint 0) */
345static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
346{
347 u32 num;
348 u32 data;
349
350 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
351 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
352 return; /* Not Support DMA */
353
354 num = ep->epnum - 1;
355
356 if (ep->direct == USB_DIR_OUT) {
357 /*---------------------------------------------------------*/
358 /* OUT */
359 data = ep->ep.maxpacket;
360 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
361
362 /*---------------------------------------------------------*/
363 /* Transfer Direct */
364 data = DCR1_EPn_DIR0;
365 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
366
367 /*---------------------------------------------------------*/
368 /* DMA Mode etc. */
369 data = EPn_STOP_MODE | EPn_STOP_SET | EPn_DMAMODE0;
370 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
371 } else {
372 /*---------------------------------------------------------*/
373 /* IN */
374 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPn_AUTO);
375
376 /*---------------------------------------------------------*/
377 /* DMA Mode etc. */
378 data = EPn_BURST_SET | EPn_DMAMODE0;
379 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
380 }
381}
382
383/*-------------------------------------------------------------------------*/
384/* DMA setting release */
385static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
386{
387 u32 num;
388 u32 data;
f6ef6c09 389 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 390
391 if (udc->vbus_active == 0)
392 return; /* VBUS OFF */
393
394 data = _nbu2ss_readl(&preg->USBSSCONF);
395 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
396 return; /* Not Support DMA */
397
398 num = ep->epnum - 1;
399
400 _nbu2ss_ep_dma_abort(udc, ep);
401
402 if (ep->direct == USB_DIR_OUT) {
403 /*---------------------------------------------------------*/
404 /* OUT */
405 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
406 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_DIR0);
407 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
408 } else {
409 /*---------------------------------------------------------*/
410 /* IN */
411 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
412 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
413 }
414}
415
416/*-------------------------------------------------------------------------*/
417/* Abort DMA */
418static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
419{
f6ef6c09 420 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 421
422 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum-1].EP_DCR1, DCR1_EPn_REQEN);
423 mdelay(DMA_DISABLE_TIME); /* DCR1_EPn_REQEN Clear */
424 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum-1].EP_DMA_CTRL, EPn_DMA_EN);
425}
426
427/*-------------------------------------------------------------------------*/
428/* Start IN Transfer */
429static void _nbu2ss_ep_in_end(
430 struct nbu2ss_udc *udc,
431 u32 epnum,
432 u32 data32,
433 u32 length
434)
435{
436 u32 data;
437 u32 num;
f6ef6c09 438 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 439
440 if (length >= sizeof(u32))
441 return;
442
443 if (epnum == 0) {
444 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
445
446 /* Writing of 1-4 bytes */
447 if (length)
448 _nbu2ss_writel(&preg->EP0_WRITE, data32);
449
450 data = ((length << 5) & EP0_DW) | EP0_DEND;
451 _nbu2ss_writel(&preg->EP0_CONTROL, data);
452
453 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
454 } else {
455 num = epnum - 1;
456
457 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
458
459 /* Writing of 1-4 bytes */
460 if (length)
461 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
462
463 data = (((((u32)length) << 5) & EPn_DW) | EPn_DEND);
464 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
465
466 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
467 }
33aa8d45
MD		 468}
469
470#ifdef USE_DMA
471/*-------------------------------------------------------------------------*/
472static void _nbu2ss_dma_map_single(
473 struct nbu2ss_udc *udc,
474 struct nbu2ss_ep *ep,
475 struct nbu2ss_req *req,
476 u8 direct
477)
478{
479 if (req->req.dma == DMA_ADDR_INVALID) {
480 if (req->unaligned)
481 req->req.dma = ep->phys_buf;
482 else {
483 req->req.dma = dma_map_single(
484 udc->gadget.dev.parent,
485 req->req.buf,
486 req->req.length,
487 (direct == USB_DIR_IN)
488 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
489 }
490 req->mapped = 1;
491 } else {
492 if (!req->unaligned)
493 dma_sync_single_for_device(
494 udc->gadget.dev.parent,
495 req->req.dma,
496 req->req.length,
497 (direct == USB_DIR_IN)
498 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
499
500 req->mapped = 0;
501 }
502}
503
504/*-------------------------------------------------------------------------*/
505static void _nbu2ss_dma_unmap_single(
506 struct nbu2ss_udc *udc,
507 struct nbu2ss_ep *ep,
508 struct nbu2ss_req *req,
509 u8 direct
510)
511{
512 u8 data[4];
513 u8 *p;
514 u32 count = 0;
515
516 if (direct == USB_DIR_OUT) {
517 count = req->req.actual % 4;
518 if (count) {
519 p = req->req.buf;
520 p += (req->req.actual - count);
521 memcpy(data, p, count);
522 }
523 }
524
525 if (req->mapped) {
526 if (req->unaligned) {
527 if (direct == USB_DIR_OUT)
528 memcpy(req->req.buf, ep->virt_buf,
529 req->req.actual & 0xfffffffc);
530 } else
531 dma_unmap_single(udc->gadget.dev.parent,
532 req->req.dma, req->req.length,
533 (direct == USB_DIR_IN)
534 ? DMA_TO_DEVICE
535 : DMA_FROM_DEVICE);
536 req->req.dma = DMA_ADDR_INVALID;
537 req->mapped = 0;
538 } else {
539 if (!req->unaligned)
540 dma_sync_single_for_cpu(udc->gadget.dev.parent,
541 req->req.dma, req->req.length,
542 (direct == USB_DIR_IN)
543 ? DMA_TO_DEVICE
544 : DMA_FROM_DEVICE);
545 }
546
547 if (count) {
548 p = req->req.buf;
549 p += (req->req.actual - count);
550 memcpy(p, data, count);
551 }
552}
553#endif
554
555/*-------------------------------------------------------------------------*/
556/* Endpoint 0 OUT Transfer (PIO) */
a2c14e97 557static int EP0_out_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
33aa8d45
MD		 558{
559 u32 i;
560 int nret = 0;
561 u32 iWordLength = 0;
f6ef6c09 562 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45
MD		 563
564 /*------------------------------------------------------------*/
565 /* Read Length */
566 iWordLength = length / sizeof(u32);
567
568 /*------------------------------------------------------------*/
569 /* PIO Read */
570 if (iWordLength) {
571 for (i = 0; i < iWordLength; i++) {
572 pBuf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
573 pBuf32++;
574 }
575 nret = iWordLength * sizeof(u32);
576 }
577
578 return nret;
579}
580
581/*-------------------------------------------------------------------------*/
582/* Endpoint 0 OUT Transfer (PIO, OverBytes) */
a2c14e97 583static int EP0_out_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
33aa8d45
MD		 584{
585 u32 i;
586 u32 iReadSize = 0;
f6ef6c09
HM		 587 union usb_reg_access Temp32;
588 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45 589
2866914c 590 if ((length > 0) && (length < sizeof(u32))) {
33aa8d45
MD		 591 Temp32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
592 for (i = 0 ; i < length ; i++)
593 pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
594 iReadSize += length;
595 }
596
597 return iReadSize;
598}
599
600/*-------------------------------------------------------------------------*/
601/* Endpoint 0 IN Transfer (PIO) */
602static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
603{
604 u32 i;
605 u32 iMaxLength = EP0_PACKETSIZE;
606 u32 iWordLength = 0;
607 u32 iWriteLength = 0;
f6ef6c09 608 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45
MD		 609
610 /*------------------------------------------------------------*/
611 /* Transfer Length */
612 if (iMaxLength < length)
613 iWordLength = iMaxLength / sizeof(u32);
614 else
615 iWordLength = length / sizeof(u32);
616
617 /*------------------------------------------------------------*/
618 /* PIO */
619 for (i = 0; i < iWordLength; i++) {
620 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, pBuf32->dw);
621 pBuf32++;
622 iWriteLength += sizeof(u32);
623 }
624
625 return iWriteLength;
626}
627
628/*-------------------------------------------------------------------------*/
629/* Endpoint 0 IN Transfer (PIO, OverBytes) */
630static int EP0_in_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 iRemainSize)
631{
632 u32 i;
f6ef6c09
HM		 633 union usb_reg_access Temp32;
634 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45 635
2866914c 636 if ((iRemainSize > 0) && (iRemainSize < sizeof(u32))) {
33aa8d45
MD		 637 for (i = 0 ; i < iRemainSize ; i++)
638 Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
639 _nbu2ss_ep_in_end(udc, 0, Temp32.dw, iRemainSize);
640
641 return iRemainSize;
642 }
643
644 return 0;
645}
646
647/*-------------------------------------------------------------------------*/
648/* Transfer NULL Packet (Epndoint 0) */
649static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
650{
651 u32 data;
652
653 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
654 data &= ~(u32)EP0_INAK;
655
656 if (pid_flag)
657 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
658 else
659 data |= (EP0_INAK_EN | EP0_DEND);
660
661 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
662
663 return 0;
664}
665
666/*-------------------------------------------------------------------------*/
667/* Receive NULL Packet (Endpoint 0) */
668static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
669{
670 u32 data;
671
672 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
673 data &= ~(u32)EP0_ONAK;
674
675 if (pid_flag)
676 data |= EP0_PIDCLR;
677
678 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
679
680 return 0;
681}
682
683/*-------------------------------------------------------------------------*/
684static int _nbu2ss_ep0_in_transfer(
685 struct nbu2ss_udc *udc,
33aa8d45
MD		 686 struct nbu2ss_req *req
687)
688{
689 u8 *pBuffer; /* IN Data Buffer */
690 u32 data;
691 u32 iRemainSize = 0;
692 int result = 0;
693
694 /*-------------------------------------------------------------*/
695 /* End confirmation */
696 if (req->req.actual == req->req.length) {
697 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
698 if (req->zero) {
666e9084 699 req->zero = false;
33aa8d45
MD		 700 EP0_send_NULL(udc, FALSE);
701 return 1;
702 }
703 }
704
705 return 0; /* Transfer End */
706 }
707
708 /*-------------------------------------------------------------*/
709 /* NAK release */
710 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
711 data |= EP0_INAK_EN;
712 data &= ~(u32)EP0_INAK;
713 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
714
715 iRemainSize = req->req.length - req->req.actual;
716 pBuffer = (u8 *)req->req.buf;
717 pBuffer += req->req.actual;
718
719 /*-------------------------------------------------------------*/
720 /* Data transfer */
721 result = EP0_in_PIO(udc, pBuffer, iRemainSize);
722
723 req->div_len = result;
724 iRemainSize -= result;
725
726 if (iRemainSize == 0) {
727 EP0_send_NULL(udc, FALSE);
728 return result;
729 }
730
731 if ((iRemainSize < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
732 pBuffer += result;
733 result += EP0_in_OverBytes(udc, pBuffer, iRemainSize);
734 req->div_len = result;
735 }
736
737 return result;
738}
739
740/*-------------------------------------------------------------------------*/
741static int _nbu2ss_ep0_out_transfer(
742 struct nbu2ss_udc *udc,
33aa8d45
MD		 743 struct nbu2ss_req *req
744)
745{
746 u8 *pBuffer;
747 u32 iRemainSize;
748 u32 iRecvLength;
749 int result = 0;
750 int fRcvZero;
751
752 /*-------------------------------------------------------------*/
753 /* Receive data confirmation */
754 iRecvLength = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
755 if (iRecvLength != 0) {
756
757 fRcvZero = 0;
758
759 iRemainSize = req->req.length - req->req.actual;
760 pBuffer = (u8 *)req->req.buf;
761 pBuffer += req->req.actual;
762
763 result = EP0_out_PIO(udc, pBuffer
764 , min(iRemainSize, iRecvLength));
765 if (result < 0)
766 return result;
767
768 req->req.actual += result;
769 iRecvLength -= result;
770
2866914c 771 if ((iRecvLength > 0) && (iRecvLength < sizeof(u32))) {
33aa8d45
MD		 772 pBuffer += result;
773 iRemainSize -= result;
774
775 result = EP0_out_OverBytes(udc, pBuffer
776 , min(iRemainSize, iRecvLength));
777 req->req.actual += result;
778 }
779 } else {
780 fRcvZero = 1;
781 }
782
783 /*-------------------------------------------------------------*/
784 /* End confirmation */
785 if (req->req.actual == req->req.length) {
786 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
787 if (req->zero) {
666e9084 788 req->zero = false;
33aa8d45
MD		 789 EP0_receive_NULL(udc, FALSE);
790 return 1;
791 }
792 }
793
794 return 0; /* Transfer End */
795 }
796
797 if ((req->req.actual % EP0_PACKETSIZE) != 0)
798 return 0; /* Short Packet Transfer End */
799
800 if (req->req.actual > req->req.length) {
88689279 801 dev_err(udc->dev, " *** Overrun Error\n");
33aa8d45
MD		 802 return -EOVERFLOW;
803 }
804
805 if (fRcvZero != 0) {
806 iRemainSize = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
807 if (iRemainSize & EP0_ONAK) {
808 /*---------------------------------------------------*/
809 /* NACK release */
810 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
811 }
812 result = 1;
813 }
814
815 return result;
816}
817
818/*-------------------------------------------------------------------------*/
819static int _nbu2ss_out_dma(
820 struct nbu2ss_udc *udc,
821 struct nbu2ss_req *req,
822 u32 num,
823 u32 length
824)
825{
e7cfb390 826 dma_addr_t pBuffer;
33aa8d45
MD		 827 u32 mpkt;
828 u32 lmpkt;
829 u32 dmacnt;
830 u32 burst = 1;
831 u32 data;
832 int result = -EINVAL;
f6ef6c09 833 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 834
835 if (req->dma_flag)
836 return 1; /* DMA is forwarded */
837
838 req->dma_flag = TRUE;
e7cfb390 839 pBuffer = req->req.dma;
33aa8d45
MD		 840 pBuffer += req->req.actual;
841
842 /* DMA Address */
843 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
844
845 /* Number of transfer packets */
846 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
847 dmacnt = (length / mpkt);
848 lmpkt = (length % mpkt) & ~(u32)0x03;
849
2866914c 850 if (dmacnt > DMA_MAX_COUNT) {
33aa8d45
MD		 851 dmacnt = DMA_MAX_COUNT;
852 lmpkt = 0;
2866914c
CM		 853 } else if (lmpkt != 0) {
854 if (dmacnt == 0)
33aa8d45
MD		 855 burst = 0; /* Burst OFF */
856 dmacnt++;
857 }
858
859 data = mpkt | (lmpkt << 16);
860 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
861
862 data = ((dmacnt & 0xff) << 16) | DCR1_EPn_DIR0 | DCR1_EPn_REQEN;
863 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
864
2866914c 865 if (burst == 0) {
33aa8d45
MD		 866 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
867 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
868 } else {
869 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
870 , (dmacnt << 16));
871 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
872 }
873 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
874
875 result = length & ~(u32)0x03;
876 req->div_len = result;
877
878 return result;
879}
880
881/*-------------------------------------------------------------------------*/
882static int _nbu2ss_epn_out_pio(
883 struct nbu2ss_udc *udc,
884 struct nbu2ss_ep *ep,
885 struct nbu2ss_req *req,
886 u32 length
887)
888{
889 u8 *pBuffer;
890 u32 i;
891 u32 data;
892 u32 iWordLength;
f6ef6c09
HM		 893 union usb_reg_access Temp32;
894 union usb_reg_access *pBuf32;
33aa8d45 895 int result = 0;
f6ef6c09 896 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 897
898 if (req->dma_flag)
899 return 1; /* DMA is forwarded */
900
901 if (length == 0)
902 return 0;
903
904 pBuffer = (u8 *)req->req.buf;
f6ef6c09 905 pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
33aa8d45
MD		 906
907 iWordLength = length / sizeof(u32);
908 if (iWordLength > 0) {
909 /*---------------------------------------------------------*/
910 /* Copy of every four bytes */
911 for (i = 0; i < iWordLength; i++) {
912 pBuf32->dw =
913 _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ);
914 pBuf32++;
915 }
916 result = iWordLength * sizeof(u32);
917 }
918
919 data = length - result;
920 if (data > 0) {
921 /*---------------------------------------------------------*/
922 /* Copy of fraction byte */
923 Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ);
924 for (i = 0 ; i < data ; i++)
925 pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
926 result += data;
927 }
928
929 req->req.actual += result;
930
931 if ((req->req.actual == req->req.length)
932 || ((req->req.actual % ep->ep.maxpacket) != 0)) {
933
934 result = 0;
935 }
936
937 return result;
938}
939
940/*-------------------------------------------------------------------------*/
941static int _nbu2ss_epn_out_data(
942 struct nbu2ss_udc *udc,
943 struct nbu2ss_ep *ep,
944 struct nbu2ss_req *req,
945 u32 data_size
946)
947{
948 u32 num;
949 u32 iBufSize;
950 int nret = 1;
951
952 if (ep->epnum == 0)
953 return -EINVAL;
954
955 num = ep->epnum - 1;
956
957 iBufSize = min((req->req.length - req->req.actual), data_size);
958
959 if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
960 && (req->req.dma != 0)
961 && (iBufSize >= sizeof(u32))) {
962 nret = _nbu2ss_out_dma(udc, req, num, iBufSize);
963 } else {
77d966f4 964 iBufSize = min_t(u32, iBufSize, ep->ep.maxpacket);
33aa8d45
MD		 965 nret = _nbu2ss_epn_out_pio(udc, ep, req, iBufSize);
966 }
967
968 return nret;
969}
970
971/*-------------------------------------------------------------------------*/
972static int _nbu2ss_epn_out_transfer(
973 struct nbu2ss_udc *udc,
974 struct nbu2ss_ep *ep,
975 struct nbu2ss_req *req
976)
977{
978 u32 num;
979 u32 iRecvLength;
980 int result = 1;
f6ef6c09 981 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 982
983 if (ep->epnum == 0)
984 return -EINVAL;
985
986 num = ep->epnum - 1;
987
988 /*-------------------------------------------------------------*/
989 /* Receive Length */
990 iRecvLength
991 = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPn_LDATA;
992
993 if (iRecvLength != 0) {
994 result = _nbu2ss_epn_out_data(udc, ep, req, iRecvLength);
995 if (iRecvLength < ep->ep.maxpacket) {
996 if (iRecvLength == result) {
997 req->req.actual += result;
998 result = 0;
999 }
1000 }
1001 } else {
1002 if ((req->req.actual == req->req.length)
1003 || ((req->req.actual % ep->ep.maxpacket) != 0)) {
1004
1005 result = 0;
1006 }
1007 }
1008
1009 if (result == 0) {
1010 if ((req->req.actual % ep->ep.maxpacket) == 0) {
1011 if (req->zero) {
666e9084 1012 req->zero = false;
33aa8d45
MD		 1013 return 1;
1014 }
1015 }
1016 }
1017
1018 if (req->req.actual > req->req.length) {
88689279
HM		 1019 dev_err(udc->dev, " Overrun Error\n");
1020 dev_err(udc->dev, " actual = %d, length = %d\n",
33aa8d45
MD		 1021 req->req.actual, req->req.length);
1022 result = -EOVERFLOW;
1023 }
1024
1025 return result;
1026}
1027
1028/*-------------------------------------------------------------------------*/
1029static int _nbu2ss_in_dma(
1030 struct nbu2ss_udc *udc,
1031 struct nbu2ss_ep *ep,
1032 struct nbu2ss_req *req,
1033 u32 num,
1034 u32 length
1035)
1036{
e7cfb390 1037 dma_addr_t pBuffer;
33aa8d45
MD		 1038 u32 mpkt; /* MaxPacketSize */
1039 u32 lmpkt; /* Last Packet Data Size */
1040 u32 dmacnt; /* IN Data Size */
1041 u32 iWriteLength;
1042 u32 data;
1043 int result = -EINVAL;
f6ef6c09 1044 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1045
1046 if (req->dma_flag)
1047 return 1; /* DMA is forwarded */
1048
1049#ifdef USE_DMA
1050 if (req->req.actual == 0)
1051 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
1052#endif
1053 req->dma_flag = TRUE;
1054
1055 /* MAX Packet Size */
1056 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
1057
1058 if ((DMA_MAX_COUNT * mpkt) < length)
1059 iWriteLength = DMA_MAX_COUNT * mpkt;
1060 else
1061 iWriteLength = length;
1062
1063 /*------------------------------------------------------------*/
1064 /* Number of transmission packets */
1065 if (mpkt < iWriteLength) {
1066 dmacnt = iWriteLength / mpkt;
1067 lmpkt = (iWriteLength % mpkt) & ~(u32)0x3;
1068 if (lmpkt != 0)
1069 dmacnt++;
1070 else
1071 lmpkt = mpkt & ~(u32)0x3;
1072
1073 } else {
1074 dmacnt = 1;
1075 lmpkt = iWriteLength & ~(u32)0x3;
1076 }
1077
1078 /* Packet setting */
1079 data = mpkt | (lmpkt << 16);
1080 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1081
1082 /* Address setting */
e7cfb390 1083 pBuffer = req->req.dma;
33aa8d45
MD		 1084 pBuffer += req->req.actual;
1085 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
1086
1087 /* Packet and DMA setting */
1088 data = ((dmacnt & 0xff) << 16) | DCR1_EPn_REQEN;
1089 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1090
1091 /* Packet setting of EPC */
1092 data = dmacnt << 16;
1093 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1094
1095 /*DMA setting of EPC */
1096 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
1097
1098 result = iWriteLength & ~(u32)0x3;
1099 req->div_len = result;
1100
1101 return result;
1102}
1103
1104/*-------------------------------------------------------------------------*/
1105static int _nbu2ss_epn_in_pio(
1106 struct nbu2ss_udc *udc,
1107 struct nbu2ss_ep *ep,
1108 struct nbu2ss_req *req,
1109 u32 length
1110)
1111{
1112 u8 *pBuffer;
1113 u32 i;
1114 u32 data;
1115 u32 iWordLength;
f6ef6c09
HM		 1116 union usb_reg_access Temp32;
1117 union usb_reg_access *pBuf32 = NULL;
33aa8d45 1118 int result = 0;
f6ef6c09 1119 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1120
1121 if (req->dma_flag)
1122 return 1; /* DMA is forwarded */
1123
1124 if (length > 0) {
1125 pBuffer = (u8 *)req->req.buf;
f6ef6c09 1126 pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
33aa8d45
MD		 1127
1128 iWordLength = length / sizeof(u32);
1129 if (iWordLength > 0) {
1130 for (i = 0; i < iWordLength; i++) {
1131 _nbu2ss_writel(
1132 &preg->EP_REGS[ep->epnum-1].EP_WRITE
1133 , pBuf32->dw
1134 );
1135
1136 pBuf32++;
1137 }
1138 result = iWordLength * sizeof(u32);
1139 }
1140 }
1141
1142 if (result != ep->ep.maxpacket) {
1143 data = length - result;
1144 Temp32.dw = 0;
1145 for (i = 0 ; i < data ; i++)
1146 Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
1147
1148 _nbu2ss_ep_in_end(udc, ep->epnum, Temp32.dw, data);
1149 result += data;
1150 }
1151
1152 req->div_len = result;
1153
1154 return result;
1155}
1156
1157/*-------------------------------------------------------------------------*/
1158static int _nbu2ss_epn_in_data(
1159 struct nbu2ss_udc *udc,
1160 struct nbu2ss_ep *ep,
1161 struct nbu2ss_req *req,
1162 u32 data_size
1163)
1164{
1165 u32 num;
1166 int nret = 1;
1167
1168 if (ep->epnum == 0)
1169 return -EINVAL;
1170
1171 num = ep->epnum - 1;
1172
1173 if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
1174 && (req->req.dma != 0)
1175 && (data_size >= sizeof(u32))) {
1176 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1177 } else {
77d966f4 1178 data_size = min_t(u32, data_size, ep->ep.maxpacket);
33aa8d45
MD		 1179 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1180 }
1181
1182 return nret;
1183}
1184
1185/*-------------------------------------------------------------------------*/
1186static int _nbu2ss_epn_in_transfer(
1187 struct nbu2ss_udc *udc,
1188 struct nbu2ss_ep *ep,
1189 struct nbu2ss_req *req
1190)
1191{
1192 u32 num;
1193 u32 iBufSize;
1194 int result = 0;
1195 u32 status;
1196
1197 if (ep->epnum == 0)
1198 return -EINVAL;
1199
1200 num = ep->epnum - 1;
1201
1202 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1203
1204 /*-------------------------------------------------------------*/
1205 /* State confirmation of FIFO */
1206 if (req->req.actual == 0) {
1207 if ((status & EPn_IN_EMPTY) == 0)
1208 return 1; /* Not Empty */
1209
1210 } else {
1211 if ((status & EPn_IN_FULL) != 0)
1212 return 1; /* Not Empty */
1213 }
1214
1215 /*-------------------------------------------------------------*/
69e98df7 1216 /* Start transfer */
33aa8d45
MD		 1217 iBufSize = req->req.length - req->req.actual;
1218 if (iBufSize > 0)
1219 result = _nbu2ss_epn_in_data(udc, ep, req, iBufSize);
1220 else if (req->req.length == 0)
1221 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1222
1223 return result;
1224}
1225
1226/*-------------------------------------------------------------------------*/
1227static int _nbu2ss_start_transfer(
1228 struct nbu2ss_udc *udc,
1229 struct nbu2ss_ep *ep,
1230 struct nbu2ss_req *req,
1231 bool bflag)
1232{
1233 int nret = -EINVAL;
1234
1235 req->dma_flag = FALSE;
1236 req->div_len = 0;
1237
1238 if (req->req.length == 0)
666e9084 1239 req->zero = false;
33aa8d45
MD		 1240 else {
1241 if ((req->req.length % ep->ep.maxpacket) == 0)
1242 req->zero = req->req.zero;
1243 else
666e9084 1244 req->zero = false;
33aa8d45
MD		 1245 }
1246
1247 if (ep->epnum == 0) {
1248 /* EP0 */
1249 switch (udc->ep0state) {
1250 case EP0_IN_DATA_PHASE:
f2b29165 1251 nret = _nbu2ss_ep0_in_transfer(udc, req);
33aa8d45
MD		 1252 break;
1253
1254 case EP0_OUT_DATA_PHASE:
f2b29165 1255 nret = _nbu2ss_ep0_out_transfer(udc, req);
33aa8d45
MD		 1256 break;
1257
1258 case EP0_IN_STATUS_PHASE:
1259 nret = EP0_send_NULL(udc, TRUE);
1260 break;
1261
1262 default:
1263 break;
1264 }
1265
1266 } else {
1267 /* EPn */
1268 if (ep->direct == USB_DIR_OUT) {
1269 /* OUT */
5a602ac4 1270 if (!bflag)
33aa8d45
MD		 1271 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1272 } else {
1273 /* IN */
1274 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1275 }
1276 }
1277
1278 return nret;
1279}
1280
1281/*-------------------------------------------------------------------------*/
1282static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1283{
1284 u32 length;
1285 bool bflag = FALSE;
1286 struct nbu2ss_req *req;
1287
e59ac747 1288 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1289 if (!req)
33aa8d45
MD		 1290 return;
1291
1292 if (ep->epnum > 0) {
1293 length = _nbu2ss_readl(
1294 &ep->udc->p_regs->EP_REGS[ep->epnum-1].EP_LEN_DCNT);
1295
1296 length &= EPn_LDATA;
1297 if (length < ep->ep.maxpacket)
1298 bflag = TRUE;
1299 }
1300
1301 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1302}
1303
1304/*-------------------------------------------------------------------------*/
1305/* Endpoint Toggle Reset */
1306static void _nbu2ss_endpoint_toggle_reset(
1307 struct nbu2ss_udc *udc,
1308 u8 ep_adrs)
1309{
1310 u8 num;
1311 u32 data;
1312
1313 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1314 return;
1315
1316 num = (ep_adrs & 0x7F) - 1;
1317
1318 if (ep_adrs & USB_DIR_IN)
1319 data = EPn_IPIDCLR;
1320 else
1321 data = EPn_BCLR | EPn_OPIDCLR;
1322
1323 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1324}
1325
1326/*-------------------------------------------------------------------------*/
1327/* Endpoint STALL set */
1328static void _nbu2ss_set_endpoint_stall(
1329 struct nbu2ss_udc *udc,
1330 u8 ep_adrs,
1331 bool bstall)
1332{
1333 u8 num, epnum;
1334 u32 data;
1335 struct nbu2ss_ep *ep;
f6ef6c09 1336 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1337
1338 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1339 if (bstall) {
1340 /* Set STALL */
1341 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1342 } else {
1343 /* Clear STALL */
1344 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1345 }
1346 } else {
1347 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1348 num = epnum - 1;
1349 ep = &udc->ep[epnum];
1350
1351 if (bstall) {
1352 /* Set STALL */
1353 ep->halted = TRUE;
1354
1355 if (ep_adrs & USB_DIR_IN)
1356 data = EPn_BCLR | EPn_ISTL;
1357 else
1358 data = EPn_OSTL_EN | EPn_OSTL;
1359
1360 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1361 } else {
1362 /* Clear STALL */
1363 ep->stalled = FALSE;
1364 if (ep_adrs & USB_DIR_IN) {
1365 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1366 , EPn_ISTL);
1367 } else {
1368 data =
1369 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1370
1371 data &= ~EPn_OSTL;
1372 data |= EPn_OSTL_EN;
1373
1374 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1375 , data);
1376 }
1377
1378 ep->stalled = FALSE;
1379 if (ep->halted) {
1380 ep->halted = FALSE;
1381 _nbu2ss_restert_transfer(ep);
1382 }
1383 }
1384 }
33aa8d45
MD		 1385}
1386
33aa8d45
MD		 1387/*-------------------------------------------------------------------------*/
1388/* Device Descriptor */
1389static struct usb_device_descriptor device_desc = {
1390 .bLength = sizeof(device_desc),
1391 .bDescriptorType = USB_DT_DEVICE,
1ff99b31 1392 .bcdUSB = cpu_to_le16(0x0200),
33aa8d45
MD		 1393 .bDeviceClass = USB_CLASS_VENDOR_SPEC,
1394 .bDeviceSubClass = 0x00,
1395 .bDeviceProtocol = 0x00,
1396 .bMaxPacketSize0 = 64,
1ff99b31
RD		 1397 .idVendor = cpu_to_le16(0x0409),
1398 .idProduct = cpu_to_le16(0xfff0),
33aa8d45
MD		 1399 .bcdDevice = 0xffff,
1400 .iManufacturer = 0x00,
1401 .iProduct = 0x00,
1402 .iSerialNumber = 0x00,
1403 .bNumConfigurations = 0x01,
1404};
1405
1406/*-------------------------------------------------------------------------*/
1407static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1408{
1409 u32 data;
1410
1411 if (mode > MAX_TEST_MODE_NUM)
1412 return;
1413
93275c80 1414 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
33aa8d45
MD		 1415
1416 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1417 data &= ~TEST_FORCE_ENABLE;
1418 data |= mode << TEST_MODE_SHIFT;
1419
1420 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1421 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1422}
1423
1424/*-------------------------------------------------------------------------*/
1425static int _nbu2ss_set_feature_device(
1426 struct nbu2ss_udc *udc,
1427 u16 selector,
1428 u16 wIndex
1429)
1430{
1431 int result = -EOPNOTSUPP;
1432
1433 switch (selector) {
1434 case USB_DEVICE_REMOTE_WAKEUP:
2866914c 1435 if (wIndex == 0x0000) {
33aa8d45
MD		 1436 udc->remote_wakeup = U2F_ENABLE;
1437 result = 0;
1438 }
1439 break;
1440
1441 case USB_DEVICE_TEST_MODE:
410c944e 1442 wIndex >>= 8;
33aa8d45
MD		 1443 if (wIndex <= MAX_TEST_MODE_NUM)
1444 result = 0;
1445 break;
1446
1447 default:
1448 break;
1449 }
1450
1451 return result;
1452}
1453
1454/*-------------------------------------------------------------------------*/
1455static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1456{
1457 u8 epnum;
1458 u32 data = 0, bit_data;
f6ef6c09 1459 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1460
1461 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1462 if (epnum == 0) {
1463 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1464 bit_data = EP0_STL;
1465
1466 } else {
1467 data = _nbu2ss_readl(&preg->EP_REGS[epnum-1].EP_CONTROL);
1468 if ((data & EPn_EN) == 0)
1469 return -1;
1470
1471 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1472 bit_data = EPn_ISTL;
1473 else
1474 bit_data = EPn_OSTL;
1475 }
1476
1477 if ((data & bit_data) == 0)
1478 return 0;
924c6ee1 1479 return 1;
33aa8d45
MD		 1480}
1481
1482/*-------------------------------------------------------------------------*/
1483static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1484{
1485 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1486 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1487 u16 selector = udc->ctrl.wValue;
1488 u16 wIndex = udc->ctrl.wIndex;
1489 u8 ep_adrs;
1490 int result = -EOPNOTSUPP;
1491
2866914c
CM		 1492 if ((udc->ctrl.wLength != 0x0000) ||
1493 (direction != USB_DIR_OUT)) {
33aa8d45
MD		 1494 return -EINVAL;
1495 }
1496
1497 switch (recipient) {
1498 case USB_RECIP_DEVICE:
1499 if (bset)
1500 result =
1501 _nbu2ss_set_feature_device(udc, selector, wIndex);
1502 break;
1503
1504 case USB_RECIP_ENDPOINT:
1505 if (0x0000 == (wIndex & 0xFF70)) {
2866914c 1506 if (selector == USB_ENDPOINT_HALT) {
33aa8d45 1507 ep_adrs = wIndex & 0xFF;
5a602ac4 1508 if (!bset) {
33aa8d45
MD		 1509 _nbu2ss_endpoint_toggle_reset(
1510 udc, ep_adrs);
1511 }
1512
1513 _nbu2ss_set_endpoint_stall(
1514 udc, ep_adrs, bset);
1515
1516 result = 0;
1517 }
1518 }
1519 break;
1520
1521 default:
1522 break;
1523 }
1524
1525 if (result >= 0)
1526 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1527
1528 return result;
1529}
1530
1531/*-------------------------------------------------------------------------*/
1532static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1533{
1534 u32 data;
1535 enum usb_device_speed speed = USB_SPEED_FULL;
1536
1537 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1538 if (data & HIGH_SPEED)
1539 speed = USB_SPEED_HIGH;
1540
1541 return speed;
1542}
1543
1544/*-------------------------------------------------------------------------*/
1545static void _nbu2ss_epn_set_stall(
1546 struct nbu2ss_udc *udc,
1547 struct nbu2ss_ep *ep
1548)
1549{
1550 u8 ep_adrs;
1551 u32 regdata;
1552 int limit_cnt = 0;
1553
f6ef6c09 1554 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1555
1556 if (ep->direct == USB_DIR_IN) {
1557 for (limit_cnt = 0
1558 ; limit_cnt < IN_DATA_EMPTY_COUNT
1559 ; limit_cnt++) {
1560
1561 regdata = _nbu2ss_readl(
1562 &preg->EP_REGS[ep->epnum-1].EP_STATUS);
1563
1564 if ((regdata & EPn_IN_DATA) == 0)
1565 break;
1566
1567 mdelay(1);
1568 }
1569 }
1570
1571 ep_adrs = ep->epnum | ep->direct;
1572 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1573}
1574
1575/*-------------------------------------------------------------------------*/
1576static int std_req_get_status(struct nbu2ss_udc *udc)
1577{
1578 u32 length;
1579 u16 status_data = 0;
1580 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1581 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1582 u8 ep_adrs;
1583 int result = -EINVAL;
1584
2866914c
CM		 1585 if ((udc->ctrl.wValue != 0x0000)
1586 || (direction != USB_DIR_IN)) {
33aa8d45
MD		 1587
1588 return result;
1589 }
1590
77d966f4 1591 length = min_t(u16, udc->ctrl.wLength, sizeof(status_data));
33aa8d45
MD		 1592
1593 switch (recipient) {
1594 case USB_RECIP_DEVICE:
1595 if (udc->ctrl.wIndex == 0x0000) {
9239d88f 1596 if (udc->gadget.is_selfpowered)
33aa8d45
MD		 1597 status_data |= (1 << USB_DEVICE_SELF_POWERED);
1598
1599 if (udc->remote_wakeup)
1600 status_data |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1601
1602 result = 0;
1603 }
1604 break;
1605
1606 case USB_RECIP_ENDPOINT:
1607 if (0x0000 == (udc->ctrl.wIndex & 0xFF70)) {
1608 ep_adrs = (u8)(udc->ctrl.wIndex & 0xFF);
1609 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1610
1611 if (result > 0)
1612 status_data |= (1 << USB_ENDPOINT_HALT);
1613 }
1614 break;
1615
1616 default:
1617 break;
1618 }
1619
1620 if (result >= 0) {
1621 memcpy(udc->ep0_buf, &status_data, length);
1622 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
f2b29165 1623 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
33aa8d45
MD		 1624
1625 } else {
88689279 1626 dev_err(udc->dev, " Error GET_STATUS\n");
33aa8d45
MD		 1627 }
1628
1629 return result;
1630}
1631
1632/*-------------------------------------------------------------------------*/
1633static int std_req_clear_feature(struct nbu2ss_udc *udc)
1634{
1635 return _nbu2ss_req_feature(udc, FALSE);
1636}
1637
1638/*-------------------------------------------------------------------------*/
1639static int std_req_set_feature(struct nbu2ss_udc *udc)
1640{
1641 return _nbu2ss_req_feature(udc, TRUE);
1642}
1643
1644/*-------------------------------------------------------------------------*/
1645static int std_req_set_address(struct nbu2ss_udc *udc)
1646{
1647 int result = 0;
1648 u32 wValue = udc->ctrl.wValue;
1649
2866914c
CM		 1650 if ((udc->ctrl.bRequestType != 0x00) ||
1651 (udc->ctrl.wIndex != 0x0000) ||
1652 (udc->ctrl.wLength != 0x0000)) {
33aa8d45
MD		 1653 return -EINVAL;
1654 }
1655
1656 if (wValue != (wValue & 0x007F))
1657 return -EINVAL;
1658
410c944e 1659 wValue <<= USB_ADRS_SHIFT;
33aa8d45
MD		 1660
1661 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1662 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1663
1664 return result;
1665}
1666
1667/*-------------------------------------------------------------------------*/
1668static int std_req_set_configuration(struct nbu2ss_udc *udc)
1669{
1670 u32 ConfigValue = (u32)(udc->ctrl.wValue & 0x00ff);
1671
2866914c
CM		 1672 if ((udc->ctrl.wIndex != 0x0000) ||
1673 (udc->ctrl.wLength != 0x0000) ||
1674 (udc->ctrl.bRequestType != 0x00)) {
33aa8d45
MD		 1675 return -EINVAL;
1676 }
1677
1678 udc->curr_config = ConfigValue;
1679
1680 if (ConfigValue > 0) {
1681 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1682 udc->devstate = USB_STATE_CONFIGURED;
1683
1684 } else {
1685 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1686 udc->devstate = USB_STATE_ADDRESS;
1687 }
1688
1689 return 0;
1690}
1691
1692/*-------------------------------------------------------------------------*/
1693static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1694{
706eb8cf 1695 if ((!udc) && (!pdata))
33aa8d45
MD		 1696 return;
1697
1698 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1699 pdata++;
1700 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1701}
1702
1703/*-------------------------------------------------------------------------*/
1704static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1705{
1706 bool bcall_back = TRUE;
1707 int nret = -EINVAL;
1708 struct usb_ctrlrequest *p_ctrl;
1709
1710 p_ctrl = &udc->ctrl;
1711 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1712
1713 /* ep0 state control */
1714 if (p_ctrl->wLength == 0) {
1715 udc->ep0state = EP0_IN_STATUS_PHASE;
1716
1717 } else {
1718 if (p_ctrl->bRequestType & USB_DIR_IN)
1719 udc->ep0state = EP0_IN_DATA_PHASE;
1720 else
1721 udc->ep0state = EP0_OUT_DATA_PHASE;
1722 }
1723
1724 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1725 switch (p_ctrl->bRequest) {
1726 case USB_REQ_GET_STATUS:
1727 nret = std_req_get_status(udc);
1728 bcall_back = FALSE;
1729 break;
1730
1731 case USB_REQ_CLEAR_FEATURE:
1732 nret = std_req_clear_feature(udc);
1733 bcall_back = FALSE;
1734 break;
1735
1736 case USB_REQ_SET_FEATURE:
1737 nret = std_req_set_feature(udc);
1738 bcall_back = FALSE;
1739 break;
1740
1741 case USB_REQ_SET_ADDRESS:
1742 nret = std_req_set_address(udc);
1743 bcall_back = FALSE;
1744 break;
1745
1746 case USB_REQ_SET_CONFIGURATION:
1747 nret = std_req_set_configuration(udc);
1748 break;
1749
1750 default:
1751 break;
1752 }
1753 }
1754
5a602ac4 1755 if (!bcall_back) {
33aa8d45
MD		 1756 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1757 if (nret >= 0) {
1758 /*--------------------------------------*/
1759 /* Status Stage */
1760 nret = EP0_send_NULL(udc, TRUE);
1761 }
1762 }
1763
1764 } else {
1765 spin_unlock(&udc->lock);
1766 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1767 spin_lock(&udc->lock);
1768 }
1769
1770 if (nret < 0)
1771 udc->ep0state = EP0_IDLE;
1772
1773 return nret;
1774}
1775
1776/*-------------------------------------------------------------------------*/
1777static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1778{
1779 int nret;
1780 struct nbu2ss_req *req;
1781 struct nbu2ss_ep *ep = &udc->ep[0];
1782
e59ac747 1783 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1784 if (!req)
33aa8d45
MD		 1785 req = &udc->ep0_req;
1786
1787 req->req.actual += req->div_len;
1788 req->div_len = 0;
1789
f2b29165 1790 nret = _nbu2ss_ep0_in_transfer(udc, req);
33aa8d45
MD		 1791 if (nret == 0) {
1792 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1793 EP0_receive_NULL(udc, TRUE);
1794 }
1795
1796 return 0;
1797}
1798
1799/*-------------------------------------------------------------------------*/
1800static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1801{
1802 int nret;
1803 struct nbu2ss_req *req;
1804 struct nbu2ss_ep *ep = &udc->ep[0];
1805
e59ac747 1806 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1807 if (!req)
33aa8d45
MD		 1808 req = &udc->ep0_req;
1809
f2b29165 1810 nret = _nbu2ss_ep0_out_transfer(udc, req);
33aa8d45
MD		 1811 if (nret == 0) {
1812 udc->ep0state = EP0_IN_STATUS_PHASE;
1813 EP0_send_NULL(udc, TRUE);
1814
1815 } else if (nret < 0) {
1816 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1817 req->req.status = nret;
1818 }
1819
1820 return 0;
1821}
1822
1823/*-------------------------------------------------------------------------*/
1824static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1825{
1826 struct nbu2ss_req *req;
1827 struct nbu2ss_ep *ep = &udc->ep[0];
1828
e59ac747 1829 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1830 if (!req) {
33aa8d45
MD		 1831 req = &udc->ep0_req;
1832 if (req->req.complete)
1833 req->req.complete(&ep->ep, &req->req);
1834
1835 } else {
1836 if (req->req.complete)
1837 _nbu2ss_ep_done(ep, req, 0);
1838 }
1839
1840 udc->ep0state = EP0_IDLE;
1841
1842 return 0;
1843}
1844
1845/*-------------------------------------------------------------------------*/
1846static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1847{
1848 int i;
1849 u32 status;
1850 u32 intr;
1851 int nret = -1;
1852
1853 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1854 intr = status & EP0_STATUS_RW_BIT;
1855 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~(u32)intr);
1856
1857 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1858 | STG_END_INT | EP0_OUT_NULL_INT);
1859
1860 if (status == 0) {
93275c80
HM		 1861 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1862 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
33aa8d45
MD		 1863 return;
1864 }
1865
1866 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1867 udc->gadget.speed = _nbu2ss_get_speed(udc);
1868
1869 for (i = 0; i < EP0_END_XFER; i++) {
1870 switch (udc->ep0state) {
1871 case EP0_IDLE:
1872 if (status & SETUP_INT) {
1873 status = 0;
1874 nret = _nbu2ss_decode_request(udc);
1875 }
1876 break;
1877
1878 case EP0_IN_DATA_PHASE:
1879 if (status & EP0_IN_INT) {
1880 status &= ~EP0_IN_INT;
1881 nret = _nbu2ss_ep0_in_data_stage(udc);
1882 }
1883 break;
1884
1885 case EP0_OUT_DATA_PHASE:
1886 if (status & EP0_OUT_INT) {
1887 status &= ~EP0_OUT_INT;
1888 nret = _nbu2ss_ep0_out_data_stage(udc);
1889 }
1890 break;
1891
1892 case EP0_IN_STATUS_PHASE:
1893 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1894 status &= ~(STG_END_INT | EP0_IN_INT);
1895 nret = _nbu2ss_ep0_status_stage(udc);
1896 }
1897 break;
1898
1899 case EP0_OUT_STATUS_PAHSE:
1900 if ((status & STG_END_INT)
1901 || (status & SETUP_INT)
1902 || (status & EP0_OUT_NULL_INT)) {
1903 status &= ~(STG_END_INT
1904 | EP0_OUT_INT
1905 | EP0_OUT_NULL_INT);
1906
1907 nret = _nbu2ss_ep0_status_stage(udc);
1908 }
1909
1910 break;
1911
1912 default:
1913 status = 0;
1914 break;
1915 }
1916
1917 if (status == 0)
1918 break;
1919 }
1920
1921 if (nret < 0) {
1922 /* Send Stall */
1923 _nbu2ss_set_endpoint_stall(udc, 0, TRUE);
1924 }
1925}
1926
1927/*-------------------------------------------------------------------------*/
1928static void _nbu2ss_ep_done(
1929 struct nbu2ss_ep *ep,
1930 struct nbu2ss_req *req,
1931 int status)
1932{
1933 struct nbu2ss_udc *udc = ep->udc;
1934
1935 list_del_init(&req->queue);
1936
1937 if (status == -ECONNRESET)
1938 _nbu2ss_fifo_flush(udc, ep);
1939
1940 if (likely(req->req.status == -EINPROGRESS))
1941 req->req.status = status;
1942
1943 if (ep->stalled)
1944 _nbu2ss_epn_set_stall(udc, ep);
1945 else {
1946 if (!list_empty(&ep->queue))
1947 _nbu2ss_restert_transfer(ep);
1948 }
1949
1950#ifdef USE_DMA
1951 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1952 (req->req.dma != 0))
1953 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1954#endif
1955
1956 spin_unlock(&udc->lock);
1957 req->req.complete(&ep->ep, &req->req);
1958 spin_lock(&udc->lock);
1959}
1960
1961/*-------------------------------------------------------------------------*/
1962static inline void _nbu2ss_epn_in_int(
1963 struct nbu2ss_udc *udc,
1964 struct nbu2ss_ep *ep,
1965 struct nbu2ss_req *req)
1966{
1967 int result = 0;
1968 u32 status;
1969
f6ef6c09 1970 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1971
1972 if (req->dma_flag)
1973 return; /* DMA is forwarded */
1974
1975 req->req.actual += req->div_len;
1976 req->div_len = 0;
1977
1978 if (req->req.actual != req->req.length) {
1979 /*---------------------------------------------------------*/
1980 /* remainder of data */
1981 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1982
1983 } else {
5cbca957 1984 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
33aa8d45
MD		 1985
1986 status =
1987 _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_STATUS);
1988
1989 if ((status & EPn_IN_FULL) == 0) {
1990 /*-----------------------------------------*/
1991 /* 0 Length Packet */
666e9084 1992 req->zero = false;
33aa8d45
MD		 1993 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1994 }
1995 return;
1996 }
1997 }
1998
1999 if (result <= 0) {
2000 /*---------------------------------------------------------*/
2001 /* Complete */
2002 _nbu2ss_ep_done(ep, req, result);
2003 }
2004}
2005
2006/*-------------------------------------------------------------------------*/
2007static inline void _nbu2ss_epn_out_int(
2008 struct nbu2ss_udc *udc,
2009 struct nbu2ss_ep *ep,
2010 struct nbu2ss_req *req)
2011{
2012 int result;
2013
2014 result = _nbu2ss_epn_out_transfer(udc, ep, req);
2015 if (result <= 0)
2016 _nbu2ss_ep_done(ep, req, result);
33aa8d45
MD		 2017}
2018
2019/*-------------------------------------------------------------------------*/
2020static inline void _nbu2ss_epn_in_dma_int(
2021 struct nbu2ss_udc *udc,
2022 struct nbu2ss_ep *ep,
2023 struct nbu2ss_req *req)
2024{
2025 u32 mpkt;
2026 u32 size;
2027 struct usb_request *preq;
2028
2029 preq = &req->req;
2030
5a602ac4 2031 if (!req->dma_flag)
33aa8d45
MD		 2032 return;
2033
2034 preq->actual += req->div_len;
2035 req->div_len = 0;
2036 req->dma_flag = FALSE;
2037
2038#ifdef USE_DMA
2039 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
2040#endif
2041
2042 if (preq->actual != preq->length) {
2043 _nbu2ss_epn_in_transfer(udc, ep, req);
2044 } else {
2045 mpkt = ep->ep.maxpacket;
2046 size = preq->actual % mpkt;
2047 if (size > 0) {
2048 if (((preq->actual & 0x03) == 0) && (size < mpkt))
2049 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
2050 } else {
2051 _nbu2ss_epn_in_int(udc, ep, req);
2052 }
2053 }
33aa8d45
MD		 2054}
2055
2056/*-------------------------------------------------------------------------*/
2057static inline void _nbu2ss_epn_out_dma_int(
2058 struct nbu2ss_udc *udc,
2059 struct nbu2ss_ep *ep,
2060 struct nbu2ss_req *req)
2061{
2062 int i;
2063 u32 num;
2064 u32 dmacnt, ep_dmacnt;
2065 u32 mpkt;
f6ef6c09 2066 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 2067
2068 num = ep->epnum - 1;
2069
2070 if (req->req.actual == req->req.length) {
5cbca957 2071 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
33aa8d45
MD		 2072 req->div_len = 0;
2073 req->dma_flag = FALSE;
2074 _nbu2ss_ep_done(ep, req, 0);
2075 return;
2076 }
2077 }
2078
2079 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
2080 & EPn_DMACNT;
2081 ep_dmacnt >>= 16;
2082
2083 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2084 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
2085 & DCR1_EPn_DMACNT;
2086 dmacnt >>= 16;
2087 if (ep_dmacnt == dmacnt)
2088 break;
2089 }
2090
2091 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_REQEN);
2092
2093 if (dmacnt != 0) {
2094 mpkt = ep->ep.maxpacket;
2095 if ((req->div_len % mpkt) == 0)
2096 req->div_len -= mpkt * dmacnt;
2097 }
2098
2099 if ((req->req.actual % ep->ep.maxpacket) > 0) {
2100 if (req->req.actual == req->div_len) {
2101 req->div_len = 0;
2102 req->dma_flag = FALSE;
2103 _nbu2ss_ep_done(ep, req, 0);
2104 return;
2105 }
2106 }
2107
2108 req->req.actual += req->div_len;
2109 req->div_len = 0;
2110 req->dma_flag = FALSE;
2111
2112 _nbu2ss_epn_out_int(udc, ep, req);
2113}
2114
2115/*-------------------------------------------------------------------------*/
2116static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2117{
2118 u32 num;
2119 u32 status;
2120
2121 struct nbu2ss_req *req;
2122 struct nbu2ss_ep *ep = &udc->ep[epnum];
2123
2124 num = epnum - 1;
2125
2126 /* Interrupt Status */
2127 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2128
2129 /* Interrupt Clear */
2130 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~(u32)status);
2131
e59ac747 2132 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 2133 if (!req) {
f02935c5 2134 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */
33aa8d45
MD		 2135 return;
2136 }
2137
2138 if (status & EPn_OUT_END_INT) {
2139 status &= ~EPn_OUT_INT;
2140 _nbu2ss_epn_out_dma_int(udc, ep, req);
2141 }
2142
2143 if (status & EPn_OUT_INT)
2144 _nbu2ss_epn_out_int(udc, ep, req);
2145
2146 if (status & EPn_IN_END_INT) {
2147 status &= ~EPn_IN_INT;
2148 _nbu2ss_epn_in_dma_int(udc, ep, req);
2149 }
2150
2151 if (status & EPn_IN_INT)
2152 _nbu2ss_epn_in_int(udc, ep, req);
2153}
2154
2155/*-------------------------------------------------------------------------*/
2156static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2157{
2158 if (epnum == 0)
2159 _nbu2ss_ep0_int(udc);
2160 else
2161 _nbu2ss_epn_int(udc, epnum);
2162}
2163
2164/*-------------------------------------------------------------------------*/
2165static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2166{
2167 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2168 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
33aa8d45
MD		 2169}
2170
33aa8d45
MD		 2171/*-------------------------------------------------------------------------*/
2172static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2173 struct nbu2ss_ep *ep,
2174 int status)
2175{
2176 struct nbu2ss_req *req;
2177
2178 /* Endpoint Disable */
2179 _nbu2ss_epn_exit(udc, ep);
2180
2181 /* DMA Disable */
2182 _nbu2ss_ep_dma_exit(udc, ep);
2183
2184 if (list_empty(&ep->queue))
2185 return 0;
2186
2187 /* called with irqs blocked */
ca3d253e 2188 list_for_each_entry(req, &ep->queue, queue) {
33aa8d45
MD		 2189 _nbu2ss_ep_done(ep, req, status);
2190 }
2191
2192 return 0;
2193}
2194
2195/*-------------------------------------------------------------------------*/
2196static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2197{
2198 struct nbu2ss_ep *ep;
2199
2200 udc->gadget.speed = USB_SPEED_UNKNOWN;
2201
2202 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2203
2204 /* Endpoint n */
2205 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2206 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2207 }
2208}
2209
2210/*-------------------------------------------------------------------------*/
2211static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2212{
2213 u32 reg_dt;
2214
33aa8d45
MD		 2215 if (udc->vbus_active == 0)
2216 return -ESHUTDOWN;
2217
2218 if (is_on) {
2219 /* D+ Pullup */
33aa8d45
MD		 2220 if (udc->driver) {
2221 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2222 | PUE2) & ~(u32)CONNECTB;
2223
2224 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2225 }
2226
2227 } else {
2228 /* D+ Pulldown */
33aa8d45
MD		 2229 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2230 & ~(u32)PUE2;
2231
2232 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2233 udc->gadget.speed = USB_SPEED_UNKNOWN;
2234 }
2235
2236 return 0;
2237}
2238
2239/*-------------------------------------------------------------------------*/
2240static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2241{
f6ef6c09 2242 struct fc_regs *p = udc->p_regs;
33aa8d45
MD		 2243
2244 if (udc->vbus_active == 0)
2245 return;
2246
2247 if (ep->epnum == 0) {
2248 /* EP0 */
2249 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2250
2251 } else {
2252 /* EPn */
2253 _nbu2ss_ep_dma_abort(udc, ep);
2254 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPn_BCLR);
2255 }
2256}
2257
2258/*-------------------------------------------------------------------------*/
2259static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2260{
2261 int waitcnt = 0;
2262
2263 if (udc->udc_enabled)
2264 return 0;
2265
33aa8d45
MD		 2266 /*
2267 Reset
2268 */
2269 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2270 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */
2271
2272 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2273 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */
2274
2275 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2276
2277 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2278
33aa8d45
MD		 2279 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
2280 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2281
2282 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2283 waitcnt++;
2284 udelay(1); /* 1us wait */
2285 if (waitcnt == EPC_PLL_LOCK_COUNT) {
88689279 2286 dev_err(udc->dev, "*** Reset Cancel failed\n");
33aa8d45
MD		 2287 return -EINVAL;
2288 }
3e2bb64d 2289 }
33aa8d45 2290
33aa8d45
MD		 2291 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2292
2293 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2294
2295 /* EP0 */
2296 _nbu2ss_ep0_enable(udc);
2297
2298 /* USB Interrupt Enable */
2299 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2300
2301 udc->udc_enabled = TRUE;
2302
2303 return 0;
2304}
2305
33aa8d45
MD		 2306/*-------------------------------------------------------------------------*/
2307static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2308{
2309 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2310 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2311}
2312
2313/*-------------------------------------------------------------------------*/
2314static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2315{
2316 if (udc->udc_enabled) {
2317 udc->udc_enabled = FALSE;
2318 _nbu2ss_reset_controller(udc);
2319 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2320 }
33aa8d45
MD		 2321}
2322
2323/*-------------------------------------------------------------------------*/
2324static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2325{
2326 int nret;
2327 u32 reg_dt;
2328
2329 /* chattering */
2330 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */
2331
2332 /* VBUS ON Check*/
2333 reg_dt = gpio_get_value(VBUS_VALUE);
2334 if (reg_dt == 0) {
2335
2336 udc->linux_suspended = 0;
2337
2338 _nbu2ss_reset_controller(udc);
93275c80 2339 dev_info(udc->dev, " ----- VBUS OFF\n");
33aa8d45
MD		 2340
2341 if (udc->vbus_active == 1) {
2342 /* VBUS OFF */
2343 udc->vbus_active = 0;
2344 if (udc->usb_suspended) {
2345 udc->usb_suspended = 0;
2346 /* _nbu2ss_reset_controller(udc); */
2347 }
2348 udc->devstate = USB_STATE_NOTATTACHED;
2349
2350 _nbu2ss_quiesce(udc);
2351 if (udc->driver) {
2352 spin_unlock(&udc->lock);
2353 udc->driver->disconnect(&udc->gadget);
2354 spin_lock(&udc->lock);
2355 }
2356
2357 _nbu2ss_disable_controller(udc);
2358 }
2359 } else {
2360 mdelay(5); /* wait (5ms) */
2361 reg_dt = gpio_get_value(VBUS_VALUE);
2362 if (reg_dt == 0)
2363 return;
2364
93275c80 2365 dev_info(udc->dev, " ----- VBUS ON\n");
33aa8d45
MD		 2366
2367 if (udc->linux_suspended)
2368 return;
2369
2370 if (udc->vbus_active == 0) {
2371 /* VBUS ON */
2372 udc->vbus_active = 1;
2373 udc->devstate = USB_STATE_POWERED;
2374
2375 nret = _nbu2ss_enable_controller(udc);
2376 if (nret < 0) {
2377 _nbu2ss_disable_controller(udc);
2378 udc->vbus_active = 0;
2379 return;
2380 }
2381
2382 _nbu2ss_pullup(udc, 1);
2383
2384#ifdef UDC_DEBUG_DUMP
2385 _nbu2ss_dump_register(udc);
2386#endif /* UDC_DEBUG_DUMP */
2387
2388 } else {
2389 if (udc->devstate == USB_STATE_POWERED)
2390 _nbu2ss_pullup(udc, 1);
2391 }
2392 }
33aa8d45
MD		 2393}
2394
2395/*-------------------------------------------------------------------------*/
2396static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2397{
2398 udc->devstate = USB_STATE_DEFAULT;
2399 udc->remote_wakeup = 0;
2400
2401 _nbu2ss_quiesce(udc);
2402
2403 udc->ep0state = EP0_IDLE;
2404}
2405
2406/*-------------------------------------------------------------------------*/
2407static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2408{
2409 if (udc->usb_suspended == 1) {
2410 udc->usb_suspended = 0;
2411 if (udc->driver && udc->driver->resume) {
2412 spin_unlock(&udc->lock);
2413 udc->driver->resume(&udc->gadget);
2414 spin_lock(&udc->lock);
2415 }
2416 }
2417}
2418
2419/*-------------------------------------------------------------------------*/
2420static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2421{
2422 u32 reg_dt;
2423
2424 if (udc->usb_suspended == 0) {
2425 reg_dt = gpio_get_value(VBUS_VALUE);
2426
2427 if (reg_dt == 0)
2428 return;
2429
2430 udc->usb_suspended = 1;
2431 if (udc->driver && udc->driver->suspend) {
2432 spin_unlock(&udc->lock);
2433 udc->driver->suspend(&udc->gadget);
2434 spin_lock(&udc->lock);
2435 }
2436
2437 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2438 }
2439}
2440
2441/*-------------------------------------------------------------------------*/
2442/* VBUS (GPIO153) Interrupt */
2443static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2444{
2445 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2446
2447 spin_lock(&udc->lock);
2448 _nbu2ss_check_vbus(udc);
2449 spin_unlock(&udc->lock);
2450
2451 return IRQ_HANDLED;
2452}
2453
2454/*-------------------------------------------------------------------------*/
2455/* Interrupt (udc) */
2456static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2457{
2458 u8 suspend_flag = 0;
2459 u32 status;
2460 u32 epnum, int_bit;
2461
2462 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
f6ef6c09 2463 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 2464
2465 if (gpio_get_value(VBUS_VALUE) == 0) {
2466 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2467 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2468 return IRQ_HANDLED;
2469 }
2470
2471 spin_lock(&udc->lock);
2472
2473 for (;;) {
2474 if (gpio_get_value(VBUS_VALUE) == 0) {
2475 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2476 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2477 status = 0;
2478 } else
2479 status = _nbu2ss_readl(&preg->USB_INT_STA);
2480
2481 if (status == 0)
2482 break;
2483
2484 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2485
2486 if (status & USB_RST_INT) {
2487 /* USB Reset */
2488 _nbu2ss_int_bus_reset(udc);
2489 }
2490
2491 if (status & RSUM_INT) {
2492 /* Resume */
2493 _nbu2ss_int_usb_resume(udc);
2494 }
2495
2496 if (status & SPND_INT) {
2497 /* Suspend */
2498 suspend_flag = 1;
2499 }
2500
2501 if (status & EPn_INT) {
2502 /* EP INT */
2503 int_bit = status >> 8;
2504
2505 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2506
2507 if (0x01 & int_bit)
2508 _nbu2ss_ep_int(udc, epnum);
2509
2510 int_bit >>= 1;
2511
2512 if (int_bit == 0)
2513 break;
2514 }
2515 }
2516 }
2517
2518 if (suspend_flag)
2519 _nbu2ss_int_usb_suspend(udc);
2520
2521 spin_unlock(&udc->lock);
2522
2523 return IRQ_HANDLED;
2524}
2525
2526/*-------------------------------------------------------------------------*/
2527/* usb_ep_ops */
2528static int nbu2ss_ep_enable(
2529 struct usb_ep *_ep,
2530 const struct usb_endpoint_descriptor *desc)
2531{
2532 u8 ep_type;
2533 unsigned long flags;
2534
2535 struct nbu2ss_ep *ep;
2536 struct nbu2ss_udc *udc;
2537
706eb8cf 2538 if ((!_ep) || (!desc)) {
88689279 2539 pr_err(" *** %s, bad param\n", __func__);
33aa8d45
MD		 2540 return -EINVAL;
2541 }
2542
2543 ep = container_of(_ep, struct nbu2ss_ep, ep);
706eb8cf 2544 if ((!ep) || (!ep->udc)) {
88689279 2545 pr_err(" *** %s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2546 return -EINVAL;
2547 }
2548
3f3efca9 2549 ep_type = usb_endpoint_type(desc);
33aa8d45
MD		 2550 if ((ep_type == USB_ENDPOINT_XFER_CONTROL)
2551 || (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2552
88689279 2553 pr_err(" *** %s, bat bmAttributes\n", __func__);
33aa8d45
MD		 2554 return -EINVAL;
2555 }
2556
2557 udc = ep->udc;
2558 if (udc->vbus_active == 0)
2559 return -ESHUTDOWN;
2560
706eb8cf 2561 if ((!udc->driver)
33aa8d45
MD		 2562 || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2563
88689279 2564 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
33aa8d45
MD		 2565 return -ESHUTDOWN;
2566 }
2567
2568 spin_lock_irqsave(&udc->lock, flags);
2569
2570 ep->desc = desc;
3f3efca9 2571 ep->epnum = usb_endpoint_num(desc);
33aa8d45
MD		 2572 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2573 ep->ep_type = ep_type;
2574 ep->wedged = 0;
2575 ep->halted = FALSE;
2576 ep->stalled = FALSE;
2577
2578 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2579
2580 /* DMA setting */
2581 _nbu2ss_ep_dma_init(udc, ep);
2582
2583 /* Endpoint setting */
2584 _nbu2ss_ep_init(udc, ep);
2585
2586 spin_unlock_irqrestore(&udc->lock, flags);
2587
2588 return 0;
2589}
2590
2591/*-------------------------------------------------------------------------*/
2592static int nbu2ss_ep_disable(struct usb_ep *_ep)
2593{
2594 struct nbu2ss_ep *ep;
2595 struct nbu2ss_udc *udc;
2596 unsigned long flags;
2597
706eb8cf 2598 if (!_ep) {
88689279 2599 pr_err(" *** %s, bad param\n", __func__);
33aa8d45
MD		 2600 return -EINVAL;
2601 }
2602
2603 ep = container_of(_ep, struct nbu2ss_ep, ep);
706eb8cf 2604 if ((!ep) || (!ep->udc)) {
88689279 2605 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2606 return -EINVAL;
2607 }
2608
2609 udc = ep->udc;
2610 if (udc->vbus_active == 0)
2611 return -ESHUTDOWN;
2612
2613 spin_lock_irqsave(&udc->lock, flags);
2614 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */
2615 spin_unlock_irqrestore(&udc->lock, flags);
2616
2617 return 0;
2618}
2619
2620/*-------------------------------------------------------------------------*/
2621static struct usb_request *nbu2ss_ep_alloc_request(
2622 struct usb_ep *ep,
2623 gfp_t gfp_flags)
2624{
2625 struct nbu2ss_req *req;
2626
2627 req = kzalloc(sizeof(*req), gfp_flags);
2628 if (!req)
2629 return 0;
2630
2631#ifdef USE_DMA
2632 req->req.dma = DMA_ADDR_INVALID;
2633#endif
2634 INIT_LIST_HEAD(&req->queue);
2635
2636 return &req->req;
2637}
2638
2639/*-------------------------------------------------------------------------*/
2640static void nbu2ss_ep_free_request(
2641 struct usb_ep *_ep,
2642 struct usb_request *_req)
2643{
2644 struct nbu2ss_req *req;
2645
706eb8cf 2646 if (_req) {
33aa8d45
MD		 2647 req = container_of(_req, struct nbu2ss_req, req);
2648
a5a89d7a 2649 kfree(req);
33aa8d45
MD		 2650 }
2651}
2652
2653/*-------------------------------------------------------------------------*/
2654static int nbu2ss_ep_queue(
2655 struct usb_ep *_ep,
2656 struct usb_request *_req,
2657 gfp_t gfp_flags)
2658{
2659 struct nbu2ss_req *req;
2660 struct nbu2ss_ep *ep;
2661 struct nbu2ss_udc *udc;
2662 unsigned long flags;
2663 bool bflag;
2664 int result = -EINVAL;
2665
2666 /* catch various bogus parameters */
706eb8cf
RTD		 2667 if ((!_ep) || (!_req)) {
2668 if (!_ep)
88689279 2669 pr_err("udc: %s --- _ep == NULL\n", __func__);
33aa8d45 2670
706eb8cf 2671 if (!_req)
88689279 2672 pr_err("udc: %s --- _req == NULL\n", __func__);
33aa8d45
MD		 2673
2674 return -EINVAL;
2675 }
2676
2677 req = container_of(_req, struct nbu2ss_req, req);
2678 if (unlikely
2679 (!_req->complete || !_req->buf
2680 || !list_empty(&req->queue))) {
2681
2682 if (!_req->complete)
88689279 2683 pr_err("udc: %s --- !_req->complete\n", __func__);
33aa8d45
MD		 2684
2685 if (!_req->buf)
88689279 2686 pr_err("udc:%s --- !_req->buf\n", __func__);
33aa8d45
MD		 2687
2688 if (!list_empty(&req->queue))
88689279 2689 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
33aa8d45
MD		 2690
2691 return -EINVAL;
2692 }
2693
2694 ep = container_of(_ep, struct nbu2ss_ep, ep);
2695 udc = ep->udc;
2696
33aa8d45 2697 if (udc->vbus_active == 0) {
93275c80 2698 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
33aa8d45
MD		 2699 return -ESHUTDOWN;
2700 }
2701
2702 if (unlikely(!udc->driver)) {
88689279
HM		 2703 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2704 udc->driver);
33aa8d45
MD		 2705 return -ESHUTDOWN;
2706 }
2707
2708 spin_lock_irqsave(&udc->lock, flags);
2709
2710#ifdef USE_DMA
e7cfb390 2711 if ((uintptr_t)req->req.buf & 0x3)
33aa8d45
MD		 2712 req->unaligned = TRUE;
2713 else
2714 req->unaligned = FALSE;
2715
2716 if (req->unaligned) {
706eb8cf 2717 if (!ep->virt_buf)
33aa8d45
MD		 2718 ep->virt_buf = (u8 *)dma_alloc_coherent(
2719 NULL, PAGE_SIZE,
4a0721bf 2720 &ep->phys_buf, GFP_ATOMIC | GFP_DMA);
33aa8d45
MD		 2721 if (ep->epnum > 0) {
2722 if (ep->direct == USB_DIR_IN)
2723 memcpy(ep->virt_buf, req->req.buf,
2724 req->req.length);
2725 }
2726 }
2727
2728 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2729 (req->req.dma != 0))
2730 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2731#endif
2732
2733 _req->status = -EINPROGRESS;
2734 _req->actual = 0;
2735
2736 bflag = list_empty(&ep->queue);
2737 list_add_tail(&req->queue, &ep->queue);
2738
5a602ac4 2739 if (bflag && !ep->stalled) {
33aa8d45
MD		 2740
2741 result = _nbu2ss_start_transfer(udc, ep, req, FALSE);
2742 if (result < 0) {
88689279
HM		 2743 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2744 result);
33aa8d45
MD		 2745 list_del(&req->queue);
2746 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2747#ifdef USE_DMA
2748 if (req->req.length < 4 &&
2749 req->req.length == req->req.actual)
2750#else
2751 if (req->req.length == req->req.actual)
2752#endif
2753 _nbu2ss_ep_done(ep, req, result);
2754 }
2755 }
2756
2757 spin_unlock_irqrestore(&udc->lock, flags);
2758
2759 return 0;
2760}
2761
2762/*-------------------------------------------------------------------------*/
2763static int nbu2ss_ep_dequeue(
2764 struct usb_ep *_ep,
2765 struct usb_request *_req)
2766{
2767 struct nbu2ss_req *req;
2768 struct nbu2ss_ep *ep;
2769 struct nbu2ss_udc *udc;
2770 unsigned long flags;
2771
33aa8d45 2772 /* catch various bogus parameters */
706eb8cf 2773 if ((!_ep) || (!_req)) {
88689279 2774 /* pr_err("%s, bad param(1)\n", __func__); */
33aa8d45
MD		 2775 return -EINVAL;
2776 }
2777
2778 ep = container_of(_ep, struct nbu2ss_ep, ep);
2779 if (!ep) {
88689279 2780 pr_err("%s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2781 return -EINVAL;
2782 }
2783
2784 udc = ep->udc;
706eb8cf 2785 if (!udc)
33aa8d45
MD		 2786 return -EINVAL;
2787
2788 spin_lock_irqsave(&udc->lock, flags);
2789
2790 /* make sure it's actually queued on this endpoint */
2791 list_for_each_entry(req, &ep->queue, queue) {
2792 if (&req->req == _req)
2793 break;
2794 }
2795 if (&req->req != _req) {
2796 spin_unlock_irqrestore(&udc->lock, flags);
2797 pr_debug("%s no queue(EINVAL)\n", __func__);
2798 return -EINVAL;
2799 }
2800
2801 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2802
2803 spin_unlock_irqrestore(&udc->lock, flags);
2804
2805 return 0;
2806}
2807
2808/*-------------------------------------------------------------------------*/
2809static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2810{
2811 u8 ep_adrs;
2812 unsigned long flags;
2813
2814 struct nbu2ss_ep *ep;
2815 struct nbu2ss_udc *udc;
2816
33aa8d45 2817 if (!_ep) {
88689279 2818 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2819 return -EINVAL;
2820 }
2821
2822 ep = container_of(_ep, struct nbu2ss_ep, ep);
2823 if (!ep) {
88689279 2824 pr_err("%s, bad ep\n", __func__);
33aa8d45
MD		 2825 return -EINVAL;
2826 }
2827
2828 udc = ep->udc;
2829 if (!udc) {
88689279 2830 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
33aa8d45
MD		 2831 return -EINVAL;
2832 }
2833
2834 spin_lock_irqsave(&udc->lock, flags);
2835
2836 ep_adrs = ep->epnum | ep->direct;
2837 if (value == 0) {
2838 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2839 ep->stalled = FALSE;
2840 } else {
2841 if (list_empty(&ep->queue))
2842 _nbu2ss_epn_set_stall(udc, ep);
2843 else
2844 ep->stalled = TRUE;
2845 }
2846
2847 if (value == 0)
2848 ep->wedged = 0;
2849
2850 spin_unlock_irqrestore(&udc->lock, flags);
2851
2852 return 0;
2853}
2854
2855static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2856{
2857 return nbu2ss_ep_set_halt(_ep, 1);
2858}
2859
2860/*-------------------------------------------------------------------------*/
2861static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2862{
2863 u32 data;
2864 struct nbu2ss_ep *ep;
2865 struct nbu2ss_udc *udc;
2866 unsigned long flags;
f6ef6c09 2867 struct fc_regs *preg;
33aa8d45 2868
33aa8d45 2869 if (!_ep) {
88689279 2870 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2871 return -EINVAL;
2872 }
2873
2874 ep = container_of(_ep, struct nbu2ss_ep, ep);
2875 if (!ep) {
88689279 2876 pr_err("%s, bad ep\n", __func__);
33aa8d45
MD		 2877 return -EINVAL;
2878 }
2879
2880 udc = ep->udc;
2881 if (!udc) {
88689279 2882 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
33aa8d45
MD		 2883 return -EINVAL;
2884 }
2885
2886 preg = udc->p_regs;
2887
2888 data = gpio_get_value(VBUS_VALUE);
2889 if (data == 0)
2890 return -EINVAL;
2891
2892 spin_lock_irqsave(&udc->lock, flags);
2893
2894 if (ep->epnum == 0) {
2895 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2896
2897 } else {
2898 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_LEN_DCNT)
2899 & EPn_LDATA;
2900 }
2901
2902 spin_unlock_irqrestore(&udc->lock, flags);
2903
2904 return 0;
2905}
2906
2907/*-------------------------------------------------------------------------*/
2908static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2909{
2910 u32 data;
2911 struct nbu2ss_ep *ep;
2912 struct nbu2ss_udc *udc;
2913 unsigned long flags;
2914
33aa8d45 2915 if (!_ep) {
88689279 2916 pr_err("udc: %s, bad param\n", __func__);
33aa8d45
MD		 2917 return;
2918 }
2919
2920 ep = container_of(_ep, struct nbu2ss_ep, ep);
bd7de5ce 2921 if (!ep) {
88689279 2922 pr_err("udc: %s, bad ep\n", __func__);
33aa8d45
MD		 2923 return;
2924 }
2925
2926 udc = ep->udc;
2927 if (!udc) {
88689279 2928 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
33aa8d45
MD		 2929 return;
2930 }
2931
2932 data = gpio_get_value(VBUS_VALUE);
2933 if (data == 0)
2934 return;
2935
2936 spin_lock_irqsave(&udc->lock, flags);
2937 _nbu2ss_fifo_flush(udc, ep);
2938 spin_unlock_irqrestore(&udc->lock, flags);
2939}
2940
2941/*-------------------------------------------------------------------------*/
2942static struct usb_ep_ops nbu2ss_ep_ops = {
2943 .enable = nbu2ss_ep_enable,
2944 .disable = nbu2ss_ep_disable,
2945
2946 .alloc_request = nbu2ss_ep_alloc_request,
2947 .free_request = nbu2ss_ep_free_request,
2948
2949 .queue = nbu2ss_ep_queue,
2950 .dequeue = nbu2ss_ep_dequeue,
2951
2952 .set_halt = nbu2ss_ep_set_halt,
2953 .set_wedge = nbu2ss_ep_set_wedge,
2954
2955 .fifo_status = nbu2ss_ep_fifo_status,
2956 .fifo_flush = nbu2ss_ep_fifo_flush,
2957};
2958
33aa8d45
MD		 2959/*-------------------------------------------------------------------------*/
2960/* usb_gadget_ops */
2961
2962/*-------------------------------------------------------------------------*/
2963static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2964{
2965 u32 data;
2966 struct nbu2ss_udc *udc;
2967
706eb8cf 2968 if (!pgadget) {
88689279 2969 pr_err("udc: %s, bad param\n", __func__);
33aa8d45
MD		 2970 return -EINVAL;
2971 }
2972
2973 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
706eb8cf 2974 if (!udc) {
88689279 2975 dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
33aa8d45
MD		 2976 return -EINVAL;
2977 }
2978
2979 data = gpio_get_value(VBUS_VALUE);
2980 if (data == 0)
2981 return -EINVAL;
2982
2983 data = _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2984
2985 return data;
2986}
2987
2988/*-------------------------------------------------------------------------*/
2989static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2990{
2991 int i;
2992 u32 data;
2993
2994 struct nbu2ss_udc *udc;
2995
706eb8cf 2996 if (!pgadget) {
88689279 2997 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2998 return -EINVAL;
2999 }
3000
3001 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
706eb8cf 3002 if (!udc) {
88689279 3003 dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
33aa8d45
MD		 3004 return -EINVAL;
3005 }
3006
3007 data = gpio_get_value(VBUS_VALUE);
3008 if (data == 0) {
93275c80 3009 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
33aa8d45
MD		 3010 return -EINVAL;
3011 }
3012
3013 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
3014
3015 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
3016 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
3017
3018 if (data & PLL_LOCK)
3019 break;
3020 }
3021
3022 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
3023
3024 return 0;
3025}
3026
3027/*-------------------------------------------------------------------------*/
3028static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
3029 int is_selfpowered)
3030{
1fa2df0c 3031 struct nbu2ss_udc *udc;
33aa8d45
MD		 3032 unsigned long flags;
3033
706eb8cf 3034 if (!pgadget) {
88689279 3035 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3036 return -EINVAL;
3037 }
3038
1fa2df0c
PC		 3039 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3040
33aa8d45 3041 spin_lock_irqsave(&udc->lock, flags);
9239d88f 3042 pgadget->is_selfpowered = (is_selfpowered != 0);
33aa8d45
MD		 3043 spin_unlock_irqrestore(&udc->lock, flags);
3044
3045 return 0;
3046}
3047
3048/*-------------------------------------------------------------------------*/
3049static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
3050{
33aa8d45
MD		 3051 return 0;
3052}
3053
3054/*-------------------------------------------------------------------------*/
3055static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned mA)
3056{
3057 struct nbu2ss_udc *udc;
3058 unsigned long flags;
3059
706eb8cf 3060 if (!pgadget) {
88689279 3061 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3062 return -EINVAL;
3063 }
3064
3065 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3066
3067 spin_lock_irqsave(&udc->lock, flags);
3068 udc->mA = mA;
3069 spin_unlock_irqrestore(&udc->lock, flags);
3070
3071 return 0;
3072}
3073
3074/*-------------------------------------------------------------------------*/
3075static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
3076{
3077 struct nbu2ss_udc *udc;
3078 unsigned long flags;
3079
706eb8cf 3080 if (!pgadget) {
88689279 3081 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3082 return -EINVAL;
3083 }
3084
3085 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3086
706eb8cf 3087 if (!udc->driver) {
f02935c5 3088 pr_warn("%s, Not Regist Driver\n", __func__);
33aa8d45
MD		 3089 return -EINVAL;
3090 }
3091
3092 if (udc->vbus_active == 0)
3093 return -ESHUTDOWN;
3094
3095 spin_lock_irqsave(&udc->lock, flags);
3096 _nbu2ss_pullup(udc, is_on);
3097 spin_unlock_irqrestore(&udc->lock, flags);
3098
3099 return 0;
3100}
3101
3102/*-------------------------------------------------------------------------*/
3103static int nbu2ss_gad_ioctl(
3104 struct usb_gadget *pgadget,
3105 unsigned code,
3106 unsigned long param)
3107{
33aa8d45
MD		 3108 return 0;
3109}
3110
33aa8d45
MD		 3111static const struct usb_gadget_ops nbu2ss_gadget_ops = {
3112 .get_frame = nbu2ss_gad_get_frame,
3113 .wakeup = nbu2ss_gad_wakeup,
3114 .set_selfpowered = nbu2ss_gad_set_selfpowered,
3115 .vbus_session = nbu2ss_gad_vbus_session,
3116 .vbus_draw = nbu2ss_gad_vbus_draw,
3117 .pullup = nbu2ss_gad_pullup,
3118 .ioctl = nbu2ss_gad_ioctl,
3119};
3120
68b5c947
RB		 3121static const struct {
3122 const char *name;
3123 const struct usb_ep_caps caps;
3124} ep_info[NUM_ENDPOINTS] = {
3125#define EP_INFO(_name, _caps) \
3126 { \
3127 .name = _name, \
3128 .caps = _caps, \
3129 }
3130
3131 EP_INFO("ep0",
3132 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
3133 EP_INFO("ep1-bulk",
3134 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3135 EP_INFO("ep2-bulk",
3136 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3137 EP_INFO("ep3in-int",
3138 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3139 EP_INFO("ep4-iso",
3140 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3141 EP_INFO("ep5-iso",
3142 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3143 EP_INFO("ep6-bulk",
3144 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3145 EP_INFO("ep7-bulk",
3146 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3147 EP_INFO("ep8in-int",
3148 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3149 EP_INFO("ep9-iso",
3150 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3151 EP_INFO("epa-iso",
3152 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3153 EP_INFO("epb-bulk",
3154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3155 EP_INFO("epc-bulk",
3156 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3157 EP_INFO("epdin-int",
3158 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3159
3160#undef EP_INFO
33aa8d45
MD		 3161};
3162
33aa8d45
MD		 3163/*-------------------------------------------------------------------------*/
3164static void __init nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3165{
3166 int i;
3167
3168 INIT_LIST_HEAD(&udc->gadget.ep_list);
3169 udc->gadget.ep0 = &udc->ep[0].ep;
3170
737fee1b
CR		 3171 for (i = 0; i < NUM_ENDPOINTS; i++) {
3172 struct nbu2ss_ep *ep = &udc->ep[i];
33aa8d45 3173
737fee1b
CR		 3174 ep->udc = udc;
3175 ep->desc = NULL;
3176
3177 ep->ep.driver_data = NULL;
68b5c947
RB		 3178 ep->ep.name = ep_info[i].name;
3179 ep->ep.caps = ep_info[i].caps;
737fee1b
CR		 3180 ep->ep.ops = &nbu2ss_ep_ops;
3181
cb009d6e
RB		 3182 usb_ep_set_maxpacket_limit(&ep->ep,
3183 i == 0 ? EP0_PACKETSIZE : EP_PACKETSIZE);
737fee1b
CR		 3184
3185 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3186 INIT_LIST_HEAD(&ep->queue);
3187 }
33aa8d45
MD		 3188
3189 list_del_init(&udc->ep[0].ep.ep_list);
3190}
3191
3192/*-------------------------------------------------------------------------*/
3193/* platform_driver */
3194static int __init nbu2ss_drv_contest_init(
3195 struct platform_device *pdev,
3196 struct nbu2ss_udc *udc)
3197{
3198 spin_lock_init(&udc->lock);
3199 udc->dev = &pdev->dev;
3200
9239d88f 3201 udc->gadget.is_selfpowered = 1;
33aa8d45
MD		 3202 udc->devstate = USB_STATE_NOTATTACHED;
3203 udc->pdev = pdev;
3204 udc->mA = 0;
3205
3206 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3207
3208 /* init Endpoint */
3209 nbu2ss_drv_ep_init(udc);
3210
3211 /* init Gadget */
3212 udc->gadget.ops = &nbu2ss_gadget_ops;
3213 udc->gadget.ep0 = &udc->ep[0].ep;
3214 udc->gadget.speed = USB_SPEED_UNKNOWN;
3215 udc->gadget.name = driver_name;
a2c14e97 3216 /* udc->gadget.is_dualspeed = 1; */
33aa8d45
MD		 3217
3218 device_initialize(&udc->gadget.dev);
3219
3220 dev_set_name(&udc->gadget.dev, "gadget");
3221 udc->gadget.dev.parent = &pdev->dev;
3222 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3223
3224 return 0;
3225}
3226
3227/*
3228 * probe - binds to the platform device
3229 */
3230static int nbu2ss_drv_probe(struct platform_device *pdev)
3231{
3232 int status = -ENODEV;
3233 struct nbu2ss_udc *udc;
96b29cac
MD		 3234 struct resource *r;
3235 int irq;
3236 void __iomem *mmio_base;
33aa8d45
MD		 3237
3238 udc = &udc_controller;
3239 memset(udc, 0, sizeof(struct nbu2ss_udc));
3240
3241 platform_set_drvdata(pdev, udc);
3242
96b29cac
MD		 3243 /* require I/O memory and IRQ to be provided as resources */
3244 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a790ebc1
SK		 3245 mmio_base = devm_ioremap_resource(&pdev->dev, r);
3246 if (IS_ERR(mmio_base))
96b29cac 3247 return PTR_ERR(mmio_base);
33aa8d45 3248
96b29cac
MD		 3249 irq = platform_get_irq(pdev, 0);
3250 if (irq < 0) {
3251 dev_err(&pdev->dev, "failed to get IRQ\n");
3252 return irq;
33aa8d45 3253 }
96b29cac
MD		 3254 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3255 0, driver_name, udc);
33aa8d45
MD		 3256
3257 /* IO Memory */
f6ef6c09 3258 udc->p_regs = (struct fc_regs *)mmio_base;
33aa8d45
MD		 3259
3260 /* USB Function Controller Interrupt */
33aa8d45 3261 if (status != 0) {
88689279 3262 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
c648a57a 3263 return status;
33aa8d45
MD		 3264 }
3265
3266 /* Driver Initialization */
3267 status = nbu2ss_drv_contest_init(pdev, udc);
3268 if (status < 0) {
3269 /* Error */
c648a57a 3270 return status;
33aa8d45
MD		 3271 }
3272
3273 /* VBUS Interrupt */
3274 irq_set_irq_type(INT_VBUS, IRQ_TYPE_EDGE_BOTH);
3275 status = request_irq(INT_VBUS,
3276 _nbu2ss_vbus_irq,
3277 IRQF_SHARED,
3278 driver_name,
3279 udc);
3280
3281 if (status != 0) {
88689279 3282 dev_err(udc->dev, "request_irq(INT_VBUS) failed\n");
c648a57a 3283 return status;
33aa8d45
MD		 3284 }
3285
3286 return status;
33aa8d45
MD		 3287}
3288
3289/*-------------------------------------------------------------------------*/
3290static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3291{
3292 struct nbu2ss_udc *udc;
3293
3294 udc = platform_get_drvdata(pdev);
706eb8cf 3295 if (!udc)
33aa8d45
MD		 3296 return;
3297
3298 _nbu2ss_disable_controller(udc);
3299}
3300
33aa8d45
MD		 3301/*-------------------------------------------------------------------------*/
3302static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3303{
3304 struct nbu2ss_udc *udc;
3305
3306 udc = platform_get_drvdata(pdev);
706eb8cf 3307 if (!udc)
33aa8d45
MD		 3308 return 0;
3309
3310 if (udc->vbus_active) {
3311 udc->vbus_active = 0;
3312 udc->devstate = USB_STATE_NOTATTACHED;
3313 udc->linux_suspended = 1;
3314
3315 if (udc->usb_suspended) {
3316 udc->usb_suspended = 0;
3317 _nbu2ss_reset_controller(udc);
3318 }
3319
3320 _nbu2ss_quiesce(udc);
3321 }
3322 _nbu2ss_disable_controller(udc);
3323
3324 return 0;
3325}
3326
3327/*-------------------------------------------------------------------------*/
3328static int nbu2ss_drv_resume(struct platform_device *pdev)
3329{
3330 u32 data;
3331 struct nbu2ss_udc *udc;
3332
3333 udc = platform_get_drvdata(pdev);
706eb8cf 3334 if (!udc)
33aa8d45
MD		 3335 return 0;
3336
3337 data = gpio_get_value(VBUS_VALUE);
3338 if (data) {
3339 udc->vbus_active = 1;
3340 udc->devstate = USB_STATE_POWERED;
3341 _nbu2ss_enable_controller(udc);
3342 _nbu2ss_pullup(udc, 1);
3343 }
3344
3345 udc->linux_suspended = 0;
3346
3347 return 0;
3348}
3349
33aa8d45
MD		 3350static struct platform_driver udc_driver = {
3351 .probe = nbu2ss_drv_probe,
3352 .shutdown = nbu2ss_drv_shutdown,
33aa8d45
MD		 3353 .suspend = nbu2ss_drv_suspend,
3354 .resume = nbu2ss_drv_resume,
3355 .driver = {
0af61e66
PG		 3356 .name = driver_name,
3357 .suppress_bind_attrs = true,
33aa8d45
MD		 3358 },
3359};
3360
0af61e66 3361builtin_platform_driver(udc_driver);
Linux 6.x block layer and io_uring tree(s)