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staging: comedi: s626: remove the ai (*insn_config) function
[linux-2.6-block.git] / drivers / staging / comedi / drivers / s626.c
CommitLineData
11e865c1
GP		 1/*
2 comedi/drivers/s626.c
3 Sensoray s626 Comedi driver
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25*/
26
27/*
28Driver: s626
29Description: Sensoray 626 driver
30Devices: [Sensoray] 626 (s626)
31Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32Updated: Fri, 15 Feb 2008 10:28:42 +0000
33Status: experimental
34
91e674e8 35Configuration options: not applicable, uses PCI auto config
11e865c1
GP		 36
37INSN_CONFIG instructions:
38 analog input:
39 none
40
41 analog output:
42 none
43
44 digital channel:
45 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
46 supported configuration options:
47 INSN_CONFIG_DIO_QUERY
48 COMEDI_INPUT
49 COMEDI_OUTPUT
50
51 encoder:
52 Every channel must be configured before reading.
53
54 Example code
55
56 insn.insn=INSN_CONFIG; //configuration instruction
57 insn.n=1; //number of operation (must be 1)
58 insn.data=&initialvalue; //initial value loaded into encoder
add74595 59 //during configuration
11e865c1
GP		 60 insn.subdev=5; //encoder subdevice
61 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
add74595 62 //to configure
11e865c1
GP		 63
64 comedi_do_insn(cf,&insn); //executing configuration
65*/
66
33782dd5 67#include <linux/pci.h>
25436dc9 68#include <linux/interrupt.h>
11e865c1
GP		 69#include <linux/kernel.h>
70#include <linux/types.h>
71
72#include "../comedidev.h"
73
11e865c1
GP		 74#include "comedi_fc.h"
75#include "s626.h"
76
e17b8e48
GS		 77#define PCI_VENDOR_ID_S626 0x1131
78#define PCI_DEVICE_ID_S626 0x7146
79#define PCI_SUBVENDOR_ID_S626 0x6000
80#define PCI_SUBDEVICE_ID_S626 0x0272
81
eb5e029e 82struct s626_private {
7d856da2 83 void __iomem *mmio;
b6c77757 84 uint8_t ai_cmd_running; /* ai_cmd is running */
25985edc 85 uint8_t ai_continous; /* continous acquisition */
9d220c6b 86 int ai_sample_count; /* number of samples to acquire */
b6c77757
BP		 87 unsigned int ai_sample_timer;
88 /* time between samples in units of the timer */
89 int ai_convert_count; /* conversion counter */
90 unsigned int ai_convert_timer;
91 /* time between conversion in units of the timer */
92 uint16_t CounterIntEnabs;
93 /* Counter interrupt enable mask for MISC2 register. */
94 uint8_t AdcItems; /* Number of items in ADC poll list. */
0a85b6f0 95 struct bufferDMA RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
4753d235 96 struct bufferDMA ANABuf;
b6c77757
BP		 97 /* DMA buffer used to receive ADC data and hold DAC data. */
98 uint32_t *pDacWBuf;
99 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
100 uint16_t Dacpol; /* Image of DAC polarity register. */
101 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
b6c77757 102 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
b6c77757
BP		 103 uint32_t I2CAdrs;
104 /* I2C device address for onboard EEPROM (board rev dependent). */
105 /* short I2Cards; */
790c5541 106 unsigned int ao_readback[S626_DAC_CHANNELS];
eb5e029e 107};
11e865c1 108
b6c77757 109/* COUNTER OBJECT ------------------------------------------------ */
eb5e029e 110struct enc_private {
b6c77757 111 /* Pointers to functions that differ for A and B counters: */
add74595
JS		 112 uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *); /* Return clock enable. */
113 uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *); /* Return interrupt source. */
114 uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *); /* Return preload trigger source. */
115 uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *); /* Return standardized operating mode. */
116 void (*PulseIndex) (struct comedi_device *dev, struct enc_private *); /* Generate soft index strobe. */
117 void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
118 void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
119 void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
120 void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
121 void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *); /* Reset event capture flags. */
b6c77757
BP		 122
123 uint16_t MyCRA; /* Address of CRA register. */
124 uint16_t MyCRB; /* Address of CRB register. */
125 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
126 /* register. */
127 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
eb5e029e 128};
11e865c1 129
eb5e029e 130#define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
11e865c1 131
b6c77757 132/* Counter overflow/index event flag masks for RDMISC2. */
6a98d36e
BP		 133#define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
134#define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
11e865c1
GP		 135#define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
136
b6c77757
BP		 137/* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
138/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
11e865c1 139
ddd9813e
HS		 140/*
141 * Enable/disable a function or test status bit(s) that are accessed
142 * through Main Control Registers 1 or 2.
143 */
144static void s626_mc_enable(struct comedi_device *dev,
145 unsigned int cmd, unsigned int reg)
146{
147 struct s626_private *devpriv = dev->private;
148 unsigned int val = (cmd << 16) | cmd;
149
7d856da2 150 writel(val, devpriv->mmio + reg);
ddd9813e 151}
11e865c1 152
c5cf4606
HS		 153static void s626_mc_disable(struct comedi_device *dev,
154 unsigned int cmd, unsigned int reg)
155{
156 struct s626_private *devpriv = dev->private;
157
7d856da2 158 writel(cmd << 16 , devpriv->mmio + reg);
c5cf4606 159}
11e865c1 160
95bb7982
HS		 161static bool s626_mc_test(struct comedi_device *dev,
162 unsigned int cmd, unsigned int reg)
163{
164 struct s626_private *devpriv = dev->private;
165 unsigned int val;
166
7d856da2 167 val = readl(devpriv->mmio + reg);
95bb7982
HS		 168
169 return (val & cmd) ? true : false;
170}
11e865c1 171
6a98d36e 172#define BUGFIX_STREG(REGADRS) (REGADRS - 4)
11e865c1 173
b6c77757 174/* Write a time slot control record to TSL2. */
6a98d36e 175#define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
11e865c1 176
b6c77757 177/* Code macros used for constructing I2C command bytes. */
6a98d36e
BP		 178#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
179#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
180#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
11e865c1 181
90d54ff2
HS		 182static const struct comedi_lrange s626_range_table = {
183 2, {
184 BIP_RANGE(5),
185 BIP_RANGE(10),
186 }
11e865c1
GP		 187};
188
6b387b70
HS		 189/* Execute a DEBI transfer. This must be called from within a */
190/* critical section. */
191static void DEBItransfer(struct comedi_device *dev)
192{
7f2f7e05
HS		 193 struct s626_private *devpriv = dev->private;
194
ddd9813e
HS		 195 /* Initiate upload of shadow RAM to DEBI control register */
196 s626_mc_enable(dev, MC2_UPLD_DEBI, P_MC2);
6b387b70 197
95bb7982
HS		 198 /*
199 * Wait for completion of upload from shadow RAM to
200 * DEBI control register.
201 */
202 while (!s626_mc_test(dev, MC2_UPLD_DEBI, P_MC2))
6b387b70
HS		 203 ;
204
be008602 205 /* Wait until DEBI transfer is done */
7d856da2 206 while (readl(devpriv->mmio + P_PSR) & PSR_DEBI_S)
6b387b70
HS		 207 ;
208}
209
210/* Initialize the DEBI interface for all transfers. */
211
212static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
213{
7f2f7e05 214 struct s626_private *devpriv = dev->private;
6b387b70 215
25f8fd5e 216 /* Set up DEBI control register value in shadow RAM */
7d856da2 217 writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD);
6b387b70
HS		 218
219 /* Execute the DEBI transfer. */
220 DEBItransfer(dev);
221
7d856da2 222 return readl(devpriv->mmio + P_DEBIAD);
6b387b70
HS		 223}
224
225/* Write a value to a gate array register. */
226static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
227{
7f2f7e05 228 struct s626_private *devpriv = dev->private;
6b387b70 229
25f8fd5e 230 /* Set up DEBI control register value in shadow RAM */
7d856da2
HS		 231 writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD);
232 writel(wdata, devpriv->mmio + P_DEBIAD);
6b387b70
HS		 233
234 /* Execute the DEBI transfer. */
235 DEBItransfer(dev);
236}
237
238/* Replace the specified bits in a gate array register. Imports: mask
239 * specifies bits that are to be preserved, wdata is new value to be
240 * or'd with the masked original.
241 */
12f4e2f2
HS		 242static void DEBIreplace(struct comedi_device *dev, unsigned int addr,
243 unsigned int mask, unsigned int wdata)
6b387b70 244{
7f2f7e05 245 struct s626_private *devpriv = dev->private;
be008602 246 unsigned int val;
6b387b70 247
12f4e2f2 248 addr &= 0xffff;
7d856da2 249 writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD);
be008602 250 DEBItransfer(dev);
6b387b70 251
7d856da2
HS		 252 writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD);
253 val = readl(devpriv->mmio + P_DEBIAD);
be008602
HS		 254 val &= mask;
255 val |= wdata;
12f4e2f2 256 writel(val & 0xffff, devpriv->mmio + P_DEBIAD);
be008602 257 DEBItransfer(dev);
6b387b70
HS		 258}
259
982e3d11
HS		 260/* ************** EEPROM ACCESS FUNCTIONS ************** */
261
262static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
263{
7f2f7e05 264 struct s626_private *devpriv = dev->private;
be008602 265 unsigned int ctrl;
7f2f7e05 266
25f8fd5e 267 /* Write I2C command to I2C Transfer Control shadow register */
7d856da2 268 writel(val, devpriv->mmio + P_I2CCTRL);
982e3d11 269
ddd9813e
HS		 270 /*
271 * Upload I2C shadow registers into working registers and
272 * wait for upload confirmation.
273 */
274 s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
95bb7982 275 while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
982e3d11
HS		 276 ;
277
be008602
HS		 278 /* Wait until I2C bus transfer is finished or an error occurs */
279 do {
7d856da2 280 ctrl = readl(devpriv->mmio + P_I2CCTRL);
be008602 281 } while ((ctrl & (I2C_BUSY | I2C_ERR)) == I2C_BUSY);
982e3d11 282
be008602
HS		 283 /* Return non-zero if I2C error occurred */
284 return ctrl & I2C_ERR;
982e3d11
HS		 285}
286
287/* Read uint8_t from EEPROM. */
288static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
289{
7f2f7e05 290 struct s626_private *devpriv = dev->private;
982e3d11
HS		 291
292 /* Send EEPROM target address. */
293 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
294 /* Byte2 = I2C command: write to I2C EEPROM device. */
295 | I2C_B1(I2C_ATTRSTOP, addr)
296 /* Byte1 = EEPROM internal target address. */
297 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
298 /* Abort function and declare error if handshake failed. */
982e3d11
HS		 299 return 0;
300 }
301 /* Execute EEPROM read. */
302 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR)
303
304 /* Byte2 = I2C */
305 /* command: read */
306 /* from I2C EEPROM */
307 /* device. */
308 |I2C_B1(I2C_ATTRSTOP, 0)
309
310 /* Byte1 receives */
311 /* uint8_t from */
312 /* EEPROM. */
313 |I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
314
315 /* Abort function and declare error if handshake failed. */
982e3d11
HS		 316 return 0;
317 }
be008602 318
7d856da2 319 return (readl(devpriv->mmio + P_I2CCTRL) >> 16) & 0xff;
982e3d11
HS		 320}
321
95414729
HS		 322/* *********** DAC FUNCTIONS *********** */
323
324/* Slot 0 base settings. */
325#define VECT0 (XSD2 | RSD3 | SIB_A2)
326/* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
327
328/* TrimDac LogicalChan-to-PhysicalChan mapping table. */
329static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
330
331/* TrimDac LogicalChan-to-EepromAdrs mapping table. */
332static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
333
334/* Private helper function: Transmit serial data to DAC via Audio
335 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
336 * Dacpol contains valid target image.
337 */
338static void SendDAC(struct comedi_device *dev, uint32_t val)
339{
7f2f7e05 340 struct s626_private *devpriv = dev->private;
95414729
HS		 341
342 /* START THE SERIAL CLOCK RUNNING ------------- */
343
344 /* Assert DAC polarity control and enable gating of DAC serial clock
345 * and audio bit stream signals. At this point in time we must be
346 * assured of being in time slot 0. If we are not in slot 0, the
347 * serial clock and audio stream signals will be disabled; this is
348 * because the following DEBIwrite statement (which enables signals
349 * to be passed through the gate array) would execute before the
350 * trailing edge of WS1/WS3 (which turns off the signals), thus
351 * causing the signals to be inactive during the DAC write.
352 */
353 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
354
355 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
356
357 /* Copy DAC setpoint value to DAC's output DMA buffer. */
358
7d856da2 359 /* writel(val, devpriv->mmio + (uint32_t)devpriv->pDacWBuf); */
95414729
HS		 360 *devpriv->pDacWBuf = val;
361
ddd9813e
HS		 362 /*
363 * Enable the output DMA transfer. This will cause the DMAC to copy
364 * the DAC's data value to A2's output FIFO. The DMA transfer will
95414729
HS		 365 * then immediately terminate because the protection address is
366 * reached upon transfer of the first DWORD value.
367 */
ddd9813e 368 s626_mc_enable(dev, MC1_A2OUT, P_MC1);
95414729
HS		 369
370 /* While the DMA transfer is executing ... */
371
25f8fd5e
HS		 372 /*
373 * Reset Audio2 output FIFO's underflow flag (along with any
374 * other FIFO underflow/overflow flags). When set, this flag
375 * will indicate that we have emerged from slot 0.
95414729 376 */
7d856da2 377 writel(ISR_AFOU, devpriv->mmio + P_ISR);
95414729
HS		 378
379 /* Wait for the DMA transfer to finish so that there will be data
380 * available in the FIFO when time slot 1 tries to transfer a DWORD
381 * from the FIFO to the output buffer register. We test for DMA
382 * Done by polling the DMAC enable flag; this flag is automatically
383 * cleared when the transfer has finished.
384 */
7d856da2 385 while (readl(devpriv->mmio + P_MC1) & MC1_A2OUT)
95414729
HS		 386 ;
387
388 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
389
390 /* FIFO data is now available, so we enable execution of time slots
391 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
392 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
393 * detection.
394 */
7d856da2 395 writel(XSD2 | RSD3 | SIB_A2, devpriv->mmio + VECTPORT(0));
95414729
HS		 396
397 /* Wait for slot 1 to execute to ensure that the Packet will be
398 * transmitted. This is detected by polling the Audio2 output FIFO
399 * underflow flag, which will be set when slot 1 execution has
400 * finished transferring the DAC's data DWORD from the output FIFO
401 * to the output buffer register.
402 */
7d856da2 403 while (!(readl(devpriv->mmio + P_SSR) & SSR_AF2_OUT))
95414729
HS		 404 ;
405
406 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
407 * back to slot 0 after executing the EOS in slot 5. Also,
408 * simultaneously shift out and in the 0x00 that is ALWAYS the value
409 * stored in the last byte to be shifted out of the FIFO's DWORD
410 * buffer register.
411 */
25f8fd5e 412 writel(XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS,
7d856da2 413 devpriv->mmio + VECTPORT(0));
95414729
HS		 414
415 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
416
417 /* Wait for the TSL to finish executing all time slots before
418 * exiting this function. We must do this so that the next DAC
419 * write doesn't start, thereby enabling clock/chip select signals:
420 *
421 * 1. Before the TSL sequence cycles back to slot 0, which disables
422 * the clock/cs signal gating and traps slot // list execution.
423 * we have not yet finished slot 5 then the clock/cs signals are
424 * still gated and we have not finished transmitting the stream.
425 *
426 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
427 * this case, the slot sequence is currently repeating, but with
428 * clock/cs signals disabled. We must wait for slot 0 to trap
429 * execution before setting up the next DAC setpoint DMA transfer
430 * and enabling the clock/cs signals. To detect the end of slot 5,
431 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
432 * the TSL has not yet finished executing slot 5 ...
433 */
7d856da2 434 if (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000) {
95414729
HS		 435 /* The trap was set on time and we are still executing somewhere
436 * in slots 2-5, so we now wait for slot 0 to execute and trap
437 * TSL execution. This is detected when FB_BUFFER2 MSB changes
438 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
439 * out/in on SD2 the 0x00 that is always referenced by slot 5.
440 */
7d856da2 441 while (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000)
95414729
HS		 442 ;
443 }
444 /* Either (1) we were too late setting the slot 0 trap; the TSL
445 * sequencer restarted slot 0 before we could set the EOS trap flag,
446 * or (2) we were not late and execution is now trapped at slot 0.
447 * In either case, we must now change slot 0 so that it will store
448 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
449 * In order to do this, we reprogram slot 0 so that it will shift in
450 * SD3, which is driven only by a pull-up resistor.
451 */
7d856da2 452 writel(RSD3 | SIB_A2 | EOS, devpriv->mmio + VECTPORT(0));
95414729
HS		 453
454 /* Wait for slot 0 to execute, at which time the TSL is setup for
455 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
456 * from 0x00 to 0xFF.
457 */
7d856da2 458 while (!(readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000))
95414729
HS		 459 ;
460}
461
462/* Private helper function: Write setpoint to an application DAC channel. */
463static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
464{
7f2f7e05 465 struct s626_private *devpriv = dev->private;
95414729
HS		 466 register uint16_t signmask;
467 register uint32_t WSImage;
468
469 /* Adjust DAC data polarity and set up Polarity Control Register */
470 /* image. */
471 signmask = 1 << chan;
472 if (dacdata < 0) {
473 dacdata = -dacdata;
474 devpriv->Dacpol |= signmask;
475 } else
476 devpriv->Dacpol &= ~signmask;
477
478 /* Limit DAC setpoint value to valid range. */
479 if ((uint16_t) dacdata > 0x1FFF)
480 dacdata = 0x1FFF;
481
482 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
483 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
484 * data to a non-existent TrimDac channel just to keep the clock
485 * running after sending data to the target DAC. This is necessary
486 * to eliminate the clock glitch that would otherwise occur at the
487 * end of the target DAC's serial data stream. When the sequence
488 * restarts at V0 (after executing V5), the gate array automatically
489 * disables gating for the DAC clock and all DAC chip selects.
490 */
491
25f8fd5e 492 /* Choose DAC chip select to be asserted */
95414729 493 WSImage = (chan & 2) ? WS1 : WS2;
25f8fd5e 494 /* Slot 2: Transmit high data byte to target DAC */
7d856da2 495 writel(XSD2 | XFIFO_1 | WSImage, devpriv->mmio + VECTPORT(2));
25f8fd5e 496 /* Slot 3: Transmit low data byte to target DAC */
7d856da2 497 writel(XSD2 | XFIFO_0 | WSImage, devpriv->mmio + VECTPORT(3));
95414729 498 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
7d856da2 499 writel(XSD2 | XFIFO_3 | WS3, devpriv->mmio + VECTPORT(4));
25f8fd5e 500 /* Slot 5: running after writing target DAC's low data byte */
7d856da2 501 writel(XSD2 | XFIFO_2 | WS3 | EOS, devpriv->mmio + VECTPORT(5));
95414729
HS		 502
503 /* Construct and transmit target DAC's serial packet:
504 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
505 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
506 * to a non-existent TrimDac channel) that serves to keep the clock
507 * running after the packet has been sent to the target DAC.
508 */
509 SendDAC(dev, 0x0F000000
510 /* Continue clock after target DAC data (write to non-existent trimdac). */
511 | 0x00004000
512 /* Address the two main dual-DAC devices (TSL's chip select enables
513 * target device). */
514 | ((uint32_t) (chan & 1) << 15)
515 /* Address the DAC channel within the device. */
516 | (uint32_t) dacdata); /* Include DAC setpoint data. */
517
518}
519
520static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
521 uint8_t DacData)
522{
7f2f7e05 523 struct s626_private *devpriv = dev->private;
95414729
HS		 524 uint32_t chan;
525
526 /* Save the new setpoint in case the application needs to read it back later. */
527 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
528
529 /* Map logical channel number to physical channel number. */
530 chan = (uint32_t) trimchan[LogicalChan];
531
532 /* Set up TSL2 records for TrimDac write operation. All slots shift
533 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
534 * can be detected.
535 */
536
25f8fd5e 537 /* Slot 2: Send high uint8_t to target TrimDac */
7d856da2 538 writel(XSD2 | XFIFO_1 | WS3, devpriv->mmio + VECTPORT(2));
25f8fd5e 539 /* Slot 3: Send low uint8_t to target TrimDac */
7d856da2 540 writel(XSD2 | XFIFO_0 | WS3, devpriv->mmio + VECTPORT(3));
25f8fd5e 541 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
7d856da2 542 writel(XSD2 | XFIFO_3 | WS1, devpriv->mmio + VECTPORT(4));
25f8fd5e 543 /* Slot 5: Send NOP low uint8_t to DAC0 */
7d856da2 544 writel(XSD2 | XFIFO_2 | WS1 | EOS, devpriv->mmio + VECTPORT(5));
95414729
HS		 545
546 /* Construct and transmit target DAC's serial packet:
547 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
548 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
549 * WORD value (that writes a channel 0 NOP command to a non-existent
550 * main DAC channel) that serves to keep the clock running after the
551 * packet has been sent to the target DAC.
552 */
553
554 /* Address the DAC channel within the trimdac device. */
555 SendDAC(dev, ((uint32_t) chan << 8)
556 | (uint32_t) DacData); /* Include DAC setpoint data. */
557}
558
559static void LoadTrimDACs(struct comedi_device *dev)
560{
561 register uint8_t i;
562
563 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
564 for (i = 0; i < ARRAY_SIZE(trimchan); i++)
565 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
566}
567
e3eb08d0
HS		 568/* ****** COUNTER FUNCTIONS ******* */
569/* All counter functions address a specific counter by means of the
570 * "Counter" argument, which is a logical counter number. The Counter
571 * argument may have any of the following legal values: 0=0A, 1=1A,
572 * 2=2A, 3=0B, 4=1B, 5=2B.
573 */
574
575/* Read a counter's output latch. */
576static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k)
577{
578 register uint32_t value;
e3eb08d0
HS		 579
580 /* Latch counts and fetch LSW of latched counts value. */
581 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
582
583 /* Fetch MSW of latched counts and combine with LSW. */
584 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
585
e3eb08d0
HS		 586 /* Return latched counts. */
587 return value;
588}
589
590/* Return/set a counter pair's latch trigger source. 0: On read
591 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
592 * latches B.
593 */
594static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
595 uint16_t value)
596{
e3eb08d0 597 DEBIreplace(dev, k->MyCRB,
12f4e2f2
HS		 598 ~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC),
599 value << CRBBIT_LATCHSRC);
e3eb08d0
HS		 600}
601
602/* Write value into counter preload register. */
603static void Preload(struct comedi_device *dev, struct enc_private *k,
604 uint32_t value)
605{
bdf5aa39 606 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value);
e3eb08d0
HS		 607 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
608 (uint16_t) (value >> 16));
609}
610
020c44f3 611static unsigned int s626_ai_reg_to_uint(int data)
11e865c1 612{
020c44f3 613 unsigned int tempdata;
11e865c1 614
020c44f3
HS		 615 tempdata = (data >> 18);
616 if (tempdata & 0x2000)
617 tempdata &= 0x1fff;
618 else
619 tempdata += (1 << 13);
11e865c1 620
020c44f3
HS		 621 return tempdata;
622}
8231eb56 623
020c44f3
HS		 624/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
625/* return 0; */
626/* } */
11e865c1 627
6baffbc2
HS		 628static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
629{
100b4edc
HS		 630 unsigned int group = chan / 16;
631 unsigned int mask = 1 << (chan - (16 * group));
6baffbc2
HS		 632 unsigned int status;
633
6baffbc2 634 /* set channel to capture positive edge */
100b4edc
HS		 635 status = DEBIread(dev, LP_RDEDGSEL(group));
636 DEBIwrite(dev, LP_WREDGSEL(group), mask | status);
6baffbc2
HS		 637
638 /* enable interrupt on selected channel */
100b4edc
HS		 639 status = DEBIread(dev, LP_RDINTSEL(group));
640 DEBIwrite(dev, LP_WRINTSEL(group), mask | status);
6baffbc2
HS		 641
642 /* enable edge capture write command */
643 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
644
645 /* enable edge capture on selected channel */
100b4edc
HS		 646 status = DEBIread(dev, LP_RDCAPSEL(group));
647 DEBIwrite(dev, LP_WRCAPSEL(group), mask | status);
6baffbc2
HS		 648
649 return 0;
650}
651
652static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
653 unsigned int mask)
654{
6baffbc2
HS		 655 /* disable edge capture write command */
656 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
657
658 /* enable edge capture on selected channel */
100b4edc 659 DEBIwrite(dev, LP_WRCAPSEL(group), mask);
6baffbc2
HS		 660
661 return 0;
662}
663
664static int s626_dio_clear_irq(struct comedi_device *dev)
665{
666 unsigned int group;
667
668 /* disable edge capture write command */
669 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
670
100b4edc
HS		 671 /* clear all dio pending events and interrupt */
672 for (group = 0; group < S626_DIO_BANKS; group++)
673 DEBIwrite(dev, LP_WRCAPSEL(group), 0xffff);
6baffbc2
HS		 674
675 return 0;
676}
677
65a17c29
HS		 678static void handle_dio_interrupt(struct comedi_device *dev,
679 uint16_t irqbit, uint8_t group)
680{
681 struct s626_private *devpriv = dev->private;
682 struct comedi_subdevice *s = dev->read_subdev;
683 struct comedi_cmd *cmd = &s->async->cmd;
684
685 s626_dio_reset_irq(dev, group, irqbit);
686
687 if (devpriv->ai_cmd_running) {
688 /* check if interrupt is an ai acquisition start trigger */
689 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
690 cmd->start_src == TRIG_EXT) {
691 /* Start executing the RPS program */
ddd9813e 692 s626_mc_enable(dev, MC1_ERPS1, P_MC1);
65a17c29
HS		 693
694 if (cmd->scan_begin_src == TRIG_EXT)
695 s626_dio_set_irq(dev, cmd->scan_begin_arg);
696 }
697 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
698 cmd->scan_begin_src == TRIG_EXT) {
ddd9813e
HS		 699 /* Trigger ADC scan loop start */
700 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
65a17c29
HS		 701
702 if (cmd->convert_src == TRIG_EXT) {
703 devpriv->ai_convert_count = cmd->chanlist_len;
704
705 s626_dio_set_irq(dev, cmd->convert_arg);
706 }
707
708 if (cmd->convert_src == TRIG_TIMER) {
709 struct enc_private *k = &encpriv[5];
710
711 devpriv->ai_convert_count = cmd->chanlist_len;
712 k->SetEnable(dev, k, CLKENAB_ALWAYS);
713 }
714 }
715 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
716 cmd->convert_src == TRIG_EXT) {
ddd9813e
HS		 717 /* Trigger ADC scan loop start */
718 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
65a17c29
HS		 719
720 devpriv->ai_convert_count--;
721 if (devpriv->ai_convert_count > 0)
722 s626_dio_set_irq(dev, cmd->convert_arg);
723 }
724 }
725}
726
727static void check_dio_interrupts(struct comedi_device *dev)
728{
729 uint16_t irqbit;
730 uint8_t group;
731
732 for (group = 0; group < S626_DIO_BANKS; group++) {
733 irqbit = 0;
734 /* read interrupt type */
735 irqbit = DEBIread(dev, LP_RDCAPFLG(group));
736
737 /* check if interrupt is generated from dio channels */
738 if (irqbit) {
739 handle_dio_interrupt(dev, irqbit, group);
740 return;
741 }
742 }
743}
744
0b9675d5
HS		 745static void check_counter_interrupts(struct comedi_device *dev)
746{
747 struct s626_private *devpriv = dev->private;
748 struct comedi_subdevice *s = dev->read_subdev;
749 struct comedi_async *async = s->async;
750 struct comedi_cmd *cmd = &async->cmd;
751 struct enc_private *k;
752 uint16_t irqbit;
753
754 /* read interrupt type */
755 irqbit = DEBIread(dev, LP_RDMISC2);
756
757 /* check interrupt on counters */
758 if (irqbit & IRQ_COINT1A) {
759 k = &encpriv[0];
760
761 /* clear interrupt capture flag */
762 k->ResetCapFlags(dev, k);
763 }
764 if (irqbit & IRQ_COINT2A) {
765 k = &encpriv[1];
766
767 /* clear interrupt capture flag */
768 k->ResetCapFlags(dev, k);
769 }
770 if (irqbit & IRQ_COINT3A) {
771 k = &encpriv[2];
772
773 /* clear interrupt capture flag */
774 k->ResetCapFlags(dev, k);
775 }
776 if (irqbit & IRQ_COINT1B) {
777 k = &encpriv[3];
778
779 /* clear interrupt capture flag */
780 k->ResetCapFlags(dev, k);
781 }
782 if (irqbit & IRQ_COINT2B) {
783 k = &encpriv[4];
784
785 /* clear interrupt capture flag */
786 k->ResetCapFlags(dev, k);
787
788 if (devpriv->ai_convert_count > 0) {
789 devpriv->ai_convert_count--;
790 if (devpriv->ai_convert_count == 0)
791 k->SetEnable(dev, k, CLKENAB_INDEX);
792
793 if (cmd->convert_src == TRIG_TIMER) {
ddd9813e
HS		 794 /* Trigger ADC scan loop start */
795 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
0b9675d5
HS		 796 }
797 }
798 }
799 if (irqbit & IRQ_COINT3B) {
800 k = &encpriv[5];
801
802 /* clear interrupt capture flag */
803 k->ResetCapFlags(dev, k);
804
805 if (cmd->scan_begin_src == TRIG_TIMER) {
ddd9813e
HS		 806 /* Trigger ADC scan loop start */
807 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
0b9675d5
HS		 808 }
809
810 if (cmd->convert_src == TRIG_TIMER) {
811 k = &encpriv[4];
812 devpriv->ai_convert_count = cmd->chanlist_len;
813 k->SetEnable(dev, k, CLKENAB_ALWAYS);
814 }
815 }
816}
817
4c2d13e0
HS		 818static bool handle_eos_interrupt(struct comedi_device *dev)
819{
820 struct s626_private *devpriv = dev->private;
821 struct comedi_subdevice *s = dev->read_subdev;
822 struct comedi_async *async = s->async;
823 struct comedi_cmd *cmd = &async->cmd;
824 /*
825 * Init ptr to DMA buffer that holds new ADC data. We skip the
826 * first uint16_t in the buffer because it contains junk data
827 * from the final ADC of the previous poll list scan.
828 */
829 int32_t *readaddr = (int32_t *)devpriv->ANABuf.LogicalBase + 1;
830 bool finished = false;
831 int i;
832
833 /* get the data and hand it over to comedi */
834 for (i = 0; i < cmd->chanlist_len; i++) {
835 short tempdata;
836
837 /*
838 * Convert ADC data to 16-bit integer values and copy
839 * to application buffer.
840 */
841 tempdata = s626_ai_reg_to_uint((int)*readaddr);
842 readaddr++;
843
844 /* put data into read buffer */
845 /* comedi_buf_put(async, tempdata); */
846 cfc_write_to_buffer(s, tempdata);
847 }
848
849 /* end of scan occurs */
850 async->events |= COMEDI_CB_EOS;
851
852 if (!devpriv->ai_continous)
853 devpriv->ai_sample_count--;
854 if (devpriv->ai_sample_count <= 0) {
855 devpriv->ai_cmd_running = 0;
856
c5cf4606
HS		 857 /* Stop RPS program */
858 s626_mc_disable(dev, MC1_ERPS1, P_MC1);
4c2d13e0
HS		 859
860 /* send end of acquisition */
861 async->events |= COMEDI_CB_EOA;
862
863 /* disable master interrupt */
864 finished = true;
865 }
866
867 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
868 s626_dio_set_irq(dev, cmd->scan_begin_arg);
869
870 /* tell comedi that data is there */
871 comedi_event(dev, s);
872
873 return finished;
874}
875
020c44f3
HS		 876static irqreturn_t s626_irq_handler(int irq, void *d)
877{
878 struct comedi_device *dev = d;
7f2f7e05 879 struct s626_private *devpriv = dev->private;
020c44f3 880 unsigned long flags;
020c44f3 881 uint32_t irqtype, irqstatus;
11e865c1 882
a7401cdd 883 if (!dev->attached)
020c44f3
HS		 884 return IRQ_NONE;
885 /* lock to avoid race with comedi_poll */
886 spin_lock_irqsave(&dev->spinlock, flags);
11e865c1 887
020c44f3 888 /* save interrupt enable register state */
7d856da2 889 irqstatus = readl(devpriv->mmio + P_IER);
11e865c1 890
020c44f3 891 /* read interrupt type */
7d856da2 892 irqtype = readl(devpriv->mmio + P_ISR);
11e865c1 893
020c44f3 894 /* disable master interrupt */
7d856da2 895 writel(0, devpriv->mmio + P_IER);
11e865c1 896
020c44f3 897 /* clear interrupt */
7d856da2 898 writel(irqtype, devpriv->mmio + P_ISR);
11e865c1 899
020c44f3
HS		 900 switch (irqtype) {
901 case IRQ_RPS1: /* end_of_scan occurs */
4c2d13e0 902 if (handle_eos_interrupt(dev))
020c44f3 903 irqstatus = 0;
020c44f3
HS		 904 break;
905 case IRQ_GPIO3: /* check dio and conter interrupt */
020c44f3 906 /* s626_dio_clear_irq(dev); */
65a17c29 907 check_dio_interrupts(dev);
0b9675d5
HS		 908 check_counter_interrupts(dev);
909 break;
020c44f3 910 }
11e865c1 911
020c44f3 912 /* enable interrupt */
7d856da2 913 writel(irqstatus, devpriv->mmio + P_IER);
b6c77757 914
020c44f3
HS		 915 spin_unlock_irqrestore(&dev->spinlock, flags);
916 return IRQ_HANDLED;
917}
b6c77757 918
020c44f3
HS		 919/*
920 * this functions build the RPS program for hardware driven acquistion
921 */
922static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
923{
7f2f7e05 924 struct s626_private *devpriv = dev->private;
020c44f3
HS		 925 register uint32_t *pRPS;
926 uint32_t JmpAdrs;
927 uint16_t i;
928 uint16_t n;
929 uint32_t LocalPPL;
930 struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
11e865c1 931
c5cf4606
HS		 932 /* Stop RPS program in case it is currently running */
933 s626_mc_disable(dev, MC1_ERPS1, P_MC1);
11e865c1 934
020c44f3
HS		 935 /* Set starting logical address to write RPS commands. */
936 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
11e865c1 937
25f8fd5e
HS		 938 /* Initialize RPS instruction pointer */
939 writel((uint32_t)devpriv->RPSBuf.PhysicalBase,
7d856da2 940 devpriv->mmio + P_RPSADDR1);
11e865c1 941
020c44f3 942 /* Construct RPS program in RPSBuf DMA buffer */
11e865c1 943
020c44f3 944 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
020c44f3
HS		 945 /* Wait for Start trigger. */
946 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
947 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
948 }
11e865c1 949
020c44f3
HS		 950 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
951 * because the first RPS DEBI Write following a non-RPS DEBI write
952 * seems to always fail. If we don't do this dummy write, the ADC
953 * gain might not be set to the value required for the first slot in
954 * the poll list; the ADC gain would instead remain unchanged from
955 * the previously programmed value.
956 */
957 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
958 /* Write DEBI Write command and address to shadow RAM. */
11e865c1 959
020c44f3
HS		 960 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
961 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
962 /* Write DEBI immediate data to shadow RAM: */
11e865c1 963
020c44f3
HS		 964 *pRPS++ = GSEL_BIPOLAR5V;
965 /* arbitrary immediate data value. */
11e865c1 966
020c44f3
HS		 967 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
968 /* Reset "shadow RAM uploaded" flag. */
969 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
970 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
11e865c1 971
020c44f3
HS		 972 /* Digitize all slots in the poll list. This is implemented as a
973 * for loop to limit the slot count to 16 in case the application
974 * forgot to set the EOPL flag in the final slot.
975 */
976 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
977 /* Convert application's poll list item to private board class
978 * format. Each app poll list item is an uint8_t with form
979 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
980 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
b6c77757 981 */
020c44f3
HS		 982 LocalPPL =
983 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
984 GSEL_BIPOLAR10V);
11e865c1 985
020c44f3
HS		 986 /* Switch ADC analog gain. */
987 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
988 /* and address to */
989 /* shadow RAM. */
990 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
991 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
992 /* immediate data to */
993 /* shadow RAM. */
994 *pRPS++ = LocalPPL;
995 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
996 /* flag. */
997 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
998 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
999 /* finish. */
11e865c1 1000
020c44f3
HS		 1001 /* Select ADC analog input channel. */
1002 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1003 /* Write DEBI command and address to shadow RAM. */
1004 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
1005 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1006 /* Write DEBI immediate data to shadow RAM. */
1007 *pRPS++ = LocalPPL;
1008 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1009 /* Reset "shadow RAM uploaded" flag. */
11e865c1 1010
020c44f3
HS		 1011 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1012 /* Invoke shadow RAM upload. */
11e865c1 1013
020c44f3
HS		 1014 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1015 /* Wait for shadow upload to finish. */
11e865c1 1016
020c44f3
HS		 1017 /* Delay at least 10 microseconds for analog input settling.
1018 * Instead of padding with NOPs, we use RPS_JUMP instructions
1019 * here; this allows us to produce a longer delay than is
1020 * possible with NOPs because each RPS_JUMP flushes the RPS'
1021 * instruction prefetch pipeline.
1022 */
1023 JmpAdrs =
1024 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1025 (uint32_t) ((unsigned long)pRPS -
1026 (unsigned long)devpriv->RPSBuf.LogicalBase);
1027 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
1028 JmpAdrs += 8; /* Repeat to implement time delay: */
1029 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
1030 *pRPS++ = JmpAdrs;
1031 }
11e865c1 1032
020c44f3 1033 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
020c44f3
HS		 1034 /* Wait for Start trigger. */
1035 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1036 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1037 }
1038 /* Start ADC by pulsing GPIO1. */
1039 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1040 *pRPS++ = GPIO_BASE | GPIO1_LO;
1041 *pRPS++ = RPS_NOP;
1042 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1043 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1044 *pRPS++ = GPIO_BASE | GPIO1_HI;
11e865c1 1045
020c44f3
HS		 1046 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1047 * busy) and for data from previous conversion to shift into FB
1048 * BUFFER 1 register.
1049 */
1050 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1051
020c44f3
HS		 1052 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1053 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1054 *pRPS++ =
1055 (uint32_t) devpriv->ANABuf.PhysicalBase +
1056 (devpriv->AdcItems << 2);
11e865c1 1057
020c44f3
HS		 1058 /* If this slot's EndOfPollList flag is set, all channels have */
1059 /* now been processed. */
1060 if (*ppl++ & EOPL) {
1061 devpriv->AdcItems++; /* Adjust poll list item count. */
1062 break; /* Exit poll list processing loop. */
1063 }
1064 }
11e865c1 1065
020c44f3
HS		 1066 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1067 * ADC to stabilize for 2 microseconds before starting the final
1068 * (dummy) conversion. This delay is necessary to allow sufficient
1069 * time between last conversion finished and the start of the dummy
1070 * conversion. Without this delay, the last conversion's data value
1071 * is sometimes set to the previous conversion's data value.
1072 */
1073 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1074 *pRPS++ = RPS_NOP;
11e865c1 1075
020c44f3
HS		 1076 /* Start a dummy conversion to cause the data from the last
1077 * conversion of interest to be shifted in.
1078 */
1079 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1080 *pRPS++ = GPIO_BASE | GPIO1_LO;
1081 *pRPS++ = RPS_NOP;
1082 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1083 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1084 *pRPS++ = GPIO_BASE | GPIO1_HI;
11e865c1 1085
020c44f3
HS		 1086 /* Wait for the data from the last conversion of interest to arrive
1087 * in FB BUFFER 1 register.
1088 */
1089 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1090
020c44f3
HS		 1091 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1092 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
1093 *pRPS++ =
1094 (uint32_t) devpriv->ANABuf.PhysicalBase + (devpriv->AdcItems << 2);
11e865c1 1095
020c44f3
HS		 1096 /* Indicate ADC scan loop is finished. */
1097 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
11e865c1 1098
020c44f3
HS		 1099 /* invoke interrupt */
1100 if (devpriv->ai_cmd_running == 1) {
020c44f3
HS		 1101 *pRPS++ = RPS_IRQ;
1102 }
1103 /* Restart RPS program at its beginning. */
1104 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
1105 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
11e865c1 1106
020c44f3
HS		 1107 /* End of RPS program build */
1108}
11e865c1 1109
e4632a71
HS		 1110#ifdef unused_code
1111static int s626_ai_rinsn(struct comedi_device *dev,
1112 struct comedi_subdevice *s,
1113 struct comedi_insn *insn,
1114 unsigned int *data)
1115{
1116 struct s626_private *devpriv = dev->private;
1117 register uint8_t i;
1118 register int32_t *readaddr;
11e865c1 1119
ddd9813e
HS		 1120 /* Trigger ADC scan loop start */
1121 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
11e865c1 1122
e4632a71 1123 /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
95bb7982 1124 while (s626_mc_test(dev, MC2_ADC_RPS, P_MC2))
e4632a71 1125 ;
11e865c1 1126
e4632a71
HS		 1127 /*
1128 * Init ptr to DMA buffer that holds new ADC data. We skip the
1129 * first uint16_t in the buffer because it contains junk data from
1130 * the final ADC of the previous poll list scan.
1131 */
1132 readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1;
11e865c1 1133
e4632a71
HS		 1134 /*
1135 * Convert ADC data to 16-bit integer values and
1136 * copy to application buffer.
1137 */
1138 for (i = 0; i < devpriv->AdcItems; i++) {
1139 *data = s626_ai_reg_to_uint(*readaddr++);
1140 data++;
1141 }
11e865c1 1142
e4632a71
HS		 1143 return i;
1144}
1145#endif
11e865c1 1146
020c44f3
HS		 1147static int s626_ai_insn_read(struct comedi_device *dev,
1148 struct comedi_subdevice *s,
1149 struct comedi_insn *insn, unsigned int *data)
1150{
7f2f7e05 1151 struct s626_private *devpriv = dev->private;
020c44f3
HS		 1152 uint16_t chan = CR_CHAN(insn->chanspec);
1153 uint16_t range = CR_RANGE(insn->chanspec);
1154 uint16_t AdcSpec = 0;
1155 uint32_t GpioImage;
be008602 1156 int tmp;
020c44f3 1157 int n;
11e865c1 1158
020c44f3 1159 /* interrupt call test */
7d856da2 1160/* writel(IRQ_GPIO3,devpriv->mmio+P_PSR); */
020c44f3
HS		 1161 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1162 * corresponding interrupt to be generated if enabled
1163 */
11e865c1 1164
020c44f3
HS		 1165 /* Convert application's ADC specification into form
1166 * appropriate for register programming.
1167 */
1168 if (range == 0)
1169 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1170 else
1171 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
11e865c1 1172
020c44f3
HS		 1173 /* Switch ADC analog gain. */
1174 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
11e865c1 1175
020c44f3
HS		 1176 /* Select ADC analog input channel. */
1177 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
11e865c1 1178
020c44f3 1179 for (n = 0; n < insn->n; n++) {
11e865c1 1180
020c44f3
HS		 1181 /* Delay 10 microseconds for analog input settling. */
1182 udelay(10);
11e865c1 1183
be008602 1184 /* Start ADC by pulsing GPIO1 low */
7d856da2 1185 GpioImage = readl(devpriv->mmio + P_GPIO);
25f8fd5e 1186 /* Assert ADC Start command */
7d856da2 1187 writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
25f8fd5e 1188 /* and stretch it out */
7d856da2
HS		 1189 writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
1190 writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
25f8fd5e 1191 /* Negate ADC Start command */
7d856da2 1192 writel(GpioImage | GPIO1_HI, devpriv->mmio + P_GPIO);
11e865c1 1193
020c44f3
HS		 1194 /* Wait for ADC to complete (GPIO2 is asserted high when */
1195 /* ADC not busy) and for data from previous conversion to */
1196 /* shift into FB BUFFER 1 register. */
11e865c1 1197
be008602 1198 /* Wait for ADC done */
7d856da2 1199 while (!(readl(devpriv->mmio + P_PSR) & PSR_GPIO2))
020c44f3 1200 ;
11e865c1 1201
be008602
HS		 1202 /* Fetch ADC data */
1203 if (n != 0) {
7d856da2 1204 tmp = readl(devpriv->mmio + P_FB_BUFFER1);
be008602
HS		 1205 data[n - 1] = s626_ai_reg_to_uint(tmp);
1206 }
11e865c1 1207
020c44f3
HS		 1208 /* Allow the ADC to stabilize for 4 microseconds before
1209 * starting the next (final) conversion. This delay is
1210 * necessary to allow sufficient time between last
1211 * conversion finished and the start of the next
1212 * conversion. Without this delay, the last conversion's
1213 * data value is sometimes set to the previous
1214 * conversion's data value.
1215 */
1216 udelay(4);
1217 }
11e865c1 1218
020c44f3
HS		 1219 /* Start a dummy conversion to cause the data from the
1220 * previous conversion to be shifted in. */
7d856da2 1221 GpioImage = readl(devpriv->mmio + P_GPIO);
020c44f3 1222 /* Assert ADC Start command */
7d856da2 1223 writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
25f8fd5e 1224 /* and stretch it out */
7d856da2
HS		 1225 writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
1226 writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
25f8fd5e 1227 /* Negate ADC Start command */
7d856da2 1228 writel(GpioImage | GPIO1_HI, devpriv->mmio + P_GPIO);
11e865c1 1229
020c44f3 1230 /* Wait for the data to arrive in FB BUFFER 1 register. */
11e865c1 1231
be008602 1232 /* Wait for ADC done */
7d856da2 1233 while (!(readl(devpriv->mmio + P_PSR) & PSR_GPIO2))
020c44f3 1234 ;
11e865c1 1235
020c44f3 1236 /* Fetch ADC data from audio interface's input shift register. */
11e865c1 1237
be008602
HS		 1238 /* Fetch ADC data */
1239 if (n != 0) {
7d856da2 1240 tmp = readl(devpriv->mmio + P_FB_BUFFER1);
be008602
HS		 1241 data[n - 1] = s626_ai_reg_to_uint(tmp);
1242 }
11e865c1 1243
020c44f3
HS		 1244 return n;
1245}
11e865c1 1246
020c44f3
HS		 1247static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1248{
11e865c1 1249
020c44f3 1250 int n;
11e865c1 1251
020c44f3
HS		 1252 for (n = 0; n < cmd->chanlist_len; n++) {
1253 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1254 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1255 else
1256 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1257 }
1258 if (n != 0)
1259 ppl[n - 1] |= EOPL;
11e865c1 1260
020c44f3
HS		 1261 return n;
1262}
11e865c1 1263
020c44f3
HS		 1264static int s626_ai_inttrig(struct comedi_device *dev,
1265 struct comedi_subdevice *s, unsigned int trignum)
1266{
1267 if (trignum != 0)
1268 return -EINVAL;
11e865c1 1269
ddd9813e
HS		 1270 /* Start executing the RPS program */
1271 s626_mc_enable(dev, MC1_ERPS1, P_MC1);
11e865c1 1272
020c44f3 1273 s->async->inttrig = NULL;
11e865c1 1274
020c44f3
HS		 1275 return 1;
1276}
11e865c1 1277
6baffbc2
HS		 1278/* This function doesn't require a particular form, this is just what
1279 * happens to be used in some of the drivers. It should convert ns
1280 * nanoseconds to a counter value suitable for programming the device.
1281 * Also, it should adjust ns so that it cooresponds to the actual time
1282 * that the device will use. */
1283static int s626_ns_to_timer(int *nanosec, int round_mode)
1284{
1285 int divider, base;
1286
1287 base = 500; /* 2MHz internal clock */
1288
1289 switch (round_mode) {
1290 case TRIG_ROUND_NEAREST:
1291 default:
1292 divider = (*nanosec + base / 2) / base;
1293 break;
1294 case TRIG_ROUND_DOWN:
1295 divider = (*nanosec) / base;
1296 break;
1297 case TRIG_ROUND_UP:
1298 divider = (*nanosec + base - 1) / base;
1299 break;
1300 }
1301
1302 *nanosec = base * divider;
1303 return divider - 1;
1304}
1305
e3eb08d0
HS		 1306static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
1307 int tick)
1308{
1309 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
1310 /* index. */
1311 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
1312 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
1313 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
1314 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
1315 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
1316 (CLKENAB_INDEX << BF_CLKENAB);
1317 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
1318 /* uint16_t enab=CLKENAB_ALWAYS; */
1319
1320 k->SetMode(dev, k, Setup, FALSE);
1321
1322 /* Set the preload register */
1323 Preload(dev, k, tick);
1324
1325 /* Software index pulse forces the preload register to load */
1326 /* into the counter */
1327 k->SetLoadTrig(dev, k, 0);
1328 k->PulseIndex(dev, k);
1329
1330 /* set reload on counter overflow */
1331 k->SetLoadTrig(dev, k, 1);
1332
1333 /* set interrupt on overflow */
1334 k->SetIntSrc(dev, k, INTSRC_OVER);
1335
1336 SetLatchSource(dev, k, valueSrclatch);
1337 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
1338}
1339
020c44f3
HS		 1340/* TO COMPLETE */
1341static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1342{
7f2f7e05 1343 struct s626_private *devpriv = dev->private;
020c44f3
HS		 1344 uint8_t ppl[16];
1345 struct comedi_cmd *cmd = &s->async->cmd;
1346 struct enc_private *k;
1347 int tick;
11e865c1 1348
020c44f3
HS		 1349 if (devpriv->ai_cmd_running) {
1350 printk(KERN_ERR "s626_ai_cmd: Another ai_cmd is running %d\n",
1351 dev->minor);
1352 return -EBUSY;
1353 }
1354 /* disable interrupt */
7d856da2 1355 writel(0, devpriv->mmio + P_IER);
11e865c1 1356
020c44f3 1357 /* clear interrupt request */
7d856da2 1358 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->mmio + P_ISR);
11e865c1 1359
020c44f3
HS		 1360 /* clear any pending interrupt */
1361 s626_dio_clear_irq(dev);
1362 /* s626_enc_clear_irq(dev); */
11e865c1 1363
020c44f3
HS		 1364 /* reset ai_cmd_running flag */
1365 devpriv->ai_cmd_running = 0;
11e865c1 1366
020c44f3 1367 /* test if cmd is valid */
bdf5aa39 1368 if (cmd == NULL)
020c44f3 1369 return -EINVAL;
11e865c1 1370
020c44f3
HS		 1371 if (dev->irq == 0) {
1372 comedi_error(dev,
1373 "s626_ai_cmd: cannot run command without an irq");
1374 return -EIO;
1375 }
11e865c1 1376
020c44f3
HS		 1377 s626_ai_load_polllist(ppl, cmd);
1378 devpriv->ai_cmd_running = 1;
1379 devpriv->ai_convert_count = 0;
11e865c1 1380
020c44f3
HS		 1381 switch (cmd->scan_begin_src) {
1382 case TRIG_FOLLOW:
1383 break;
1384 case TRIG_TIMER:
1385 /* set a conter to generate adc trigger at scan_begin_arg interval */
1386 k = &encpriv[5];
1387 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1388 cmd->flags & TRIG_ROUND_MASK);
11e865c1 1389
020c44f3
HS		 1390 /* load timer value and enable interrupt */
1391 s626_timer_load(dev, k, tick);
1392 k->SetEnable(dev, k, CLKENAB_ALWAYS);
020c44f3
HS		 1393 break;
1394 case TRIG_EXT:
1395 /* set the digital line and interrupt for scan trigger */
1396 if (cmd->start_src != TRIG_EXT)
1397 s626_dio_set_irq(dev, cmd->scan_begin_arg);
020c44f3
HS		 1398 break;
1399 }
11e865c1 1400
020c44f3
HS		 1401 switch (cmd->convert_src) {
1402 case TRIG_NOW:
1403 break;
1404 case TRIG_TIMER:
1405 /* set a conter to generate adc trigger at convert_arg interval */
1406 k = &encpriv[4];
1407 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
1408 cmd->flags & TRIG_ROUND_MASK);
11e865c1 1409
020c44f3
HS		 1410 /* load timer value and enable interrupt */
1411 s626_timer_load(dev, k, tick);
1412 k->SetEnable(dev, k, CLKENAB_INDEX);
020c44f3
HS		 1413 break;
1414 case TRIG_EXT:
1415 /* set the digital line and interrupt for convert trigger */
1416 if (cmd->scan_begin_src != TRIG_EXT
1417 && cmd->start_src == TRIG_EXT)
1418 s626_dio_set_irq(dev, cmd->convert_arg);
020c44f3
HS		 1419 break;
1420 }
11e865c1 1421
020c44f3
HS		 1422 switch (cmd->stop_src) {
1423 case TRIG_COUNT:
1424 /* data arrives as one packet */
1425 devpriv->ai_sample_count = cmd->stop_arg;
1426 devpriv->ai_continous = 0;
1427 break;
1428 case TRIG_NONE:
1429 /* continous acquisition */
1430 devpriv->ai_continous = 1;
1431 devpriv->ai_sample_count = 0;
1432 break;
11e865c1 1433 }
11e865c1 1434
020c44f3 1435 ResetADC(dev, ppl);
11e865c1 1436
020c44f3
HS		 1437 switch (cmd->start_src) {
1438 case TRIG_NOW:
ddd9813e
HS		 1439 /* Trigger ADC scan loop start */
1440 /* s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); */
11e865c1 1441
ddd9813e
HS		 1442 /* Start executing the RPS program */
1443 s626_mc_enable(dev, MC1_ERPS1, P_MC1);
11e865c1 1444
020c44f3
HS		 1445 s->async->inttrig = NULL;
1446 break;
1447 case TRIG_EXT:
1448 /* configure DIO channel for acquisition trigger */
1449 s626_dio_set_irq(dev, cmd->start_arg);
11e865c1 1450
020c44f3
HS		 1451 s->async->inttrig = NULL;
1452 break;
1453 case TRIG_INT:
1454 s->async->inttrig = s626_ai_inttrig;
1455 break;
11e865c1 1456 }
b6c77757 1457
020c44f3 1458 /* enable interrupt */
7d856da2 1459 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->mmio + P_IER);
b6c77757 1460
020c44f3
HS		 1461 return 0;
1462}
b6c77757 1463
020c44f3
HS		 1464static int s626_ai_cmdtest(struct comedi_device *dev,
1465 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1466{
1467 int err = 0;
1468 int tmp;
b6c77757 1469
27020ffe 1470 /* Step 1 : check if triggers are trivially valid */
b6c77757 1471
27020ffe
HS		 1472 err |= cfc_check_trigger_src(&cmd->start_src,
1473 TRIG_NOW | TRIG_INT | TRIG_EXT);
1474 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
1475 TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
1476 err |= cfc_check_trigger_src(&cmd->convert_src,
1477 TRIG_TIMER | TRIG_EXT | TRIG_NOW);
1478 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1479 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
11e865c1 1480
020c44f3
HS		 1481 if (err)
1482 return 1;
11e865c1 1483
27020ffe 1484 /* Step 2a : make sure trigger sources are unique */
11e865c1 1485
27020ffe
HS		 1486 err |= cfc_check_trigger_is_unique(cmd->start_src);
1487 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1488 err |= cfc_check_trigger_is_unique(cmd->convert_src);
1489 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1490
1491 /* Step 2b : and mutually compatible */
020c44f3
HS		 1492
1493 if (err)
1494 return 2;
1495
1496 /* step 3: make sure arguments are trivially compatible */
1497
53a254b9
HS		 1498 if (cmd->start_src != TRIG_EXT)
1499 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1500 if (cmd->start_src == TRIG_EXT)
1501 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
11e865c1 1502
53a254b9
HS		 1503 if (cmd->scan_begin_src == TRIG_EXT)
1504 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
11e865c1 1505
53a254b9
HS		 1506 if (cmd->convert_src == TRIG_EXT)
1507 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
11e865c1 1508
020c44f3
HS		 1509#define MAX_SPEED 200000 /* in nanoseconds */
1510#define MIN_SPEED 2000000000 /* in nanoseconds */
11e865c1 1511
020c44f3 1512 if (cmd->scan_begin_src == TRIG_TIMER) {
53a254b9
HS		 1513 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1514 MAX_SPEED);
1515 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
1516 MIN_SPEED);
020c44f3
HS		 1517 } else {
1518 /* external trigger */
1519 /* should be level/edge, hi/lo specification here */
1520 /* should specify multiple external triggers */
53a254b9 1521/* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
020c44f3
HS		 1522 }
1523 if (cmd->convert_src == TRIG_TIMER) {
53a254b9
HS		 1524 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, MAX_SPEED);
1525 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, MIN_SPEED);
020c44f3
HS		 1526 } else {
1527 /* external trigger */
1528 /* see above */
53a254b9 1529/* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
020c44f3 1530 }
11e865c1 1531
53a254b9
HS		 1532 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1533
1534 if (cmd->stop_src == TRIG_COUNT)
1535 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
1536 else /* TRIG_NONE */
1537 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
11e865c1 1538
020c44f3
HS		 1539 if (err)
1540 return 3;
1541
1542 /* step 4: fix up any arguments */
1543
1544 if (cmd->scan_begin_src == TRIG_TIMER) {
1545 tmp = cmd->scan_begin_arg;
1546 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1547 cmd->flags & TRIG_ROUND_MASK);
1548 if (tmp != cmd->scan_begin_arg)
1549 err++;
1550 }
1551 if (cmd->convert_src == TRIG_TIMER) {
1552 tmp = cmd->convert_arg;
1553 s626_ns_to_timer((int *)&cmd->convert_arg,
1554 cmd->flags & TRIG_ROUND_MASK);
1555 if (tmp != cmd->convert_arg)
1556 err++;
1557 if (cmd->scan_begin_src == TRIG_TIMER &&
1558 cmd->scan_begin_arg <
1559 cmd->convert_arg * cmd->scan_end_arg) {
1560 cmd->scan_begin_arg =
1561 cmd->convert_arg * cmd->scan_end_arg;
1562 err++;
1563 }
11e865c1 1564 }
11e865c1 1565
020c44f3
HS		 1566 if (err)
1567 return 4;
1568
1569 return 0;
11e865c1
GP		 1570}
1571
020c44f3 1572static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
11e865c1 1573{
7f2f7e05
HS		 1574 struct s626_private *devpriv = dev->private;
1575
c5cf4606
HS		 1576 /* Stop RPS program in case it is currently running */
1577 s626_mc_disable(dev, MC1_ERPS1, P_MC1);
11e865c1 1578
020c44f3 1579 /* disable master interrupt */
7d856da2 1580 writel(0, devpriv->mmio + P_IER);
11e865c1 1581
020c44f3 1582 devpriv->ai_cmd_running = 0;
11e865c1 1583
020c44f3
HS		 1584 return 0;
1585}
11e865c1 1586
020c44f3
HS		 1587static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1588 struct comedi_insn *insn, unsigned int *data)
11e865c1 1589{
7f2f7e05 1590 struct s626_private *devpriv = dev->private;
020c44f3 1591 int i;
11e865c1 1592 uint16_t chan = CR_CHAN(insn->chanspec);
020c44f3 1593 int16_t dacdata;
11e865c1 1594
020c44f3
HS		 1595 for (i = 0; i < insn->n; i++) {
1596 dacdata = (int16_t) data[i];
1597 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
1598 dacdata -= (0x1fff);
11e865c1 1599
020c44f3
HS		 1600 SetDAC(dev, chan, dacdata);
1601 }
11e865c1 1602
020c44f3
HS		 1603 return i;
1604}
11e865c1 1605
020c44f3
HS		 1606static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1607 struct comedi_insn *insn, unsigned int *data)
1608{
7f2f7e05 1609 struct s626_private *devpriv = dev->private;
020c44f3 1610 int i;
11e865c1 1611
020c44f3
HS		 1612 for (i = 0; i < insn->n; i++)
1613 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
11e865c1 1614
020c44f3
HS		 1615 return i;
1616}
11e865c1 1617
020c44f3
HS		 1618/* *************** DIGITAL I/O FUNCTIONS ***************
1619 * All DIO functions address a group of DIO channels by means of
1620 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
1621 * ports A, B and C, respectively.
1622 */
11e865c1 1623
020c44f3
HS		 1624static void s626_dio_init(struct comedi_device *dev)
1625{
1626 uint16_t group;
11e865c1 1627
020c44f3
HS		 1628 /* Prepare to treat writes to WRCapSel as capture disables. */
1629 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
11e865c1 1630
020c44f3
HS		 1631 /* For each group of sixteen channels ... */
1632 for (group = 0; group < S626_DIO_BANKS; group++) {
100b4edc
HS		 1633 /* Disable all interrupts */
1634 DEBIwrite(dev, LP_WRINTSEL(group), 0);
1635 /* Disable all event captures */
1636 DEBIwrite(dev, LP_WRCAPSEL(group), 0xffff);
1637 /* Init all DIOs to default edge polarity */
1638 DEBIwrite(dev, LP_WREDGSEL(group), 0);
1639 /* Program all outputs to inactive state */
1640 DEBIwrite(dev, LP_WRDOUT(group), 0);
11e865c1 1641 }
020c44f3 1642}
11e865c1 1643
020c44f3
HS		 1644static int s626_dio_insn_bits(struct comedi_device *dev,
1645 struct comedi_subdevice *s,
1515e522
HS		 1646 struct comedi_insn *insn,
1647 unsigned int *data)
020c44f3 1648{
100b4edc 1649 unsigned long group = (unsigned long)s->private;
1515e522
HS		 1650 unsigned long mask = data[0];
1651 unsigned long bits = data[1];
100b4edc 1652
1515e522
HS		 1653 if (mask) {
1654 /* Check if requested channels are configured for output */
1655 if ((s->io_bits & mask) != mask)
020c44f3 1656 return -EIO;
11e865c1 1657
1515e522
HS		 1658 s->state &= ~mask;
1659 s->state |= (bits & mask);
11e865c1 1660
100b4edc 1661 DEBIwrite(dev, LP_WRDOUT(group), s->state);
020c44f3 1662 }
100b4edc 1663 data[1] = DEBIread(dev, LP_RDDIN(group));
11e865c1 1664
020c44f3 1665 return insn->n;
11e865c1
GP		 1666}
1667
020c44f3
HS		 1668static int s626_dio_insn_config(struct comedi_device *dev,
1669 struct comedi_subdevice *s,
e920fad2
HS		 1670 struct comedi_insn *insn,
1671 unsigned int *data)
11e865c1 1672{
100b4edc 1673 unsigned long group = (unsigned long)s->private;
e920fad2
HS		 1674 unsigned int chan = CR_CHAN(insn->chanspec);
1675 unsigned int mask = 1 << chan;
11e865c1 1676
020c44f3
HS		 1677 switch (data[0]) {
1678 case INSN_CONFIG_DIO_QUERY:
e920fad2 1679 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
020c44f3
HS		 1680 return insn->n;
1681 break;
1682 case COMEDI_INPUT:
e920fad2 1683 s->io_bits &= ~mask;
020c44f3
HS		 1684 break;
1685 case COMEDI_OUTPUT:
e920fad2 1686 s->io_bits |= mask;
020c44f3
HS		 1687 break;
1688 default:
1689 return -EINVAL;
1690 break;
11e865c1 1691 }
100b4edc 1692 DEBIwrite(dev, LP_WRDOUT(group), s->io_bits);
11e865c1 1693
e920fad2 1694 return insn->n;
11e865c1
GP		 1695}
1696
020c44f3
HS		 1697/* Now this function initializes the value of the counter (data[0])
1698 and set the subdevice. To complete with trigger and interrupt
1699 configuration */
affdc230
IA		 1700/* FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
1701 * what is being configured, but this function appears to be using data[0]
1702 * as a variable. */
020c44f3
HS		 1703static int s626_enc_insn_config(struct comedi_device *dev,
1704 struct comedi_subdevice *s,
1705 struct comedi_insn *insn, unsigned int *data)
1706{
1707 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
1708 /* index. */
1709 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
1710 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
1711 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
1712 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
1713 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
1714 (CLKENAB_INDEX << BF_CLKENAB);
1715 /* uint16_t DisableIntSrc=TRUE; */
1716 /* uint32_t Preloadvalue; //Counter initial value */
1717 uint16_t valueSrclatch = LATCHSRC_AB_READ;
1718 uint16_t enab = CLKENAB_ALWAYS;
1719 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1 1720
020c44f3 1721 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
11e865c1 1722
020c44f3 1723 k->SetMode(dev, k, Setup, TRUE);
b655c2c4 1724 Preload(dev, k, data[0]);
020c44f3
HS		 1725 k->PulseIndex(dev, k);
1726 SetLatchSource(dev, k, valueSrclatch);
1727 k->SetEnable(dev, k, (uint16_t) (enab != 0));
11e865c1 1728
020c44f3
HS		 1729 return insn->n;
1730}
11e865c1 1731
020c44f3
HS		 1732static int s626_enc_insn_read(struct comedi_device *dev,
1733 struct comedi_subdevice *s,
1734 struct comedi_insn *insn, unsigned int *data)
1735{
11e865c1 1736
020c44f3
HS		 1737 int n;
1738 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1 1739
020c44f3
HS		 1740 for (n = 0; n < insn->n; n++)
1741 data[n] = ReadLatch(dev, k);
11e865c1 1742
020c44f3
HS		 1743 return n;
1744}
11e865c1 1745
020c44f3
HS		 1746static int s626_enc_insn_write(struct comedi_device *dev,
1747 struct comedi_subdevice *s,
1748 struct comedi_insn *insn, unsigned int *data)
1749{
11e865c1 1750
020c44f3 1751 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1 1752
020c44f3
HS		 1753 /* Set the preload register */
1754 Preload(dev, k, data[0]);
11e865c1 1755
020c44f3
HS		 1756 /* Software index pulse forces the preload register to load */
1757 /* into the counter */
1758 k->SetLoadTrig(dev, k, 0);
1759 k->PulseIndex(dev, k);
1760 k->SetLoadTrig(dev, k, 2);
11e865c1 1761
020c44f3 1762 return 1;
11e865c1
GP		 1763}
1764
020c44f3 1765static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
11e865c1 1766{
020c44f3
HS		 1767 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
1768 /* MISC2 register. */
1769 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
1770 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
1771}
11e865c1 1772
020c44f3
HS		 1773static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
1774 size_t bsize)
1775{
f574af6d 1776 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
020c44f3
HS		 1777 void *vbptr;
1778 dma_addr_t vpptr;
11e865c1 1779
020c44f3
HS		 1780 if (pdma == NULL)
1781 return;
1782 /* find the matching allocation from the board struct */
11e865c1 1783
020c44f3
HS		 1784 vbptr = pdma->LogicalBase;
1785 vpptr = pdma->PhysicalBase;
1786 if (vbptr) {
f574af6d 1787 pci_free_consistent(pcidev, bsize, vbptr, vpptr);
020c44f3
HS		 1788 pdma->LogicalBase = NULL;
1789 pdma->PhysicalBase = 0;
020c44f3 1790 }
11e865c1
GP		 1791}
1792
020c44f3
HS		 1793/* ****** PRIVATE COUNTER FUNCTIONS ****** */
1794
020c44f3 1795/* Reset a counter's index and overflow event capture flags. */
11e865c1 1796
020c44f3
HS		 1797static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k)
1798{
12f4e2f2 1799 DEBIreplace(dev, k->MyCRB, ~CRBMSK_INTCTRL,
020c44f3
HS		 1800 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
1801}
11e865c1 1802
020c44f3
HS		 1803static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k)
1804{
12f4e2f2 1805 DEBIreplace(dev, k->MyCRB, ~CRBMSK_INTCTRL,
020c44f3 1806 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
11e865c1
GP		 1807}
1808
020c44f3
HS		 1809/* Return counter setup in a format (COUNTER_SETUP) that is consistent */
1810/* for both A and B counters. */
11e865c1 1811
020c44f3
HS		 1812static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k)
1813{
1814 register uint16_t cra;
1815 register uint16_t crb;
1816 register uint16_t setup;
11e865c1 1817
020c44f3
HS		 1818 /* Fetch CRA and CRB register images. */
1819 cra = DEBIread(dev, k->MyCRA);
1820 crb = DEBIread(dev, k->MyCRB);
11e865c1 1821
020c44f3
HS		 1822 /* Populate the standardized counter setup bit fields. Note: */
1823 /* IndexSrc is restricted to ENC_X or IndxPol. */
1824 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
1825 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
1826 |((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
1827 |((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
1828 |((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
1829 |((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
11e865c1 1830
020c44f3
HS		 1831 /* Adjust mode-dependent parameters. */
1832 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
1833 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1834 |((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
1835 |(MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
11e865c1 1836
020c44f3
HS		 1837 else /* If Counter mode (ClkSrcA<1> == 0): */
1838 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
1839 |((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
1840 |(((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
1841 (MULT_X1 << STDBIT_CLKMULT) :
1842 ((cra >> (CRABIT_CLKMULT_A -
1843 STDBIT_CLKMULT)) & STDMSK_CLKMULT)));
1844
1845 /* Return adjusted counter setup. */
1846 return setup;
11e865c1
GP		 1847}
1848
020c44f3 1849static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k)
11e865c1 1850{
020c44f3
HS		 1851 register uint16_t cra;
1852 register uint16_t crb;
1853 register uint16_t setup;
11e865c1 1854
020c44f3
HS		 1855 /* Fetch CRA and CRB register images. */
1856 cra = DEBIread(dev, k->MyCRA);
1857 crb = DEBIread(dev, k->MyCRB);
11e865c1 1858
020c44f3
HS		 1859 /* Populate the standardized counter setup bit fields. Note: */
1860 /* IndexSrc is restricted to ENC_X or IndxPol. */
1861 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
1862 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
1863 |((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
1864 |((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
1865 |((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
1866 |((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
11e865c1 1867
020c44f3
HS		 1868 /* Adjust mode-dependent parameters. */
1869 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
1870 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
1871 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
1872 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
b6c77757 1873
020c44f3
HS		 1874 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
1875 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1876 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
1877 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
b6c77757 1878
020c44f3
HS		 1879 else /* If Counter mode (ClkSrcB<1> == 0): */
1880 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1881 |((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
1882 |((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
11e865c1 1883
020c44f3
HS		 1884 /* Return adjusted counter setup. */
1885 return setup;
b6c77757 1886}
11e865c1 1887
020c44f3
HS		 1888/*
1889 * Set the operating mode for the specified counter. The setup
1890 * parameter is treated as a COUNTER_SETUP data type. The following
1891 * parameters are programmable (all other parms are ignored): ClkMult,
1892 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
1893 */
11e865c1 1894
020c44f3
HS		 1895static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
1896 uint16_t Setup, uint16_t DisableIntSrc)
11e865c1 1897{
7f2f7e05 1898 struct s626_private *devpriv = dev->private;
020c44f3
HS		 1899 register uint16_t cra;
1900 register uint16_t crb;
1901 register uint16_t setup = Setup; /* Cache the Standard Setup. */
0a85b6f0 1902
020c44f3
HS		 1903 /* Initialize CRA and CRB images. */
1904 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
1905 |((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
0a85b6f0 1906
020c44f3
HS		 1907 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
1908 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
f10fe574 1909
020c44f3
HS		 1910 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
1911 if (!DisableIntSrc)
1912 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
1913 CRABIT_INTSRC_A));
11e865c1 1914
020c44f3
HS		 1915 /* Populate all mode-dependent attributes of CRA & CRB images. */
1916 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
1917 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
1918 /* (Extender valid only for B counters). */
11e865c1 1919
020c44f3
HS		 1920 case CLKSRC_TIMER: /* Timer Mode: */
1921 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
1922 |((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
1923 |(1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
1924 |(MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
1925 break;
11e865c1 1926
020c44f3
HS		 1927 default: /* Counter Mode: */
1928 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
1929 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
1930 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
1931 (MULT_X1 << CRABIT_CLKMULT_A) :
1932 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
1933 STDBIT_CLKMULT))));
1934 }
11e865c1 1935
020c44f3
HS		 1936 /* Force positive index polarity if IndxSrc is software-driven only, */
1937 /* otherwise pass it through. */
1938 if (~setup & STDMSK_INDXSRC)
1939 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
1940 STDBIT_INDXPOL));
11e865c1 1941
020c44f3
HS		 1942 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
1943 /* enable mask to indicate the counter interrupt is disabled. */
1944 if (DisableIntSrc)
1945 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
11e865c1 1946
020c44f3
HS		 1947 /* While retaining CounterB and LatchSrc configurations, program the */
1948 /* new counter operating mode. */
1949 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
12f4e2f2 1950 DEBIreplace(dev, k->MyCRB, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A), crb);
11e865c1
GP		 1951}
1952
020c44f3
HS		 1953static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
1954 uint16_t Setup, uint16_t DisableIntSrc)
11e865c1 1955{
7f2f7e05 1956 struct s626_private *devpriv = dev->private;
020c44f3
HS		 1957 register uint16_t cra;
1958 register uint16_t crb;
1959 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 1960
020c44f3
HS		 1961 /* Initialize CRA and CRB images. */
1962 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
1963
1964 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
1965 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
1966 |((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
1967
1968 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
1969 if (!DisableIntSrc)
1970 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
1971 CRBBIT_INTSRC_B));
1972
1973 /* Populate all mode-dependent attributes of CRA & CRB images. */
1974 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
1975 case CLKSRC_TIMER: /* Timer Mode: */
1976 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
1977 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
1978 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
1979 |(MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
1980 break;
11e865c1 1981
020c44f3
HS		 1982 case CLKSRC_EXTENDER: /* Extender Mode: */
1983 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
1984 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
1985 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
1986 |(MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
1987 break;
11e865c1 1988
020c44f3
HS		 1989 default: /* Counter Mode: */
1990 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
1991 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
1992 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
1993 (MULT_X1 << CRBBIT_CLKMULT_B) :
1994 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
1995 STDBIT_CLKMULT))));
1996 }
b6c77757 1997
020c44f3
HS		 1998 /* Force positive index polarity if IndxSrc is software-driven only, */
1999 /* otherwise pass it through. */
2000 if (~setup & STDMSK_INDXSRC)
2001 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
2002 CRBBIT_INDXPOL_B));
b6c77757 2003
020c44f3
HS		 2004 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2005 /* enable mask to indicate the counter interrupt is disabled. */
2006 if (DisableIntSrc)
2007 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
11e865c1 2008
020c44f3
HS		 2009 /* While retaining CounterA and LatchSrc configurations, program the */
2010 /* new counter operating mode. */
12f4e2f2 2011 DEBIreplace(dev, k->MyCRA, ~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B), cra);
020c44f3 2012 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
11e865c1
GP		 2013}
2014
020c44f3 2015/* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
11e865c1 2016
020c44f3
HS		 2017static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
2018 uint16_t enab)
11e865c1 2019{
12f4e2f2
HS		 2020 DEBIreplace(dev, k->MyCRB, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A),
2021 enab << CRBBIT_CLKENAB_A);
020c44f3 2022}
11e865c1 2023
020c44f3
HS		 2024static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
2025 uint16_t enab)
2026{
12f4e2f2
HS		 2027 DEBIreplace(dev, k->MyCRB, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B),
2028 enab << CRBBIT_CLKENAB_B);
020c44f3 2029}
11e865c1 2030
020c44f3
HS		 2031static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k)
2032{
2033 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
2034}
11e865c1 2035
020c44f3
HS		 2036static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k)
2037{
2038 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
2039}
11e865c1 2040
020c44f3
HS		 2041/*
2042 * static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k )
2043 * {
2044 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
2045 * }
2046 */
11e865c1 2047
020c44f3
HS		 2048/*
2049 * Return/set the event that will trigger transfer of the preload
2050 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
2051 * 2=OverflowA (B counters only), 3=disabled.
2052 */
11e865c1 2053
020c44f3
HS		 2054static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
2055 uint16_t Trig)
2056{
12f4e2f2
HS		 2057 DEBIreplace(dev, k->MyCRA, ~CRAMSK_LOADSRC_A,
2058 Trig << CRABIT_LOADSRC_A);
020c44f3 2059}
11e865c1 2060
020c44f3
HS		 2061static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
2062 uint16_t Trig)
2063{
12f4e2f2
HS		 2064 DEBIreplace(dev, k->MyCRB, ~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL),
2065 Trig << CRBBIT_LOADSRC_B);
020c44f3 2066}
11e865c1 2067
020c44f3
HS		 2068static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k)
2069{
2070 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
2071}
11e865c1 2072
020c44f3
HS		 2073static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k)
2074{
2075 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
2076}
11e865c1 2077
020c44f3
HS		 2078/* Return/set counter interrupt source and clear any captured
2079 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
2080 * 2=IndexOnly, 3=IndexAndOverflow.
2081 */
b6c77757 2082
020c44f3
HS		 2083static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
2084 uint16_t IntSource)
2085{
7f2f7e05
HS		 2086 struct s626_private *devpriv = dev->private;
2087
020c44f3 2088 /* Reset any pending counter overflow or index captures. */
12f4e2f2 2089 DEBIreplace(dev, k->MyCRB, ~CRBMSK_INTCTRL,
020c44f3 2090 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
11e865c1 2091
020c44f3
HS		 2092 /* Program counter interrupt source. */
2093 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
12f4e2f2 2094 IntSource << CRABIT_INTSRC_A);
020c44f3
HS		 2095
2096 /* Update MISC2 interrupt enable mask. */
2097 devpriv->CounterIntEnabs =
2098 (devpriv->CounterIntEnabs & ~k->
2099 MyEventBits[3]) | k->MyEventBits[IntSource];
11e865c1
GP		 2100}
2101
020c44f3
HS		 2102static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
2103 uint16_t IntSource)
11e865c1 2104{
7f2f7e05 2105 struct s626_private *devpriv = dev->private;
020c44f3
HS		 2106 uint16_t crb;
2107
2108 /* Cache writeable CRB register image. */
2109 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
2110
2111 /* Reset any pending counter overflow or index captures. */
2112 DEBIwrite(dev, k->MyCRB,
2113 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
2114
2115 /* Program counter interrupt source. */
2116 DEBIwrite(dev, k->MyCRB,
2117 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
2118 CRBBIT_INTSRC_B)));
2119
2120 /* Update MISC2 interrupt enable mask. */
2121 devpriv->CounterIntEnabs =
2122 (devpriv->CounterIntEnabs & ~k->
2123 MyEventBits[3]) | k->MyEventBits[IntSource];
11e865c1
GP		 2124}
2125
020c44f3
HS		 2126static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k)
2127{
2128 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
2129}
11e865c1 2130
020c44f3 2131static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k)
11e865c1 2132{
020c44f3
HS		 2133 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
2134}
11e865c1 2135
020c44f3 2136/* Return/set the clock multiplier. */
11e865c1 2137
020c44f3
HS		 2138/* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2139/* { */
2140/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
2141/* } */
11e865c1 2142
020c44f3
HS		 2143/* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) */
2144/* { */
2145/* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
2146/* } */
11e865c1 2147
020c44f3 2148/* Return/set the clock polarity. */
11e865c1 2149
020c44f3
HS		 2150/* static void SetClkPol( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
2151/* { */
2152/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
2153/* } */
11e865c1 2154
020c44f3
HS		 2155/* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) */
2156/* { */
2157/* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
2158/* } */
11e865c1 2159
020c44f3 2160/* Return/set the clock source. */
11e865c1 2161
020c44f3
HS		 2162/* static void SetClkSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
2163/* { */
2164/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
2165/* } */
11e865c1 2166
020c44f3
HS		 2167/* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ) */
2168/* { */
2169/* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
2170/* } */
11e865c1 2171
020c44f3 2172/* Return/set the index polarity. */
11e865c1 2173
020c44f3
HS		 2174/* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2175/* { */
2176/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
2177/* } */
11e865c1 2178
020c44f3
HS		 2179/* static uint16_t GetIndexPol(struct comedi_device *dev, struct enc_private *k ) */
2180/* { */
2181/* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
2182/* } */
11e865c1 2183
020c44f3 2184/* Return/set the index source. */
11e865c1 2185
020c44f3
HS		 2186/* static void SetIndexSrc(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2187/* { */
020c44f3
HS		 2188/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
2189/* } */
11e865c1 2190
020c44f3
HS		 2191/* static uint16_t GetIndexSrc(struct comedi_device *dev, struct enc_private *k ) */
2192/* { */
2193/* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
2194/* } */
11e865c1 2195
020c44f3 2196/* Generate an index pulse. */
11e865c1 2197
020c44f3
HS		 2198static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k)
2199{
2200 register uint16_t cra;
11e865c1 2201
020c44f3
HS		 2202 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
2203 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
020c44f3 2204 DEBIwrite(dev, k->MyCRA, cra);
11e865c1
GP		 2205}
2206
020c44f3
HS		 2207static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k)
2208{
2209 register uint16_t crb;
11e865c1 2210
020c44f3
HS		 2211 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
2212 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
2213 DEBIwrite(dev, k->MyCRB, crb);
2214}
11e865c1 2215
878cf954
HS		 2216static struct enc_private enc_private_data[] = {
2217 {
2218 .GetEnable = GetEnable_A,
2219 .GetIntSrc = GetIntSrc_A,
2220 .GetLoadTrig = GetLoadTrig_A,
2221 .GetMode = GetMode_A,
2222 .PulseIndex = PulseIndex_A,
2223 .SetEnable = SetEnable_A,
2224 .SetIntSrc = SetIntSrc_A,
2225 .SetLoadTrig = SetLoadTrig_A,
2226 .SetMode = SetMode_A,
2227 .ResetCapFlags = ResetCapFlags_A,
2228 .MyCRA = LP_CR0A,
2229 .MyCRB = LP_CR0B,
2230 .MyLatchLsw = LP_CNTR0ALSW,
2231 .MyEventBits = EVBITS(0),
2232 }, {
2233 .GetEnable = GetEnable_A,
2234 .GetIntSrc = GetIntSrc_A,
2235 .GetLoadTrig = GetLoadTrig_A,
2236 .GetMode = GetMode_A,
2237 .PulseIndex = PulseIndex_A,
2238 .SetEnable = SetEnable_A,
2239 .SetIntSrc = SetIntSrc_A,
2240 .SetLoadTrig = SetLoadTrig_A,
2241 .SetMode = SetMode_A,
2242 .ResetCapFlags = ResetCapFlags_A,
2243 .MyCRA = LP_CR1A,
2244 .MyCRB = LP_CR1B,
2245 .MyLatchLsw = LP_CNTR1ALSW,
2246 .MyEventBits = EVBITS(1),
2247 }, {
2248 .GetEnable = GetEnable_A,
2249 .GetIntSrc = GetIntSrc_A,
2250 .GetLoadTrig = GetLoadTrig_A,
2251 .GetMode = GetMode_A,
2252 .PulseIndex = PulseIndex_A,
2253 .SetEnable = SetEnable_A,
2254 .SetIntSrc = SetIntSrc_A,
2255 .SetLoadTrig = SetLoadTrig_A,
2256 .SetMode = SetMode_A,
2257 .ResetCapFlags = ResetCapFlags_A,
2258 .MyCRA = LP_CR2A,
2259 .MyCRB = LP_CR2B,
2260 .MyLatchLsw = LP_CNTR2ALSW,
2261 .MyEventBits = EVBITS(2),
2262 }, {
2263 .GetEnable = GetEnable_B,
2264 .GetIntSrc = GetIntSrc_B,
2265 .GetLoadTrig = GetLoadTrig_B,
2266 .GetMode = GetMode_B,
2267 .PulseIndex = PulseIndex_B,
2268 .SetEnable = SetEnable_B,
2269 .SetIntSrc = SetIntSrc_B,
2270 .SetLoadTrig = SetLoadTrig_B,
2271 .SetMode = SetMode_B,
2272 .ResetCapFlags = ResetCapFlags_B,
2273 .MyCRA = LP_CR0A,
2274 .MyCRB = LP_CR0B,
2275 .MyLatchLsw = LP_CNTR0BLSW,
2276 .MyEventBits = EVBITS(3),
2277 }, {
2278 .GetEnable = GetEnable_B,
2279 .GetIntSrc = GetIntSrc_B,
2280 .GetLoadTrig = GetLoadTrig_B,
2281 .GetMode = GetMode_B,
2282 .PulseIndex = PulseIndex_B,
2283 .SetEnable = SetEnable_B,
2284 .SetIntSrc = SetIntSrc_B,
2285 .SetLoadTrig = SetLoadTrig_B,
2286 .SetMode = SetMode_B,
2287 .ResetCapFlags = ResetCapFlags_B,
2288 .MyCRA = LP_CR1A,
2289 .MyCRB = LP_CR1B,
2290 .MyLatchLsw = LP_CNTR1BLSW,
2291 .MyEventBits = EVBITS(4),
2292 }, {
2293 .GetEnable = GetEnable_B,
2294 .GetIntSrc = GetIntSrc_B,
2295 .GetLoadTrig = GetLoadTrig_B,
2296 .GetMode = GetMode_B,
2297 .PulseIndex = PulseIndex_B,
2298 .SetEnable = SetEnable_B,
2299 .SetIntSrc = SetIntSrc_B,
2300 .SetLoadTrig = SetLoadTrig_B,
2301 .SetMode = SetMode_B,
2302 .ResetCapFlags = ResetCapFlags_B,
2303 .MyCRA = LP_CR2A,
2304 .MyCRB = LP_CR2B,
2305 .MyLatchLsw = LP_CNTR2BLSW,
2306 .MyEventBits = EVBITS(5),
2307 },
2308};
2309
020c44f3 2310static void CountersInit(struct comedi_device *dev)
11e865c1 2311{
020c44f3
HS		 2312 int chan;
2313 struct enc_private *k;
2314 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2315 /* index. */
2316 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2317 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
2318 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2319 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
2320 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2321 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
11e865c1 2322
020c44f3
HS		 2323 /* Disable all counter interrupts and clear any captured counter events. */
2324 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2325 k = &encpriv[chan];
2326 k->SetMode(dev, k, Setup, TRUE);
2327 k->SetIntSrc(dev, k, 0);
2328 k->ResetCapFlags(dev, k);
2329 k->SetEnable(dev, k, CLKENAB_ALWAYS);
2330 }
020c44f3 2331}
11e865c1 2332
b7047895
HS		 2333static int s626_allocate_dma_buffers(struct comedi_device *dev)
2334{
2335 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
7f2f7e05 2336 struct s626_private *devpriv = dev->private;
b7047895
HS		 2337 void *addr;
2338 dma_addr_t appdma;
2339
b7047895
HS		 2340 addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2341 if (!addr)
2342 return -ENOMEM;
2343 devpriv->ANABuf.LogicalBase = addr;
2344 devpriv->ANABuf.PhysicalBase = appdma;
2345
b7047895
HS		 2346 addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2347 if (!addr)
2348 return -ENOMEM;
2349 devpriv->RPSBuf.LogicalBase = addr;
2350 devpriv->RPSBuf.PhysicalBase = appdma;
2351
b7047895
HS		 2352 return 0;
2353}
2354
80ec9510 2355static void s626_initialize(struct comedi_device *dev)
020c44f3 2356{
7f2f7e05 2357 struct s626_private *devpriv = dev->private;
68ad0ae0
HS		 2358 dma_addr_t pPhysBuf;
2359 uint16_t chan;
020c44f3 2360 int i;
11e865c1 2361
54a2a02e 2362 /* Enable DEBI and audio pins, enable I2C interface */
ddd9813e 2363 s626_mc_enable(dev, MC1_DEBI | MC1_AUDIO | MC1_I2C, P_MC1);
54a2a02e
HS		 2364
2365 /*
2366 * Configure DEBI operating mode
2367 *
2368 * Local bus is 16 bits wide
2369 * Declare DEBI transfer timeout interval
2370 * Set up byte lane steering
2371 * Intel-compatible local bus (DEBI never times out)
2372 */
25f8fd5e
HS		 2373 writel(DEBI_CFG_SLAVE16 |
2374 (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
2375 DEBI_SWAP | DEBI_CFG_INTEL,
7d856da2 2376 devpriv->mmio + P_DEBICFG);
54a2a02e
HS		 2377
2378 /* Disable MMU paging */
7d856da2 2379 writel(DEBI_PAGE_DISABLE, devpriv->mmio + P_DEBIPAGE);
54a2a02e
HS		 2380
2381 /* Init GPIO so that ADC Start* is negated */
7d856da2 2382 writel(GPIO_BASE | GPIO1_HI, devpriv->mmio + P_GPIO);
68ad0ae0 2383
17553c88
HS		 2384 /* I2C device address for onboard eeprom (revb) */
2385 devpriv->I2CAdrs = 0xA0;
11e865c1 2386
54a2a02e
HS		 2387 /*
2388 * Issue an I2C ABORT command to halt any I2C
2389 * operation in progress and reset BUSY flag.
2390 */
7d856da2 2391 writel(I2C_CLKSEL | I2C_ABORT, devpriv->mmio + P_I2CSTAT);
ddd9813e 2392 s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
7d856da2 2393 while (!(readl(devpriv->mmio + P_MC2) & MC2_UPLD_IIC))
68ad0ae0 2394 ;
68ad0ae0 2395
54a2a02e
HS		 2396 /*
2397 * Per SAA7146 data sheet, write to STATUS
2398 * reg twice to reset all I2C error flags.
2399 */
68ad0ae0 2400 for (i = 0; i < 2; i++) {
7d856da2 2401 writel(I2C_CLKSEL, devpriv->mmio + P_I2CSTAT);
ddd9813e 2402 s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
95bb7982 2403 while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
020c44f3 2404 ;
68ad0ae0 2405 }
11e865c1 2406
54a2a02e
HS		 2407 /*
2408 * Init audio interface functional attributes: set DAC/ADC
68ad0ae0
HS		 2409 * serial clock rates, invert DAC serial clock so that
2410 * DAC data setup times are satisfied, enable DAC serial
2411 * clock out.
2412 */
7d856da2 2413 writel(ACON2_INIT, devpriv->mmio + P_ACON2);
11e865c1 2414
54a2a02e
HS		 2415 /*
2416 * Set up TSL1 slot list, which is used to control the
68ad0ae0 2417 * accumulation of ADC data: RSD1 = shift data in on SD1.
54a2a02e
HS		 2418 * SIB_A1 = store data uint8_t at next available location
2419 * in FB BUFFER1 register.
2420 */
7d856da2
HS		 2421 writel(RSD1 | SIB_A1, devpriv->mmio + P_TSL1);
2422 writel(RSD1 | SIB_A1 | EOS, devpriv->mmio + P_TSL1 + 4);
11e865c1 2423
54a2a02e 2424 /* Enable TSL1 slot list so that it executes all the time */
7d856da2 2425 writel(ACON1_ADCSTART, devpriv->mmio + P_ACON1);
11e865c1 2426
54a2a02e
HS		 2427 /*
2428 * Initialize RPS registers used for ADC
2429 */
11e865c1 2430
54a2a02e 2431 /* Physical start of RPS program */
25f8fd5e 2432 writel((uint32_t)devpriv->RPSBuf.PhysicalBase,
7d856da2 2433 devpriv->mmio + P_RPSADDR1);
54a2a02e 2434 /* RPS program performs no explicit mem writes */
7d856da2 2435 writel(0, devpriv->mmio + P_RPSPAGE1);
54a2a02e 2436 /* Disable RPS timeouts */
7d856da2 2437 writel(0, devpriv->mmio + P_RPS1_TOUT);
11e865c1 2438
59747847
HS		 2439#if 0
2440 /*
2441 * SAA7146 BUG WORKAROUND
2442 *
2443 * Initialize SAA7146 ADC interface to a known state by
2444 * invoking ADCs until FB BUFFER 1 register shows that it
2445 * is correctly receiving ADC data. This is necessary
2446 * because the SAA7146 ADC interface does not start up in
2447 * a defined state after a PCI reset.
68ad0ae0 2448 */
11e865c1 2449
59747847
HS		 2450 {
2451 uint8_t PollList;
2452 uint16_t AdcData;
2453 uint16_t StartVal;
2454 uint16_t index;
2455 unsigned int data[16];
2456
2457 /* Create a simple polling list for analog input channel 0 */
2458 PollList = EOPL;
2459 ResetADC(dev, &PollList);
2460
2461 /* Get initial ADC value */
2462 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2463 StartVal = data[0];
2464
2465 /*
2466 * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION.
2467 *
2468 * Invoke ADCs until the new ADC value differs from the initial
2469 * value or a timeout occurs. The timeout protects against the
2470 * possibility that the driver is restarting and the ADC data is a
2471 * fixed value resulting from the applied ADC analog input being
2472 * unusually quiet or at the rail.
2473 */
2474 for (index = 0; index < 500; index++) {
2475 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2476 AdcData = data[0];
2477 if (AdcData != StartVal)
2478 break;
2479 }
2480
2481 }
2482#endif /* SAA7146 BUG WORKAROUND */
11e865c1 2483
54a2a02e
HS		 2484 /*
2485 * Initialize the DAC interface
2486 */
11e865c1 2487
54a2a02e
HS		 2488 /*
2489 * Init Audio2's output DMAC attributes:
2490 * burst length = 1 DWORD
2491 * threshold = 1 DWORD.
68ad0ae0 2492 */
7d856da2 2493 writel(0, devpriv->mmio + P_PCI_BT_A);
68ad0ae0 2494
54a2a02e
HS		 2495 /*
2496 * Init Audio2's output DMA physical addresses. The protection
68ad0ae0
HS		 2497 * address is set to 1 DWORD past the base address so that a
2498 * single DWORD will be transferred each time a DMA transfer is
54a2a02e
HS		 2499 * enabled.
2500 */
68ad0ae0
HS		 2501 pPhysBuf = devpriv->ANABuf.PhysicalBase +
2502 (DAC_WDMABUF_OS * sizeof(uint32_t));
7d856da2 2503 writel((uint32_t)pPhysBuf, devpriv->mmio + P_BASEA2_OUT);
25f8fd5e 2504 writel((uint32_t)(pPhysBuf + sizeof(uint32_t)),
7d856da2 2505 devpriv->mmio + P_PROTA2_OUT);
68ad0ae0 2506
54a2a02e
HS		 2507 /*
2508 * Cache Audio2's output DMA buffer logical address. This is
2509 * where DAC data is buffered for A2 output DMA transfers.
2510 */
68ad0ae0
HS		 2511 devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase +
2512 DAC_WDMABUF_OS;
2513
54a2a02e
HS		 2514 /*
2515 * Audio2's output channels does not use paging. The
2516 * protection violation handling bit is set so that the
2517 * DMAC will automatically halt and its PCI address pointer
2518 * will be reset when the protection address is reached.
2519 */
7d856da2 2520 writel(8, devpriv->mmio + P_PAGEA2_OUT);
68ad0ae0 2521
54a2a02e
HS		 2522 /*
2523 * Initialize time slot list 2 (TSL2), which is used to control
68ad0ae0
HS		 2524 * the clock generation for and serialization of data to be sent
2525 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
2526 * execution; this permits other slots to be safely modified
2527 * without first turning off the TSL sequencer (which is
2528 * apparently impossible to do). Also, SD3 (which is driven by a
2529 * pull-up resistor) is shifted in and stored to the MSB of
2530 * FB_BUFFER2 to be used as evidence that the slot sequence has
2531 * not yet finished executing.
2532 */
11e865c1 2533
54a2a02e 2534 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
7d856da2 2535 writel(XSD2 | RSD3 | SIB_A2 | EOS, devpriv->mmio + VECTPORT(0));
11e865c1 2536
54a2a02e
HS		 2537 /*
2538 * Initialize slot 1, which is constant. Slot 1 causes a
68ad0ae0
HS		 2539 * DWORD to be transferred from audio channel 2's output FIFO
2540 * to the FIFO's output buffer so that it can be serialized
2541 * and sent to the DAC during subsequent slots. All remaining
2542 * slots are dynamically populated as required by the target
2543 * DAC device.
2544 */
54a2a02e
HS		 2545
2546 /* Slot 1: Fetch DWORD from Audio2's output FIFO */
7d856da2 2547 writel(LF_A2, devpriv->mmio + VECTPORT(1));
11e865c1 2548
54a2a02e 2549 /* Start DAC's audio interface (TSL2) running */
7d856da2 2550 writel(ACON1_DACSTART, devpriv->mmio + P_ACON1);
11e865c1 2551
54a2a02e
HS		 2552 /*
2553 * Init Trim DACs to calibrated values. Do it twice because the
68ad0ae0
HS		 2554 * SAA7146 audio channel does not always reset properly and
2555 * sometimes causes the first few TrimDAC writes to malfunction.
2556 */
68ad0ae0 2557 LoadTrimDACs(dev);
54a2a02e 2558 LoadTrimDACs(dev);
11e865c1 2559
54a2a02e
HS		 2560 /*
2561 * Manually init all gate array hardware in case this is a soft
68ad0ae0
HS		 2562 * reset (we have no way of determining whether this is a warm
2563 * or cold start). This is necessary because the gate array will
2564 * reset only in response to a PCI hard reset; there is no soft
54a2a02e
HS		 2565 * reset function.
2566 */
11e865c1 2567
54a2a02e
HS		 2568 /*
2569 * Init all DAC outputs to 0V and init all DAC setpoint and
68ad0ae0
HS		 2570 * polarity images.
2571 */
2572 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
2573 SetDAC(dev, chan, 0);
11e865c1 2574
54a2a02e 2575 /* Init counters */
68ad0ae0 2576 CountersInit(dev);
11e865c1 2577
54a2a02e
HS		 2578 /*
2579 * Without modifying the state of the Battery Backup enab, disable
68ad0ae0
HS		 2580 * the watchdog timer, set DIO channels 0-5 to operate in the
2581 * standard DIO (vs. counter overflow) mode, disable the battery
2582 * charger, and reset the watchdog interval selector to zero.
2583 */
2584 WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) &
2585 MISC2_BATT_ENABLE));
11e865c1 2586
54a2a02e 2587 /* Initialize the digital I/O subsystem */
68ad0ae0 2588 s626_dio_init(dev);
11e865c1 2589
68ad0ae0 2590 /* enable interrupt test */
7d856da2 2591 /* writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->mmio + P_IER); */
80ec9510
HS		 2592}
2593
a690b7e5 2594static int s626_auto_attach(struct comedi_device *dev,
750af5e5 2595 unsigned long context_unused)
80ec9510 2596{
750af5e5 2597 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
7f2f7e05 2598 struct s626_private *devpriv;
80ec9510
HS		 2599 struct comedi_subdevice *s;
2600 int ret;
2601
80ec9510
HS		 2602 dev->board_name = dev->driver->driver_name;
2603
c34fa261
HS		 2604 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
2605 if (!devpriv)
2606 return -ENOMEM;
2607 dev->private = devpriv;
80ec9510 2608
818f569f 2609 ret = comedi_pci_enable(dev);
80ec9510
HS		 2610 if (ret)
2611 return ret;
80ec9510 2612
7d856da2
HS		 2613 devpriv->mmio = ioremap(pci_resource_start(pcidev, 0),
2614 pci_resource_len(pcidev, 0));
2615 if (!devpriv->mmio)
80ec9510
HS		 2616 return -ENOMEM;
2617
2618 /* disable master interrupt */
7d856da2 2619 writel(0, devpriv->mmio + P_IER);
80ec9510
HS		 2620
2621 /* soft reset */
7d856da2 2622 writel(MC1_SOFT_RESET, devpriv->mmio + P_MC1);
80ec9510
HS		 2623
2624 /* DMA FIXME DMA// */
2625
2626 ret = s626_allocate_dma_buffers(dev);
2627 if (ret)
2628 return ret;
2629
2630 if (pcidev->irq) {
2631 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2632 dev->board_name, dev);
2633
2634 if (ret == 0)
2635 dev->irq = pcidev->irq;
2636 }
2637
2638 ret = comedi_alloc_subdevices(dev, 6);
2639 if (ret)
2640 return ret;
2641
f0717f5d 2642 s = &dev->subdevices[0];
80ec9510
HS		 2643 /* analog input subdevice */
2644 dev->read_subdev = s;
ca2f1091
HS		 2645 s->type = COMEDI_SUBD_AI;
2646 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
2647 s->n_chan = S626_ADC_CHANNELS;
2648 s->maxdata = 0x3fff;
2649 s->range_table = &s626_range_table;
2650 s->len_chanlist = S626_ADC_CHANNELS;
ca2f1091
HS		 2651 s->insn_read = s626_ai_insn_read;
2652 s->do_cmd = s626_ai_cmd;
2653 s->do_cmdtest = s626_ai_cmdtest;
2654 s->cancel = s626_ai_cancel;
80ec9510 2655
f0717f5d 2656 s = &dev->subdevices[1];
80ec9510 2657 /* analog output subdevice */
ca2f1091
HS		 2658 s->type = COMEDI_SUBD_AO;
2659 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2660 s->n_chan = S626_DAC_CHANNELS;
2661 s->maxdata = 0x3fff;
2662 s->range_table = &range_bipolar10;
2663 s->insn_write = s626_ao_winsn;
2664 s->insn_read = s626_ao_rinsn;
80ec9510 2665
f0717f5d 2666 s = &dev->subdevices[2];
80ec9510 2667 /* digital I/O subdevice */
ca2f1091
HS		 2668 s->type = COMEDI_SUBD_DIO;
2669 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2670 s->n_chan = 16;
2671 s->maxdata = 1;
2672 s->io_bits = 0xffff;
2673 s->private = (void *)0; /* DIO group 0 */
2674 s->range_table = &range_digital;
2675 s->insn_config = s626_dio_insn_config;
2676 s->insn_bits = s626_dio_insn_bits;
80ec9510 2677
f0717f5d 2678 s = &dev->subdevices[3];
80ec9510 2679 /* digital I/O subdevice */
ca2f1091
HS		 2680 s->type = COMEDI_SUBD_DIO;
2681 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2682 s->n_chan = 16;
2683 s->maxdata = 1;
2684 s->io_bits = 0xffff;
2685 s->private = (void *)1; /* DIO group 1 */
2686 s->range_table = &range_digital;
2687 s->insn_config = s626_dio_insn_config;
2688 s->insn_bits = s626_dio_insn_bits;
80ec9510 2689
f0717f5d 2690 s = &dev->subdevices[4];
80ec9510 2691 /* digital I/O subdevice */
ca2f1091
HS		 2692 s->type = COMEDI_SUBD_DIO;
2693 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2694 s->n_chan = 16;
2695 s->maxdata = 1;
2696 s->io_bits = 0xffff;
2697 s->private = (void *)2; /* DIO group 2 */
2698 s->range_table = &range_digital;
2699 s->insn_config = s626_dio_insn_config;
2700 s->insn_bits = s626_dio_insn_bits;
80ec9510 2701
f0717f5d 2702 s = &dev->subdevices[5];
80ec9510 2703 /* encoder (counter) subdevice */
ca2f1091
HS		 2704 s->type = COMEDI_SUBD_COUNTER;
2705 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2706 s->n_chan = S626_ENCODER_CHANNELS;
2707 s->maxdata = 0xffffff;
2708 s->private = enc_private_data;
2709 s->range_table = &range_unknown;
2710 s->insn_config = s626_enc_insn_config;
2711 s->insn_read = s626_enc_insn_read;
2712 s->insn_write = s626_enc_insn_write;
80ec9510 2713
80ec9510 2714 s626_initialize(dev);
11e865c1 2715
f996ab29
HS		 2716 dev_info(dev->class_dev, "%s attached\n", dev->board_name);
2717
2718 return 0;
11e865c1
GP		 2719}
2720
020c44f3 2721static void s626_detach(struct comedi_device *dev)
11e865c1 2722{
7f2f7e05 2723 struct s626_private *devpriv = dev->private;
f574af6d 2724
020c44f3
HS		 2725 if (devpriv) {
2726 /* stop ai_command */
2727 devpriv->ai_cmd_running = 0;
11e865c1 2728
7d856da2 2729 if (devpriv->mmio) {
020c44f3 2730 /* interrupt mask */
25f8fd5e 2731 /* Disable master interrupt */
7d856da2 2732 writel(0, devpriv->mmio + P_IER);
25f8fd5e
HS		 2733 /* Clear board's IRQ status flag */
2734 writel(IRQ_GPIO3 | IRQ_RPS1,
7d856da2 2735 devpriv->mmio + P_ISR);
11e865c1 2736
020c44f3
HS		 2737 /* Disable the watchdog timer and battery charger. */
2738 WriteMISC2(dev, 0);
11e865c1 2739
25f8fd5e 2740 /* Close all interfaces on 7146 device */
7d856da2
HS		 2741 writel(MC1_SHUTDOWN, devpriv->mmio + P_MC1);
2742 writel(ACON1_BASE, devpriv->mmio + P_ACON1);
11e865c1 2743
020c44f3
HS		 2744 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
2745 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
2746 }
b6c77757 2747
020c44f3
HS		 2748 if (dev->irq)
2749 free_irq(dev->irq, dev);
7d856da2
HS		 2750 if (devpriv->mmio)
2751 iounmap(devpriv->mmio);
f574af6d 2752 }
7f072f54 2753 comedi_pci_disable(dev);
11e865c1 2754}
7122b76d 2755
75e6301b 2756static struct comedi_driver s626_driver = {
7122b76d
HS		 2757 .driver_name = "s626",
2758 .module = THIS_MODULE,
750af5e5 2759 .auto_attach = s626_auto_attach,
7122b76d
HS		 2760 .detach = s626_detach,
2761};
2762
a690b7e5 2763static int s626_pci_probe(struct pci_dev *dev,
b8f4ac23 2764 const struct pci_device_id *id)
7122b76d 2765{
b8f4ac23 2766 return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
7122b76d
HS		 2767}
2768
7122b76d
HS		 2769/*
2770 * For devices with vendor:device id == 0x1131:0x7146 you must specify
2771 * also subvendor:subdevice ids, because otherwise it will conflict with
2772 * Philips SAA7146 media/dvb based cards.
2773 */
2774static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
2775 { PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626,
2776 PCI_SUBVENDOR_ID_S626, PCI_SUBDEVICE_ID_S626, 0, 0, 0 },
2777 { 0 }
2778};
2779MODULE_DEVICE_TABLE(pci, s626_pci_table);
2780
75e6301b
HS		 2781static struct pci_driver s626_pci_driver = {
2782 .name = "s626",
7122b76d 2783 .id_table = s626_pci_table,
75e6301b 2784 .probe = s626_pci_probe,
9901a4d7 2785 .remove = comedi_pci_auto_unconfig,
7122b76d 2786};
75e6301b 2787module_comedi_pci_driver(s626_driver, s626_pci_driver);
7122b76d
HS		 2788
2789MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2790MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2791MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)