Commit | Line | Data |
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11e865c1 | 1 | /* |
7f32c7c4 IA |
2 | * comedi/drivers/s626.c |
3 | * Sensoray s626 Comedi driver | |
4 | * | |
5 | * COMEDI - Linux Control and Measurement Device Interface | |
6 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
7 | * | |
8 | * Based on Sensoray Model 626 Linux driver Version 0.2 | |
9 | * Copyright (C) 2002-2004 Sensoray Co., Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
11e865c1 GP |
21 | |
22 | /* | |
7f32c7c4 IA |
23 | * Driver: s626 |
24 | * Description: Sensoray 626 driver | |
25 | * Devices: [Sensoray] 626 (s626) | |
26 | * Authors: Gianluca Palli <gpalli@deis.unibo.it>, | |
27 | * Updated: Fri, 15 Feb 2008 10:28:42 +0000 | |
28 | * Status: experimental | |
29 | ||
30 | * Configuration options: not applicable, uses PCI auto config | |
31 | ||
32 | * INSN_CONFIG instructions: | |
33 | * analog input: | |
34 | * none | |
35 | * | |
36 | * analog output: | |
37 | * none | |
38 | * | |
39 | * digital channel: | |
40 | * s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels | |
41 | * supported configuration options: | |
42 | * INSN_CONFIG_DIO_QUERY | |
43 | * COMEDI_INPUT | |
44 | * COMEDI_OUTPUT | |
45 | * | |
46 | * encoder: | |
47 | * Every channel must be configured before reading. | |
48 | * | |
49 | * Example code | |
50 | * | |
51 | * insn.insn=INSN_CONFIG; //configuration instruction | |
52 | * insn.n=1; //number of operation (must be 1) | |
53 | * insn.data=&initialvalue; //initial value loaded into encoder | |
54 | * //during configuration | |
55 | * insn.subdev=5; //encoder subdevice | |
56 | * insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel | |
57 | * //to configure | |
58 | * | |
59 | * comedi_do_insn(cf,&insn); //executing configuration | |
60 | */ | |
11e865c1 | 61 | |
ce157f80 HS |
62 | #include <linux/module.h> |
63 | #include <linux/delay.h> | |
33782dd5 | 64 | #include <linux/pci.h> |
25436dc9 | 65 | #include <linux/interrupt.h> |
11e865c1 GP |
66 | #include <linux/kernel.h> |
67 | #include <linux/types.h> | |
68 | ||
69 | #include "../comedidev.h" | |
70 | ||
11e865c1 GP |
71 | #include "comedi_fc.h" |
72 | #include "s626.h" | |
73 | ||
dbb263f5 | 74 | struct s626_buffer_dma { |
8e06d662 IA |
75 | dma_addr_t physical_base; |
76 | void *logical_base; | |
77 | }; | |
78 | ||
eb5e029e | 79 | struct s626_private { |
7d856da2 | 80 | void __iomem *mmio; |
8ee52611 | 81 | uint8_t ai_cmd_running; /* ai_cmd is running */ |
e6132fc9 | 82 | uint8_t ai_continuous; /* continuous acquisition */ |
8ee52611 IA |
83 | int ai_sample_count; /* number of samples to acquire */ |
84 | unsigned int ai_sample_timer; /* time between samples in | |
85 | * units of the timer */ | |
86 | int ai_convert_count; /* conversion counter */ | |
87 | unsigned int ai_convert_timer; /* time between conversion in | |
88 | * units of the timer */ | |
07a36d66 | 89 | uint16_t counter_int_enabs; /* counter interrupt enable mask |
8ee52611 | 90 | * for MISC2 register */ |
07a36d66 | 91 | uint8_t adc_items; /* number of items in ADC poll list */ |
dbb263f5 | 92 | struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1) |
8ee52611 | 93 | * program */ |
dbb263f5 | 94 | struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data |
8ee52611 | 95 | * and hold DAC data */ |
07a36d66 | 96 | uint32_t *dac_wbuf; /* pointer to logical adrs of DMA buffer |
8ee52611 | 97 | * used to hold DAC data */ |
07a36d66 IA |
98 | uint16_t dacpol; /* image of DAC polarity register */ |
99 | uint8_t trim_setpoint[12]; /* images of TrimDAC setpoints */ | |
100 | uint32_t i2c_adrs; /* I2C device address for onboard EEPROM | |
8ee52611 | 101 | * (board rev dependent) */ |
790c5541 | 102 | unsigned int ao_readback[S626_DAC_CHANNELS]; |
eb5e029e | 103 | }; |
11e865c1 | 104 | |
8ee52611 | 105 | /* COUNTER OBJECT ------------------------------------------------ */ |
3a305a66 | 106 | struct s626_enc_info { |
8ee52611 IA |
107 | /* Pointers to functions that differ for A and B counters: */ |
108 | /* Return clock enable. */ | |
3a305a66 IA |
109 | uint16_t(*get_enable)(struct comedi_device *dev, |
110 | const struct s626_enc_info *k); | |
8ee52611 | 111 | /* Return interrupt source. */ |
b075ac8e | 112 | uint16_t(*get_int_src)(struct comedi_device *dev, |
3a305a66 | 113 | const struct s626_enc_info *k); |
8ee52611 | 114 | /* Return preload trigger source. */ |
b075ac8e | 115 | uint16_t(*get_load_trig)(struct comedi_device *dev, |
3a305a66 | 116 | const struct s626_enc_info *k); |
8ee52611 | 117 | /* Return standardized operating mode. */ |
3a305a66 IA |
118 | uint16_t(*get_mode)(struct comedi_device *dev, |
119 | const struct s626_enc_info *k); | |
8ee52611 | 120 | /* Generate soft index strobe. */ |
3a305a66 IA |
121 | void (*pulse_index)(struct comedi_device *dev, |
122 | const struct s626_enc_info *k); | |
8ee52611 | 123 | /* Program clock enable. */ |
3a305a66 IA |
124 | void (*set_enable)(struct comedi_device *dev, |
125 | const struct s626_enc_info *k, uint16_t enab); | |
8ee52611 | 126 | /* Program interrupt source. */ |
3a305a66 IA |
127 | void (*set_int_src)(struct comedi_device *dev, |
128 | const struct s626_enc_info *k, uint16_t int_source); | |
8ee52611 | 129 | /* Program preload trigger source. */ |
3a305a66 IA |
130 | void (*set_load_trig)(struct comedi_device *dev, |
131 | const struct s626_enc_info *k, uint16_t trig); | |
8ee52611 | 132 | /* Program standardized operating mode. */ |
3a305a66 IA |
133 | void (*set_mode)(struct comedi_device *dev, |
134 | const struct s626_enc_info *k, uint16_t setup, | |
135 | uint16_t disable_int_src); | |
8ee52611 | 136 | /* Reset event capture flags. */ |
b075ac8e | 137 | void (*reset_cap_flags)(struct comedi_device *dev, |
3a305a66 | 138 | const struct s626_enc_info *k); |
8ee52611 | 139 | |
b075ac8e IA |
140 | uint16_t my_cra; /* address of CRA register */ |
141 | uint16_t my_crb; /* address of CRB register */ | |
142 | uint16_t my_latch_lsw; /* address of Latch least-significant-word | |
8ee52611 | 143 | * register */ |
b075ac8e | 144 | uint16_t my_event_bits[4]; /* bit translations for IntSrc -->RDMISC2 */ |
eb5e029e | 145 | }; |
11e865c1 | 146 | |
8ee52611 | 147 | /* Counter overflow/index event flag masks for RDMISC2. */ |
676921c9 IA |
148 | #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4))) |
149 | #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10))) | |
150 | #define S626_EVBITS(C) { 0, S626_OVERMASK(C), S626_INDXMASK(C), \ | |
151 | S626_OVERMASK(C) | S626_INDXMASK(C) } | |
11e865c1 | 152 | |
8ee52611 IA |
153 | /* |
154 | * Translation table to map IntSrc into equivalent RDMISC2 event flag bits. | |
31de1948 | 155 | * static const uint16_t s626_event_bits[][4] = |
676921c9 IA |
156 | * { S626_EVBITS(0), S626_EVBITS(1), S626_EVBITS(2), S626_EVBITS(3), |
157 | * S626_EVBITS(4), S626_EVBITS(5) }; | |
8ee52611 | 158 | */ |
11e865c1 | 159 | |
ddd9813e HS |
160 | /* |
161 | * Enable/disable a function or test status bit(s) that are accessed | |
162 | * through Main Control Registers 1 or 2. | |
163 | */ | |
164 | static void s626_mc_enable(struct comedi_device *dev, | |
165 | unsigned int cmd, unsigned int reg) | |
166 | { | |
167 | struct s626_private *devpriv = dev->private; | |
168 | unsigned int val = (cmd << 16) | cmd; | |
169 | ||
bb49cddc | 170 | mmiowb(); |
7d856da2 | 171 | writel(val, devpriv->mmio + reg); |
ddd9813e | 172 | } |
11e865c1 | 173 | |
c5cf4606 HS |
174 | static void s626_mc_disable(struct comedi_device *dev, |
175 | unsigned int cmd, unsigned int reg) | |
176 | { | |
177 | struct s626_private *devpriv = dev->private; | |
178 | ||
7d856da2 | 179 | writel(cmd << 16 , devpriv->mmio + reg); |
bb49cddc | 180 | mmiowb(); |
c5cf4606 | 181 | } |
11e865c1 | 182 | |
95bb7982 HS |
183 | static bool s626_mc_test(struct comedi_device *dev, |
184 | unsigned int cmd, unsigned int reg) | |
185 | { | |
186 | struct s626_private *devpriv = dev->private; | |
187 | unsigned int val; | |
188 | ||
7d856da2 | 189 | val = readl(devpriv->mmio + reg); |
95bb7982 HS |
190 | |
191 | return (val & cmd) ? true : false; | |
192 | } | |
11e865c1 | 193 | |
676921c9 | 194 | #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4) |
11e865c1 | 195 | |
8ee52611 | 196 | /* Write a time slot control record to TSL2. */ |
d8515652 | 197 | #define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2)) |
11e865c1 | 198 | |
90d54ff2 HS |
199 | static const struct comedi_lrange s626_range_table = { |
200 | 2, { | |
201 | BIP_RANGE(5), | |
481ac510 | 202 | BIP_RANGE(10) |
90d54ff2 | 203 | } |
11e865c1 GP |
204 | }; |
205 | ||
8ee52611 IA |
206 | /* |
207 | * Execute a DEBI transfer. This must be called from within a critical section. | |
208 | */ | |
31de1948 | 209 | static void s626_debi_transfer(struct comedi_device *dev) |
6b387b70 | 210 | { |
7f2f7e05 HS |
211 | struct s626_private *devpriv = dev->private; |
212 | ||
ddd9813e | 213 | /* Initiate upload of shadow RAM to DEBI control register */ |
d8515652 | 214 | s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2); |
6b387b70 | 215 | |
95bb7982 HS |
216 | /* |
217 | * Wait for completion of upload from shadow RAM to | |
218 | * DEBI control register. | |
219 | */ | |
d8515652 | 220 | while (!s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2)) |
6b387b70 HS |
221 | ; |
222 | ||
be008602 | 223 | /* Wait until DEBI transfer is done */ |
d8515652 | 224 | while (readl(devpriv->mmio + S626_P_PSR) & S626_PSR_DEBI_S) |
6b387b70 HS |
225 | ; |
226 | } | |
227 | ||
8ee52611 IA |
228 | /* |
229 | * Read a value from a gate array register. | |
230 | */ | |
31de1948 | 231 | static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr) |
6b387b70 | 232 | { |
7f2f7e05 | 233 | struct s626_private *devpriv = dev->private; |
6b387b70 | 234 | |
25f8fd5e | 235 | /* Set up DEBI control register value in shadow RAM */ |
d8515652 | 236 | writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD); |
6b387b70 HS |
237 | |
238 | /* Execute the DEBI transfer. */ | |
31de1948 | 239 | s626_debi_transfer(dev); |
6b387b70 | 240 | |
d8515652 | 241 | return readl(devpriv->mmio + S626_P_DEBIAD); |
6b387b70 HS |
242 | } |
243 | ||
8ee52611 IA |
244 | /* |
245 | * Write a value to a gate array register. | |
246 | */ | |
31de1948 IA |
247 | static void s626_debi_write(struct comedi_device *dev, uint16_t addr, |
248 | uint16_t wdata) | |
6b387b70 | 249 | { |
7f2f7e05 | 250 | struct s626_private *devpriv = dev->private; |
6b387b70 | 251 | |
25f8fd5e | 252 | /* Set up DEBI control register value in shadow RAM */ |
d8515652 IA |
253 | writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD); |
254 | writel(wdata, devpriv->mmio + S626_P_DEBIAD); | |
6b387b70 HS |
255 | |
256 | /* Execute the DEBI transfer. */ | |
31de1948 | 257 | s626_debi_transfer(dev); |
6b387b70 HS |
258 | } |
259 | ||
8ee52611 IA |
260 | /* |
261 | * Replace the specified bits in a gate array register. Imports: mask | |
6b387b70 HS |
262 | * specifies bits that are to be preserved, wdata is new value to be |
263 | * or'd with the masked original. | |
264 | */ | |
31de1948 IA |
265 | static void s626_debi_replace(struct comedi_device *dev, unsigned int addr, |
266 | unsigned int mask, unsigned int wdata) | |
6b387b70 | 267 | { |
7f2f7e05 | 268 | struct s626_private *devpriv = dev->private; |
be008602 | 269 | unsigned int val; |
6b387b70 | 270 | |
12f4e2f2 | 271 | addr &= 0xffff; |
d8515652 | 272 | writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD); |
31de1948 | 273 | s626_debi_transfer(dev); |
6b387b70 | 274 | |
d8515652 IA |
275 | writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD); |
276 | val = readl(devpriv->mmio + S626_P_DEBIAD); | |
be008602 HS |
277 | val &= mask; |
278 | val |= wdata; | |
d8515652 | 279 | writel(val & 0xffff, devpriv->mmio + S626_P_DEBIAD); |
31de1948 | 280 | s626_debi_transfer(dev); |
6b387b70 HS |
281 | } |
282 | ||
982e3d11 HS |
283 | /* ************** EEPROM ACCESS FUNCTIONS ************** */ |
284 | ||
31de1948 | 285 | static uint32_t s626_i2c_handshake(struct comedi_device *dev, uint32_t val) |
982e3d11 | 286 | { |
7f2f7e05 | 287 | struct s626_private *devpriv = dev->private; |
be008602 | 288 | unsigned int ctrl; |
7f2f7e05 | 289 | |
25f8fd5e | 290 | /* Write I2C command to I2C Transfer Control shadow register */ |
d8515652 | 291 | writel(val, devpriv->mmio + S626_P_I2CCTRL); |
982e3d11 | 292 | |
ddd9813e HS |
293 | /* |
294 | * Upload I2C shadow registers into working registers and | |
295 | * wait for upload confirmation. | |
296 | */ | |
d8515652 IA |
297 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
298 | while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2)) | |
982e3d11 HS |
299 | ; |
300 | ||
be008602 HS |
301 | /* Wait until I2C bus transfer is finished or an error occurs */ |
302 | do { | |
d8515652 IA |
303 | ctrl = readl(devpriv->mmio + S626_P_I2CCTRL); |
304 | } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY); | |
982e3d11 | 305 | |
be008602 | 306 | /* Return non-zero if I2C error occurred */ |
d8515652 | 307 | return ctrl & S626_I2C_ERR; |
982e3d11 HS |
308 | } |
309 | ||
8ee52611 | 310 | /* Read uint8_t from EEPROM. */ |
31de1948 | 311 | static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr) |
982e3d11 | 312 | { |
7f2f7e05 | 313 | struct s626_private *devpriv = dev->private; |
982e3d11 | 314 | |
8ee52611 IA |
315 | /* |
316 | * Send EEPROM target address: | |
317 | * Byte2 = I2C command: write to I2C EEPROM device. | |
318 | * Byte1 = EEPROM internal target address. | |
319 | * Byte0 = Not sent. | |
320 | */ | |
d8515652 IA |
321 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
322 | devpriv->i2c_adrs) | | |
323 | S626_I2C_B1(S626_I2C_ATTRSTOP, addr) | | |
324 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) | |
8ee52611 | 325 | /* Abort function and declare error if handshake failed. */ |
982e3d11 | 326 | return 0; |
982e3d11 | 327 | |
8ee52611 IA |
328 | /* |
329 | * Execute EEPROM read: | |
330 | * Byte2 = I2C command: read from I2C EEPROM device. | |
331 | * Byte1 receives uint8_t from EEPROM. | |
332 | * Byte0 = Not sent. | |
333 | */ | |
d8515652 | 334 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
31de1948 | 335 | (devpriv->i2c_adrs | 1)) | |
d8515652 IA |
336 | S626_I2C_B1(S626_I2C_ATTRSTOP, 0) | |
337 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) | |
8ee52611 | 338 | /* Abort function and declare error if handshake failed. */ |
982e3d11 | 339 | return 0; |
be008602 | 340 | |
d8515652 | 341 | return (readl(devpriv->mmio + S626_P_I2CCTRL) >> 16) & 0xff; |
982e3d11 HS |
342 | } |
343 | ||
95414729 HS |
344 | /* *********** DAC FUNCTIONS *********** */ |
345 | ||
8ee52611 | 346 | /* TrimDac LogicalChan-to-PhysicalChan mapping table. */ |
31de1948 | 347 | static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 }; |
95414729 | 348 | |
8ee52611 | 349 | /* TrimDac LogicalChan-to-EepromAdrs mapping table. */ |
31de1948 | 350 | static const uint8_t s626_trimadrs[] = { |
8ee52611 IA |
351 | 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 |
352 | }; | |
95414729 | 353 | |
8ee52611 IA |
354 | /* |
355 | * Private helper function: Transmit serial data to DAC via Audio | |
95414729 | 356 | * channel 2. Assumes: (1) TSL2 slot records initialized, and (2) |
07a36d66 | 357 | * dacpol contains valid target image. |
95414729 | 358 | */ |
31de1948 | 359 | static void s626_send_dac(struct comedi_device *dev, uint32_t val) |
95414729 | 360 | { |
7f2f7e05 | 361 | struct s626_private *devpriv = dev->private; |
95414729 HS |
362 | |
363 | /* START THE SERIAL CLOCK RUNNING ------------- */ | |
364 | ||
8ee52611 IA |
365 | /* |
366 | * Assert DAC polarity control and enable gating of DAC serial clock | |
95414729 HS |
367 | * and audio bit stream signals. At this point in time we must be |
368 | * assured of being in time slot 0. If we are not in slot 0, the | |
369 | * serial clock and audio stream signals will be disabled; this is | |
31de1948 IA |
370 | * because the following s626_debi_write statement (which enables |
371 | * signals to be passed through the gate array) would execute before | |
372 | * the trailing edge of WS1/WS3 (which turns off the signals), thus | |
95414729 HS |
373 | * causing the signals to be inactive during the DAC write. |
374 | */ | |
d8515652 | 375 | s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol); |
95414729 HS |
376 | |
377 | /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */ | |
378 | ||
379 | /* Copy DAC setpoint value to DAC's output DMA buffer. */ | |
07a36d66 IA |
380 | /* writel(val, devpriv->mmio + (uint32_t)devpriv->dac_wbuf); */ |
381 | *devpriv->dac_wbuf = val; | |
95414729 | 382 | |
ddd9813e HS |
383 | /* |
384 | * Enable the output DMA transfer. This will cause the DMAC to copy | |
385 | * the DAC's data value to A2's output FIFO. The DMA transfer will | |
95414729 HS |
386 | * then immediately terminate because the protection address is |
387 | * reached upon transfer of the first DWORD value. | |
388 | */ | |
d8515652 | 389 | s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1); |
95414729 | 390 | |
8ee52611 | 391 | /* While the DMA transfer is executing ... */ |
95414729 | 392 | |
25f8fd5e HS |
393 | /* |
394 | * Reset Audio2 output FIFO's underflow flag (along with any | |
395 | * other FIFO underflow/overflow flags). When set, this flag | |
396 | * will indicate that we have emerged from slot 0. | |
95414729 | 397 | */ |
d8515652 | 398 | writel(S626_ISR_AFOU, devpriv->mmio + S626_P_ISR); |
95414729 | 399 | |
8ee52611 IA |
400 | /* |
401 | * Wait for the DMA transfer to finish so that there will be data | |
95414729 HS |
402 | * available in the FIFO when time slot 1 tries to transfer a DWORD |
403 | * from the FIFO to the output buffer register. We test for DMA | |
404 | * Done by polling the DMAC enable flag; this flag is automatically | |
405 | * cleared when the transfer has finished. | |
406 | */ | |
d8515652 | 407 | while (readl(devpriv->mmio + S626_P_MC1) & S626_MC1_A2OUT) |
95414729 HS |
408 | ; |
409 | ||
410 | /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */ | |
411 | ||
8ee52611 IA |
412 | /* |
413 | * FIFO data is now available, so we enable execution of time slots | |
95414729 HS |
414 | * 1 and higher by clearing the EOS flag in slot 0. Note that SD3 |
415 | * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list | |
416 | * detection. | |
417 | */ | |
d8515652 IA |
418 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2, |
419 | devpriv->mmio + S626_VECTPORT(0)); | |
95414729 | 420 | |
8ee52611 IA |
421 | /* |
422 | * Wait for slot 1 to execute to ensure that the Packet will be | |
95414729 HS |
423 | * transmitted. This is detected by polling the Audio2 output FIFO |
424 | * underflow flag, which will be set when slot 1 execution has | |
425 | * finished transferring the DAC's data DWORD from the output FIFO | |
426 | * to the output buffer register. | |
427 | */ | |
d8515652 | 428 | while (!(readl(devpriv->mmio + S626_P_SSR) & S626_SSR_AF2_OUT)) |
95414729 HS |
429 | ; |
430 | ||
8ee52611 IA |
431 | /* |
432 | * Set up to trap execution at slot 0 when the TSL sequencer cycles | |
95414729 HS |
433 | * back to slot 0 after executing the EOS in slot 5. Also, |
434 | * simultaneously shift out and in the 0x00 that is ALWAYS the value | |
435 | * stored in the last byte to be shifted out of the FIFO's DWORD | |
436 | * buffer register. | |
437 | */ | |
d8515652 | 438 | writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS, |
676921c9 | 439 | devpriv->mmio + S626_VECTPORT(0)); |
95414729 HS |
440 | |
441 | /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */ | |
442 | ||
8ee52611 IA |
443 | /* |
444 | * Wait for the TSL to finish executing all time slots before | |
95414729 HS |
445 | * exiting this function. We must do this so that the next DAC |
446 | * write doesn't start, thereby enabling clock/chip select signals: | |
447 | * | |
448 | * 1. Before the TSL sequence cycles back to slot 0, which disables | |
449 | * the clock/cs signal gating and traps slot // list execution. | |
450 | * we have not yet finished slot 5 then the clock/cs signals are | |
451 | * still gated and we have not finished transmitting the stream. | |
452 | * | |
453 | * 2. While slots 2-5 are executing due to a late slot 0 trap. In | |
454 | * this case, the slot sequence is currently repeating, but with | |
455 | * clock/cs signals disabled. We must wait for slot 0 to trap | |
456 | * execution before setting up the next DAC setpoint DMA transfer | |
457 | * and enabling the clock/cs signals. To detect the end of slot 5, | |
458 | * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If | |
459 | * the TSL has not yet finished executing slot 5 ... | |
460 | */ | |
d8515652 | 461 | if (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000) { |
8ee52611 IA |
462 | /* |
463 | * The trap was set on time and we are still executing somewhere | |
95414729 HS |
464 | * in slots 2-5, so we now wait for slot 0 to execute and trap |
465 | * TSL execution. This is detected when FB_BUFFER2 MSB changes | |
466 | * from 0xFF to 0x00, which slot 0 causes to happen by shifting | |
467 | * out/in on SD2 the 0x00 that is always referenced by slot 5. | |
468 | */ | |
d8515652 | 469 | while (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000) |
95414729 HS |
470 | ; |
471 | } | |
8ee52611 IA |
472 | /* |
473 | * Either (1) we were too late setting the slot 0 trap; the TSL | |
95414729 HS |
474 | * sequencer restarted slot 0 before we could set the EOS trap flag, |
475 | * or (2) we were not late and execution is now trapped at slot 0. | |
476 | * In either case, we must now change slot 0 so that it will store | |
477 | * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes. | |
478 | * In order to do this, we reprogram slot 0 so that it will shift in | |
479 | * SD3, which is driven only by a pull-up resistor. | |
480 | */ | |
d8515652 IA |
481 | writel(S626_RSD3 | S626_SIB_A2 | S626_EOS, |
482 | devpriv->mmio + S626_VECTPORT(0)); | |
95414729 | 483 | |
8ee52611 IA |
484 | /* |
485 | * Wait for slot 0 to execute, at which time the TSL is setup for | |
95414729 HS |
486 | * the next DAC write. This is detected when FB_BUFFER2 MSB changes |
487 | * from 0x00 to 0xFF. | |
488 | */ | |
d8515652 | 489 | while (!(readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000)) |
95414729 HS |
490 | ; |
491 | } | |
492 | ||
8ee52611 IA |
493 | /* |
494 | * Private helper function: Write setpoint to an application DAC channel. | |
495 | */ | |
31de1948 | 496 | static void s626_set_dac(struct comedi_device *dev, uint16_t chan, |
3de00ee4 | 497 | int16_t dacdata) |
95414729 | 498 | { |
7f2f7e05 | 499 | struct s626_private *devpriv = dev->private; |
8ee52611 | 500 | uint16_t signmask; |
f1f7efce | 501 | uint32_t ws_image; |
8ee52611 | 502 | uint32_t val; |
95414729 | 503 | |
8ee52611 IA |
504 | /* |
505 | * Adjust DAC data polarity and set up Polarity Control Register image. | |
506 | */ | |
95414729 HS |
507 | signmask = 1 << chan; |
508 | if (dacdata < 0) { | |
509 | dacdata = -dacdata; | |
07a36d66 | 510 | devpriv->dacpol |= signmask; |
8ee52611 | 511 | } else { |
07a36d66 | 512 | devpriv->dacpol &= ~signmask; |
8ee52611 | 513 | } |
95414729 | 514 | |
8ee52611 IA |
515 | /* Limit DAC setpoint value to valid range. */ |
516 | if ((uint16_t)dacdata > 0x1FFF) | |
95414729 HS |
517 | dacdata = 0x1FFF; |
518 | ||
8ee52611 IA |
519 | /* |
520 | * Set up TSL2 records (aka "vectors") for DAC update. Vectors V2 | |
95414729 HS |
521 | * and V3 transmit the setpoint to the target DAC. V4 and V5 send |
522 | * data to a non-existent TrimDac channel just to keep the clock | |
523 | * running after sending data to the target DAC. This is necessary | |
524 | * to eliminate the clock glitch that would otherwise occur at the | |
525 | * end of the target DAC's serial data stream. When the sequence | |
526 | * restarts at V0 (after executing V5), the gate array automatically | |
527 | * disables gating for the DAC clock and all DAC chip selects. | |
528 | */ | |
529 | ||
25f8fd5e | 530 | /* Choose DAC chip select to be asserted */ |
d8515652 | 531 | ws_image = (chan & 2) ? S626_WS1 : S626_WS2; |
25f8fd5e | 532 | /* Slot 2: Transmit high data byte to target DAC */ |
d8515652 IA |
533 | writel(S626_XSD2 | S626_XFIFO_1 | ws_image, |
534 | devpriv->mmio + S626_VECTPORT(2)); | |
25f8fd5e | 535 | /* Slot 3: Transmit low data byte to target DAC */ |
d8515652 IA |
536 | writel(S626_XSD2 | S626_XFIFO_0 | ws_image, |
537 | devpriv->mmio + S626_VECTPORT(3)); | |
95414729 | 538 | /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */ |
d8515652 IA |
539 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3, |
540 | devpriv->mmio + S626_VECTPORT(4)); | |
25f8fd5e | 541 | /* Slot 5: running after writing target DAC's low data byte */ |
d8515652 IA |
542 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS, |
543 | devpriv->mmio + S626_VECTPORT(5)); | |
95414729 | 544 | |
8ee52611 IA |
545 | /* |
546 | * Construct and transmit target DAC's serial packet: | |
547 | * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>, | |
95414729 HS |
548 | * and D<12:0> is the DAC setpoint. Append a WORD value (that writes |
549 | * to a non-existent TrimDac channel) that serves to keep the clock | |
550 | * running after the packet has been sent to the target DAC. | |
551 | */ | |
8ee52611 IA |
552 | val = 0x0F000000; /* Continue clock after target DAC data |
553 | * (write to non-existent trimdac). */ | |
554 | val |= 0x00004000; /* Address the two main dual-DAC devices | |
555 | * (TSL's chip select enables target device). */ | |
556 | val |= ((uint32_t)(chan & 1) << 15); /* Address the DAC channel | |
557 | * within the device. */ | |
558 | val |= (uint32_t)dacdata; /* Include DAC setpoint data. */ | |
31de1948 | 559 | s626_send_dac(dev, val); |
95414729 HS |
560 | } |
561 | ||
31de1948 IA |
562 | static void s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan, |
563 | uint8_t dac_data) | |
95414729 | 564 | { |
7f2f7e05 | 565 | struct s626_private *devpriv = dev->private; |
95414729 HS |
566 | uint32_t chan; |
567 | ||
8ee52611 IA |
568 | /* |
569 | * Save the new setpoint in case the application needs to read it back | |
570 | * later. | |
571 | */ | |
f1f7efce | 572 | devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data; |
95414729 | 573 | |
8ee52611 | 574 | /* Map logical channel number to physical channel number. */ |
31de1948 | 575 | chan = s626_trimchan[logical_chan]; |
95414729 | 576 | |
8ee52611 IA |
577 | /* |
578 | * Set up TSL2 records for TrimDac write operation. All slots shift | |
95414729 HS |
579 | * 0xFF in from pulled-up SD3 so that the end of the slot sequence |
580 | * can be detected. | |
581 | */ | |
582 | ||
25f8fd5e | 583 | /* Slot 2: Send high uint8_t to target TrimDac */ |
d8515652 IA |
584 | writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3, |
585 | devpriv->mmio + S626_VECTPORT(2)); | |
25f8fd5e | 586 | /* Slot 3: Send low uint8_t to target TrimDac */ |
d8515652 IA |
587 | writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3, |
588 | devpriv->mmio + S626_VECTPORT(3)); | |
25f8fd5e | 589 | /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */ |
d8515652 IA |
590 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1, |
591 | devpriv->mmio + S626_VECTPORT(4)); | |
25f8fd5e | 592 | /* Slot 5: Send NOP low uint8_t to DAC0 */ |
d8515652 IA |
593 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS, |
594 | devpriv->mmio + S626_VECTPORT(5)); | |
95414729 | 595 | |
8ee52611 IA |
596 | /* |
597 | * Construct and transmit target DAC's serial packet: | |
598 | * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the | |
95414729 HS |
599 | * DAC channel's address, and D<7:0> is the DAC setpoint. Append a |
600 | * WORD value (that writes a channel 0 NOP command to a non-existent | |
601 | * main DAC channel) that serves to keep the clock running after the | |
602 | * packet has been sent to the target DAC. | |
603 | */ | |
604 | ||
8ee52611 IA |
605 | /* |
606 | * Address the DAC channel within the trimdac device. | |
607 | * Include DAC setpoint data. | |
608 | */ | |
31de1948 | 609 | s626_send_dac(dev, (chan << 8) | dac_data); |
95414729 HS |
610 | } |
611 | ||
31de1948 | 612 | static void s626_load_trim_dacs(struct comedi_device *dev) |
95414729 | 613 | { |
8ee52611 | 614 | uint8_t i; |
95414729 | 615 | |
8ee52611 | 616 | /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */ |
31de1948 IA |
617 | for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) |
618 | s626_write_trim_dac(dev, i, | |
619 | s626_i2c_read(dev, s626_trimadrs[i])); | |
95414729 HS |
620 | } |
621 | ||
e3eb08d0 | 622 | /* ****** COUNTER FUNCTIONS ******* */ |
8ee52611 IA |
623 | |
624 | /* | |
625 | * All counter functions address a specific counter by means of the | |
e3eb08d0 HS |
626 | * "Counter" argument, which is a logical counter number. The Counter |
627 | * argument may have any of the following legal values: 0=0A, 1=1A, | |
628 | * 2=2A, 3=0B, 4=1B, 5=2B. | |
629 | */ | |
630 | ||
8ee52611 IA |
631 | /* |
632 | * Read a counter's output latch. | |
633 | */ | |
31de1948 IA |
634 | static uint32_t s626_read_latch(struct comedi_device *dev, |
635 | const struct s626_enc_info *k) | |
e3eb08d0 | 636 | { |
8ee52611 | 637 | uint32_t value; |
e3eb08d0 | 638 | |
8ee52611 | 639 | /* Latch counts and fetch LSW of latched counts value. */ |
31de1948 | 640 | value = s626_debi_read(dev, k->my_latch_lsw); |
e3eb08d0 | 641 | |
8ee52611 | 642 | /* Fetch MSW of latched counts and combine with LSW. */ |
31de1948 | 643 | value |= ((uint32_t)s626_debi_read(dev, k->my_latch_lsw + 2) << 16); |
e3eb08d0 | 644 | |
8ee52611 | 645 | /* Return latched counts. */ |
e3eb08d0 HS |
646 | return value; |
647 | } | |
648 | ||
8ee52611 IA |
649 | /* |
650 | * Return/set a counter pair's latch trigger source. 0: On read | |
e3eb08d0 HS |
651 | * access, 1: A index latches A, 2: B index latches B, 3: A overflow |
652 | * latches B. | |
653 | */ | |
31de1948 IA |
654 | static void s626_set_latch_source(struct comedi_device *dev, |
655 | const struct s626_enc_info *k, uint16_t value) | |
e3eb08d0 | 656 | { |
d8515652 IA |
657 | s626_debi_replace(dev, k->my_crb, |
658 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC), | |
0830ada5 | 659 | S626_SET_CRB_LATCHSRC(value)); |
e3eb08d0 HS |
660 | } |
661 | ||
8ee52611 IA |
662 | /* |
663 | * Write value into counter preload register. | |
664 | */ | |
31de1948 IA |
665 | static void s626_preload(struct comedi_device *dev, |
666 | const struct s626_enc_info *k, uint32_t value) | |
e3eb08d0 | 667 | { |
31de1948 IA |
668 | s626_debi_write(dev, k->my_latch_lsw, value); |
669 | s626_debi_write(dev, k->my_latch_lsw + 2, value >> 16); | |
e3eb08d0 HS |
670 | } |
671 | ||
010be96f IA |
672 | /* ****** PRIVATE COUNTER FUNCTIONS ****** */ |
673 | ||
674 | /* | |
675 | * Reset a counter's index and overflow event capture flags. | |
676 | */ | |
31de1948 IA |
677 | static void s626_reset_cap_flags_a(struct comedi_device *dev, |
678 | const struct s626_enc_info *k) | |
010be96f | 679 | { |
d8515652 | 680 | s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL, |
0830ada5 IA |
681 | (S626_SET_CRB_INTRESETCMD(1) | |
682 | S626_SET_CRB_INTRESET_A(1))); | |
010be96f IA |
683 | } |
684 | ||
31de1948 IA |
685 | static void s626_reset_cap_flags_b(struct comedi_device *dev, |
686 | const struct s626_enc_info *k) | |
010be96f | 687 | { |
d8515652 | 688 | s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL, |
0830ada5 IA |
689 | (S626_SET_CRB_INTRESETCMD(1) | |
690 | S626_SET_CRB_INTRESET_B(1))); | |
010be96f IA |
691 | } |
692 | ||
693 | /* | |
694 | * Return counter setup in a format (COUNTER_SETUP) that is consistent | |
695 | * for both A and B counters. | |
696 | */ | |
31de1948 IA |
697 | static uint16_t s626_get_mode_a(struct comedi_device *dev, |
698 | const struct s626_enc_info *k) | |
010be96f IA |
699 | { |
700 | uint16_t cra; | |
701 | uint16_t crb; | |
702 | uint16_t setup; | |
0830ada5 | 703 | unsigned cntsrc, clkmult, clkpol, encmode; |
010be96f IA |
704 | |
705 | /* Fetch CRA and CRB register images. */ | |
31de1948 IA |
706 | cra = s626_debi_read(dev, k->my_cra); |
707 | crb = s626_debi_read(dev, k->my_crb); | |
010be96f IA |
708 | |
709 | /* | |
710 | * Populate the standardized counter setup bit fields. | |
010be96f | 711 | */ |
0830ada5 IA |
712 | setup = |
713 | /* LoadSrc = LoadSrcA. */ | |
714 | S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) | | |
715 | /* LatchSrc = LatchSrcA. */ | |
716 | S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) | | |
717 | /* IntSrc = IntSrcA. */ | |
718 | S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) | | |
2cea19fa IA |
719 | /* IndxSrc = IndxSrcA. */ |
720 | S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) | | |
0830ada5 IA |
721 | /* IndxPol = IndxPolA. */ |
722 | S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) | | |
723 | /* ClkEnab = ClkEnabA. */ | |
724 | S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb)); | |
010be96f IA |
725 | |
726 | /* Adjust mode-dependent parameters. */ | |
0830ada5 IA |
727 | cntsrc = S626_GET_CRA_CNTSRC_A(cra); |
728 | if (cntsrc & S626_CNTSRC_SYSCLK) { | |
622ec01a | 729 | /* Timer mode (CntSrcA<1> == 1): */ |
0830ada5 | 730 | encmode = S626_ENCMODE_TIMER; |
622ec01a | 731 | /* Set ClkPol to indicate count direction (CntSrcA<0>). */ |
0830ada5 | 732 | clkpol = cntsrc & 1; |
010be96f | 733 | /* ClkMult must be 1x in Timer mode. */ |
7a1046e5 | 734 | clkmult = S626_CLKMULT_1X; |
010be96f | 735 | } else { |
622ec01a | 736 | /* Counter mode (CntSrcA<1> == 0): */ |
0830ada5 | 737 | encmode = S626_ENCMODE_COUNTER; |
010be96f | 738 | /* Pass through ClkPol. */ |
0830ada5 | 739 | clkpol = S626_GET_CRA_CLKPOL_A(cra); |
010be96f | 740 | /* Force ClkMult to 1x if not legal, else pass through. */ |
0830ada5 | 741 | clkmult = S626_GET_CRA_CLKMULT_A(cra); |
7a1046e5 IA |
742 | if (clkmult == S626_CLKMULT_SPECIAL) |
743 | clkmult = S626_CLKMULT_1X; | |
010be96f | 744 | } |
0830ada5 IA |
745 | setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) | |
746 | S626_SET_STD_CLKPOL(clkpol); | |
010be96f IA |
747 | |
748 | /* Return adjusted counter setup. */ | |
749 | return setup; | |
750 | } | |
751 | ||
31de1948 IA |
752 | static uint16_t s626_get_mode_b(struct comedi_device *dev, |
753 | const struct s626_enc_info *k) | |
010be96f IA |
754 | { |
755 | uint16_t cra; | |
756 | uint16_t crb; | |
757 | uint16_t setup; | |
0830ada5 | 758 | unsigned cntsrc, clkmult, clkpol, encmode; |
010be96f IA |
759 | |
760 | /* Fetch CRA and CRB register images. */ | |
31de1948 IA |
761 | cra = s626_debi_read(dev, k->my_cra); |
762 | crb = s626_debi_read(dev, k->my_crb); | |
010be96f IA |
763 | |
764 | /* | |
765 | * Populate the standardized counter setup bit fields. | |
010be96f | 766 | */ |
0830ada5 IA |
767 | setup = |
768 | /* IntSrc = IntSrcB. */ | |
769 | S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) | | |
770 | /* LatchSrc = LatchSrcB. */ | |
771 | S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) | | |
772 | /* LoadSrc = LoadSrcB. */ | |
773 | S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) | | |
774 | /* IndxPol = IndxPolB. */ | |
775 | S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) | | |
776 | /* ClkEnab = ClkEnabB. */ | |
777 | S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) | | |
2cea19fa IA |
778 | /* IndxSrc = IndxSrcB. */ |
779 | S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra)); | |
010be96f IA |
780 | |
781 | /* Adjust mode-dependent parameters. */ | |
0830ada5 IA |
782 | cntsrc = S626_GET_CRA_CNTSRC_B(cra); |
783 | clkmult = S626_GET_CRB_CLKMULT_B(crb); | |
7a1046e5 IA |
784 | if (clkmult == S626_CLKMULT_SPECIAL) { |
785 | /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */ | |
0830ada5 | 786 | encmode = S626_ENCMODE_EXTENDER; |
010be96f | 787 | /* Indicate multiplier is 1x. */ |
7a1046e5 | 788 | clkmult = S626_CLKMULT_1X; |
622ec01a | 789 | /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */ |
0830ada5 IA |
790 | clkpol = cntsrc & 1; |
791 | } else if (cntsrc & S626_CNTSRC_SYSCLK) { | |
622ec01a | 792 | /* Timer mode (CntSrcB<1> == 1): */ |
0830ada5 | 793 | encmode = S626_ENCMODE_TIMER; |
010be96f | 794 | /* Indicate multiplier is 1x. */ |
7a1046e5 | 795 | clkmult = S626_CLKMULT_1X; |
622ec01a | 796 | /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */ |
0830ada5 | 797 | clkpol = cntsrc & 1; |
010be96f | 798 | } else { |
622ec01a | 799 | /* If Counter mode (CntSrcB<1> == 0): */ |
0830ada5 | 800 | encmode = S626_ENCMODE_COUNTER; |
010be96f | 801 | /* Clock multiplier is passed through. */ |
010be96f | 802 | /* Clock polarity is passed through. */ |
0830ada5 | 803 | clkpol = S626_GET_CRB_CLKPOL_B(crb); |
010be96f | 804 | } |
0830ada5 IA |
805 | setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) | |
806 | S626_SET_STD_CLKPOL(clkpol); | |
010be96f IA |
807 | |
808 | /* Return adjusted counter setup. */ | |
809 | return setup; | |
810 | } | |
811 | ||
17afeac2 IA |
812 | /* |
813 | * Set the operating mode for the specified counter. The setup | |
814 | * parameter is treated as a COUNTER_SETUP data type. The following | |
815 | * parameters are programmable (all other parms are ignored): ClkMult, | |
816 | * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc. | |
817 | */ | |
31de1948 IA |
818 | static void s626_set_mode_a(struct comedi_device *dev, |
819 | const struct s626_enc_info *k, uint16_t setup, | |
820 | uint16_t disable_int_src) | |
17afeac2 IA |
821 | { |
822 | struct s626_private *devpriv = dev->private; | |
823 | uint16_t cra; | |
824 | uint16_t crb; | |
0830ada5 | 825 | unsigned cntsrc, clkmult, clkpol; |
17afeac2 IA |
826 | |
827 | /* Initialize CRA and CRB images. */ | |
828 | /* Preload trigger is passed through. */ | |
0830ada5 | 829 | cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup)); |
2cea19fa IA |
830 | /* IndexSrc is passed through. */ |
831 | cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup)); | |
17afeac2 IA |
832 | |
833 | /* Reset any pending CounterA event captures. */ | |
0830ada5 | 834 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1); |
17afeac2 | 835 | /* Clock enable is passed through. */ |
0830ada5 | 836 | crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup)); |
17afeac2 IA |
837 | |
838 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ | |
839 | if (!disable_int_src) | |
0830ada5 | 840 | cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup)); |
17afeac2 IA |
841 | |
842 | /* Populate all mode-dependent attributes of CRA & CRB images. */ | |
0830ada5 IA |
843 | clkpol = S626_GET_STD_CLKPOL(setup); |
844 | switch (S626_GET_STD_ENCMODE(setup)) { | |
622ec01a | 845 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
d8515652 | 846 | /* Force to Timer mode (Extender valid only for B counters). */ |
622ec01a IA |
847 | /* Fall through to case S626_ENCMODE_TIMER: */ |
848 | case S626_ENCMODE_TIMER: /* Timer Mode: */ | |
849 | /* CntSrcA<1> selects system clock */ | |
0830ada5 | 850 | cntsrc = S626_CNTSRC_SYSCLK; |
622ec01a | 851 | /* Count direction (CntSrcA<0>) obtained from ClkPol. */ |
0830ada5 | 852 | cntsrc |= clkpol; |
17afeac2 | 853 | /* ClkPolA behaves as always-on clock enable. */ |
0830ada5 | 854 | clkpol = 1; |
17afeac2 | 855 | /* ClkMult must be 1x. */ |
7a1046e5 | 856 | clkmult = S626_CLKMULT_1X; |
17afeac2 IA |
857 | break; |
858 | default: /* Counter Mode: */ | |
859 | /* Select ENC_C and ENC_D as clock/direction inputs. */ | |
0830ada5 | 860 | cntsrc = S626_CNTSRC_ENCODER; |
17afeac2 | 861 | /* Clock polarity is passed through. */ |
17afeac2 | 862 | /* Force multiplier to x1 if not legal, else pass through. */ |
0830ada5 | 863 | clkmult = S626_GET_STD_CLKMULT(setup); |
7a1046e5 IA |
864 | if (clkmult == S626_CLKMULT_SPECIAL) |
865 | clkmult = S626_CLKMULT_1X; | |
17afeac2 IA |
866 | break; |
867 | } | |
0830ada5 IA |
868 | cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) | |
869 | S626_SET_CRA_CLKMULT_A(clkmult); | |
17afeac2 IA |
870 | |
871 | /* | |
872 | * Force positive index polarity if IndxSrc is software-driven only, | |
873 | * otherwise pass it through. | |
874 | */ | |
2cea19fa | 875 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
0830ada5 | 876 | cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup)); |
17afeac2 IA |
877 | |
878 | /* | |
879 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt | |
880 | * enable mask to indicate the counter interrupt is disabled. | |
881 | */ | |
882 | if (disable_int_src) | |
883 | devpriv->counter_int_enabs &= ~k->my_event_bits[3]; | |
884 | ||
885 | /* | |
886 | * While retaining CounterB and LatchSrc configurations, program the | |
887 | * new counter operating mode. | |
888 | */ | |
d8515652 | 889 | s626_debi_replace(dev, k->my_cra, |
622ec01a | 890 | S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra); |
d8515652 IA |
891 | s626_debi_replace(dev, k->my_crb, |
892 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb); | |
17afeac2 IA |
893 | } |
894 | ||
31de1948 IA |
895 | static void s626_set_mode_b(struct comedi_device *dev, |
896 | const struct s626_enc_info *k, uint16_t setup, | |
897 | uint16_t disable_int_src) | |
17afeac2 IA |
898 | { |
899 | struct s626_private *devpriv = dev->private; | |
900 | uint16_t cra; | |
901 | uint16_t crb; | |
0830ada5 | 902 | unsigned cntsrc, clkmult, clkpol; |
17afeac2 IA |
903 | |
904 | /* Initialize CRA and CRB images. */ | |
2cea19fa IA |
905 | /* IndexSrc is passed through. */ |
906 | cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup)); | |
17afeac2 IA |
907 | |
908 | /* Reset event captures and disable interrupts. */ | |
0830ada5 | 909 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1); |
17afeac2 | 910 | /* Clock enable is passed through. */ |
0830ada5 | 911 | crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup)); |
17afeac2 | 912 | /* Preload trigger source is passed through. */ |
0830ada5 | 913 | crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup)); |
17afeac2 IA |
914 | |
915 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ | |
916 | if (!disable_int_src) | |
0830ada5 | 917 | crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup)); |
17afeac2 IA |
918 | |
919 | /* Populate all mode-dependent attributes of CRA & CRB images. */ | |
0830ada5 IA |
920 | clkpol = S626_GET_STD_CLKPOL(setup); |
921 | switch (S626_GET_STD_ENCMODE(setup)) { | |
622ec01a IA |
922 | case S626_ENCMODE_TIMER: /* Timer Mode: */ |
923 | /* CntSrcB<1> selects system clock */ | |
0830ada5 | 924 | cntsrc = S626_CNTSRC_SYSCLK; |
622ec01a | 925 | /* with direction (CntSrcB<0>) obtained from ClkPol. */ |
0830ada5 | 926 | cntsrc |= clkpol; |
17afeac2 | 927 | /* ClkPolB behaves as always-on clock enable. */ |
0830ada5 | 928 | clkpol = 1; |
17afeac2 | 929 | /* ClkMultB must be 1x. */ |
7a1046e5 | 930 | clkmult = S626_CLKMULT_1X; |
17afeac2 | 931 | break; |
622ec01a IA |
932 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
933 | /* CntSrcB source is OverflowA (same as "timer") */ | |
0830ada5 | 934 | cntsrc = S626_CNTSRC_SYSCLK; |
17afeac2 | 935 | /* with direction obtained from ClkPol. */ |
0830ada5 | 936 | cntsrc |= clkpol; |
17afeac2 | 937 | /* ClkPolB controls IndexB -- always set to active. */ |
0830ada5 | 938 | clkpol = 1; |
17afeac2 | 939 | /* ClkMultB selects OverflowA as the clock source. */ |
7a1046e5 | 940 | clkmult = S626_CLKMULT_SPECIAL; |
17afeac2 IA |
941 | break; |
942 | default: /* Counter Mode: */ | |
943 | /* Select ENC_C and ENC_D as clock/direction inputs. */ | |
0830ada5 | 944 | cntsrc = S626_CNTSRC_ENCODER; |
17afeac2 | 945 | /* ClkPol is passed through. */ |
17afeac2 | 946 | /* Force ClkMult to x1 if not legal, otherwise pass through. */ |
0830ada5 | 947 | clkmult = S626_GET_STD_CLKMULT(setup); |
7a1046e5 IA |
948 | if (clkmult == S626_CLKMULT_SPECIAL) |
949 | clkmult = S626_CLKMULT_1X; | |
17afeac2 IA |
950 | break; |
951 | } | |
0830ada5 IA |
952 | cra |= S626_SET_CRA_CNTSRC_B(cntsrc); |
953 | crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult); | |
17afeac2 IA |
954 | |
955 | /* | |
956 | * Force positive index polarity if IndxSrc is software-driven only, | |
957 | * otherwise pass it through. | |
958 | */ | |
2cea19fa | 959 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
0830ada5 | 960 | crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup)); |
17afeac2 IA |
961 | |
962 | /* | |
963 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt | |
964 | * enable mask to indicate the counter interrupt is disabled. | |
965 | */ | |
966 | if (disable_int_src) | |
967 | devpriv->counter_int_enabs &= ~k->my_event_bits[3]; | |
968 | ||
969 | /* | |
970 | * While retaining CounterA and LatchSrc configurations, program the | |
971 | * new counter operating mode. | |
972 | */ | |
d8515652 | 973 | s626_debi_replace(dev, k->my_cra, |
622ec01a | 974 | ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra); |
d8515652 IA |
975 | s626_debi_replace(dev, k->my_crb, |
976 | S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb); | |
17afeac2 IA |
977 | } |
978 | ||
979 | /* | |
980 | * Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. | |
981 | */ | |
31de1948 IA |
982 | static void s626_set_enable_a(struct comedi_device *dev, |
983 | const struct s626_enc_info *k, uint16_t enab) | |
17afeac2 | 984 | { |
d8515652 IA |
985 | s626_debi_replace(dev, k->my_crb, |
986 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), | |
0830ada5 | 987 | S626_SET_CRB_CLKENAB_A(enab)); |
17afeac2 IA |
988 | } |
989 | ||
31de1948 IA |
990 | static void s626_set_enable_b(struct comedi_device *dev, |
991 | const struct s626_enc_info *k, uint16_t enab) | |
17afeac2 | 992 | { |
d8515652 IA |
993 | s626_debi_replace(dev, k->my_crb, |
994 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_B), | |
0830ada5 | 995 | S626_SET_CRB_CLKENAB_B(enab)); |
17afeac2 IA |
996 | } |
997 | ||
31de1948 IA |
998 | static uint16_t s626_get_enable_a(struct comedi_device *dev, |
999 | const struct s626_enc_info *k) | |
17afeac2 | 1000 | { |
0830ada5 | 1001 | return S626_GET_CRB_CLKENAB_A(s626_debi_read(dev, k->my_crb)); |
17afeac2 IA |
1002 | } |
1003 | ||
31de1948 IA |
1004 | static uint16_t s626_get_enable_b(struct comedi_device *dev, |
1005 | const struct s626_enc_info *k) | |
17afeac2 | 1006 | { |
0830ada5 | 1007 | return S626_GET_CRB_CLKENAB_B(s626_debi_read(dev, k->my_crb)); |
17afeac2 IA |
1008 | } |
1009 | ||
1010 | #ifdef unused | |
31de1948 IA |
1011 | static uint16_t s626_get_latch_source(struct comedi_device *dev, |
1012 | const struct s626_enc_info *k) | |
17afeac2 | 1013 | { |
0830ada5 | 1014 | return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, k->my_crb)); |
17afeac2 IA |
1015 | } |
1016 | #endif | |
1017 | ||
1018 | /* | |
1019 | * Return/set the event that will trigger transfer of the preload | |
1020 | * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow, | |
1021 | * 2=OverflowA (B counters only), 3=disabled. | |
1022 | */ | |
31de1948 IA |
1023 | static void s626_set_load_trig_a(struct comedi_device *dev, |
1024 | const struct s626_enc_info *k, uint16_t trig) | |
17afeac2 | 1025 | { |
d8515652 | 1026 | s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_LOADSRC_A, |
0830ada5 | 1027 | S626_SET_CRA_LOADSRC_A(trig)); |
17afeac2 IA |
1028 | } |
1029 | ||
31de1948 IA |
1030 | static void s626_set_load_trig_b(struct comedi_device *dev, |
1031 | const struct s626_enc_info *k, uint16_t trig) | |
17afeac2 | 1032 | { |
d8515652 IA |
1033 | s626_debi_replace(dev, k->my_crb, |
1034 | ~(S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL), | |
0830ada5 | 1035 | S626_SET_CRB_LOADSRC_B(trig)); |
17afeac2 IA |
1036 | } |
1037 | ||
31de1948 IA |
1038 | static uint16_t s626_get_load_trig_a(struct comedi_device *dev, |
1039 | const struct s626_enc_info *k) | |
17afeac2 | 1040 | { |
0830ada5 | 1041 | return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev, k->my_cra)); |
17afeac2 IA |
1042 | } |
1043 | ||
31de1948 IA |
1044 | static uint16_t s626_get_load_trig_b(struct comedi_device *dev, |
1045 | const struct s626_enc_info *k) | |
17afeac2 | 1046 | { |
0830ada5 | 1047 | return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev, k->my_crb)); |
17afeac2 IA |
1048 | } |
1049 | ||
bc284a2a IA |
1050 | /* |
1051 | * Return/set counter interrupt source and clear any captured | |
1052 | * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly, | |
1053 | * 2=IndexOnly, 3=IndexAndOverflow. | |
1054 | */ | |
31de1948 IA |
1055 | static void s626_set_int_src_a(struct comedi_device *dev, |
1056 | const struct s626_enc_info *k, | |
1057 | uint16_t int_source) | |
bc284a2a IA |
1058 | { |
1059 | struct s626_private *devpriv = dev->private; | |
1060 | ||
1061 | /* Reset any pending counter overflow or index captures. */ | |
d8515652 | 1062 | s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL, |
0830ada5 IA |
1063 | (S626_SET_CRB_INTRESETCMD(1) | |
1064 | S626_SET_CRB_INTRESET_A(1))); | |
bc284a2a IA |
1065 | |
1066 | /* Program counter interrupt source. */ | |
d8515652 | 1067 | s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_INTSRC_A, |
0830ada5 | 1068 | S626_SET_CRA_INTSRC_A(int_source)); |
bc284a2a IA |
1069 | |
1070 | /* Update MISC2 interrupt enable mask. */ | |
1071 | devpriv->counter_int_enabs = | |
1072 | (devpriv->counter_int_enabs & ~k->my_event_bits[3]) | | |
1073 | k->my_event_bits[int_source]; | |
1074 | } | |
1075 | ||
31de1948 IA |
1076 | static void s626_set_int_src_b(struct comedi_device *dev, |
1077 | const struct s626_enc_info *k, | |
1078 | uint16_t int_source) | |
bc284a2a IA |
1079 | { |
1080 | struct s626_private *devpriv = dev->private; | |
1081 | uint16_t crb; | |
1082 | ||
1083 | /* Cache writeable CRB register image. */ | |
d8515652 | 1084 | crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL; |
bc284a2a IA |
1085 | |
1086 | /* Reset any pending counter overflow or index captures. */ | |
0830ada5 IA |
1087 | s626_debi_write(dev, k->my_crb, (crb | S626_SET_CRB_INTRESETCMD(1) | |
1088 | S626_SET_CRB_INTRESET_B(1))); | |
bc284a2a IA |
1089 | |
1090 | /* Program counter interrupt source. */ | |
0830ada5 IA |
1091 | s626_debi_write(dev, k->my_crb, ((crb & ~S626_CRBMSK_INTSRC_B) | |
1092 | S626_SET_CRB_INTSRC_B(int_source))); | |
bc284a2a IA |
1093 | |
1094 | /* Update MISC2 interrupt enable mask. */ | |
1095 | devpriv->counter_int_enabs = | |
1096 | (devpriv->counter_int_enabs & ~k->my_event_bits[3]) | | |
1097 | k->my_event_bits[int_source]; | |
1098 | } | |
1099 | ||
31de1948 IA |
1100 | static uint16_t s626_get_int_src_a(struct comedi_device *dev, |
1101 | const struct s626_enc_info *k) | |
bc284a2a | 1102 | { |
0830ada5 | 1103 | return S626_GET_CRA_INTSRC_A(s626_debi_read(dev, k->my_cra)); |
bc284a2a IA |
1104 | } |
1105 | ||
31de1948 IA |
1106 | static uint16_t s626_get_int_src_b(struct comedi_device *dev, |
1107 | const struct s626_enc_info *k) | |
bc284a2a | 1108 | { |
0830ada5 | 1109 | return S626_GET_CRB_INTSRC_B(s626_debi_read(dev, k->my_crb)); |
bc284a2a IA |
1110 | } |
1111 | ||
1112 | #ifdef unused | |
1113 | /* | |
1114 | * Return/set the clock multiplier. | |
1115 | */ | |
31de1948 IA |
1116 | static void s626_set_clk_mult(struct comedi_device *dev, |
1117 | const struct s626_enc_info *k, uint16_t value) | |
bc284a2a | 1118 | { |
d8515652 | 1119 | k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKMULT) | |
0830ada5 | 1120 | S626_SET_STD_CLKMULT(value)), false); |
bc284a2a IA |
1121 | } |
1122 | ||
31de1948 IA |
1123 | static uint16_t s626_get_clk_mult(struct comedi_device *dev, |
1124 | const struct s626_enc_info *k) | |
bc284a2a | 1125 | { |
0830ada5 | 1126 | return S626_GET_STD_CLKMULT(k->get_mode(dev, k)); |
bc284a2a IA |
1127 | } |
1128 | ||
1129 | /* | |
1130 | * Return/set the clock polarity. | |
1131 | */ | |
31de1948 IA |
1132 | static void s626_set_clk_pol(struct comedi_device *dev, |
1133 | const struct s626_enc_info *k, uint16_t value) | |
bc284a2a | 1134 | { |
d8515652 | 1135 | k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKPOL) | |
0830ada5 | 1136 | S626_SET_STD_CLKPOL(value)), false); |
bc284a2a IA |
1137 | } |
1138 | ||
31de1948 IA |
1139 | static uint16_t s626_get_clk_pol(struct comedi_device *dev, |
1140 | const struct s626_enc_info *k) | |
bc284a2a | 1141 | { |
0830ada5 | 1142 | return S626_GET_STD_CLKPOL(k->get_mode(dev, k)); |
bc284a2a IA |
1143 | } |
1144 | ||
1145 | /* | |
622ec01a | 1146 | * Return/set the encoder mode. |
bc284a2a | 1147 | */ |
622ec01a IA |
1148 | static void s626_set_enc_mode(struct comedi_device *dev, |
1149 | const struct s626_enc_info *k, uint16_t value) | |
bc284a2a | 1150 | { |
622ec01a | 1151 | k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_ENCMODE) | |
0830ada5 | 1152 | S626_SET_STD_ENCMODE(value)), false); |
bc284a2a IA |
1153 | } |
1154 | ||
622ec01a IA |
1155 | static uint16_t s626_get_enc_mode(struct comedi_device *dev, |
1156 | const struct s626_enc_info *k) | |
bc284a2a | 1157 | { |
0830ada5 | 1158 | return S626_GET_STD_ENCMODE(k->get_mode(dev, k)); |
bc284a2a IA |
1159 | } |
1160 | ||
1161 | /* | |
1162 | * Return/set the index polarity. | |
1163 | */ | |
31de1948 IA |
1164 | static void s626_set_index_pol(struct comedi_device *dev, |
1165 | const struct s626_enc_info *k, uint16_t value) | |
bc284a2a | 1166 | { |
d8515652 | 1167 | k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXPOL) | |
0830ada5 | 1168 | S626_SET_STD_INDXPOL(value != 0)), false); |
bc284a2a IA |
1169 | } |
1170 | ||
31de1948 IA |
1171 | static uint16_t s626_get_index_pol(struct comedi_device *dev, |
1172 | const struct s626_enc_info *k) | |
bc284a2a | 1173 | { |
0830ada5 | 1174 | return S626_GET_STD_INDXPOL(k->get_mode(dev, k)); |
bc284a2a IA |
1175 | } |
1176 | ||
1177 | /* | |
1178 | * Return/set the index source. | |
1179 | */ | |
31de1948 IA |
1180 | static void s626_set_index_src(struct comedi_device *dev, |
1181 | const struct s626_enc_info *k, uint16_t value) | |
bc284a2a | 1182 | { |
d8515652 | 1183 | k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXSRC) | |
0830ada5 | 1184 | S626_SET_STD_INDXSRC(value != 0)), false); |
bc284a2a IA |
1185 | } |
1186 | ||
31de1948 IA |
1187 | static uint16_t s626_get_index_src(struct comedi_device *dev, |
1188 | const struct s626_enc_info *k) | |
bc284a2a | 1189 | { |
0830ada5 | 1190 | return S626_GET_STD_INDXSRC(k->get_mode(dev, k)); |
bc284a2a IA |
1191 | } |
1192 | #endif | |
1193 | ||
1194 | /* | |
1195 | * Generate an index pulse. | |
1196 | */ | |
31de1948 IA |
1197 | static void s626_pulse_index_a(struct comedi_device *dev, |
1198 | const struct s626_enc_info *k) | |
bc284a2a IA |
1199 | { |
1200 | uint16_t cra; | |
1201 | ||
31de1948 | 1202 | cra = s626_debi_read(dev, k->my_cra); |
bc284a2a | 1203 | /* Pulse index. */ |
d8515652 | 1204 | s626_debi_write(dev, k->my_cra, (cra ^ S626_CRAMSK_INDXPOL_A)); |
31de1948 | 1205 | s626_debi_write(dev, k->my_cra, cra); |
bc284a2a IA |
1206 | } |
1207 | ||
31de1948 IA |
1208 | static void s626_pulse_index_b(struct comedi_device *dev, |
1209 | const struct s626_enc_info *k) | |
bc284a2a IA |
1210 | { |
1211 | uint16_t crb; | |
1212 | ||
d8515652 | 1213 | crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL; |
bc284a2a | 1214 | /* Pulse index. */ |
d8515652 | 1215 | s626_debi_write(dev, k->my_crb, (crb ^ S626_CRBMSK_INDXPOL_B)); |
31de1948 | 1216 | s626_debi_write(dev, k->my_crb, crb); |
bc284a2a IA |
1217 | } |
1218 | ||
3f1f219c IA |
1219 | static const struct s626_enc_info s626_enc_chan_info[] = { |
1220 | { | |
31de1948 IA |
1221 | .get_enable = s626_get_enable_a, |
1222 | .get_int_src = s626_get_int_src_a, | |
1223 | .get_load_trig = s626_get_load_trig_a, | |
1224 | .get_mode = s626_get_mode_a, | |
1225 | .pulse_index = s626_pulse_index_a, | |
1226 | .set_enable = s626_set_enable_a, | |
1227 | .set_int_src = s626_set_int_src_a, | |
1228 | .set_load_trig = s626_set_load_trig_a, | |
1229 | .set_mode = s626_set_mode_a, | |
1230 | .reset_cap_flags = s626_reset_cap_flags_a, | |
d8515652 IA |
1231 | .my_cra = S626_LP_CR0A, |
1232 | .my_crb = S626_LP_CR0B, | |
1233 | .my_latch_lsw = S626_LP_CNTR0ALSW, | |
676921c9 | 1234 | .my_event_bits = S626_EVBITS(0), |
3f1f219c | 1235 | }, { |
31de1948 IA |
1236 | .get_enable = s626_get_enable_a, |
1237 | .get_int_src = s626_get_int_src_a, | |
1238 | .get_load_trig = s626_get_load_trig_a, | |
1239 | .get_mode = s626_get_mode_a, | |
1240 | .pulse_index = s626_pulse_index_a, | |
1241 | .set_enable = s626_set_enable_a, | |
1242 | .set_int_src = s626_set_int_src_a, | |
1243 | .set_load_trig = s626_set_load_trig_a, | |
1244 | .set_mode = s626_set_mode_a, | |
1245 | .reset_cap_flags = s626_reset_cap_flags_a, | |
d8515652 IA |
1246 | .my_cra = S626_LP_CR1A, |
1247 | .my_crb = S626_LP_CR1B, | |
1248 | .my_latch_lsw = S626_LP_CNTR1ALSW, | |
676921c9 | 1249 | .my_event_bits = S626_EVBITS(1), |
3f1f219c | 1250 | }, { |
31de1948 IA |
1251 | .get_enable = s626_get_enable_a, |
1252 | .get_int_src = s626_get_int_src_a, | |
1253 | .get_load_trig = s626_get_load_trig_a, | |
1254 | .get_mode = s626_get_mode_a, | |
1255 | .pulse_index = s626_pulse_index_a, | |
1256 | .set_enable = s626_set_enable_a, | |
1257 | .set_int_src = s626_set_int_src_a, | |
1258 | .set_load_trig = s626_set_load_trig_a, | |
1259 | .set_mode = s626_set_mode_a, | |
1260 | .reset_cap_flags = s626_reset_cap_flags_a, | |
d8515652 IA |
1261 | .my_cra = S626_LP_CR2A, |
1262 | .my_crb = S626_LP_CR2B, | |
1263 | .my_latch_lsw = S626_LP_CNTR2ALSW, | |
676921c9 | 1264 | .my_event_bits = S626_EVBITS(2), |
3f1f219c | 1265 | }, { |
31de1948 IA |
1266 | .get_enable = s626_get_enable_b, |
1267 | .get_int_src = s626_get_int_src_b, | |
1268 | .get_load_trig = s626_get_load_trig_b, | |
1269 | .get_mode = s626_get_mode_b, | |
1270 | .pulse_index = s626_pulse_index_b, | |
1271 | .set_enable = s626_set_enable_b, | |
1272 | .set_int_src = s626_set_int_src_b, | |
1273 | .set_load_trig = s626_set_load_trig_b, | |
1274 | .set_mode = s626_set_mode_b, | |
1275 | .reset_cap_flags = s626_reset_cap_flags_b, | |
d8515652 IA |
1276 | .my_cra = S626_LP_CR0A, |
1277 | .my_crb = S626_LP_CR0B, | |
1278 | .my_latch_lsw = S626_LP_CNTR0BLSW, | |
676921c9 | 1279 | .my_event_bits = S626_EVBITS(3), |
3f1f219c | 1280 | }, { |
31de1948 IA |
1281 | .get_enable = s626_get_enable_b, |
1282 | .get_int_src = s626_get_int_src_b, | |
1283 | .get_load_trig = s626_get_load_trig_b, | |
1284 | .get_mode = s626_get_mode_b, | |
1285 | .pulse_index = s626_pulse_index_b, | |
1286 | .set_enable = s626_set_enable_b, | |
1287 | .set_int_src = s626_set_int_src_b, | |
1288 | .set_load_trig = s626_set_load_trig_b, | |
1289 | .set_mode = s626_set_mode_b, | |
1290 | .reset_cap_flags = s626_reset_cap_flags_b, | |
d8515652 IA |
1291 | .my_cra = S626_LP_CR1A, |
1292 | .my_crb = S626_LP_CR1B, | |
1293 | .my_latch_lsw = S626_LP_CNTR1BLSW, | |
676921c9 | 1294 | .my_event_bits = S626_EVBITS(4), |
3f1f219c | 1295 | }, { |
31de1948 IA |
1296 | .get_enable = s626_get_enable_b, |
1297 | .get_int_src = s626_get_int_src_b, | |
1298 | .get_load_trig = s626_get_load_trig_b, | |
1299 | .get_mode = s626_get_mode_b, | |
1300 | .pulse_index = s626_pulse_index_b, | |
1301 | .set_enable = s626_set_enable_b, | |
1302 | .set_int_src = s626_set_int_src_b, | |
1303 | .set_load_trig = s626_set_load_trig_b, | |
1304 | .set_mode = s626_set_mode_b, | |
1305 | .reset_cap_flags = s626_reset_cap_flags_b, | |
d8515652 IA |
1306 | .my_cra = S626_LP_CR2A, |
1307 | .my_crb = S626_LP_CR2B, | |
1308 | .my_latch_lsw = S626_LP_CNTR2BLSW, | |
676921c9 | 1309 | .my_event_bits = S626_EVBITS(5), |
3f1f219c IA |
1310 | }, |
1311 | }; | |
1312 | ||
5fd4b711 | 1313 | static unsigned int s626_ai_reg_to_uint(unsigned int data) |
11e865c1 | 1314 | { |
5fd4b711 | 1315 | return ((data >> 18) & 0x3fff) ^ 0x2000; |
020c44f3 | 1316 | } |
8231eb56 | 1317 | |
6baffbc2 HS |
1318 | static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan) |
1319 | { | |
100b4edc HS |
1320 | unsigned int group = chan / 16; |
1321 | unsigned int mask = 1 << (chan - (16 * group)); | |
6baffbc2 HS |
1322 | unsigned int status; |
1323 | ||
6baffbc2 | 1324 | /* set channel to capture positive edge */ |
d8515652 IA |
1325 | status = s626_debi_read(dev, S626_LP_RDEDGSEL(group)); |
1326 | s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status); | |
6baffbc2 HS |
1327 | |
1328 | /* enable interrupt on selected channel */ | |
d8515652 IA |
1329 | status = s626_debi_read(dev, S626_LP_RDINTSEL(group)); |
1330 | s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status); | |
6baffbc2 HS |
1331 | |
1332 | /* enable edge capture write command */ | |
d8515652 | 1333 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP); |
6baffbc2 HS |
1334 | |
1335 | /* enable edge capture on selected channel */ | |
d8515652 IA |
1336 | status = s626_debi_read(dev, S626_LP_RDCAPSEL(group)); |
1337 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status); | |
6baffbc2 HS |
1338 | |
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group, | |
1343 | unsigned int mask) | |
1344 | { | |
6baffbc2 | 1345 | /* disable edge capture write command */ |
d8515652 | 1346 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
6baffbc2 HS |
1347 | |
1348 | /* enable edge capture on selected channel */ | |
d8515652 | 1349 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask); |
6baffbc2 HS |
1350 | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | static int s626_dio_clear_irq(struct comedi_device *dev) | |
1355 | { | |
1356 | unsigned int group; | |
1357 | ||
1358 | /* disable edge capture write command */ | |
d8515652 | 1359 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
6baffbc2 | 1360 | |
100b4edc HS |
1361 | /* clear all dio pending events and interrupt */ |
1362 | for (group = 0; group < S626_DIO_BANKS; group++) | |
d8515652 | 1363 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); |
6baffbc2 HS |
1364 | |
1365 | return 0; | |
1366 | } | |
1367 | ||
31de1948 IA |
1368 | static void s626_handle_dio_interrupt(struct comedi_device *dev, |
1369 | uint16_t irqbit, uint8_t group) | |
65a17c29 HS |
1370 | { |
1371 | struct s626_private *devpriv = dev->private; | |
1372 | struct comedi_subdevice *s = dev->read_subdev; | |
1373 | struct comedi_cmd *cmd = &s->async->cmd; | |
1374 | ||
1375 | s626_dio_reset_irq(dev, group, irqbit); | |
1376 | ||
1377 | if (devpriv->ai_cmd_running) { | |
1378 | /* check if interrupt is an ai acquisition start trigger */ | |
1379 | if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 && | |
1380 | cmd->start_src == TRIG_EXT) { | |
1381 | /* Start executing the RPS program */ | |
d8515652 | 1382 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
65a17c29 HS |
1383 | |
1384 | if (cmd->scan_begin_src == TRIG_EXT) | |
1385 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
1386 | } | |
1387 | if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 && | |
1388 | cmd->scan_begin_src == TRIG_EXT) { | |
ddd9813e | 1389 | /* Trigger ADC scan loop start */ |
d8515652 | 1390 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
65a17c29 HS |
1391 | |
1392 | if (cmd->convert_src == TRIG_EXT) { | |
1393 | devpriv->ai_convert_count = cmd->chanlist_len; | |
1394 | ||
1395 | s626_dio_set_irq(dev, cmd->convert_arg); | |
1396 | } | |
1397 | ||
1398 | if (cmd->convert_src == TRIG_TIMER) { | |
3a305a66 IA |
1399 | const struct s626_enc_info *k = |
1400 | &s626_enc_chan_info[5]; | |
65a17c29 HS |
1401 | |
1402 | devpriv->ai_convert_count = cmd->chanlist_len; | |
d8515652 | 1403 | k->set_enable(dev, k, S626_CLKENAB_ALWAYS); |
65a17c29 HS |
1404 | } |
1405 | } | |
1406 | if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 && | |
1407 | cmd->convert_src == TRIG_EXT) { | |
ddd9813e | 1408 | /* Trigger ADC scan loop start */ |
d8515652 | 1409 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
65a17c29 HS |
1410 | |
1411 | devpriv->ai_convert_count--; | |
1412 | if (devpriv->ai_convert_count > 0) | |
1413 | s626_dio_set_irq(dev, cmd->convert_arg); | |
1414 | } | |
1415 | } | |
1416 | } | |
1417 | ||
31de1948 | 1418 | static void s626_check_dio_interrupts(struct comedi_device *dev) |
65a17c29 HS |
1419 | { |
1420 | uint16_t irqbit; | |
1421 | uint8_t group; | |
1422 | ||
1423 | for (group = 0; group < S626_DIO_BANKS; group++) { | |
1424 | irqbit = 0; | |
1425 | /* read interrupt type */ | |
d8515652 | 1426 | irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group)); |
65a17c29 HS |
1427 | |
1428 | /* check if interrupt is generated from dio channels */ | |
1429 | if (irqbit) { | |
31de1948 | 1430 | s626_handle_dio_interrupt(dev, irqbit, group); |
65a17c29 HS |
1431 | return; |
1432 | } | |
1433 | } | |
1434 | } | |
1435 | ||
31de1948 | 1436 | static void s626_check_counter_interrupts(struct comedi_device *dev) |
0b9675d5 HS |
1437 | { |
1438 | struct s626_private *devpriv = dev->private; | |
1439 | struct comedi_subdevice *s = dev->read_subdev; | |
1440 | struct comedi_async *async = s->async; | |
1441 | struct comedi_cmd *cmd = &async->cmd; | |
3a305a66 | 1442 | const struct s626_enc_info *k; |
0b9675d5 HS |
1443 | uint16_t irqbit; |
1444 | ||
1445 | /* read interrupt type */ | |
d8515652 | 1446 | irqbit = s626_debi_read(dev, S626_LP_RDMISC2); |
0b9675d5 HS |
1447 | |
1448 | /* check interrupt on counters */ | |
d8515652 | 1449 | if (irqbit & S626_IRQ_COINT1A) { |
3a305a66 | 1450 | k = &s626_enc_chan_info[0]; |
0b9675d5 HS |
1451 | |
1452 | /* clear interrupt capture flag */ | |
b075ac8e | 1453 | k->reset_cap_flags(dev, k); |
0b9675d5 | 1454 | } |
d8515652 | 1455 | if (irqbit & S626_IRQ_COINT2A) { |
3a305a66 | 1456 | k = &s626_enc_chan_info[1]; |
0b9675d5 HS |
1457 | |
1458 | /* clear interrupt capture flag */ | |
b075ac8e | 1459 | k->reset_cap_flags(dev, k); |
0b9675d5 | 1460 | } |
d8515652 | 1461 | if (irqbit & S626_IRQ_COINT3A) { |
3a305a66 | 1462 | k = &s626_enc_chan_info[2]; |
0b9675d5 HS |
1463 | |
1464 | /* clear interrupt capture flag */ | |
b075ac8e | 1465 | k->reset_cap_flags(dev, k); |
0b9675d5 | 1466 | } |
d8515652 | 1467 | if (irqbit & S626_IRQ_COINT1B) { |
3a305a66 | 1468 | k = &s626_enc_chan_info[3]; |
0b9675d5 HS |
1469 | |
1470 | /* clear interrupt capture flag */ | |
b075ac8e | 1471 | k->reset_cap_flags(dev, k); |
0b9675d5 | 1472 | } |
d8515652 | 1473 | if (irqbit & S626_IRQ_COINT2B) { |
3a305a66 | 1474 | k = &s626_enc_chan_info[4]; |
0b9675d5 HS |
1475 | |
1476 | /* clear interrupt capture flag */ | |
b075ac8e | 1477 | k->reset_cap_flags(dev, k); |
0b9675d5 HS |
1478 | |
1479 | if (devpriv->ai_convert_count > 0) { | |
1480 | devpriv->ai_convert_count--; | |
1481 | if (devpriv->ai_convert_count == 0) | |
d8515652 | 1482 | k->set_enable(dev, k, S626_CLKENAB_INDEX); |
0b9675d5 HS |
1483 | |
1484 | if (cmd->convert_src == TRIG_TIMER) { | |
ddd9813e | 1485 | /* Trigger ADC scan loop start */ |
d8515652 IA |
1486 | s626_mc_enable(dev, S626_MC2_ADC_RPS, |
1487 | S626_P_MC2); | |
0b9675d5 HS |
1488 | } |
1489 | } | |
1490 | } | |
d8515652 | 1491 | if (irqbit & S626_IRQ_COINT3B) { |
3a305a66 | 1492 | k = &s626_enc_chan_info[5]; |
0b9675d5 HS |
1493 | |
1494 | /* clear interrupt capture flag */ | |
b075ac8e | 1495 | k->reset_cap_flags(dev, k); |
0b9675d5 HS |
1496 | |
1497 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
ddd9813e | 1498 | /* Trigger ADC scan loop start */ |
d8515652 | 1499 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
0b9675d5 HS |
1500 | } |
1501 | ||
1502 | if (cmd->convert_src == TRIG_TIMER) { | |
3a305a66 | 1503 | k = &s626_enc_chan_info[4]; |
0b9675d5 | 1504 | devpriv->ai_convert_count = cmd->chanlist_len; |
d8515652 | 1505 | k->set_enable(dev, k, S626_CLKENAB_ALWAYS); |
0b9675d5 HS |
1506 | } |
1507 | } | |
1508 | } | |
1509 | ||
31de1948 | 1510 | static bool s626_handle_eos_interrupt(struct comedi_device *dev) |
4c2d13e0 HS |
1511 | { |
1512 | struct s626_private *devpriv = dev->private; | |
1513 | struct comedi_subdevice *s = dev->read_subdev; | |
1514 | struct comedi_async *async = s->async; | |
1515 | struct comedi_cmd *cmd = &async->cmd; | |
1516 | /* | |
1517 | * Init ptr to DMA buffer that holds new ADC data. We skip the | |
1518 | * first uint16_t in the buffer because it contains junk data | |
1519 | * from the final ADC of the previous poll list scan. | |
1520 | */ | |
5fd4b711 | 1521 | uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1; |
4c2d13e0 HS |
1522 | bool finished = false; |
1523 | int i; | |
1524 | ||
1525 | /* get the data and hand it over to comedi */ | |
1526 | for (i = 0; i < cmd->chanlist_len; i++) { | |
5fd4b711 | 1527 | unsigned short tempdata; |
4c2d13e0 HS |
1528 | |
1529 | /* | |
1530 | * Convert ADC data to 16-bit integer values and copy | |
1531 | * to application buffer. | |
1532 | */ | |
5fd4b711 | 1533 | tempdata = s626_ai_reg_to_uint(*readaddr); |
4c2d13e0 HS |
1534 | readaddr++; |
1535 | ||
1536 | /* put data into read buffer */ | |
1537 | /* comedi_buf_put(async, tempdata); */ | |
1538 | cfc_write_to_buffer(s, tempdata); | |
1539 | } | |
1540 | ||
1541 | /* end of scan occurs */ | |
1542 | async->events |= COMEDI_CB_EOS; | |
1543 | ||
e6132fc9 | 1544 | if (!devpriv->ai_continuous) |
4c2d13e0 HS |
1545 | devpriv->ai_sample_count--; |
1546 | if (devpriv->ai_sample_count <= 0) { | |
1547 | devpriv->ai_cmd_running = 0; | |
1548 | ||
c5cf4606 | 1549 | /* Stop RPS program */ |
d8515652 | 1550 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
4c2d13e0 HS |
1551 | |
1552 | /* send end of acquisition */ | |
1553 | async->events |= COMEDI_CB_EOA; | |
1554 | ||
1555 | /* disable master interrupt */ | |
1556 | finished = true; | |
1557 | } | |
1558 | ||
1559 | if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) | |
1560 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
1561 | ||
1562 | /* tell comedi that data is there */ | |
1563 | comedi_event(dev, s); | |
1564 | ||
1565 | return finished; | |
1566 | } | |
1567 | ||
020c44f3 HS |
1568 | static irqreturn_t s626_irq_handler(int irq, void *d) |
1569 | { | |
1570 | struct comedi_device *dev = d; | |
7f2f7e05 | 1571 | struct s626_private *devpriv = dev->private; |
020c44f3 | 1572 | unsigned long flags; |
020c44f3 | 1573 | uint32_t irqtype, irqstatus; |
11e865c1 | 1574 | |
a7401cdd | 1575 | if (!dev->attached) |
020c44f3 | 1576 | return IRQ_NONE; |
8ee52611 | 1577 | /* lock to avoid race with comedi_poll */ |
020c44f3 | 1578 | spin_lock_irqsave(&dev->spinlock, flags); |
11e865c1 | 1579 | |
020c44f3 | 1580 | /* save interrupt enable register state */ |
d8515652 | 1581 | irqstatus = readl(devpriv->mmio + S626_P_IER); |
11e865c1 | 1582 | |
020c44f3 | 1583 | /* read interrupt type */ |
d8515652 | 1584 | irqtype = readl(devpriv->mmio + S626_P_ISR); |
11e865c1 | 1585 | |
020c44f3 | 1586 | /* disable master interrupt */ |
d8515652 | 1587 | writel(0, devpriv->mmio + S626_P_IER); |
11e865c1 | 1588 | |
020c44f3 | 1589 | /* clear interrupt */ |
d8515652 | 1590 | writel(irqtype, devpriv->mmio + S626_P_ISR); |
11e865c1 | 1591 | |
020c44f3 | 1592 | switch (irqtype) { |
d8515652 | 1593 | case S626_IRQ_RPS1: /* end_of_scan occurs */ |
31de1948 | 1594 | if (s626_handle_eos_interrupt(dev)) |
020c44f3 | 1595 | irqstatus = 0; |
020c44f3 | 1596 | break; |
d8515652 | 1597 | case S626_IRQ_GPIO3: /* check dio and counter interrupt */ |
020c44f3 | 1598 | /* s626_dio_clear_irq(dev); */ |
31de1948 IA |
1599 | s626_check_dio_interrupts(dev); |
1600 | s626_check_counter_interrupts(dev); | |
0b9675d5 | 1601 | break; |
020c44f3 | 1602 | } |
11e865c1 | 1603 | |
020c44f3 | 1604 | /* enable interrupt */ |
d8515652 | 1605 | writel(irqstatus, devpriv->mmio + S626_P_IER); |
b6c77757 | 1606 | |
020c44f3 HS |
1607 | spin_unlock_irqrestore(&dev->spinlock, flags); |
1608 | return IRQ_HANDLED; | |
1609 | } | |
b6c77757 | 1610 | |
020c44f3 | 1611 | /* |
8ee52611 | 1612 | * This function builds the RPS program for hardware driven acquisition. |
020c44f3 | 1613 | */ |
31de1948 | 1614 | static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) |
020c44f3 | 1615 | { |
7f2f7e05 | 1616 | struct s626_private *devpriv = dev->private; |
9c9ab3c1 HS |
1617 | struct comedi_subdevice *s = dev->read_subdev; |
1618 | struct comedi_cmd *cmd = &s->async->cmd; | |
f1f7efce IA |
1619 | uint32_t *rps; |
1620 | uint32_t jmp_adrs; | |
020c44f3 HS |
1621 | uint16_t i; |
1622 | uint16_t n; | |
f1f7efce | 1623 | uint32_t local_ppl; |
11e865c1 | 1624 | |
c5cf4606 | 1625 | /* Stop RPS program in case it is currently running */ |
d8515652 | 1626 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 1627 | |
8ee52611 | 1628 | /* Set starting logical address to write RPS commands. */ |
f1f7efce | 1629 | rps = (uint32_t *)devpriv->rps_buf.logical_base; |
11e865c1 | 1630 | |
25f8fd5e | 1631 | /* Initialize RPS instruction pointer */ |
07a36d66 | 1632 | writel((uint32_t)devpriv->rps_buf.physical_base, |
d8515652 | 1633 | devpriv->mmio + S626_P_RPSADDR1); |
11e865c1 | 1634 | |
07a36d66 | 1635 | /* Construct RPS program in rps_buf DMA buffer */ |
020c44f3 | 1636 | if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) { |
8ee52611 | 1637 | /* Wait for Start trigger. */ |
d8515652 IA |
1638 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1639 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; | |
020c44f3 | 1640 | } |
11e865c1 | 1641 | |
8ee52611 IA |
1642 | /* |
1643 | * SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary | |
020c44f3 HS |
1644 | * because the first RPS DEBI Write following a non-RPS DEBI write |
1645 | * seems to always fail. If we don't do this dummy write, the ADC | |
1646 | * gain might not be set to the value required for the first slot in | |
1647 | * the poll list; the ADC gain would instead remain unchanged from | |
1648 | * the previously programmed value. | |
1649 | */ | |
020c44f3 | 1650 | /* Write DEBI Write command and address to shadow RAM. */ |
d8515652 IA |
1651 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1652 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; | |
1653 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); | |
8ee52611 | 1654 | /* Write DEBI immediate data to shadow RAM: */ |
d8515652 IA |
1655 | *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ |
1656 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; | |
8ee52611 | 1657 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 IA |
1658 | /* Invoke shadow RAM upload. */ |
1659 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; | |
1660 | /* Wait for shadow upload to finish. */ | |
1661 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; | |
11e865c1 | 1662 | |
8ee52611 IA |
1663 | /* |
1664 | * Digitize all slots in the poll list. This is implemented as a | |
020c44f3 | 1665 | * for loop to limit the slot count to 16 in case the application |
d8515652 | 1666 | * forgot to set the S626_EOPL flag in the final slot. |
020c44f3 | 1667 | */ |
07a36d66 IA |
1668 | for (devpriv->adc_items = 0; devpriv->adc_items < 16; |
1669 | devpriv->adc_items++) { | |
8ee52611 IA |
1670 | /* |
1671 | * Convert application's poll list item to private board class | |
020c44f3 HS |
1672 | * format. Each app poll list item is an uint8_t with form |
1673 | * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 = | |
1674 | * +-10V, 1 = +-5V, and EOPL = End of Poll List marker. | |
b6c77757 | 1675 | */ |
d8515652 IA |
1676 | local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V : |
1677 | S626_GSEL_BIPOLAR10V); | |
8ee52611 IA |
1678 | |
1679 | /* Switch ADC analog gain. */ | |
1680 | /* Write DEBI command and address to shadow RAM. */ | |
d8515652 IA |
1681 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1682 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; | |
8ee52611 | 1683 | /* Write DEBI immediate data to shadow RAM. */ |
d8515652 | 1684 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); |
f1f7efce | 1685 | *rps++ = local_ppl; |
8ee52611 | 1686 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 | 1687 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
8ee52611 | 1688 | /* Invoke shadow RAM upload. */ |
d8515652 | 1689 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
8ee52611 | 1690 | /* Wait for shadow upload to finish. */ |
d8515652 | 1691 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
8ee52611 | 1692 | /* Select ADC analog input channel. */ |
d8515652 | 1693 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
8ee52611 | 1694 | /* Write DEBI command and address to shadow RAM. */ |
d8515652 IA |
1695 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL; |
1696 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); | |
8ee52611 | 1697 | /* Write DEBI immediate data to shadow RAM. */ |
f1f7efce | 1698 | *rps++ = local_ppl; |
8ee52611 | 1699 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 | 1700 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
8ee52611 | 1701 | /* Invoke shadow RAM upload. */ |
d8515652 | 1702 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
8ee52611 | 1703 | /* Wait for shadow upload to finish. */ |
d8515652 | 1704 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
11e865c1 | 1705 | |
8ee52611 IA |
1706 | /* |
1707 | * Delay at least 10 microseconds for analog input settling. | |
d8515652 IA |
1708 | * Instead of padding with NOPs, we use S626_RPS_JUMP |
1709 | * instructions here; this allows us to produce a longer delay | |
1710 | * than is possible with NOPs because each S626_RPS_JUMP | |
1711 | * flushes the RPS' instruction prefetch pipeline. | |
020c44f3 | 1712 | */ |
f1f7efce | 1713 | jmp_adrs = |
07a36d66 | 1714 | (uint32_t)devpriv->rps_buf.physical_base + |
f1f7efce | 1715 | (uint32_t)((unsigned long)rps - |
07a36d66 IA |
1716 | (unsigned long)devpriv-> |
1717 | rps_buf.logical_base); | |
d8515652 | 1718 | for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) { |
f1f7efce | 1719 | jmp_adrs += 8; /* Repeat to implement time delay: */ |
d8515652 IA |
1720 | /* Jump to next RPS instruction. */ |
1721 | *rps++ = S626_RPS_JUMP; | |
f1f7efce | 1722 | *rps++ = jmp_adrs; |
020c44f3 | 1723 | } |
11e865c1 | 1724 | |
020c44f3 | 1725 | if (cmd != NULL && cmd->convert_src != TRIG_NOW) { |
8ee52611 | 1726 | /* Wait for Start trigger. */ |
d8515652 IA |
1727 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1728 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; | |
020c44f3 | 1729 | } |
8ee52611 IA |
1730 | /* Start ADC by pulsing GPIO1. */ |
1731 | /* Begin ADC Start pulse. */ | |
d8515652 IA |
1732 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1733 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; | |
1734 | *rps++ = S626_RPS_NOP; | |
8ee52611 IA |
1735 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
1736 | /* End ADC Start pulse. */ | |
d8515652 IA |
1737 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1738 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; | |
8ee52611 IA |
1739 | /* |
1740 | * Wait for ADC to complete (GPIO2 is asserted high when ADC not | |
020c44f3 HS |
1741 | * busy) and for data from previous conversion to shift into FB |
1742 | * BUFFER 1 register. | |
1743 | */ | |
d8515652 IA |
1744 | /* Wait for ADC done. */ |
1745 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; | |
11e865c1 | 1746 | |
8ee52611 | 1747 | /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */ |
d8515652 IA |
1748 | *rps++ = S626_RPS_STREG | |
1749 | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); | |
f1f7efce IA |
1750 | *rps++ = (uint32_t)devpriv->ana_buf.physical_base + |
1751 | (devpriv->adc_items << 2); | |
11e865c1 | 1752 | |
8ee52611 IA |
1753 | /* |
1754 | * If this slot's EndOfPollList flag is set, all channels have | |
1755 | * now been processed. | |
1756 | */ | |
d8515652 | 1757 | if (*ppl++ & S626_EOPL) { |
07a36d66 | 1758 | devpriv->adc_items++; /* Adjust poll list item count. */ |
8ee52611 | 1759 | break; /* Exit poll list processing loop. */ |
020c44f3 HS |
1760 | } |
1761 | } | |
11e865c1 | 1762 | |
8ee52611 IA |
1763 | /* |
1764 | * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the | |
020c44f3 HS |
1765 | * ADC to stabilize for 2 microseconds before starting the final |
1766 | * (dummy) conversion. This delay is necessary to allow sufficient | |
1767 | * time between last conversion finished and the start of the dummy | |
1768 | * conversion. Without this delay, the last conversion's data value | |
1769 | * is sometimes set to the previous conversion's data value. | |
1770 | */ | |
d8515652 IA |
1771 | for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++) |
1772 | *rps++ = S626_RPS_NOP; | |
11e865c1 | 1773 | |
8ee52611 IA |
1774 | /* |
1775 | * Start a dummy conversion to cause the data from the last | |
020c44f3 HS |
1776 | * conversion of interest to be shifted in. |
1777 | */ | |
d8515652 IA |
1778 | /* Begin ADC Start pulse. */ |
1779 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); | |
1780 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; | |
1781 | *rps++ = S626_RPS_NOP; | |
020c44f3 | 1782 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
d8515652 IA |
1783 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */ |
1784 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; | |
11e865c1 | 1785 | |
8ee52611 IA |
1786 | /* |
1787 | * Wait for the data from the last conversion of interest to arrive | |
020c44f3 HS |
1788 | * in FB BUFFER 1 register. |
1789 | */ | |
d8515652 | 1790 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */ |
11e865c1 | 1791 | |
8ee52611 | 1792 | /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */ |
d8515652 | 1793 | *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); |
f1f7efce IA |
1794 | *rps++ = (uint32_t)devpriv->ana_buf.physical_base + |
1795 | (devpriv->adc_items << 2); | |
11e865c1 | 1796 | |
8ee52611 IA |
1797 | /* Indicate ADC scan loop is finished. */ |
1798 | /* Signal ReadADC() that scan is done. */ | |
d8515652 | 1799 | /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */ |
11e865c1 | 1800 | |
020c44f3 | 1801 | /* invoke interrupt */ |
8ee52611 | 1802 | if (devpriv->ai_cmd_running == 1) |
d8515652 | 1803 | *rps++ = S626_RPS_IRQ; |
11e865c1 | 1804 | |
8ee52611 | 1805 | /* Restart RPS program at its beginning. */ |
d8515652 | 1806 | *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */ |
f1f7efce | 1807 | *rps++ = (uint32_t)devpriv->rps_buf.physical_base; |
8ee52611 IA |
1808 | |
1809 | /* End of RPS program build */ | |
020c44f3 | 1810 | } |
11e865c1 | 1811 | |
e4632a71 HS |
1812 | #ifdef unused_code |
1813 | static int s626_ai_rinsn(struct comedi_device *dev, | |
1814 | struct comedi_subdevice *s, | |
1815 | struct comedi_insn *insn, | |
1816 | unsigned int *data) | |
1817 | { | |
1818 | struct s626_private *devpriv = dev->private; | |
8ee52611 IA |
1819 | uint8_t i; |
1820 | int32_t *readaddr; | |
11e865c1 | 1821 | |
ddd9813e | 1822 | /* Trigger ADC scan loop start */ |
d8515652 | 1823 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
11e865c1 | 1824 | |
e4632a71 | 1825 | /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */ |
d8515652 | 1826 | while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2)) |
e4632a71 | 1827 | ; |
11e865c1 | 1828 | |
e4632a71 HS |
1829 | /* |
1830 | * Init ptr to DMA buffer that holds new ADC data. We skip the | |
1831 | * first uint16_t in the buffer because it contains junk data from | |
1832 | * the final ADC of the previous poll list scan. | |
1833 | */ | |
07a36d66 | 1834 | readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1; |
11e865c1 | 1835 | |
e4632a71 HS |
1836 | /* |
1837 | * Convert ADC data to 16-bit integer values and | |
1838 | * copy to application buffer. | |
1839 | */ | |
07a36d66 | 1840 | for (i = 0; i < devpriv->adc_items; i++) { |
e4632a71 HS |
1841 | *data = s626_ai_reg_to_uint(*readaddr++); |
1842 | data++; | |
1843 | } | |
11e865c1 | 1844 | |
e4632a71 HS |
1845 | return i; |
1846 | } | |
1847 | #endif | |
11e865c1 | 1848 | |
020c44f3 HS |
1849 | static int s626_ai_insn_read(struct comedi_device *dev, |
1850 | struct comedi_subdevice *s, | |
1851 | struct comedi_insn *insn, unsigned int *data) | |
1852 | { | |
7f2f7e05 | 1853 | struct s626_private *devpriv = dev->private; |
020c44f3 HS |
1854 | uint16_t chan = CR_CHAN(insn->chanspec); |
1855 | uint16_t range = CR_RANGE(insn->chanspec); | |
f1f7efce IA |
1856 | uint16_t adc_spec = 0; |
1857 | uint32_t gpio_image; | |
5fd4b711 | 1858 | uint32_t tmp; |
020c44f3 | 1859 | int n; |
11e865c1 | 1860 | |
8ee52611 IA |
1861 | /* |
1862 | * Convert application's ADC specification into form | |
020c44f3 HS |
1863 | * appropriate for register programming. |
1864 | */ | |
1865 | if (range == 0) | |
d8515652 | 1866 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V); |
020c44f3 | 1867 | else |
d8515652 | 1868 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V); |
11e865c1 | 1869 | |
8ee52611 | 1870 | /* Switch ADC analog gain. */ |
d8515652 | 1871 | s626_debi_write(dev, S626_LP_GSEL, adc_spec); /* Set gain. */ |
11e865c1 | 1872 | |
8ee52611 | 1873 | /* Select ADC analog input channel. */ |
d8515652 | 1874 | s626_debi_write(dev, S626_LP_ISEL, adc_spec); /* Select channel. */ |
11e865c1 | 1875 | |
020c44f3 | 1876 | for (n = 0; n < insn->n; n++) { |
8ee52611 | 1877 | /* Delay 10 microseconds for analog input settling. */ |
020c44f3 | 1878 | udelay(10); |
11e865c1 | 1879 | |
be008602 | 1880 | /* Start ADC by pulsing GPIO1 low */ |
d8515652 | 1881 | gpio_image = readl(devpriv->mmio + S626_P_GPIO); |
25f8fd5e | 1882 | /* Assert ADC Start command */ |
d8515652 IA |
1883 | writel(gpio_image & ~S626_GPIO1_HI, |
1884 | devpriv->mmio + S626_P_GPIO); | |
25f8fd5e | 1885 | /* and stretch it out */ |
d8515652 IA |
1886 | writel(gpio_image & ~S626_GPIO1_HI, |
1887 | devpriv->mmio + S626_P_GPIO); | |
1888 | writel(gpio_image & ~S626_GPIO1_HI, | |
1889 | devpriv->mmio + S626_P_GPIO); | |
25f8fd5e | 1890 | /* Negate ADC Start command */ |
d8515652 | 1891 | writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); |
11e865c1 | 1892 | |
8ee52611 IA |
1893 | /* |
1894 | * Wait for ADC to complete (GPIO2 is asserted high when | |
1895 | * ADC not busy) and for data from previous conversion to | |
1896 | * shift into FB BUFFER 1 register. | |
1897 | */ | |
11e865c1 | 1898 | |
be008602 | 1899 | /* Wait for ADC done */ |
d8515652 | 1900 | while (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_GPIO2)) |
020c44f3 | 1901 | ; |
11e865c1 | 1902 | |
be008602 HS |
1903 | /* Fetch ADC data */ |
1904 | if (n != 0) { | |
d8515652 | 1905 | tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1); |
be008602 HS |
1906 | data[n - 1] = s626_ai_reg_to_uint(tmp); |
1907 | } | |
11e865c1 | 1908 | |
8ee52611 IA |
1909 | /* |
1910 | * Allow the ADC to stabilize for 4 microseconds before | |
020c44f3 HS |
1911 | * starting the next (final) conversion. This delay is |
1912 | * necessary to allow sufficient time between last | |
1913 | * conversion finished and the start of the next | |
1914 | * conversion. Without this delay, the last conversion's | |
1915 | * data value is sometimes set to the previous | |
1916 | * conversion's data value. | |
1917 | */ | |
1918 | udelay(4); | |
1919 | } | |
11e865c1 | 1920 | |
8ee52611 IA |
1921 | /* |
1922 | * Start a dummy conversion to cause the data from the | |
1923 | * previous conversion to be shifted in. | |
1924 | */ | |
d8515652 | 1925 | gpio_image = readl(devpriv->mmio + S626_P_GPIO); |
020c44f3 | 1926 | /* Assert ADC Start command */ |
d8515652 | 1927 | writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); |
25f8fd5e | 1928 | /* and stretch it out */ |
d8515652 IA |
1929 | writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); |
1930 | writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); | |
25f8fd5e | 1931 | /* Negate ADC Start command */ |
d8515652 | 1932 | writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); |
11e865c1 | 1933 | |
8ee52611 | 1934 | /* Wait for the data to arrive in FB BUFFER 1 register. */ |
11e865c1 | 1935 | |
be008602 | 1936 | /* Wait for ADC done */ |
d8515652 | 1937 | while (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_GPIO2)) |
020c44f3 | 1938 | ; |
11e865c1 | 1939 | |
8ee52611 | 1940 | /* Fetch ADC data from audio interface's input shift register. */ |
11e865c1 | 1941 | |
be008602 HS |
1942 | /* Fetch ADC data */ |
1943 | if (n != 0) { | |
d8515652 | 1944 | tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1); |
be008602 HS |
1945 | data[n - 1] = s626_ai_reg_to_uint(tmp); |
1946 | } | |
11e865c1 | 1947 | |
020c44f3 HS |
1948 | return n; |
1949 | } | |
11e865c1 | 1950 | |
020c44f3 HS |
1951 | static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd) |
1952 | { | |
020c44f3 | 1953 | int n; |
11e865c1 | 1954 | |
020c44f3 | 1955 | for (n = 0; n < cmd->chanlist_len; n++) { |
8ee52611 | 1956 | if (CR_RANGE(cmd->chanlist[n]) == 0) |
d8515652 | 1957 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V; |
020c44f3 | 1958 | else |
d8515652 | 1959 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V; |
020c44f3 HS |
1960 | } |
1961 | if (n != 0) | |
d8515652 | 1962 | ppl[n - 1] |= S626_EOPL; |
11e865c1 | 1963 | |
020c44f3 HS |
1964 | return n; |
1965 | } | |
11e865c1 | 1966 | |
020c44f3 HS |
1967 | static int s626_ai_inttrig(struct comedi_device *dev, |
1968 | struct comedi_subdevice *s, unsigned int trignum) | |
1969 | { | |
1970 | if (trignum != 0) | |
1971 | return -EINVAL; | |
11e865c1 | 1972 | |
ddd9813e | 1973 | /* Start executing the RPS program */ |
d8515652 | 1974 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 1975 | |
020c44f3 | 1976 | s->async->inttrig = NULL; |
11e865c1 | 1977 | |
020c44f3 HS |
1978 | return 1; |
1979 | } | |
11e865c1 | 1980 | |
8ee52611 IA |
1981 | /* |
1982 | * This function doesn't require a particular form, this is just what | |
6baffbc2 HS |
1983 | * happens to be used in some of the drivers. It should convert ns |
1984 | * nanoseconds to a counter value suitable for programming the device. | |
1985 | * Also, it should adjust ns so that it cooresponds to the actual time | |
8ee52611 IA |
1986 | * that the device will use. |
1987 | */ | |
6baffbc2 HS |
1988 | static int s626_ns_to_timer(int *nanosec, int round_mode) |
1989 | { | |
1990 | int divider, base; | |
1991 | ||
1992 | base = 500; /* 2MHz internal clock */ | |
1993 | ||
1994 | switch (round_mode) { | |
1995 | case TRIG_ROUND_NEAREST: | |
1996 | default: | |
1997 | divider = (*nanosec + base / 2) / base; | |
1998 | break; | |
1999 | case TRIG_ROUND_DOWN: | |
2000 | divider = (*nanosec) / base; | |
2001 | break; | |
2002 | case TRIG_ROUND_UP: | |
2003 | divider = (*nanosec + base - 1) / base; | |
2004 | break; | |
2005 | } | |
2006 | ||
2007 | *nanosec = base * divider; | |
2008 | return divider - 1; | |
2009 | } | |
2010 | ||
3a305a66 IA |
2011 | static void s626_timer_load(struct comedi_device *dev, |
2012 | const struct s626_enc_info *k, int tick) | |
e3eb08d0 | 2013 | { |
f1f7efce | 2014 | uint16_t setup = |
d8515652 | 2015 | /* Preload upon index. */ |
0830ada5 | 2016 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 2017 | /* Disable hardware index. */ |
0830ada5 | 2018 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 2019 | /* Operating mode is Timer. */ |
0830ada5 | 2020 | S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) | |
d8515652 | 2021 | /* Count direction is Down. */ |
0830ada5 | 2022 | S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) | |
d8515652 | 2023 | /* Clock multiplier is 1x. */ |
0830ada5 IA |
2024 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
2025 | /* Enabled by index */ | |
2026 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); | |
d8515652 IA |
2027 | uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA; |
2028 | /* uint16_t enab = S626_CLKENAB_ALWAYS; */ | |
e3eb08d0 | 2029 | |
c3e3a56d | 2030 | k->set_mode(dev, k, setup, false); |
e3eb08d0 | 2031 | |
8ee52611 | 2032 | /* Set the preload register */ |
31de1948 | 2033 | s626_preload(dev, k, tick); |
e3eb08d0 | 2034 | |
8ee52611 IA |
2035 | /* |
2036 | * Software index pulse forces the preload register to load | |
2037 | * into the counter | |
2038 | */ | |
b075ac8e IA |
2039 | k->set_load_trig(dev, k, 0); |
2040 | k->pulse_index(dev, k); | |
e3eb08d0 HS |
2041 | |
2042 | /* set reload on counter overflow */ | |
b075ac8e | 2043 | k->set_load_trig(dev, k, 1); |
e3eb08d0 HS |
2044 | |
2045 | /* set interrupt on overflow */ | |
d8515652 | 2046 | k->set_int_src(dev, k, S626_INTSRC_OVER); |
e3eb08d0 | 2047 | |
31de1948 | 2048 | s626_set_latch_source(dev, k, value_latchsrc); |
b075ac8e | 2049 | /* k->set_enable(dev, k, (uint16_t)(enab != 0)); */ |
e3eb08d0 HS |
2050 | } |
2051 | ||
8ee52611 | 2052 | /* TO COMPLETE */ |
020c44f3 HS |
2053 | static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
2054 | { | |
7f2f7e05 | 2055 | struct s626_private *devpriv = dev->private; |
020c44f3 HS |
2056 | uint8_t ppl[16]; |
2057 | struct comedi_cmd *cmd = &s->async->cmd; | |
3a305a66 | 2058 | const struct s626_enc_info *k; |
020c44f3 | 2059 | int tick; |
11e865c1 | 2060 | |
020c44f3 | 2061 | if (devpriv->ai_cmd_running) { |
730b8e15 IA |
2062 | dev_err(dev->class_dev, |
2063 | "s626_ai_cmd: Another ai_cmd is running\n"); | |
020c44f3 HS |
2064 | return -EBUSY; |
2065 | } | |
2066 | /* disable interrupt */ | |
d8515652 | 2067 | writel(0, devpriv->mmio + S626_P_IER); |
11e865c1 | 2068 | |
020c44f3 | 2069 | /* clear interrupt request */ |
d8515652 | 2070 | writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, devpriv->mmio + S626_P_ISR); |
11e865c1 | 2071 | |
020c44f3 HS |
2072 | /* clear any pending interrupt */ |
2073 | s626_dio_clear_irq(dev); | |
8ee52611 | 2074 | /* s626_enc_clear_irq(dev); */ |
11e865c1 | 2075 | |
020c44f3 HS |
2076 | /* reset ai_cmd_running flag */ |
2077 | devpriv->ai_cmd_running = 0; | |
11e865c1 | 2078 | |
8ee52611 | 2079 | /* test if cmd is valid */ |
bdf5aa39 | 2080 | if (cmd == NULL) |
020c44f3 | 2081 | return -EINVAL; |
11e865c1 | 2082 | |
020c44f3 HS |
2083 | s626_ai_load_polllist(ppl, cmd); |
2084 | devpriv->ai_cmd_running = 1; | |
2085 | devpriv->ai_convert_count = 0; | |
11e865c1 | 2086 | |
020c44f3 HS |
2087 | switch (cmd->scan_begin_src) { |
2088 | case TRIG_FOLLOW: | |
2089 | break; | |
2090 | case TRIG_TIMER: | |
8ee52611 IA |
2091 | /* |
2092 | * set a counter to generate adc trigger at scan_begin_arg | |
2093 | * interval | |
2094 | */ | |
3a305a66 | 2095 | k = &s626_enc_chan_info[5]; |
020c44f3 HS |
2096 | tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg, |
2097 | cmd->flags & TRIG_ROUND_MASK); | |
11e865c1 | 2098 | |
020c44f3 HS |
2099 | /* load timer value and enable interrupt */ |
2100 | s626_timer_load(dev, k, tick); | |
d8515652 | 2101 | k->set_enable(dev, k, S626_CLKENAB_ALWAYS); |
020c44f3 HS |
2102 | break; |
2103 | case TRIG_EXT: | |
8ee52611 | 2104 | /* set the digital line and interrupt for scan trigger */ |
020c44f3 HS |
2105 | if (cmd->start_src != TRIG_EXT) |
2106 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
020c44f3 HS |
2107 | break; |
2108 | } | |
11e865c1 | 2109 | |
020c44f3 HS |
2110 | switch (cmd->convert_src) { |
2111 | case TRIG_NOW: | |
2112 | break; | |
2113 | case TRIG_TIMER: | |
8ee52611 IA |
2114 | /* |
2115 | * set a counter to generate adc trigger at convert_arg | |
2116 | * interval | |
2117 | */ | |
3a305a66 | 2118 | k = &s626_enc_chan_info[4]; |
020c44f3 HS |
2119 | tick = s626_ns_to_timer((int *)&cmd->convert_arg, |
2120 | cmd->flags & TRIG_ROUND_MASK); | |
11e865c1 | 2121 | |
020c44f3 HS |
2122 | /* load timer value and enable interrupt */ |
2123 | s626_timer_load(dev, k, tick); | |
d8515652 | 2124 | k->set_enable(dev, k, S626_CLKENAB_INDEX); |
020c44f3 HS |
2125 | break; |
2126 | case TRIG_EXT: | |
8ee52611 IA |
2127 | /* set the digital line and interrupt for convert trigger */ |
2128 | if (cmd->scan_begin_src != TRIG_EXT && | |
2129 | cmd->start_src == TRIG_EXT) | |
020c44f3 | 2130 | s626_dio_set_irq(dev, cmd->convert_arg); |
020c44f3 HS |
2131 | break; |
2132 | } | |
11e865c1 | 2133 | |
020c44f3 HS |
2134 | switch (cmd->stop_src) { |
2135 | case TRIG_COUNT: | |
8ee52611 | 2136 | /* data arrives as one packet */ |
020c44f3 | 2137 | devpriv->ai_sample_count = cmd->stop_arg; |
e6132fc9 | 2138 | devpriv->ai_continuous = 0; |
020c44f3 HS |
2139 | break; |
2140 | case TRIG_NONE: | |
8ee52611 | 2141 | /* continuous acquisition */ |
e6132fc9 | 2142 | devpriv->ai_continuous = 1; |
e4317ce8 | 2143 | devpriv->ai_sample_count = 1; |
020c44f3 | 2144 | break; |
11e865c1 | 2145 | } |
11e865c1 | 2146 | |
31de1948 | 2147 | s626_reset_adc(dev, ppl); |
11e865c1 | 2148 | |
020c44f3 HS |
2149 | switch (cmd->start_src) { |
2150 | case TRIG_NOW: | |
ddd9813e | 2151 | /* Trigger ADC scan loop start */ |
d8515652 | 2152 | /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */ |
11e865c1 | 2153 | |
ddd9813e | 2154 | /* Start executing the RPS program */ |
d8515652 | 2155 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
020c44f3 HS |
2156 | s->async->inttrig = NULL; |
2157 | break; | |
2158 | case TRIG_EXT: | |
2159 | /* configure DIO channel for acquisition trigger */ | |
2160 | s626_dio_set_irq(dev, cmd->start_arg); | |
020c44f3 HS |
2161 | s->async->inttrig = NULL; |
2162 | break; | |
2163 | case TRIG_INT: | |
2164 | s->async->inttrig = s626_ai_inttrig; | |
2165 | break; | |
11e865c1 | 2166 | } |
b6c77757 | 2167 | |
020c44f3 | 2168 | /* enable interrupt */ |
d8515652 | 2169 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, devpriv->mmio + S626_P_IER); |
b6c77757 | 2170 | |
020c44f3 HS |
2171 | return 0; |
2172 | } | |
b6c77757 | 2173 | |
020c44f3 HS |
2174 | static int s626_ai_cmdtest(struct comedi_device *dev, |
2175 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
2176 | { | |
2177 | int err = 0; | |
2178 | int tmp; | |
b6c77757 | 2179 | |
27020ffe | 2180 | /* Step 1 : check if triggers are trivially valid */ |
b6c77757 | 2181 | |
27020ffe | 2182 | err |= cfc_check_trigger_src(&cmd->start_src, |
8ee52611 | 2183 | TRIG_NOW | TRIG_INT | TRIG_EXT); |
27020ffe | 2184 | err |= cfc_check_trigger_src(&cmd->scan_begin_src, |
8ee52611 | 2185 | TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW); |
27020ffe | 2186 | err |= cfc_check_trigger_src(&cmd->convert_src, |
8ee52611 | 2187 | TRIG_TIMER | TRIG_EXT | TRIG_NOW); |
27020ffe HS |
2188 | err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
2189 | err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
11e865c1 | 2190 | |
020c44f3 HS |
2191 | if (err) |
2192 | return 1; | |
11e865c1 | 2193 | |
27020ffe | 2194 | /* Step 2a : make sure trigger sources are unique */ |
11e865c1 | 2195 | |
27020ffe HS |
2196 | err |= cfc_check_trigger_is_unique(cmd->start_src); |
2197 | err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); | |
2198 | err |= cfc_check_trigger_is_unique(cmd->convert_src); | |
2199 | err |= cfc_check_trigger_is_unique(cmd->stop_src); | |
2200 | ||
2201 | /* Step 2b : and mutually compatible */ | |
020c44f3 HS |
2202 | |
2203 | if (err) | |
2204 | return 2; | |
2205 | ||
2206 | /* step 3: make sure arguments are trivially compatible */ | |
2207 | ||
53a254b9 HS |
2208 | if (cmd->start_src != TRIG_EXT) |
2209 | err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); | |
2210 | if (cmd->start_src == TRIG_EXT) | |
2211 | err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39); | |
53a254b9 HS |
2212 | if (cmd->scan_begin_src == TRIG_EXT) |
2213 | err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39); | |
53a254b9 HS |
2214 | if (cmd->convert_src == TRIG_EXT) |
2215 | err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39); | |
11e865c1 | 2216 | |
676921c9 IA |
2217 | #define S626_MAX_SPEED 200000 /* in nanoseconds */ |
2218 | #define S626_MIN_SPEED 2000000000 /* in nanoseconds */ | |
11e865c1 | 2219 | |
020c44f3 | 2220 | if (cmd->scan_begin_src == TRIG_TIMER) { |
53a254b9 | 2221 | err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, |
676921c9 | 2222 | S626_MAX_SPEED); |
53a254b9 | 2223 | err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, |
676921c9 | 2224 | S626_MIN_SPEED); |
020c44f3 HS |
2225 | } else { |
2226 | /* external trigger */ | |
2227 | /* should be level/edge, hi/lo specification here */ | |
2228 | /* should specify multiple external triggers */ | |
8ee52611 | 2229 | /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */ |
020c44f3 HS |
2230 | } |
2231 | if (cmd->convert_src == TRIG_TIMER) { | |
676921c9 IA |
2232 | err |= cfc_check_trigger_arg_min(&cmd->convert_arg, |
2233 | S626_MAX_SPEED); | |
2234 | err |= cfc_check_trigger_arg_max(&cmd->convert_arg, | |
2235 | S626_MIN_SPEED); | |
020c44f3 HS |
2236 | } else { |
2237 | /* external trigger */ | |
2238 | /* see above */ | |
8ee52611 | 2239 | /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */ |
020c44f3 | 2240 | } |
11e865c1 | 2241 | |
53a254b9 HS |
2242 | err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); |
2243 | ||
2244 | if (cmd->stop_src == TRIG_COUNT) | |
2245 | err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); | |
2246 | else /* TRIG_NONE */ | |
2247 | err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); | |
11e865c1 | 2248 | |
020c44f3 HS |
2249 | if (err) |
2250 | return 3; | |
2251 | ||
2252 | /* step 4: fix up any arguments */ | |
2253 | ||
2254 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
2255 | tmp = cmd->scan_begin_arg; | |
2256 | s626_ns_to_timer((int *)&cmd->scan_begin_arg, | |
2257 | cmd->flags & TRIG_ROUND_MASK); | |
2258 | if (tmp != cmd->scan_begin_arg) | |
2259 | err++; | |
2260 | } | |
2261 | if (cmd->convert_src == TRIG_TIMER) { | |
2262 | tmp = cmd->convert_arg; | |
2263 | s626_ns_to_timer((int *)&cmd->convert_arg, | |
2264 | cmd->flags & TRIG_ROUND_MASK); | |
2265 | if (tmp != cmd->convert_arg) | |
2266 | err++; | |
2267 | if (cmd->scan_begin_src == TRIG_TIMER && | |
8ee52611 IA |
2268 | cmd->scan_begin_arg < cmd->convert_arg * |
2269 | cmd->scan_end_arg) { | |
2270 | cmd->scan_begin_arg = cmd->convert_arg * | |
2271 | cmd->scan_end_arg; | |
020c44f3 HS |
2272 | err++; |
2273 | } | |
11e865c1 | 2274 | } |
11e865c1 | 2275 | |
020c44f3 HS |
2276 | if (err) |
2277 | return 4; | |
2278 | ||
2279 | return 0; | |
11e865c1 GP |
2280 | } |
2281 | ||
020c44f3 | 2282 | static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
11e865c1 | 2283 | { |
7f2f7e05 HS |
2284 | struct s626_private *devpriv = dev->private; |
2285 | ||
c5cf4606 | 2286 | /* Stop RPS program in case it is currently running */ |
d8515652 | 2287 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 2288 | |
020c44f3 | 2289 | /* disable master interrupt */ |
d8515652 | 2290 | writel(0, devpriv->mmio + S626_P_IER); |
11e865c1 | 2291 | |
020c44f3 | 2292 | devpriv->ai_cmd_running = 0; |
11e865c1 | 2293 | |
020c44f3 HS |
2294 | return 0; |
2295 | } | |
11e865c1 | 2296 | |
020c44f3 HS |
2297 | static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, |
2298 | struct comedi_insn *insn, unsigned int *data) | |
11e865c1 | 2299 | { |
7f2f7e05 | 2300 | struct s626_private *devpriv = dev->private; |
020c44f3 | 2301 | int i; |
11e865c1 | 2302 | uint16_t chan = CR_CHAN(insn->chanspec); |
020c44f3 | 2303 | int16_t dacdata; |
11e865c1 | 2304 | |
020c44f3 HS |
2305 | for (i = 0; i < insn->n; i++) { |
2306 | dacdata = (int16_t) data[i]; | |
2307 | devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i]; | |
2308 | dacdata -= (0x1fff); | |
11e865c1 | 2309 | |
31de1948 | 2310 | s626_set_dac(dev, chan, dacdata); |
020c44f3 | 2311 | } |
11e865c1 | 2312 | |
020c44f3 HS |
2313 | return i; |
2314 | } | |
11e865c1 | 2315 | |
020c44f3 HS |
2316 | static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
2317 | struct comedi_insn *insn, unsigned int *data) | |
2318 | { | |
7f2f7e05 | 2319 | struct s626_private *devpriv = dev->private; |
020c44f3 | 2320 | int i; |
11e865c1 | 2321 | |
020c44f3 HS |
2322 | for (i = 0; i < insn->n; i++) |
2323 | data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)]; | |
11e865c1 | 2324 | |
020c44f3 HS |
2325 | return i; |
2326 | } | |
11e865c1 | 2327 | |
8ee52611 IA |
2328 | /* *************** DIGITAL I/O FUNCTIONS *************** */ |
2329 | ||
2330 | /* | |
020c44f3 HS |
2331 | * All DIO functions address a group of DIO channels by means of |
2332 | * "group" argument. group may be 0, 1 or 2, which correspond to DIO | |
2333 | * ports A, B and C, respectively. | |
2334 | */ | |
11e865c1 | 2335 | |
020c44f3 HS |
2336 | static void s626_dio_init(struct comedi_device *dev) |
2337 | { | |
2338 | uint16_t group; | |
11e865c1 | 2339 | |
8ee52611 | 2340 | /* Prepare to treat writes to WRCapSel as capture disables. */ |
d8515652 | 2341 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
11e865c1 | 2342 | |
8ee52611 | 2343 | /* For each group of sixteen channels ... */ |
020c44f3 | 2344 | for (group = 0; group < S626_DIO_BANKS; group++) { |
100b4edc | 2345 | /* Disable all interrupts */ |
d8515652 | 2346 | s626_debi_write(dev, S626_LP_WRINTSEL(group), 0); |
100b4edc | 2347 | /* Disable all event captures */ |
d8515652 | 2348 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); |
100b4edc | 2349 | /* Init all DIOs to default edge polarity */ |
d8515652 | 2350 | s626_debi_write(dev, S626_LP_WREDGSEL(group), 0); |
100b4edc | 2351 | /* Program all outputs to inactive state */ |
d8515652 | 2352 | s626_debi_write(dev, S626_LP_WRDOUT(group), 0); |
11e865c1 | 2353 | } |
020c44f3 | 2354 | } |
11e865c1 | 2355 | |
020c44f3 HS |
2356 | static int s626_dio_insn_bits(struct comedi_device *dev, |
2357 | struct comedi_subdevice *s, | |
1515e522 HS |
2358 | struct comedi_insn *insn, |
2359 | unsigned int *data) | |
020c44f3 | 2360 | { |
100b4edc | 2361 | unsigned long group = (unsigned long)s->private; |
11e865c1 | 2362 | |
6ea79c1d | 2363 | if (comedi_dio_update_state(s, data)) |
d8515652 | 2364 | s626_debi_write(dev, S626_LP_WRDOUT(group), s->state); |
6ea79c1d | 2365 | |
d8515652 | 2366 | data[1] = s626_debi_read(dev, S626_LP_RDDIN(group)); |
11e865c1 | 2367 | |
020c44f3 | 2368 | return insn->n; |
11e865c1 GP |
2369 | } |
2370 | ||
020c44f3 HS |
2371 | static int s626_dio_insn_config(struct comedi_device *dev, |
2372 | struct comedi_subdevice *s, | |
e920fad2 HS |
2373 | struct comedi_insn *insn, |
2374 | unsigned int *data) | |
11e865c1 | 2375 | { |
100b4edc | 2376 | unsigned long group = (unsigned long)s->private; |
ddf62f2c HS |
2377 | int ret; |
2378 | ||
2379 | ret = comedi_dio_insn_config(dev, s, insn, data, 0); | |
2380 | if (ret) | |
2381 | return ret; | |
11e865c1 | 2382 | |
d8515652 | 2383 | s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits); |
11e865c1 | 2384 | |
e920fad2 | 2385 | return insn->n; |
11e865c1 GP |
2386 | } |
2387 | ||
8ee52611 IA |
2388 | /* |
2389 | * Now this function initializes the value of the counter (data[0]) | |
2390 | * and set the subdevice. To complete with trigger and interrupt | |
2391 | * configuration. | |
2392 | * | |
2393 | * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating | |
affdc230 | 2394 | * what is being configured, but this function appears to be using data[0] |
8ee52611 IA |
2395 | * as a variable. |
2396 | */ | |
020c44f3 HS |
2397 | static int s626_enc_insn_config(struct comedi_device *dev, |
2398 | struct comedi_subdevice *s, | |
2399 | struct comedi_insn *insn, unsigned int *data) | |
2400 | { | |
f1f7efce | 2401 | uint16_t setup = |
d8515652 | 2402 | /* Preload upon index. */ |
0830ada5 | 2403 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 2404 | /* Disable hardware index. */ |
0830ada5 | 2405 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 2406 | /* Operating mode is Counter. */ |
0830ada5 | 2407 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
d8515652 | 2408 | /* Active high clock. */ |
0830ada5 | 2409 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
d8515652 | 2410 | /* Clock multiplier is 1x. */ |
0830ada5 IA |
2411 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
2412 | /* Enabled by index */ | |
2413 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); | |
c3e3a56d | 2414 | /* uint16_t disable_int_src = true; */ |
8ee52611 | 2415 | /* uint32_t Preloadvalue; //Counter initial value */ |
d8515652 IA |
2416 | uint16_t value_latchsrc = S626_LATCHSRC_AB_READ; |
2417 | uint16_t enab = S626_CLKENAB_ALWAYS; | |
3a305a66 IA |
2418 | const struct s626_enc_info *k = |
2419 | &s626_enc_chan_info[CR_CHAN(insn->chanspec)]; | |
11e865c1 | 2420 | |
8ee52611 | 2421 | /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */ |
11e865c1 | 2422 | |
c3e3a56d | 2423 | k->set_mode(dev, k, setup, true); |
31de1948 | 2424 | s626_preload(dev, k, data[0]); |
b075ac8e | 2425 | k->pulse_index(dev, k); |
31de1948 | 2426 | s626_set_latch_source(dev, k, value_latchsrc); |
b075ac8e | 2427 | k->set_enable(dev, k, (enab != 0)); |
11e865c1 | 2428 | |
020c44f3 HS |
2429 | return insn->n; |
2430 | } | |
11e865c1 | 2431 | |
020c44f3 HS |
2432 | static int s626_enc_insn_read(struct comedi_device *dev, |
2433 | struct comedi_subdevice *s, | |
2434 | struct comedi_insn *insn, unsigned int *data) | |
2435 | { | |
020c44f3 | 2436 | int n; |
3a305a66 IA |
2437 | const struct s626_enc_info *k = |
2438 | &s626_enc_chan_info[CR_CHAN(insn->chanspec)]; | |
11e865c1 | 2439 | |
020c44f3 | 2440 | for (n = 0; n < insn->n; n++) |
31de1948 | 2441 | data[n] = s626_read_latch(dev, k); |
11e865c1 | 2442 | |
020c44f3 HS |
2443 | return n; |
2444 | } | |
11e865c1 | 2445 | |
020c44f3 HS |
2446 | static int s626_enc_insn_write(struct comedi_device *dev, |
2447 | struct comedi_subdevice *s, | |
2448 | struct comedi_insn *insn, unsigned int *data) | |
2449 | { | |
3a305a66 IA |
2450 | const struct s626_enc_info *k = |
2451 | &s626_enc_chan_info[CR_CHAN(insn->chanspec)]; | |
11e865c1 | 2452 | |
8ee52611 | 2453 | /* Set the preload register */ |
31de1948 | 2454 | s626_preload(dev, k, data[0]); |
11e865c1 | 2455 | |
8ee52611 IA |
2456 | /* |
2457 | * Software index pulse forces the preload register to load | |
2458 | * into the counter | |
2459 | */ | |
b075ac8e IA |
2460 | k->set_load_trig(dev, k, 0); |
2461 | k->pulse_index(dev, k); | |
2462 | k->set_load_trig(dev, k, 2); | |
11e865c1 | 2463 | |
020c44f3 | 2464 | return 1; |
11e865c1 GP |
2465 | } |
2466 | ||
31de1948 | 2467 | static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image) |
11e865c1 | 2468 | { |
d8515652 IA |
2469 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE); |
2470 | s626_debi_write(dev, S626_LP_WRMISC2, new_image); | |
2471 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE); | |
020c44f3 | 2472 | } |
11e865c1 | 2473 | |
31de1948 IA |
2474 | static void s626_close_dma_b(struct comedi_device *dev, |
2475 | struct s626_buffer_dma *pdma, size_t bsize) | |
020c44f3 | 2476 | { |
f574af6d | 2477 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
020c44f3 HS |
2478 | void *vbptr; |
2479 | dma_addr_t vpptr; | |
11e865c1 | 2480 | |
020c44f3 HS |
2481 | if (pdma == NULL) |
2482 | return; | |
11e865c1 | 2483 | |
8ee52611 | 2484 | /* find the matching allocation from the board struct */ |
3a387506 IA |
2485 | vbptr = pdma->logical_base; |
2486 | vpptr = pdma->physical_base; | |
020c44f3 | 2487 | if (vbptr) { |
f574af6d | 2488 | pci_free_consistent(pcidev, bsize, vbptr, vpptr); |
3a387506 IA |
2489 | pdma->logical_base = NULL; |
2490 | pdma->physical_base = 0; | |
020c44f3 | 2491 | } |
11e865c1 GP |
2492 | } |
2493 | ||
31de1948 | 2494 | static void s626_counters_init(struct comedi_device *dev) |
11e865c1 | 2495 | { |
020c44f3 | 2496 | int chan; |
3a305a66 | 2497 | const struct s626_enc_info *k; |
f1f7efce | 2498 | uint16_t setup = |
d8515652 | 2499 | /* Preload upon index. */ |
0830ada5 | 2500 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 2501 | /* Disable hardware index. */ |
0830ada5 | 2502 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 2503 | /* Operating mode is counter. */ |
0830ada5 | 2504 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
d8515652 | 2505 | /* Active high clock. */ |
0830ada5 | 2506 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
d8515652 | 2507 | /* Clock multiplier is 1x. */ |
0830ada5 | 2508 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
d8515652 | 2509 | /* Enabled by index */ |
0830ada5 | 2510 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); |
8ee52611 IA |
2511 | |
2512 | /* | |
2513 | * Disable all counter interrupts and clear any captured counter events. | |
2514 | */ | |
020c44f3 | 2515 | for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) { |
3a305a66 | 2516 | k = &s626_enc_chan_info[chan]; |
c3e3a56d | 2517 | k->set_mode(dev, k, setup, true); |
b075ac8e IA |
2518 | k->set_int_src(dev, k, 0); |
2519 | k->reset_cap_flags(dev, k); | |
d8515652 | 2520 | k->set_enable(dev, k, S626_CLKENAB_ALWAYS); |
020c44f3 | 2521 | } |
020c44f3 | 2522 | } |
11e865c1 | 2523 | |
b7047895 HS |
2524 | static int s626_allocate_dma_buffers(struct comedi_device *dev) |
2525 | { | |
2526 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); | |
7f2f7e05 | 2527 | struct s626_private *devpriv = dev->private; |
b7047895 HS |
2528 | void *addr; |
2529 | dma_addr_t appdma; | |
2530 | ||
d8515652 | 2531 | addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); |
b7047895 HS |
2532 | if (!addr) |
2533 | return -ENOMEM; | |
07a36d66 IA |
2534 | devpriv->ana_buf.logical_base = addr; |
2535 | devpriv->ana_buf.physical_base = appdma; | |
b7047895 | 2536 | |
d8515652 | 2537 | addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); |
b7047895 HS |
2538 | if (!addr) |
2539 | return -ENOMEM; | |
07a36d66 IA |
2540 | devpriv->rps_buf.logical_base = addr; |
2541 | devpriv->rps_buf.physical_base = appdma; | |
b7047895 | 2542 | |
b7047895 HS |
2543 | return 0; |
2544 | } | |
2545 | ||
80ec9510 | 2546 | static void s626_initialize(struct comedi_device *dev) |
020c44f3 | 2547 | { |
7f2f7e05 | 2548 | struct s626_private *devpriv = dev->private; |
f1f7efce | 2549 | dma_addr_t phys_buf; |
68ad0ae0 | 2550 | uint16_t chan; |
020c44f3 | 2551 | int i; |
11e865c1 | 2552 | |
54a2a02e | 2553 | /* Enable DEBI and audio pins, enable I2C interface */ |
d8515652 IA |
2554 | s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C, |
2555 | S626_P_MC1); | |
54a2a02e HS |
2556 | |
2557 | /* | |
8ee52611 | 2558 | * Configure DEBI operating mode |
54a2a02e | 2559 | * |
8ee52611 IA |
2560 | * Local bus is 16 bits wide |
2561 | * Declare DEBI transfer timeout interval | |
2562 | * Set up byte lane steering | |
2563 | * Intel-compatible local bus (DEBI never times out) | |
54a2a02e | 2564 | */ |
d8515652 IA |
2565 | writel(S626_DEBI_CFG_SLAVE16 | |
2566 | (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP | | |
2567 | S626_DEBI_CFG_INTEL, devpriv->mmio + S626_P_DEBICFG); | |
54a2a02e HS |
2568 | |
2569 | /* Disable MMU paging */ | |
d8515652 | 2570 | writel(S626_DEBI_PAGE_DISABLE, devpriv->mmio + S626_P_DEBIPAGE); |
54a2a02e HS |
2571 | |
2572 | /* Init GPIO so that ADC Start* is negated */ | |
d8515652 | 2573 | writel(S626_GPIO_BASE | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); |
68ad0ae0 | 2574 | |
17553c88 | 2575 | /* I2C device address for onboard eeprom (revb) */ |
07a36d66 | 2576 | devpriv->i2c_adrs = 0xA0; |
11e865c1 | 2577 | |
54a2a02e HS |
2578 | /* |
2579 | * Issue an I2C ABORT command to halt any I2C | |
2580 | * operation in progress and reset BUSY flag. | |
2581 | */ | |
d8515652 IA |
2582 | writel(S626_I2C_CLKSEL | S626_I2C_ABORT, |
2583 | devpriv->mmio + S626_P_I2CSTAT); | |
2584 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); | |
2585 | while (!(readl(devpriv->mmio + S626_P_MC2) & S626_MC2_UPLD_IIC)) | |
68ad0ae0 | 2586 | ; |
68ad0ae0 | 2587 | |
54a2a02e HS |
2588 | /* |
2589 | * Per SAA7146 data sheet, write to STATUS | |
2590 | * reg twice to reset all I2C error flags. | |
2591 | */ | |
68ad0ae0 | 2592 | for (i = 0; i < 2; i++) { |
d8515652 IA |
2593 | writel(S626_I2C_CLKSEL, devpriv->mmio + S626_P_I2CSTAT); |
2594 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); | |
2595 | while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2)) | |
020c44f3 | 2596 | ; |
68ad0ae0 | 2597 | } |
11e865c1 | 2598 | |
54a2a02e HS |
2599 | /* |
2600 | * Init audio interface functional attributes: set DAC/ADC | |
68ad0ae0 HS |
2601 | * serial clock rates, invert DAC serial clock so that |
2602 | * DAC data setup times are satisfied, enable DAC serial | |
2603 | * clock out. | |
2604 | */ | |
d8515652 | 2605 | writel(S626_ACON2_INIT, devpriv->mmio + S626_P_ACON2); |
11e865c1 | 2606 | |
54a2a02e HS |
2607 | /* |
2608 | * Set up TSL1 slot list, which is used to control the | |
d8515652 IA |
2609 | * accumulation of ADC data: S626_RSD1 = shift data in on SD1. |
2610 | * S626_SIB_A1 = store data uint8_t at next available location | |
54a2a02e HS |
2611 | * in FB BUFFER1 register. |
2612 | */ | |
d8515652 IA |
2613 | writel(S626_RSD1 | S626_SIB_A1, devpriv->mmio + S626_P_TSL1); |
2614 | writel(S626_RSD1 | S626_SIB_A1 | S626_EOS, | |
2615 | devpriv->mmio + S626_P_TSL1 + 4); | |
11e865c1 | 2616 | |
54a2a02e | 2617 | /* Enable TSL1 slot list so that it executes all the time */ |
d8515652 | 2618 | writel(S626_ACON1_ADCSTART, devpriv->mmio + S626_P_ACON1); |
11e865c1 | 2619 | |
54a2a02e HS |
2620 | /* |
2621 | * Initialize RPS registers used for ADC | |
2622 | */ | |
11e865c1 | 2623 | |
54a2a02e | 2624 | /* Physical start of RPS program */ |
07a36d66 | 2625 | writel((uint32_t)devpriv->rps_buf.physical_base, |
d8515652 | 2626 | devpriv->mmio + S626_P_RPSADDR1); |
54a2a02e | 2627 | /* RPS program performs no explicit mem writes */ |
d8515652 | 2628 | writel(0, devpriv->mmio + S626_P_RPSPAGE1); |
54a2a02e | 2629 | /* Disable RPS timeouts */ |
d8515652 | 2630 | writel(0, devpriv->mmio + S626_P_RPS1_TOUT); |
11e865c1 | 2631 | |
59747847 HS |
2632 | #if 0 |
2633 | /* | |
2634 | * SAA7146 BUG WORKAROUND | |
2635 | * | |
2636 | * Initialize SAA7146 ADC interface to a known state by | |
2637 | * invoking ADCs until FB BUFFER 1 register shows that it | |
2638 | * is correctly receiving ADC data. This is necessary | |
2639 | * because the SAA7146 ADC interface does not start up in | |
2640 | * a defined state after a PCI reset. | |
68ad0ae0 | 2641 | */ |
59747847 | 2642 | { |
9c9ab3c1 | 2643 | struct comedi_subdevice *s = dev->read_subdev; |
f1f7efce IA |
2644 | uint8_t poll_list; |
2645 | uint16_t adc_data; | |
2646 | uint16_t start_val; | |
8ee52611 IA |
2647 | uint16_t index; |
2648 | unsigned int data[16]; | |
59747847 | 2649 | |
8ee52611 | 2650 | /* Create a simple polling list for analog input channel 0 */ |
d8515652 | 2651 | poll_list = S626_EOPL; |
31de1948 | 2652 | s626_reset_adc(dev, &poll_list); |
59747847 | 2653 | |
8ee52611 | 2654 | /* Get initial ADC value */ |
9c9ab3c1 | 2655 | s626_ai_rinsn(dev, s, NULL, data); |
f1f7efce | 2656 | start_val = data[0]; |
59747847 | 2657 | |
8ee52611 IA |
2658 | /* |
2659 | * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED | |
2660 | * EXECUTION. | |
2661 | * | |
2662 | * Invoke ADCs until the new ADC value differs from the initial | |
2663 | * value or a timeout occurs. The timeout protects against the | |
2664 | * possibility that the driver is restarting and the ADC data is | |
2665 | * a fixed value resulting from the applied ADC analog input | |
2666 | * being unusually quiet or at the rail. | |
2667 | */ | |
2668 | for (index = 0; index < 500; index++) { | |
9c9ab3c1 | 2669 | s626_ai_rinsn(dev, s, NULL, data); |
f1f7efce IA |
2670 | adc_data = data[0]; |
2671 | if (adc_data != start_val) | |
8ee52611 IA |
2672 | break; |
2673 | } | |
59747847 HS |
2674 | } |
2675 | #endif /* SAA7146 BUG WORKAROUND */ | |
11e865c1 | 2676 | |
54a2a02e HS |
2677 | /* |
2678 | * Initialize the DAC interface | |
2679 | */ | |
11e865c1 | 2680 | |
54a2a02e HS |
2681 | /* |
2682 | * Init Audio2's output DMAC attributes: | |
2683 | * burst length = 1 DWORD | |
2684 | * threshold = 1 DWORD. | |
68ad0ae0 | 2685 | */ |
d8515652 | 2686 | writel(0, devpriv->mmio + S626_P_PCI_BT_A); |
68ad0ae0 | 2687 | |
54a2a02e HS |
2688 | /* |
2689 | * Init Audio2's output DMA physical addresses. The protection | |
68ad0ae0 HS |
2690 | * address is set to 1 DWORD past the base address so that a |
2691 | * single DWORD will be transferred each time a DMA transfer is | |
54a2a02e HS |
2692 | * enabled. |
2693 | */ | |
f1f7efce | 2694 | phys_buf = devpriv->ana_buf.physical_base + |
d8515652 IA |
2695 | (S626_DAC_WDMABUF_OS * sizeof(uint32_t)); |
2696 | writel((uint32_t)phys_buf, devpriv->mmio + S626_P_BASEA2_OUT); | |
f1f7efce | 2697 | writel((uint32_t)(phys_buf + sizeof(uint32_t)), |
d8515652 | 2698 | devpriv->mmio + S626_P_PROTA2_OUT); |
68ad0ae0 | 2699 | |
54a2a02e HS |
2700 | /* |
2701 | * Cache Audio2's output DMA buffer logical address. This is | |
2702 | * where DAC data is buffered for A2 output DMA transfers. | |
2703 | */ | |
07a36d66 | 2704 | devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base + |
d8515652 | 2705 | S626_DAC_WDMABUF_OS; |
68ad0ae0 | 2706 | |
54a2a02e HS |
2707 | /* |
2708 | * Audio2's output channels does not use paging. The | |
2709 | * protection violation handling bit is set so that the | |
2710 | * DMAC will automatically halt and its PCI address pointer | |
2711 | * will be reset when the protection address is reached. | |
2712 | */ | |
d8515652 | 2713 | writel(8, devpriv->mmio + S626_P_PAGEA2_OUT); |
68ad0ae0 | 2714 | |
54a2a02e HS |
2715 | /* |
2716 | * Initialize time slot list 2 (TSL2), which is used to control | |
68ad0ae0 HS |
2717 | * the clock generation for and serialization of data to be sent |
2718 | * to the DAC devices. Slot 0 is a NOP that is used to trap TSL | |
2719 | * execution; this permits other slots to be safely modified | |
2720 | * without first turning off the TSL sequencer (which is | |
2721 | * apparently impossible to do). Also, SD3 (which is driven by a | |
2722 | * pull-up resistor) is shifted in and stored to the MSB of | |
2723 | * FB_BUFFER2 to be used as evidence that the slot sequence has | |
2724 | * not yet finished executing. | |
2725 | */ | |
11e865c1 | 2726 | |
54a2a02e | 2727 | /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */ |
d8515652 IA |
2728 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS, |
2729 | devpriv->mmio + S626_VECTPORT(0)); | |
11e865c1 | 2730 | |
54a2a02e HS |
2731 | /* |
2732 | * Initialize slot 1, which is constant. Slot 1 causes a | |
68ad0ae0 HS |
2733 | * DWORD to be transferred from audio channel 2's output FIFO |
2734 | * to the FIFO's output buffer so that it can be serialized | |
2735 | * and sent to the DAC during subsequent slots. All remaining | |
2736 | * slots are dynamically populated as required by the target | |
2737 | * DAC device. | |
2738 | */ | |
54a2a02e HS |
2739 | |
2740 | /* Slot 1: Fetch DWORD from Audio2's output FIFO */ | |
d8515652 | 2741 | writel(S626_LF_A2, devpriv->mmio + S626_VECTPORT(1)); |
11e865c1 | 2742 | |
54a2a02e | 2743 | /* Start DAC's audio interface (TSL2) running */ |
d8515652 | 2744 | writel(S626_ACON1_DACSTART, devpriv->mmio + S626_P_ACON1); |
11e865c1 | 2745 | |
54a2a02e HS |
2746 | /* |
2747 | * Init Trim DACs to calibrated values. Do it twice because the | |
68ad0ae0 HS |
2748 | * SAA7146 audio channel does not always reset properly and |
2749 | * sometimes causes the first few TrimDAC writes to malfunction. | |
2750 | */ | |
31de1948 IA |
2751 | s626_load_trim_dacs(dev); |
2752 | s626_load_trim_dacs(dev); | |
11e865c1 | 2753 | |
54a2a02e HS |
2754 | /* |
2755 | * Manually init all gate array hardware in case this is a soft | |
68ad0ae0 HS |
2756 | * reset (we have no way of determining whether this is a warm |
2757 | * or cold start). This is necessary because the gate array will | |
2758 | * reset only in response to a PCI hard reset; there is no soft | |
54a2a02e HS |
2759 | * reset function. |
2760 | */ | |
11e865c1 | 2761 | |
54a2a02e HS |
2762 | /* |
2763 | * Init all DAC outputs to 0V and init all DAC setpoint and | |
68ad0ae0 HS |
2764 | * polarity images. |
2765 | */ | |
2766 | for (chan = 0; chan < S626_DAC_CHANNELS; chan++) | |
31de1948 | 2767 | s626_set_dac(dev, chan, 0); |
11e865c1 | 2768 | |
54a2a02e | 2769 | /* Init counters */ |
31de1948 | 2770 | s626_counters_init(dev); |
11e865c1 | 2771 | |
54a2a02e HS |
2772 | /* |
2773 | * Without modifying the state of the Battery Backup enab, disable | |
68ad0ae0 HS |
2774 | * the watchdog timer, set DIO channels 0-5 to operate in the |
2775 | * standard DIO (vs. counter overflow) mode, disable the battery | |
2776 | * charger, and reset the watchdog interval selector to zero. | |
2777 | */ | |
d8515652 IA |
2778 | s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) & |
2779 | S626_MISC2_BATT_ENABLE)); | |
11e865c1 | 2780 | |
54a2a02e | 2781 | /* Initialize the digital I/O subsystem */ |
68ad0ae0 | 2782 | s626_dio_init(dev); |
80ec9510 HS |
2783 | } |
2784 | ||
a690b7e5 | 2785 | static int s626_auto_attach(struct comedi_device *dev, |
750af5e5 | 2786 | unsigned long context_unused) |
80ec9510 | 2787 | { |
750af5e5 | 2788 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
7f2f7e05 | 2789 | struct s626_private *devpriv; |
80ec9510 HS |
2790 | struct comedi_subdevice *s; |
2791 | int ret; | |
2792 | ||
0bdab509 | 2793 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
c34fa261 HS |
2794 | if (!devpriv) |
2795 | return -ENOMEM; | |
80ec9510 | 2796 | |
818f569f | 2797 | ret = comedi_pci_enable(dev); |
80ec9510 HS |
2798 | if (ret) |
2799 | return ret; | |
80ec9510 | 2800 | |
5970b102 | 2801 | devpriv->mmio = pci_ioremap_bar(pcidev, 0); |
7d856da2 | 2802 | if (!devpriv->mmio) |
80ec9510 HS |
2803 | return -ENOMEM; |
2804 | ||
2805 | /* disable master interrupt */ | |
d8515652 | 2806 | writel(0, devpriv->mmio + S626_P_IER); |
80ec9510 HS |
2807 | |
2808 | /* soft reset */ | |
d8515652 | 2809 | writel(S626_MC1_SOFT_RESET, devpriv->mmio + S626_P_MC1); |
80ec9510 HS |
2810 | |
2811 | /* DMA FIXME DMA// */ | |
2812 | ||
2813 | ret = s626_allocate_dma_buffers(dev); | |
2814 | if (ret) | |
2815 | return ret; | |
2816 | ||
2817 | if (pcidev->irq) { | |
2818 | ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED, | |
2819 | dev->board_name, dev); | |
2820 | ||
2821 | if (ret == 0) | |
2822 | dev->irq = pcidev->irq; | |
2823 | } | |
2824 | ||
2825 | ret = comedi_alloc_subdevices(dev, 6); | |
2826 | if (ret) | |
2827 | return ret; | |
2828 | ||
f0717f5d | 2829 | s = &dev->subdevices[0]; |
80ec9510 | 2830 | /* analog input subdevice */ |
ca2f1091 | 2831 | s->type = COMEDI_SUBD_AI; |
f95321f3 | 2832 | s->subdev_flags = SDF_READABLE | SDF_DIFF; |
ca2f1091 HS |
2833 | s->n_chan = S626_ADC_CHANNELS; |
2834 | s->maxdata = 0x3fff; | |
2835 | s->range_table = &s626_range_table; | |
2836 | s->len_chanlist = S626_ADC_CHANNELS; | |
ca2f1091 | 2837 | s->insn_read = s626_ai_insn_read; |
2281befd HS |
2838 | if (dev->irq) { |
2839 | dev->read_subdev = s; | |
f95321f3 | 2840 | s->subdev_flags |= SDF_CMD_READ; |
2281befd HS |
2841 | s->do_cmd = s626_ai_cmd; |
2842 | s->do_cmdtest = s626_ai_cmdtest; | |
2843 | s->cancel = s626_ai_cancel; | |
2844 | } | |
80ec9510 | 2845 | |
f0717f5d | 2846 | s = &dev->subdevices[1]; |
80ec9510 | 2847 | /* analog output subdevice */ |
ca2f1091 HS |
2848 | s->type = COMEDI_SUBD_AO; |
2849 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2850 | s->n_chan = S626_DAC_CHANNELS; | |
2851 | s->maxdata = 0x3fff; | |
2852 | s->range_table = &range_bipolar10; | |
2853 | s->insn_write = s626_ao_winsn; | |
2854 | s->insn_read = s626_ao_rinsn; | |
80ec9510 | 2855 | |
f0717f5d | 2856 | s = &dev->subdevices[2]; |
80ec9510 | 2857 | /* digital I/O subdevice */ |
ca2f1091 HS |
2858 | s->type = COMEDI_SUBD_DIO; |
2859 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2860 | s->n_chan = 16; | |
2861 | s->maxdata = 1; | |
2862 | s->io_bits = 0xffff; | |
2863 | s->private = (void *)0; /* DIO group 0 */ | |
2864 | s->range_table = &range_digital; | |
2865 | s->insn_config = s626_dio_insn_config; | |
2866 | s->insn_bits = s626_dio_insn_bits; | |
80ec9510 | 2867 | |
f0717f5d | 2868 | s = &dev->subdevices[3]; |
80ec9510 | 2869 | /* digital I/O subdevice */ |
ca2f1091 HS |
2870 | s->type = COMEDI_SUBD_DIO; |
2871 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2872 | s->n_chan = 16; | |
2873 | s->maxdata = 1; | |
2874 | s->io_bits = 0xffff; | |
2875 | s->private = (void *)1; /* DIO group 1 */ | |
2876 | s->range_table = &range_digital; | |
2877 | s->insn_config = s626_dio_insn_config; | |
2878 | s->insn_bits = s626_dio_insn_bits; | |
80ec9510 | 2879 | |
f0717f5d | 2880 | s = &dev->subdevices[4]; |
80ec9510 | 2881 | /* digital I/O subdevice */ |
ca2f1091 HS |
2882 | s->type = COMEDI_SUBD_DIO; |
2883 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2884 | s->n_chan = 16; | |
2885 | s->maxdata = 1; | |
2886 | s->io_bits = 0xffff; | |
2887 | s->private = (void *)2; /* DIO group 2 */ | |
2888 | s->range_table = &range_digital; | |
8ee52611 | 2889 | s->insn_config = s626_dio_insn_config; |
ca2f1091 | 2890 | s->insn_bits = s626_dio_insn_bits; |
80ec9510 | 2891 | |
f0717f5d | 2892 | s = &dev->subdevices[5]; |
80ec9510 | 2893 | /* encoder (counter) subdevice */ |
ca2f1091 HS |
2894 | s->type = COMEDI_SUBD_COUNTER; |
2895 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL; | |
2896 | s->n_chan = S626_ENCODER_CHANNELS; | |
2897 | s->maxdata = 0xffffff; | |
ca2f1091 HS |
2898 | s->range_table = &range_unknown; |
2899 | s->insn_config = s626_enc_insn_config; | |
2900 | s->insn_read = s626_enc_insn_read; | |
2901 | s->insn_write = s626_enc_insn_write; | |
80ec9510 | 2902 | |
80ec9510 | 2903 | s626_initialize(dev); |
11e865c1 | 2904 | |
f996ab29 | 2905 | return 0; |
11e865c1 GP |
2906 | } |
2907 | ||
020c44f3 | 2908 | static void s626_detach(struct comedi_device *dev) |
11e865c1 | 2909 | { |
7f2f7e05 | 2910 | struct s626_private *devpriv = dev->private; |
f574af6d | 2911 | |
020c44f3 HS |
2912 | if (devpriv) { |
2913 | /* stop ai_command */ | |
2914 | devpriv->ai_cmd_running = 0; | |
11e865c1 | 2915 | |
7d856da2 | 2916 | if (devpriv->mmio) { |
020c44f3 | 2917 | /* interrupt mask */ |
25f8fd5e | 2918 | /* Disable master interrupt */ |
d8515652 | 2919 | writel(0, devpriv->mmio + S626_P_IER); |
25f8fd5e | 2920 | /* Clear board's IRQ status flag */ |
d8515652 IA |
2921 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, |
2922 | devpriv->mmio + S626_P_ISR); | |
11e865c1 | 2923 | |
8ee52611 | 2924 | /* Disable the watchdog timer and battery charger. */ |
31de1948 | 2925 | s626_write_misc2(dev, 0); |
11e865c1 | 2926 | |
25f8fd5e | 2927 | /* Close all interfaces on 7146 device */ |
d8515652 IA |
2928 | writel(S626_MC1_SHUTDOWN, devpriv->mmio + S626_P_MC1); |
2929 | writel(S626_ACON1_BASE, devpriv->mmio + S626_P_ACON1); | |
11e865c1 | 2930 | |
d8515652 IA |
2931 | s626_close_dma_b(dev, &devpriv->rps_buf, |
2932 | S626_DMABUF_SIZE); | |
2933 | s626_close_dma_b(dev, &devpriv->ana_buf, | |
2934 | S626_DMABUF_SIZE); | |
020c44f3 | 2935 | } |
b6c77757 | 2936 | |
020c44f3 HS |
2937 | if (dev->irq) |
2938 | free_irq(dev->irq, dev); | |
7d856da2 HS |
2939 | if (devpriv->mmio) |
2940 | iounmap(devpriv->mmio); | |
f574af6d | 2941 | } |
7f072f54 | 2942 | comedi_pci_disable(dev); |
11e865c1 | 2943 | } |
7122b76d | 2944 | |
75e6301b | 2945 | static struct comedi_driver s626_driver = { |
7122b76d HS |
2946 | .driver_name = "s626", |
2947 | .module = THIS_MODULE, | |
750af5e5 | 2948 | .auto_attach = s626_auto_attach, |
7122b76d HS |
2949 | .detach = s626_detach, |
2950 | }; | |
2951 | ||
a690b7e5 | 2952 | static int s626_pci_probe(struct pci_dev *dev, |
b8f4ac23 | 2953 | const struct pci_device_id *id) |
7122b76d | 2954 | { |
b8f4ac23 | 2955 | return comedi_pci_auto_config(dev, &s626_driver, id->driver_data); |
7122b76d HS |
2956 | } |
2957 | ||
7122b76d HS |
2958 | /* |
2959 | * For devices with vendor:device id == 0x1131:0x7146 you must specify | |
2960 | * also subvendor:subdevice ids, because otherwise it will conflict with | |
2961 | * Philips SAA7146 media/dvb based cards. | |
2962 | */ | |
41e043fc | 2963 | static const struct pci_device_id s626_pci_table[] = { |
498c5070 IA |
2964 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146, |
2965 | 0x6000, 0x0272) }, | |
7122b76d HS |
2966 | { 0 } |
2967 | }; | |
2968 | MODULE_DEVICE_TABLE(pci, s626_pci_table); | |
2969 | ||
75e6301b HS |
2970 | static struct pci_driver s626_pci_driver = { |
2971 | .name = "s626", | |
7122b76d | 2972 | .id_table = s626_pci_table, |
75e6301b | 2973 | .probe = s626_pci_probe, |
9901a4d7 | 2974 | .remove = comedi_pci_auto_unconfig, |
7122b76d | 2975 | }; |
75e6301b | 2976 | module_comedi_pci_driver(s626_driver, s626_pci_driver); |
7122b76d HS |
2977 | |
2978 | MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>"); | |
2979 | MODULE_DESCRIPTION("Sensoray 626 Comedi driver module"); | |
2980 | MODULE_LICENSE("GPL"); |