[linux-2.6-block.git] / drivers / staging / comedi / drivers / ni_tio_internal.h

/*
    drivers/ni_tio_internal.h
    Header file for NI general purpose counter support code (ni_tio.c and
    ni_tiocmd.c)

    COMEDI - Linux Control and Measurement Device Interface

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
*/

#ifndef _COMEDI_NI_TIO_INTERNAL_H
#define _COMEDI_NI_TIO_INTERNAL_H

#include "ni_tio.h"

#define NITIO_AUTO_INC_REG(x)		(NITIO_G0_AUTO_INC + (x))
#define NITIO_CMD_REG(x)		(NITIO_G0_CMD + (x))
#define NITIO_SW_SAVE_REG(x)		(NITIO_G0_SW_SAVE + (x))
#define NITIO_MODE_REG(x)		(NITIO_G0_MODE + (x))
#define NITIO_LOADA_REG(x)		(NITIO_G0_LOADA + (x))
#define NITIO_LOADB_REG(x)		(NITIO_G0_LOADB + (x))

static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_CNT_MODE;
	case 1:
		return NITIO_G1_CNT_MODE;
	case 2:
		return NITIO_G2_CNT_MODE;
	case 3:
		return NITIO_G3_CNT_MODE;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_INPUT_SEL;
	case 1:
		return NITIO_G1_INPUT_SEL;
	case 2:
		return NITIO_G2_INPUT_SEL;
	case 3:
		return NITIO_G3_INPUT_SEL;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
	case 1:
		return NITIO_G01_RESET;
	case 2:
	case 3:
		return NITIO_G23_RESET;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
	case 1:
		return NITIO_G01_STATUS1;
	case 2:
	case 3:
		return NITIO_G23_STATUS1;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
	case 1:
		return NITIO_G01_STATUS2;
	case 2:
	case 3:
		return NITIO_G23_STATUS2;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
	case 1:
		return NITIO_G01_STATUS;
	case 2:
	case 3:
		return NITIO_G23_STATUS;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_GATE2;
	case 1:
		return NITIO_G1_GATE2;
	case 2:
		return NITIO_G2_GATE2;
	case 3:
		return NITIO_G3_GATE2;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_DMA_CFG;
	case 1:
		return NITIO_G1_DMA_CFG;
	case 2:
		return NITIO_G2_DMA_CFG;
	case 3:
		return NITIO_G3_DMA_CFG;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_DMA_STATUS;
	case 1:
		return NITIO_G1_DMA_STATUS;
	case 2:
		return NITIO_G2_DMA_STATUS;
	case 3:
		return NITIO_G3_DMA_STATUS;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_ABZ;
	case 1:
		return NITIO_G1_ABZ;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_INT_ACK;
	case 1:
		return NITIO_G1_INT_ACK;
	case 2:
		return NITIO_G2_INT_ACK;
	case 3:
		return NITIO_G3_INT_ACK;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Status_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_STATUS;
	case 1:
		return NITIO_G1_STATUS;
	case 2:
		return NITIO_G2_STATUS;
	case 3:
		return NITIO_G3_STATUS;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(unsigned idx)
{
	switch (idx) {
	case 0:
		return NITIO_G0_INT_ENA;
	case 1:
		return NITIO_G1_INT_ENA;
	case 2:
		return NITIO_G2_INT_ENA;
	case 3:
		return NITIO_G3_INT_ENA;
	}
	return 0;
}

enum Gi_Auto_Increment_Reg_Bits {
	Gi_Auto_Increment_Mask = 0xff
};

#define Gi_Up_Down_Shift 5
enum Gi_Command_Reg_Bits {
	Gi_Arm_Bit = 0x1,
	Gi_Save_Trace_Bit = 0x2,
	Gi_Load_Bit = 0x4,
	Gi_Disarm_Bit = 0x10,
	Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
	Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
	Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
	Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
	Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
	Gi_Write_Switch_Bit = 0x80,
	Gi_Synchronize_Gate_Bit = 0x100,
	Gi_Little_Big_Endian_Bit = 0x200,
	Gi_Bank_Switch_Start_Bit = 0x400,
	Gi_Bank_Switch_Mode_Bit = 0x800,
	Gi_Bank_Switch_Enable_Bit = 0x1000,
	Gi_Arm_Copy_Bit = 0x2000,
	Gi_Save_Trace_Copy_Bit = 0x4000,
	Gi_Disarm_Copy_Bit = 0x8000
};

#define Gi_Index_Phase_Bitshift 5
#define Gi_HW_Arm_Select_Shift 8
enum Gi_Counting_Mode_Reg_Bits {
	Gi_Counting_Mode_Mask = 0x7,
	Gi_Counting_Mode_Normal_Bits = 0x0,
	Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
	Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
	Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
	Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
	Gi_Counting_Mode_Sync_Source_Bits = 0x6,
	Gi_Index_Mode_Bit = 0x10,
	Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
	/* from m-series example code, not documented in 660x register level
	 * manual */
	Gi_HW_Arm_Enable_Bit = 0x80,
	/* from m-series example code, not documented in 660x register level
	 * manual */
	Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
	Gi_660x_Prescale_X8_Bit = 0x1000,
	Gi_M_Series_Prescale_X8_Bit = 0x2000,
	Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
	/* must be set for clocks over 40MHz, which includes synchronous
	 * counting and quadrature modes */
	Gi_660x_Alternate_Sync_Bit = 0x2000,
	Gi_M_Series_Alternate_Sync_Bit = 0x4000,
	/* from m-series example code, not documented in 660x register level
	 * manual */
	Gi_660x_Prescale_X2_Bit = 0x4000,
	Gi_M_Series_Prescale_X2_Bit = 0x8000,
};

#define Gi_Source_Select_Shift 2
#define Gi_Gate_Select_Shift 7
enum Gi_Input_Select_Bits {
	Gi_Read_Acknowledges_Irq = 0x1,	/*  not present on 660x */
	Gi_Write_Acknowledges_Irq = 0x2,	/*  not present on 660x */
	Gi_Source_Select_Mask = 0x7c,
	Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
	Gi_Gate_Select_Load_Source_Bit = 0x1000,
	Gi_Or_Gate_Bit = 0x2000,
	Gi_Output_Polarity_Bit = 0x4000,	/* set to invert */
	Gi_Source_Polarity_Bit = 0x8000	/* set to invert */
};

enum Gi_Mode_Bits {
	Gi_Gating_Mode_Mask = 0x3,
	Gi_Gating_Disabled_Bits = 0x0,
	Gi_Level_Gating_Bits = 0x1,
	Gi_Rising_Edge_Gating_Bits = 0x2,
	Gi_Falling_Edge_Gating_Bits = 0x3,
	Gi_Gate_On_Both_Edges_Bit = 0x4,	/* used in conjunction with
						 * rising edge gating mode */
	Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
	Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
	Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
	Gi_Edge_Gate_Starts_Bits = 0x10,
	Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
	Gi_Stop_Mode_Mask = 0x60,
	Gi_Stop_on_Gate_Bits = 0x00,
	Gi_Stop_on_Gate_or_TC_Bits = 0x20,
	Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
	Gi_Load_Source_Select_Bit = 0x80,
	Gi_Output_Mode_Mask = 0x300,
	Gi_Output_TC_Pulse_Bits = 0x100,
	Gi_Output_TC_Toggle_Bits = 0x200,
	Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
	Gi_Counting_Once_Mask = 0xc00,
	Gi_No_Hardware_Disarm_Bits = 0x000,
	Gi_Disarm_at_TC_Bits = 0x400,
	Gi_Disarm_at_Gate_Bits = 0x800,
	Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
	Gi_Loading_On_TC_Bit = 0x1000,
	Gi_Gate_Polarity_Bit = 0x2000,
	Gi_Loading_On_Gate_Bit = 0x4000,
	Gi_Reload_Source_Switching_Bit = 0x8000
};

#define Gi_Second_Gate_Select_Shift 7
/*FIXME: m-series has a second gate subselect bit */
/*FIXME: m-series second gate sources are undocumented (by NI)*/
enum Gi_Second_Gate_Bits {
	Gi_Second_Gate_Mode_Bit = 0x1,
	Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
	Gi_Second_Gate_Polarity_Bit = 0x2000,
	Gi_Second_Gate_Subselect_Bit = 0x4000,	/* m-series only */
	Gi_Source_Subselect_Bit = 0x8000	/* m-series only */
};
static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
{
	return (second_gate_select << Gi_Second_Gate_Select_Shift) &
	    Gi_Second_Gate_Select_Mask;
}

enum Gxx_Status_Bits {
	G0_Save_Bit = 0x1,
	G1_Save_Bit = 0x2,
	G0_Counting_Bit = 0x4,
	G1_Counting_Bit = 0x8,
	G0_Next_Load_Source_Bit = 0x10,
	G1_Next_Load_Source_Bit = 0x20,
	G0_Stale_Data_Bit = 0x40,
	G1_Stale_Data_Bit = 0x80,
	G0_Armed_Bit = 0x100,
	G1_Armed_Bit = 0x200,
	G0_No_Load_Between_Gates_Bit = 0x400,
	G1_No_Load_Between_Gates_Bit = 0x800,
	G0_TC_Error_Bit = 0x1000,
	G1_TC_Error_Bit = 0x2000,
	G0_Gate_Error_Bit = 0x4000,
	G1_Gate_Error_Bit = 0x8000
};
static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Counting_Bit;
	return G0_Counting_Bit;
}

static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Armed_Bit;
	return G0_Armed_Bit;
}

static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
							   counter_index)
{
	if (counter_index % 2)
		return G1_Next_Load_Source_Bit;
	return G0_Next_Load_Source_Bit;
}

static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Stale_Data_Bit;
	return G0_Stale_Data_Bit;
}

static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_TC_Error_Bit;
	return G0_TC_Error_Bit;
}

static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Gate_Error_Bit;
	return G0_Gate_Error_Bit;
}

/* joint reset register bits */
static inline unsigned Gi_Reset_Bit(unsigned counter_index)
{
	return 0x1 << (2 + (counter_index % 2));
}

enum Gxx_Joint_Status2_Bits {
	G0_Output_Bit = 0x1,
	G1_Output_Bit = 0x2,
	G0_HW_Save_Bit = 0x1000,
	G1_HW_Save_Bit = 0x2000,
	G0_Permanent_Stale_Bit = 0x4000,
	G1_Permanent_Stale_Bit = 0x8000
};
static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
								 counter_index)
{
	if (counter_index % 2)
		return G1_Permanent_Stale_Bit;
	return G0_Permanent_Stale_Bit;
}

enum Gi_DMA_Config_Reg_Bits {
	Gi_DMA_Enable_Bit = 0x1,
	Gi_DMA_Write_Bit = 0x2,
	Gi_DMA_Int_Bit = 0x4
};

enum Gi_DMA_Status_Reg_Bits {
	Gi_DMA_Readbank_Bit = 0x2000,
	Gi_DRQ_Error_Bit = 0x4000,
	Gi_DRQ_Status_Bit = 0x8000
};

enum G02_Interrupt_Acknowledge_Bits {
	G0_Gate_Error_Confirm_Bit = 0x20,
	G0_TC_Error_Confirm_Bit = 0x40
};
enum G13_Interrupt_Acknowledge_Bits {
	G1_Gate_Error_Confirm_Bit = 0x2,
	G1_TC_Error_Confirm_Bit = 0x4
};
static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Gate_Error_Confirm_Bit;
	return G0_Gate_Error_Confirm_Bit;
}

static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_TC_Error_Confirm_Bit;
	return G0_TC_Error_Confirm_Bit;
}

/* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
enum Gxx_Interrupt_Acknowledge_Bits {
	Gi_TC_Interrupt_Ack_Bit = 0x4000,
	Gi_Gate_Interrupt_Ack_Bit = 0x8000
};

enum Gi_Status_Bits {
	Gi_Gate_Interrupt_Bit = 0x4,
	Gi_TC_Bit = 0x8,
	Gi_Interrupt_Bit = 0x8000
};

enum G02_Interrupt_Enable_Bits {
	G0_TC_Interrupt_Enable_Bit = 0x40,
	G0_Gate_Interrupt_Enable_Bit = 0x100
};
enum G13_Interrupt_Enable_Bits {
	G1_TC_Interrupt_Enable_Bit = 0x200,
	G1_Gate_Interrupt_Enable_Bit = 0x400
};
static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
{
	unsigned bit;

	if (counter_index % 2)
		bit = G1_Gate_Interrupt_Enable_Bit;
	else
		bit = G0_Gate_Interrupt_Enable_Bit;
	return bit;
}

static inline void write_register(struct ni_gpct *counter, unsigned bits,
				  enum ni_gpct_register reg)
{
	BUG_ON(reg >= NITIO_NUM_REGS);
	counter->counter_dev->write_register(counter, bits, reg);
}

static inline unsigned read_register(struct ni_gpct *counter,
				     enum ni_gpct_register reg)
{
	BUG_ON(reg >= NITIO_NUM_REGS);
	return counter->counter_dev->read_register(counter, reg);
}

static inline int ni_tio_counting_mode_registers_present(const struct
							 ni_gpct_device
							 *counter_dev)
{
	switch (counter_dev->variant) {
	case ni_gpct_variant_e_series:
		return 0;
		break;
	case ni_gpct_variant_m_series:
	case ni_gpct_variant_660x:
		return 1;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
					     enum ni_gpct_register
					     register_index, unsigned bit_mask,
					     unsigned bit_values,
					     unsigned transient_bit_values)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	unsigned long flags;

	BUG_ON(register_index >= NITIO_NUM_REGS);
	spin_lock_irqsave(&counter_dev->regs_lock, flags);
	counter_dev->regs[register_index] &= ~bit_mask;
	counter_dev->regs[register_index] |= (bit_values & bit_mask);
	write_register(counter,
		       counter_dev->regs[register_index] | transient_bit_values,
		       register_index);
	mmiowb();
	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
}

/* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
 * twiddled in interrupt context, or whose software copy may be read in
 * interrupt context.
 */
static inline void ni_tio_set_bits(struct ni_gpct *counter,
				   enum ni_gpct_register register_index,
				   unsigned bit_mask, unsigned bit_values)
{
	ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
				  0x0);
}

/* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
whose bits might be modified in interrupt context, or whose software copy
might need to be read in interrupt context.
*/
static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
					    enum ni_gpct_register
					    register_index)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	unsigned long flags;
	unsigned value;

	BUG_ON(register_index >= NITIO_NUM_REGS);
	spin_lock_irqsave(&counter_dev->regs_lock, flags);
	value = counter_dev->regs[register_index];
	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
	return value;
}

int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
			unsigned int gate_source);

#endif /* _COMEDI_NI_TIO_INTERNAL_H */
Commit	Line	Data
cb7859a9 FMH	1	/*
	2	drivers/ni_tio_internal.h
	3	Header file for NI general purpose counter support code (ni_tio.c and
	4	ni_tiocmd.c)
	5
	6	COMEDI - Linux Control and Measurement Device Interface
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
cb7859a9 FMH	17	*/
	18
	19	#ifndef _COMEDI_NI_TIO_INTERNAL_H
	20	#define _COMEDI_NI_TIO_INTERNAL_H
	21
	22	#include "ni_tio.h"
	23
e062f51b	24	#define NITIO_AUTO_INC_REG(x) (NITIO_G0_AUTO_INC + (x))
e25ef744	25	#define NITIO_CMD_REG(x) (NITIO_G0_CMD + (x))
67c68de0	26	#define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x))
0101791e	27	#define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x))
720712f4	28	#define NITIO_LOADA_REG(x) (NITIO_G0_LOADA + (x))
cc7a164b	29	#define NITIO_LOADB_REG(x) (NITIO_G0_LOADB + (x))
cb7859a9	30
12375292	31	static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned idx)
cb7859a9	32	{
12375292	33	switch (idx) {
cb7859a9	34	case 0:
12375292	35	return NITIO_G0_CNT_MODE;
cb7859a9	36	case 1:
12375292	37	return NITIO_G1_CNT_MODE;
cb7859a9	38	case 2:
12375292	39	return NITIO_G2_CNT_MODE;
cb7859a9	40	case 3:
12375292	41	return NITIO_G3_CNT_MODE;
cb7859a9 FMH	42	}
	43	return 0;
	44	}
	45
12375292	46	static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned idx)
cb7859a9	47	{
12375292	48	switch (idx) {
cb7859a9	49	case 0:
12375292	50	return NITIO_G0_INPUT_SEL;
cb7859a9	51	case 1:
12375292	52	return NITIO_G1_INPUT_SEL;
cb7859a9	53	case 2:
12375292	54	return NITIO_G2_INPUT_SEL;
cb7859a9	55	case 3:
12375292	56	return NITIO_G3_INPUT_SEL;
cb7859a9 FMH	57	}
	58	return 0;
	59	}
	60
12375292	61	static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned idx)
cb7859a9	62	{
12375292	63	switch (idx) {
cb7859a9 FMH	64	case 0:
cb7859a9 FMH	65	case 1:
12375292	66	return NITIO_G01_RESET;
cb7859a9 FMH	67	case 2:
cb7859a9 FMH	68	case 3:
12375292	69	return NITIO_G23_RESET;
cb7859a9 FMH	70	}
	71	return 0;
	72	}
	73
12375292	74	static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned idx)
cb7859a9	75	{
12375292	76	switch (idx) {
cb7859a9 FMH	77	case 0:
cb7859a9 FMH	78	case 1:
12375292	79	return NITIO_G01_STATUS1;
cb7859a9 FMH	80	case 2:
cb7859a9 FMH	81	case 3:
12375292	82	return NITIO_G23_STATUS1;
cb7859a9 FMH	83	}
	84	return 0;
	85	}
	86
12375292	87	static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned idx)
cb7859a9	88	{
12375292	89	switch (idx) {
cb7859a9 FMH	90	case 0:
cb7859a9 FMH	91	case 1:
12375292	92	return NITIO_G01_STATUS2;
cb7859a9 FMH	93	case 2:
cb7859a9 FMH	94	case 3:
12375292	95	return NITIO_G23_STATUS2;
cb7859a9 FMH	96	}
	97	return 0;
	98	}
	99
12375292	100	static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned idx)
cb7859a9	101	{
12375292	102	switch (idx) {
cb7859a9 FMH	103	case 0:
cb7859a9 FMH	104	case 1:
12375292	105	return NITIO_G01_STATUS;
cb7859a9 FMH	106	case 2:
cb7859a9 FMH	107	case 3:
12375292	108	return NITIO_G23_STATUS;
cb7859a9 FMH	109	}
	110	return 0;
	111	}
	112
12375292	113	static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(unsigned idx)
cb7859a9	114	{
12375292	115	switch (idx) {
cb7859a9	116	case 0:
12375292	117	return NITIO_G0_GATE2;
cb7859a9	118	case 1:
12375292	119	return NITIO_G1_GATE2;
cb7859a9	120	case 2:
12375292	121	return NITIO_G2_GATE2;
cb7859a9	122	case 3:
12375292	123	return NITIO_G3_GATE2;
cb7859a9 FMH	124	}
	125	return 0;
	126	}
	127
12375292	128	static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(unsigned idx)
cb7859a9	129	{
12375292	130	switch (idx) {
cb7859a9	131	case 0:
12375292	132	return NITIO_G0_DMA_CFG;
cb7859a9	133	case 1:
12375292	134	return NITIO_G1_DMA_CFG;
cb7859a9	135	case 2:
12375292	136	return NITIO_G2_DMA_CFG;
cb7859a9	137	case 3:
12375292	138	return NITIO_G3_DMA_CFG;
cb7859a9 FMH	139	}
	140	return 0;
	141	}
	142
12375292	143	static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(unsigned idx)
cb7859a9	144	{
12375292	145	switch (idx) {
cb7859a9	146	case 0:
12375292	147	return NITIO_G0_DMA_STATUS;
cb7859a9	148	case 1:
12375292	149	return NITIO_G1_DMA_STATUS;
cb7859a9	150	case 2:
12375292	151	return NITIO_G2_DMA_STATUS;
cb7859a9	152	case 3:
12375292	153	return NITIO_G3_DMA_STATUS;
cb7859a9 FMH	154	}
	155	return 0;
	156	}
	157
12375292	158	static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(unsigned idx)
cb7859a9	159	{
12375292	160	switch (idx) {
cb7859a9	161	case 0:
12375292	162	return NITIO_G0_ABZ;
cb7859a9	163	case 1:
12375292	164	return NITIO_G1_ABZ;
cb7859a9 FMH	165	}
	166	return 0;
	167	}
	168
12375292	169	static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(unsigned idx)
cb7859a9	170	{
12375292	171	switch (idx) {
cb7859a9	172	case 0:
12375292	173	return NITIO_G0_INT_ACK;
cb7859a9	174	case 1:
12375292	175	return NITIO_G1_INT_ACK;
cb7859a9	176	case 2:
12375292	177	return NITIO_G2_INT_ACK;
cb7859a9	178	case 3:
12375292	179	return NITIO_G3_INT_ACK;
cb7859a9 FMH	180	}
	181	return 0;
	182	}
	183
12375292	184	static inline enum ni_gpct_register NITIO_Gi_Status_Reg(unsigned idx)
cb7859a9	185	{
12375292	186	switch (idx) {
cb7859a9	187	case 0:
12375292	188	return NITIO_G0_STATUS;
cb7859a9	189	case 1:
12375292	190	return NITIO_G1_STATUS;
cb7859a9	191	case 2:
12375292	192	return NITIO_G2_STATUS;
cb7859a9	193	case 3:
12375292	194	return NITIO_G3_STATUS;
cb7859a9 FMH	195	}
	196	return 0;
	197	}
	198
12375292	199	static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(unsigned idx)
cb7859a9	200	{
12375292	201	switch (idx) {
cb7859a9	202	case 0:
12375292	203	return NITIO_G0_INT_ENA;
cb7859a9	204	case 1:
12375292	205	return NITIO_G1_INT_ENA;
cb7859a9	206	case 2:
12375292	207	return NITIO_G2_INT_ENA;
cb7859a9	208	case 3:
12375292	209	return NITIO_G3_INT_ENA;
cb7859a9 FMH	210	}
	211	return 0;
	212	}
	213
	214	enum Gi_Auto_Increment_Reg_Bits {
	215	Gi_Auto_Increment_Mask = 0xff
	216	};
	217
	218	#define Gi_Up_Down_Shift 5
	219	enum Gi_Command_Reg_Bits {
	220	Gi_Arm_Bit = 0x1,
	221	Gi_Save_Trace_Bit = 0x2,
	222	Gi_Load_Bit = 0x4,
	223	Gi_Disarm_Bit = 0x10,
	224	Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
	225	Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
	226	Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
	227	Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
	228	Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
	229	Gi_Write_Switch_Bit = 0x80,
	230	Gi_Synchronize_Gate_Bit = 0x100,
	231	Gi_Little_Big_Endian_Bit = 0x200,
	232	Gi_Bank_Switch_Start_Bit = 0x400,
	233	Gi_Bank_Switch_Mode_Bit = 0x800,
	234	Gi_Bank_Switch_Enable_Bit = 0x1000,
	235	Gi_Arm_Copy_Bit = 0x2000,
	236	Gi_Save_Trace_Copy_Bit = 0x4000,
	237	Gi_Disarm_Copy_Bit = 0x8000
	238	};
	239
	240	#define Gi_Index_Phase_Bitshift 5
	241	#define Gi_HW_Arm_Select_Shift 8
	242	enum Gi_Counting_Mode_Reg_Bits {
	243	Gi_Counting_Mode_Mask = 0x7,
	244	Gi_Counting_Mode_Normal_Bits = 0x0,
	245	Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
	246	Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
	247	Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
	248	Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
	249	Gi_Counting_Mode_Sync_Source_Bits = 0x6,
	250	Gi_Index_Mode_Bit = 0x10,
	251	Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
	252	Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
	253	Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
	254	Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
	255	Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
35c81aaa TK	256	/* from m-series example code, not documented in 660x register level
	257	* manual */
	258	Gi_HW_Arm_Enable_Bit = 0x80,
	259	/* from m-series example code, not documented in 660x register level
	260	* manual */
	261	Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
cb7859a9 FMH	262	Gi_660x_Prescale_X8_Bit = 0x1000,
	263	Gi_M_Series_Prescale_X8_Bit = 0x2000,
	264	Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
35c81aaa TK	265	/* must be set for clocks over 40MHz, which includes synchronous
35c81aaa TK	266	* counting and quadrature modes */
cb7859a9 FMH	267	Gi_660x_Alternate_Sync_Bit = 0x2000,
cb7859a9 FMH	268	Gi_M_Series_Alternate_Sync_Bit = 0x4000,
35c81aaa TK	269	/* from m-series example code, not documented in 660x register level
	270	* manual */
	271	Gi_660x_Prescale_X2_Bit = 0x4000,
cb7859a9 FMH	272	Gi_M_Series_Prescale_X2_Bit = 0x8000,
	273	};
	274
	275	#define Gi_Source_Select_Shift 2
	276	#define Gi_Gate_Select_Shift 7
	277	enum Gi_Input_Select_Bits {
2696fb57 BP	278	Gi_Read_Acknowledges_Irq = 0x1, /* not present on 660x */
2696fb57 BP	279	Gi_Write_Acknowledges_Irq = 0x2, /* not present on 660x */
cb7859a9 FMH	280	Gi_Source_Select_Mask = 0x7c,
	281	Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
	282	Gi_Gate_Select_Load_Source_Bit = 0x1000,
	283	Gi_Or_Gate_Bit = 0x2000,
	284	Gi_Output_Polarity_Bit = 0x4000, /* set to invert */
	285	Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
	286	};
	287
	288	enum Gi_Mode_Bits {
	289	Gi_Gating_Mode_Mask = 0x3,
	290	Gi_Gating_Disabled_Bits = 0x0,
	291	Gi_Level_Gating_Bits = 0x1,
	292	Gi_Rising_Edge_Gating_Bits = 0x2,
	293	Gi_Falling_Edge_Gating_Bits = 0x3,
35c81aaa TK	294	Gi_Gate_On_Both_Edges_Bit = 0x4, /* used in conjunction with
35c81aaa TK	295	* rising edge gating mode */
cb7859a9 FMH	296	Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
	297	Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
	298	Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
	299	Gi_Edge_Gate_Starts_Bits = 0x10,
	300	Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
	301	Gi_Stop_Mode_Mask = 0x60,
	302	Gi_Stop_on_Gate_Bits = 0x00,
	303	Gi_Stop_on_Gate_or_TC_Bits = 0x20,
	304	Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
	305	Gi_Load_Source_Select_Bit = 0x80,
	306	Gi_Output_Mode_Mask = 0x300,
	307	Gi_Output_TC_Pulse_Bits = 0x100,
	308	Gi_Output_TC_Toggle_Bits = 0x200,
	309	Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
	310	Gi_Counting_Once_Mask = 0xc00,
	311	Gi_No_Hardware_Disarm_Bits = 0x000,
	312	Gi_Disarm_at_TC_Bits = 0x400,
	313	Gi_Disarm_at_Gate_Bits = 0x800,
	314	Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
	315	Gi_Loading_On_TC_Bit = 0x1000,
	316	Gi_Gate_Polarity_Bit = 0x2000,
	317	Gi_Loading_On_Gate_Bit = 0x4000,
	318	Gi_Reload_Source_Switching_Bit = 0x8000
	319	};
	320
	321	#define Gi_Second_Gate_Select_Shift 7
	322	/FIXME: m-series has a second gate subselect bit /
	323	/FIXME: m-series second gate sources are undocumented (by NI)/
	324	enum Gi_Second_Gate_Bits {
	325	Gi_Second_Gate_Mode_Bit = 0x1,
	326	Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
	327	Gi_Second_Gate_Polarity_Bit = 0x2000,
	328	Gi_Second_Gate_Subselect_Bit = 0x4000, /* m-series only */
	329	Gi_Source_Subselect_Bit = 0x8000 /* m-series only */
	330	};
	331	static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
	332	{
	333	return (second_gate_select << Gi_Second_Gate_Select_Shift) &
0a85b6f0	334	Gi_Second_Gate_Select_Mask;
cb7859a9 FMH	335	}
	336
	337	enum Gxx_Status_Bits {
	338	G0_Save_Bit = 0x1,
	339	G1_Save_Bit = 0x2,
	340	G0_Counting_Bit = 0x4,
	341	G1_Counting_Bit = 0x8,
	342	G0_Next_Load_Source_Bit = 0x10,
	343	G1_Next_Load_Source_Bit = 0x20,
	344	G0_Stale_Data_Bit = 0x40,
	345	G1_Stale_Data_Bit = 0x80,
	346	G0_Armed_Bit = 0x100,
	347	G1_Armed_Bit = 0x200,
	348	G0_No_Load_Between_Gates_Bit = 0x400,
	349	G1_No_Load_Between_Gates_Bit = 0x800,
	350	G0_TC_Error_Bit = 0x1000,
	351	G1_TC_Error_Bit = 0x2000,
	352	G0_Gate_Error_Bit = 0x4000,
	353	G1_Gate_Error_Bit = 0x8000
	354	};
	355	static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
	356	{
	357	if (counter_index % 2)
	358	return G1_Counting_Bit;
	359	return G0_Counting_Bit;
	360	}
0a85b6f0	361
cb7859a9 FMH	362	static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
	363	{
	364	if (counter_index % 2)
	365	return G1_Armed_Bit;
	366	return G0_Armed_Bit;
	367	}
0a85b6f0	368
cb7859a9	369	static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
0a85b6f0	370	counter_index)
cb7859a9 FMH	371	{
	372	if (counter_index % 2)
	373	return G1_Next_Load_Source_Bit;
	374	return G0_Next_Load_Source_Bit;
	375	}
0a85b6f0	376
cb7859a9 FMH	377	static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
	378	{
	379	if (counter_index % 2)
	380	return G1_Stale_Data_Bit;
	381	return G0_Stale_Data_Bit;
	382	}
0a85b6f0	383
cb7859a9 FMH	384	static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
	385	{
	386	if (counter_index % 2)
	387	return G1_TC_Error_Bit;
	388	return G0_TC_Error_Bit;
	389	}
0a85b6f0	390
cb7859a9 FMH	391	static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
	392	{
	393	if (counter_index % 2)
	394	return G1_Gate_Error_Bit;
	395	return G0_Gate_Error_Bit;
	396	}
	397
	398	/* joint reset register bits */
	399	static inline unsigned Gi_Reset_Bit(unsigned counter_index)
	400	{
	401	return 0x1 << (2 + (counter_index % 2));
	402	}
	403
	404	enum Gxx_Joint_Status2_Bits {
	405	G0_Output_Bit = 0x1,
	406	G1_Output_Bit = 0x2,
	407	G0_HW_Save_Bit = 0x1000,
	408	G1_HW_Save_Bit = 0x2000,
	409	G0_Permanent_Stale_Bit = 0x4000,
	410	G1_Permanent_Stale_Bit = 0x8000
	411	};
	412	static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
0a85b6f0	413	counter_index)
cb7859a9 FMH	414	{
	415	if (counter_index % 2)
	416	return G1_Permanent_Stale_Bit;
	417	return G0_Permanent_Stale_Bit;
	418	}
	419
	420	enum Gi_DMA_Config_Reg_Bits {
	421	Gi_DMA_Enable_Bit = 0x1,
	422	Gi_DMA_Write_Bit = 0x2,
	423	Gi_DMA_Int_Bit = 0x4
	424	};
	425
	426	enum Gi_DMA_Status_Reg_Bits {
	427	Gi_DMA_Readbank_Bit = 0x2000,
	428	Gi_DRQ_Error_Bit = 0x4000,
	429	Gi_DRQ_Status_Bit = 0x8000
	430	};
	431
	432	enum G02_Interrupt_Acknowledge_Bits {
	433	G0_Gate_Error_Confirm_Bit = 0x20,
	434	G0_TC_Error_Confirm_Bit = 0x40
	435	};
	436	enum G13_Interrupt_Acknowledge_Bits {
	437	G1_Gate_Error_Confirm_Bit = 0x2,
	438	G1_TC_Error_Confirm_Bit = 0x4
	439	};
	440	static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
	441	{
	442	if (counter_index % 2)
	443	return G1_Gate_Error_Confirm_Bit;
	444	return G0_Gate_Error_Confirm_Bit;
	445	}
0a85b6f0	446
cb7859a9 FMH	447	static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
	448	{
	449	if (counter_index % 2)
	450	return G1_TC_Error_Confirm_Bit;
	451	return G0_TC_Error_Confirm_Bit;
	452	}
	453
2696fb57	454	/* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
cb7859a9 FMH	455	enum Gxx_Interrupt_Acknowledge_Bits {
	456	Gi_TC_Interrupt_Ack_Bit = 0x4000,
	457	Gi_Gate_Interrupt_Ack_Bit = 0x8000
	458	};
	459
	460	enum Gi_Status_Bits {
	461	Gi_Gate_Interrupt_Bit = 0x4,
	462	Gi_TC_Bit = 0x8,
	463	Gi_Interrupt_Bit = 0x8000
	464	};
	465
	466	enum G02_Interrupt_Enable_Bits {
	467	G0_TC_Interrupt_Enable_Bit = 0x40,
	468	G0_Gate_Interrupt_Enable_Bit = 0x100
	469	};
	470	enum G13_Interrupt_Enable_Bits {
	471	G1_TC_Interrupt_Enable_Bit = 0x200,
	472	G1_Gate_Interrupt_Enable_Bit = 0x400
	473	};
	474	static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
	475	{
	476	unsigned bit;
	477
933df659	478	if (counter_index % 2)
cb7859a9	479	bit = G1_Gate_Interrupt_Enable_Bit;
933df659	480	else
cb7859a9	481	bit = G0_Gate_Interrupt_Enable_Bit;
cb7859a9 FMH	482	return bit;
	483	}
	484
	485	static inline void write_register(struct ni_gpct *counter, unsigned bits,
0a85b6f0	486	enum ni_gpct_register reg)
cb7859a9	487	{
12375292	488	BUG_ON(reg >= NITIO_NUM_REGS);
cb7859a9 FMH	489	counter->counter_dev->write_register(counter, bits, reg);
	490	}
	491
	492	static inline unsigned read_register(struct ni_gpct *counter,
0a85b6f0	493	enum ni_gpct_register reg)
cb7859a9	494	{
12375292	495	BUG_ON(reg >= NITIO_NUM_REGS);
cb7859a9 FMH	496	return counter->counter_dev->read_register(counter, reg);
	497	}
	498
0a85b6f0 MT	499	static inline int ni_tio_counting_mode_registers_present(const struct
	500	ni_gpct_device
	501	*counter_dev)
cb7859a9 FMH	502	{
	503	switch (counter_dev->variant) {
	504	case ni_gpct_variant_e_series:
	505	return 0;
	506	break;
	507	case ni_gpct_variant_m_series:
	508	case ni_gpct_variant_660x:
	509	return 1;
	510	break;
	511	default:
	512	BUG();
	513	break;
	514	}
	515	return 0;
	516	}
	517
	518	static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
0a85b6f0 MT	519	enum ni_gpct_register
	520	register_index, unsigned bit_mask,
	521	unsigned bit_values,
	522	unsigned transient_bit_values)
cb7859a9 FMH	523	{
	524	struct ni_gpct_device *counter_dev = counter->counter_dev;
	525	unsigned long flags;
	526
12375292	527	BUG_ON(register_index >= NITIO_NUM_REGS);
5f74ea14	528	spin_lock_irqsave(&counter_dev->regs_lock, flags);
cb7859a9 FMH	529	counter_dev->regs[register_index] &= ~bit_mask;
	530	counter_dev->regs[register_index] \|= (bit_values & bit_mask);
	531	write_register(counter,
0a85b6f0 MT	532	counter_dev->regs[register_index] \| transient_bit_values,
0a85b6f0 MT	533	register_index);
cb7859a9	534	mmiowb();
5f74ea14	535	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
cb7859a9 FMH	536	}
	537
	538	/* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
35c81aaa TK	539	* twiddled in interrupt context, or whose software copy may be read in
	540	* interrupt context.
	541	*/
cb7859a9	542	static inline void ni_tio_set_bits(struct ni_gpct *counter,
0a85b6f0 MT	543	enum ni_gpct_register register_index,
0a85b6f0 MT	544	unsigned bit_mask, unsigned bit_values)
cb7859a9 FMH	545	{
cb7859a9 FMH	546	ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
0a85b6f0	547	0x0);
cb7859a9 FMH	548	}
	549
	550	/* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
	551	whose bits might be modified in interrupt context, or whose software copy
	552	might need to be read in interrupt context.
	553	*/
	554	static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
0a85b6f0 MT	555	enum ni_gpct_register
0a85b6f0 MT	556	register_index)
cb7859a9 FMH	557	{
	558	struct ni_gpct_device *counter_dev = counter->counter_dev;
	559	unsigned long flags;
	560	unsigned value;
	561
12375292	562	BUG_ON(register_index >= NITIO_NUM_REGS);
5f74ea14	563	spin_lock_irqsave(&counter_dev->regs_lock, flags);
cb7859a9	564	value = counter_dev->regs[register_index];
5f74ea14	565	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
cb7859a9 FMH	566	return value;
	567	}
	568
	569	int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
	570	int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
0a85b6f0	571	unsigned int gate_source);
cb7859a9 FMH	572
cb7859a9 FMH	573	#endif /* _COMEDI_NI_TIO_INTERNAL_H */