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Staging: Comedi: Lindent changes to comdi driver in staging tree
[linux-2.6-block.git] / drivers / staging / comedi / drivers / ni_tio.c
CommitLineData
cb7859a9
FMH		 1/*
2 comedi/drivers/ni_tio.c
3 Support for NI general purpose counters
4
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22/*
23Driver: ni_tio
24Description: National Instruments general purpose counters
25Devices:
26Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27 Herman.Bruyninckx@mech.kuleuven.ac.be,
28 Wim.Meeussen@mech.kuleuven.ac.be,
29 Klaas.Gadeyne@mech.kuleuven.ac.be,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
31Updated: Thu Nov 16 09:50:32 EST 2006
32Status: works
33
34This module is not used directly by end-users. Rather, it
35is used by other drivers (for example ni_660x and ni_pcimio)
36to provide support for NI's general purpose counters. It was
37originally based on the counter code from ni_660x.c and
38ni_mio_common.c.
39
40References:
41DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
42DAQ 6601/6602 User Manual (NI 322137B-01)
43340934b.pdf DAQ-STC reference manual
44
45*/
46/*
47TODO:
48 Support use of both banks X and Y
49*/
50
51#include "ni_tio_internal.h"
52
53static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
0a85b6f0 54 unsigned generic_clock_source);
cb7859a9
FMH		 55static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
56
57MODULE_AUTHOR("Comedi <comedi@comedi.org>");
58MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
59MODULE_LICENSE("GPL");
60
61static inline enum Gi_Counting_Mode_Reg_Bits Gi_Alternate_Sync_Bit(enum
0a85b6f0
MT		 62 ni_gpct_variant
63 variant)
cb7859a9
FMH		 64{
65 switch (variant) {
66 case ni_gpct_variant_e_series:
67 return 0;
68 break;
69 case ni_gpct_variant_m_series:
70 return Gi_M_Series_Alternate_Sync_Bit;
71 break;
72 case ni_gpct_variant_660x:
73 return Gi_660x_Alternate_Sync_Bit;
74 break;
75 default:
76 BUG();
77 break;
78 }
79 return 0;
80}
0a85b6f0 81
cb7859a9 82static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X2_Bit(enum
0a85b6f0
MT		 83 ni_gpct_variant
84 variant)
cb7859a9
FMH		 85{
86 switch (variant) {
87 case ni_gpct_variant_e_series:
88 return 0;
89 break;
90 case ni_gpct_variant_m_series:
91 return Gi_M_Series_Prescale_X2_Bit;
92 break;
93 case ni_gpct_variant_660x:
94 return Gi_660x_Prescale_X2_Bit;
95 break;
96 default:
97 BUG();
98 break;
99 }
100 return 0;
101}
0a85b6f0 102
cb7859a9 103static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X8_Bit(enum
0a85b6f0
MT		 104 ni_gpct_variant
105 variant)
cb7859a9
FMH		 106{
107 switch (variant) {
108 case ni_gpct_variant_e_series:
109 return 0;
110 break;
111 case ni_gpct_variant_m_series:
112 return Gi_M_Series_Prescale_X8_Bit;
113 break;
114 case ni_gpct_variant_660x:
115 return Gi_660x_Prescale_X8_Bit;
116 break;
117 default:
118 BUG();
119 break;
120 }
121 return 0;
122}
0a85b6f0 123
cb7859a9 124static inline enum Gi_Counting_Mode_Reg_Bits Gi_HW_Arm_Select_Mask(enum
0a85b6f0
MT		 125 ni_gpct_variant
126 variant)
cb7859a9
FMH		 127{
128 switch (variant) {
129 case ni_gpct_variant_e_series:
130 return 0;
131 break;
132 case ni_gpct_variant_m_series:
133 return Gi_M_Series_HW_Arm_Select_Mask;
134 break;
135 case ni_gpct_variant_660x:
136 return Gi_660x_HW_Arm_Select_Mask;
137 break;
138 default:
139 BUG();
140 break;
141 }
142 return 0;
143}
144
145/* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
146enum ni_660x_clock_source {
147 NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
148 NI_660x_Source_Pin_i_Clock = 0x1,
149 NI_660x_Next_Gate_Clock = 0xa,
150 NI_660x_Timebase_2_Clock = 0x12, /* 100KHz */
151 NI_660x_Next_TC_Clock = 0x13,
152 NI_660x_Timebase_3_Clock = 0x1e, /* 80MHz */
153 NI_660x_Logic_Low_Clock = 0x1f,
154};
155static const unsigned ni_660x_max_rtsi_channel = 6;
156static inline unsigned NI_660x_RTSI_Clock(unsigned n)
157{
158 BUG_ON(n > ni_660x_max_rtsi_channel);
dae0dc30 159 return 0xb + n;
cb7859a9 160}
0a85b6f0 161
cb7859a9
FMH		 162static const unsigned ni_660x_max_source_pin = 7;
163static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
164{
165 BUG_ON(n > ni_660x_max_source_pin);
dae0dc30 166 return 0x2 + n;
cb7859a9
FMH		 167}
168
169/* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
170enum ni_m_series_clock_source {
171 NI_M_Series_Timebase_1_Clock = 0x0, /* 20MHz */
172 NI_M_Series_Timebase_2_Clock = 0x12, /* 100KHz */
173 NI_M_Series_Next_TC_Clock = 0x13,
174 NI_M_Series_Next_Gate_Clock = 0x14, /* when Gi_Src_SubSelect = 0 */
175 NI_M_Series_PXI_Star_Trigger_Clock = 0x14, /* when Gi_Src_SubSelect = 1 */
176 NI_M_Series_PXI10_Clock = 0x1d,
177 NI_M_Series_Timebase_3_Clock = 0x1e, /* 80MHz, when Gi_Src_SubSelect = 0 */
178 NI_M_Series_Analog_Trigger_Out_Clock = 0x1e, /* when Gi_Src_SubSelect = 1 */
179 NI_M_Series_Logic_Low_Clock = 0x1f,
180};
181static const unsigned ni_m_series_max_pfi_channel = 15;
182static inline unsigned NI_M_Series_PFI_Clock(unsigned n)
183{
184 BUG_ON(n > ni_m_series_max_pfi_channel);
185 if (n < 10)
186 return 1 + n;
187 else
188 return 0xb + n;
189}
0a85b6f0 190
cb7859a9
FMH		 191static const unsigned ni_m_series_max_rtsi_channel = 7;
192static inline unsigned NI_M_Series_RTSI_Clock(unsigned n)
193{
194 BUG_ON(n > ni_m_series_max_rtsi_channel);
195 if (n == 7)
196 return 0x1b;
197 else
198 return 0xb + n;
199}
200
201enum ni_660x_gate_select {
202 NI_660x_Source_Pin_i_Gate_Select = 0x0,
203 NI_660x_Gate_Pin_i_Gate_Select = 0x1,
204 NI_660x_Next_SRC_Gate_Select = 0xa,
205 NI_660x_Next_Out_Gate_Select = 0x14,
206 NI_660x_Logic_Low_Gate_Select = 0x1f,
207};
208static const unsigned ni_660x_max_gate_pin = 7;
209static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
210{
211 BUG_ON(n > ni_660x_max_gate_pin);
212 return 0x2 + n;
213}
0a85b6f0 214
cb7859a9
FMH		 215static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
216{
217 BUG_ON(n > ni_660x_max_rtsi_channel);
218 return 0xb + n;
219}
220
221enum ni_m_series_gate_select {
222 NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
223 NI_M_Series_AI_START2_Gate_Select = 0x12,
224 NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
225 NI_M_Series_Next_Out_Gate_Select = 0x14,
226 NI_M_Series_AI_START1_Gate_Select = 0x1c,
227 NI_M_Series_Next_SRC_Gate_Select = 0x1d,
228 NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
229 NI_M_Series_Logic_Low_Gate_Select = 0x1f,
230};
231static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
232{
233 BUG_ON(n > ni_m_series_max_rtsi_channel);
234 if (n == 7)
235 return 0x1b;
236 return 0xb + n;
237}
0a85b6f0 238
cb7859a9
FMH		 239static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
240{
241 BUG_ON(n > ni_m_series_max_pfi_channel);
242 if (n < 10)
243 return 1 + n;
244 return 0xb + n;
245}
246
247static inline unsigned Gi_Source_Select_Bits(unsigned source)
248{
249 return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
250}
0a85b6f0 251
cb7859a9
FMH		 252static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
253{
254 return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
255}
256
257enum ni_660x_second_gate_select {
258 NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
259 NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
260 NI_660x_Next_SRC_Second_Gate_Select = 0xa,
261 NI_660x_Next_Out_Second_Gate_Select = 0x14,
262 NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
263 NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
264};
265static const unsigned ni_660x_max_up_down_pin = 7;
266static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
267{
268 BUG_ON(n > ni_660x_max_up_down_pin);
269 return 0x2 + n;
270}
0a85b6f0 271
cb7859a9
FMH		 272static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
273{
274 BUG_ON(n > ni_660x_max_rtsi_channel);
275 return 0xb + n;
276}
277
790c5541 278static const unsigned int counter_status_mask =
0a85b6f0 279 COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
cb7859a9
FMH		 280
281static int __init ni_tio_init_module(void)
282{
283 return 0;
284}
285
286module_init(ni_tio_init_module);
287
288static void __exit ni_tio_cleanup_module(void)
289{
290}
291
292module_exit(ni_tio_cleanup_module);
293
0a85b6f0
MT		 294struct ni_gpct_device *ni_gpct_device_construct(struct comedi_device *dev,
295 void (*write_register) (struct
296 ni_gpct
297 *
298 counter,
299 unsigned
300 bits,
301 enum
302 ni_gpct_register
303 reg),
304 unsigned (*read_register)
305 (struct ni_gpct * counter,
306 enum ni_gpct_register reg),
307 enum ni_gpct_variant variant,
308 unsigned num_counters)
cb7859a9
FMH		 309{
310 unsigned i;
311
312 struct ni_gpct_device *counter_dev =
0a85b6f0 313 kzalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
cb7859a9
FMH		 314 if (counter_dev == NULL)
315 return NULL;
316 counter_dev->dev = dev;
317 counter_dev->write_register = write_register;
318 counter_dev->read_register = read_register;
319 counter_dev->variant = variant;
320 spin_lock_init(&counter_dev->regs_lock);
321 BUG_ON(num_counters == 0);
322 counter_dev->counters =
0a85b6f0 323 kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
cb7859a9
FMH		 324 if (counter_dev->counters == NULL) {
325 kfree(counter_dev);
326 return NULL;
327 }
328 for (i = 0; i < num_counters; ++i) {
329 counter_dev->counters[i].counter_dev = counter_dev;
330 spin_lock_init(&counter_dev->counters[i].lock);
331 }
332 counter_dev->num_counters = num_counters;
333 return counter_dev;
334}
335
336void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
337{
338 if (counter_dev->counters == NULL)
339 return;
340 kfree(counter_dev->counters);
341 kfree(counter_dev);
342}
343
344static int ni_tio_second_gate_registers_present(const struct ni_gpct_device
0a85b6f0 345 *counter_dev)
cb7859a9
FMH		 346{
347 switch (counter_dev->variant) {
348 case ni_gpct_variant_e_series:
349 return 0;
350 break;
351 case ni_gpct_variant_m_series:
352 case ni_gpct_variant_660x:
353 return 1;
354 break;
355 default:
356 BUG();
357 break;
358 }
359 return 0;
360}
361
362static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
363{
364 write_register(counter, Gi_Reset_Bit(counter->counter_index),
0a85b6f0 365 NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
cb7859a9
FMH		 366}
367
368void ni_tio_init_counter(struct ni_gpct *counter)
369{
370 struct ni_gpct_device *counter_dev = counter->counter_dev;
371
372 ni_tio_reset_count_and_disarm(counter);
373 /* initialize counter registers */
374 counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] =
0a85b6f0 375 0x0;
cb7859a9 376 write_register(counter,
0a85b6f0
MT		 377 counter_dev->
378 regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
379 NITIO_Gi_Autoincrement_Reg(counter->counter_index));
cb7859a9 380 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
0a85b6f0 381 ~0, Gi_Synchronize_Gate_Bit);
cb7859a9 382 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
0a85b6f0 383 0);
cb7859a9
FMH		 384 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
385 write_register(counter,
0a85b6f0
MT		 386 counter_dev->
387 regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
388 NITIO_Gi_LoadA_Reg(counter->counter_index));
cb7859a9
FMH		 389 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
390 write_register(counter,
0a85b6f0
MT		 391 counter_dev->
392 regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
393 NITIO_Gi_LoadB_Reg(counter->counter_index));
cb7859a9 394 ni_tio_set_bits(counter,
0a85b6f0
MT		 395 NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0,
396 0);
cb7859a9
FMH		 397 if (ni_tio_counting_mode_registers_present(counter_dev)) {
398 ni_tio_set_bits(counter,
0a85b6f0
MT		 399 NITIO_Gi_Counting_Mode_Reg(counter->
400 counter_index), ~0,
401 0);
cb7859a9
FMH		 402 }
403 if (ni_tio_second_gate_registers_present(counter_dev)) {
0a85b6f0
MT		 404 counter_dev->
405 regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] =
406 0x0;
cb7859a9 407 write_register(counter,
0a85b6f0
MT		 408 counter_dev->
409 regs[NITIO_Gi_Second_Gate_Reg
410 (counter->counter_index)],
411 NITIO_Gi_Second_Gate_Reg(counter->
412 counter_index));
cb7859a9
FMH		 413 }
414 ni_tio_set_bits(counter,
0a85b6f0
MT		 415 NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0,
416 0x0);
cb7859a9 417 ni_tio_set_bits(counter,
0a85b6f0
MT		 418 NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
419 ~0, 0x0);
cb7859a9
FMH		 420}
421
790c5541 422static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
cb7859a9 423{
790c5541 424 unsigned int status = 0;
cb7859a9 425 const unsigned bits = read_register(counter,
0a85b6f0
MT		 426 NITIO_Gxx_Status_Reg(counter->
427 counter_index));
cb7859a9
FMH		 428 if (bits & Gi_Armed_Bit(counter->counter_index)) {
429 status |= COMEDI_COUNTER_ARMED;
430 if (bits & Gi_Counting_Bit(counter->counter_index))
431 status |= COMEDI_COUNTER_COUNTING;
432 }
433 return status;
434}
435
436static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
437{
438 struct ni_gpct_device *counter_dev = counter->counter_dev;
439 const unsigned counting_mode_reg =
0a85b6f0 440 NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
cb7859a9
FMH		 441 static const uint64_t min_normal_sync_period_ps = 25000;
442 const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
0a85b6f0
MT		 443 ni_tio_generic_clock_src_select
444 (counter));
cb7859a9
FMH		 445
446 if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
447 return;
448
449 switch (ni_tio_get_soft_copy(counter,
0a85b6f0
MT		 450 counting_mode_reg) & Gi_Counting_Mode_Mask)
451 {
cb7859a9
FMH		 452 case Gi_Counting_Mode_QuadratureX1_Bits:
453 case Gi_Counting_Mode_QuadratureX2_Bits:
454 case Gi_Counting_Mode_QuadratureX4_Bits:
455 case Gi_Counting_Mode_Sync_Source_Bits:
456 force_alt_sync = 1;
457 break;
458 default:
459 break;
460 }
461 /* It's not clear what we should do if clock_period is unknown, so we are not
462 using the alt sync bit in that case, but allow the caller to decide by using the
463 force_alt_sync parameter. */
464 if (force_alt_sync ||
0a85b6f0 465 (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
cb7859a9 466 ni_tio_set_bits(counter, counting_mode_reg,
0a85b6f0
MT		 467 Gi_Alternate_Sync_Bit(counter_dev->variant),
468 Gi_Alternate_Sync_Bit(counter_dev->variant));
cb7859a9
FMH		 469 } else {
470 ni_tio_set_bits(counter, counting_mode_reg,
0a85b6f0
MT		 471 Gi_Alternate_Sync_Bit(counter_dev->variant),
472 0x0);
cb7859a9
FMH		 473 }
474}
475
476static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
477{
478 struct ni_gpct_device *counter_dev = counter->counter_dev;
479 unsigned mode_reg_mask;
480 unsigned mode_reg_values;
481 unsigned input_select_bits = 0;
482 /* these bits map directly on to the mode register */
483 static const unsigned mode_reg_direct_mask =
0a85b6f0
MT		 484 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
485 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
486 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
487 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
cb7859a9
FMH		 488
489 mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
490 mode_reg_values = mode & mode_reg_direct_mask;
491 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
492 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
493 break;
494 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
495 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
496 break;
497 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
498 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
499 mode_reg_mask |= Gi_Gating_Mode_Mask;
500 mode_reg_values |= Gi_Level_Gating_Bits;
501 break;
502 default:
503 break;
504 }
505 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
0a85b6f0 506 mode_reg_mask, mode_reg_values);
cb7859a9
FMH		 507
508 if (ni_tio_counting_mode_registers_present(counter_dev)) {
509 unsigned counting_mode_bits = 0;
510 counting_mode_bits |=
0a85b6f0
MT		 511 (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
512 Gi_Counting_Mode_Mask;
cb7859a9 513 counting_mode_bits |=
0a85b6f0
MT		 514 ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
515 Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
cb7859a9
FMH		 516 if (mode & NI_GPCT_INDEX_ENABLE_BIT) {
517 counting_mode_bits |= Gi_Index_Mode_Bit;
518 }
519 ni_tio_set_bits(counter,
0a85b6f0
MT		 520 NITIO_Gi_Counting_Mode_Reg(counter->
521 counter_index),
522 Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
523 Gi_Index_Mode_Bit, counting_mode_bits);
cb7859a9
FMH		 524 ni_tio_set_sync_mode(counter, 0);
525 }
526
527 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
0a85b6f0
MT		 528 Gi_Up_Down_Mask,
529 (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
530 Gi_Up_Down_Shift);
cb7859a9
FMH		 531
532 if (mode & NI_GPCT_OR_GATE_BIT) {
533 input_select_bits |= Gi_Or_Gate_Bit;
534 }
535 if (mode & NI_GPCT_INVERT_OUTPUT_BIT) {
536 input_select_bits |= Gi_Output_Polarity_Bit;
537 }
538 ni_tio_set_bits(counter,
0a85b6f0
MT		 539 NITIO_Gi_Input_Select_Reg(counter->counter_index),
540 Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
541 Gi_Output_Polarity_Bit, input_select_bits);
cb7859a9
FMH		 542
543 return 0;
544}
545
546int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
547{
548 struct ni_gpct_device *counter_dev = counter->counter_dev;
549
550 unsigned command_transient_bits = 0;
551
552 if (arm) {
553 switch (start_trigger) {
554 case NI_GPCT_ARM_IMMEDIATE:
555 command_transient_bits |= Gi_Arm_Bit;
556 break;
557 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
558 command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
559 break;
560 default:
561 break;
562 }
563 if (ni_tio_counting_mode_registers_present(counter_dev)) {
564 unsigned counting_mode_bits = 0;
565
566 switch (start_trigger) {
567 case NI_GPCT_ARM_IMMEDIATE:
568 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
569 break;
570 default:
571 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
572 /* pass-through the least significant bits so we can figure out what select later */
573 unsigned hw_arm_select_bits =
0a85b6f0
MT		 574 (start_trigger <<
575 Gi_HW_Arm_Select_Shift) &
576 Gi_HW_Arm_Select_Mask
577 (counter_dev->variant);
cb7859a9
FMH		 578
579 counting_mode_bits |=
0a85b6f0
MT		 580 Gi_HW_Arm_Enable_Bit |
581 hw_arm_select_bits;
cb7859a9
FMH		 582 } else {
583 return -EINVAL;
584 }
585 break;
586 }
587 ni_tio_set_bits(counter,
0a85b6f0
MT		 588 NITIO_Gi_Counting_Mode_Reg
589 (counter->counter_index),
590 Gi_HW_Arm_Select_Mask
591 (counter_dev->variant) |
592 Gi_HW_Arm_Enable_Bit,
593 counting_mode_bits);
cb7859a9
FMH		 594 }
595 } else {
596 command_transient_bits |= Gi_Disarm_Bit;
597 }
598 ni_tio_set_bits_transient(counter,
0a85b6f0
MT		 599 NITIO_Gi_Command_Reg(counter->counter_index),
600 0, 0, command_transient_bits);
cb7859a9
FMH		 601 return 0;
602}
603
790c5541 604static unsigned ni_660x_source_select_bits(unsigned int clock_source)
cb7859a9
FMH		 605{
606 unsigned ni_660x_clock;
607 unsigned i;
608 const unsigned clock_select_bits =
0a85b6f0 609 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
cb7859a9
FMH		 610
611 switch (clock_select_bits) {
612 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
613 ni_660x_clock = NI_660x_Timebase_1_Clock;
614 break;
615 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
616 ni_660x_clock = NI_660x_Timebase_2_Clock;
617 break;
618 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
619 ni_660x_clock = NI_660x_Timebase_3_Clock;
620 break;
621 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
622 ni_660x_clock = NI_660x_Logic_Low_Clock;
623 break;
624 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
625 ni_660x_clock = NI_660x_Source_Pin_i_Clock;
626 break;
627 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
628 ni_660x_clock = NI_660x_Next_Gate_Clock;
629 break;
630 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
631 ni_660x_clock = NI_660x_Next_TC_Clock;
632 break;
633 default:
634 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
635 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
636 ni_660x_clock = NI_660x_RTSI_Clock(i);
637 break;
638 }
639 }
640 if (i <= ni_660x_max_rtsi_channel)
641 break;
642 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
643 if (clock_select_bits ==
0a85b6f0 644 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
cb7859a9
FMH		 645 ni_660x_clock = NI_660x_Source_Pin_Clock(i);
646 break;
647 }
648 }
649 if (i <= ni_660x_max_source_pin)
650 break;
651 ni_660x_clock = 0;
652 BUG();
653 break;
654 }
655 return Gi_Source_Select_Bits(ni_660x_clock);
656}
657
790c5541 658static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
cb7859a9
FMH		 659{
660 unsigned ni_m_series_clock;
661 unsigned i;
662 const unsigned clock_select_bits =
0a85b6f0 663 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
cb7859a9
FMH		 664 switch (clock_select_bits) {
665 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
666 ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
667 break;
668 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
669 ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
670 break;
671 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
672 ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
673 break;
674 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
675 ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
676 break;
677 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
678 ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
679 break;
680 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
681 ni_m_series_clock = NI_M_Series_Next_TC_Clock;
682 break;
683 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
684 ni_m_series_clock = NI_M_Series_PXI10_Clock;
685 break;
686 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
687 ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
688 break;
689 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
690 ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
691 break;
692 default:
693 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
694 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
695 ni_m_series_clock = NI_M_Series_RTSI_Clock(i);
696 break;
697 }
698 }
699 if (i <= ni_m_series_max_rtsi_channel)
700 break;
701 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
702 if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
703 ni_m_series_clock = NI_M_Series_PFI_Clock(i);
704 break;
705 }
706 }
707 if (i <= ni_m_series_max_pfi_channel)
708 break;
5f74ea14 709 printk("invalid clock source 0x%lx\n",
0a85b6f0 710 (unsigned long)clock_source);
cb7859a9
FMH		 711 BUG();
712 ni_m_series_clock = 0;
713 break;
714 }
715 return Gi_Source_Select_Bits(ni_m_series_clock);
716};
717
718static void ni_tio_set_source_subselect(struct ni_gpct *counter,
0a85b6f0 719 unsigned int clock_source)
cb7859a9
FMH		 720{
721 struct ni_gpct_device *counter_dev = counter->counter_dev;
722 const unsigned second_gate_reg =
0a85b6f0 723 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
cb7859a9
FMH		 724
725 if (counter_dev->variant != ni_gpct_variant_m_series)
726 return;
727 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
728 /* Gi_Source_Subselect is zero */
729 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
730 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
731 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
732 break;
733 /* Gi_Source_Subselect is one */
734 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
735 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
736 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
737 break;
738 /* Gi_Source_Subselect doesn't matter */
739 default:
740 return;
741 break;
742 }
743 write_register(counter, counter_dev->regs[second_gate_reg],
0a85b6f0 744 second_gate_reg);
cb7859a9
FMH		 745}
746
747static int ni_tio_set_clock_src(struct ni_gpct *counter,
0a85b6f0
MT		 748 unsigned int clock_source,
749 unsigned int period_ns)
cb7859a9
FMH		 750{
751 struct ni_gpct_device *counter_dev = counter->counter_dev;
752 unsigned input_select_bits = 0;
753 static const uint64_t pico_per_nano = 1000;
754
755/*FIXME: validate clock source */
756 switch (counter_dev->variant) {
757 case ni_gpct_variant_660x:
758 input_select_bits |= ni_660x_source_select_bits(clock_source);
759 break;
760 case ni_gpct_variant_e_series:
761 case ni_gpct_variant_m_series:
762 input_select_bits |=
0a85b6f0 763 ni_m_series_source_select_bits(clock_source);
cb7859a9
FMH		 764 break;
765 default:
766 BUG();
767 break;
768 }
769 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
770 input_select_bits |= Gi_Source_Polarity_Bit;
771 ni_tio_set_bits(counter,
0a85b6f0
MT		 772 NITIO_Gi_Input_Select_Reg(counter->counter_index),
773 Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
774 input_select_bits);
cb7859a9
FMH		 775 ni_tio_set_source_subselect(counter, clock_source);
776 if (ni_tio_counting_mode_registers_present(counter_dev)) {
777 const unsigned prescaling_mode =
0a85b6f0 778 clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
cb7859a9
FMH		 779 unsigned counting_mode_bits = 0;
780
781 switch (prescaling_mode) {
782 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
783 break;
784 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
785 counting_mode_bits |=
0a85b6f0 786 Gi_Prescale_X2_Bit(counter_dev->variant);
cb7859a9
FMH		 787 break;
788 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
789 counting_mode_bits |=
0a85b6f0 790 Gi_Prescale_X8_Bit(counter_dev->variant);
cb7859a9
FMH		 791 break;
792 default:
793 return -EINVAL;
794 break;
795 }
796 ni_tio_set_bits(counter,
0a85b6f0
MT		 797 NITIO_Gi_Counting_Mode_Reg(counter->
798 counter_index),
799 Gi_Prescale_X2_Bit(counter_dev->variant) |
800 Gi_Prescale_X8_Bit(counter_dev->variant),
801 counting_mode_bits);
cb7859a9
FMH		 802 }
803 counter->clock_period_ps = pico_per_nano * period_ns;
804 ni_tio_set_sync_mode(counter, 0);
805 return 0;
806}
807
808static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
809{
810 struct ni_gpct_device *counter_dev = counter->counter_dev;
811 const unsigned counting_mode_bits = ni_tio_get_soft_copy(counter,
0a85b6f0
MT		 812 NITIO_Gi_Counting_Mode_Reg
813 (counter->
814 counter_index));
cb7859a9
FMH		 815 unsigned bits = 0;
816
817 if (ni_tio_get_soft_copy(counter,
0a85b6f0
MT		 818 NITIO_Gi_Input_Select_Reg
819 (counter->counter_index)) &
820 Gi_Source_Polarity_Bit)
cb7859a9
FMH		 821 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
822 if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
823 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
824 if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
825 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
826 return bits;
827}
828
829static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
830{
831 struct ni_gpct_device *counter_dev = counter->counter_dev;
832 const unsigned second_gate_reg =
0a85b6f0 833 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
cb7859a9
FMH		 834 unsigned clock_source = 0;
835 unsigned i;
836 const unsigned input_select = (ni_tio_get_soft_copy(counter,
0a85b6f0
MT		 837 NITIO_Gi_Input_Select_Reg
838 (counter->counter_index))
839 & Gi_Source_Select_Mask) >>
840 Gi_Source_Select_Shift;
cb7859a9
FMH		 841
842 switch (input_select) {
843 case NI_M_Series_Timebase_1_Clock:
844 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
845 break;
846 case NI_M_Series_Timebase_2_Clock:
847 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
848 break;
849 case NI_M_Series_Timebase_3_Clock:
0a85b6f0
MT		 850 if (counter_dev->regs[second_gate_reg] &
851 Gi_Source_Subselect_Bit)
cb7859a9 852 clock_source =
0a85b6f0 853 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
cb7859a9
FMH		 854 else
855 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
856 break;
857 case NI_M_Series_Logic_Low_Clock:
858 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
859 break;
860 case NI_M_Series_Next_Gate_Clock:
0a85b6f0
MT		 861 if (counter_dev->regs[second_gate_reg] &
862 Gi_Source_Subselect_Bit)
cb7859a9
FMH		 863 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
864 else
865 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
866 break;
867 case NI_M_Series_PXI10_Clock:
868 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
869 break;
870 case NI_M_Series_Next_TC_Clock:
871 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
872 break;
873 default:
874 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
875 if (input_select == NI_M_Series_RTSI_Clock(i)) {
876 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
877 break;
878 }
879 }
880 if (i <= ni_m_series_max_rtsi_channel)
881 break;
882 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
883 if (input_select == NI_M_Series_PFI_Clock(i)) {
884 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
885 break;
886 }
887 }
888 if (i <= ni_m_series_max_pfi_channel)
889 break;
890 BUG();
891 break;
892 }
893 clock_source |= ni_tio_clock_src_modifiers(counter);
894 return clock_source;
895}
896
897static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
898{
899 unsigned clock_source = 0;
900 unsigned i;
901 const unsigned input_select = (ni_tio_get_soft_copy(counter,
0a85b6f0
MT		 902 NITIO_Gi_Input_Select_Reg
903 (counter->counter_index))
904 & Gi_Source_Select_Mask) >>
905 Gi_Source_Select_Shift;
cb7859a9
FMH		 906
907 switch (input_select) {
908 case NI_660x_Timebase_1_Clock:
909 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
910 break;
911 case NI_660x_Timebase_2_Clock:
912 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
913 break;
914 case NI_660x_Timebase_3_Clock:
915 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
916 break;
917 case NI_660x_Logic_Low_Clock:
918 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
919 break;
920 case NI_660x_Source_Pin_i_Clock:
921 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
922 break;
923 case NI_660x_Next_Gate_Clock:
924 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
925 break;
926 case NI_660x_Next_TC_Clock:
927 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
928 break;
929 default:
930 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
931 if (input_select == NI_660x_RTSI_Clock(i)) {
932 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
933 break;
934 }
935 }
936 if (i <= ni_660x_max_rtsi_channel)
937 break;
938 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
939 if (input_select == NI_660x_Source_Pin_Clock(i)) {
940 clock_source =
0a85b6f0 941 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
cb7859a9
FMH		 942 break;
943 }
944 }
945 if (i <= ni_660x_max_source_pin)
946 break;
947 BUG();
948 break;
949 }
950 clock_source |= ni_tio_clock_src_modifiers(counter);
951 return clock_source;
952}
953
954static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
955{
956 switch (counter->counter_dev->variant) {
957 case ni_gpct_variant_e_series:
958 case ni_gpct_variant_m_series:
959 return ni_m_series_clock_src_select(counter);
960 break;
961 case ni_gpct_variant_660x:
962 return ni_660x_clock_src_select(counter);
963 break;
964 default:
965 BUG();
966 break;
967 }
968 return 0;
969}
970
971static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
0a85b6f0 972 unsigned generic_clock_source)
cb7859a9
FMH		 973{
974 uint64_t clock_period_ps;
975
976 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
977 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
978 clock_period_ps = 50000;
979 break;
980 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
981 clock_period_ps = 10000000;
982 break;
983 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
984 clock_period_ps = 12500;
985 break;
986 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
987 clock_period_ps = 100000;
988 break;
989 default:
990 /* clock period is specified by user with prescaling already taken into account. */
991 return counter->clock_period_ps;
992 break;
993 }
994
995 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
996 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
997 break;
998 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
999 clock_period_ps *= 2;
1000 break;
1001 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
1002 clock_period_ps *= 8;
1003 break;
1004 default:
1005 BUG();
1006 break;
1007 }
1008 return clock_period_ps;
1009}
1010
1011static void ni_tio_get_clock_src(struct ni_gpct *counter,
0a85b6f0
MT		 1012 unsigned int *clock_source,
1013 unsigned int *period_ns)
cb7859a9
FMH		 1014{
1015 static const unsigned pico_per_nano = 1000;
1016 uint64_t temp64;
1017 *clock_source = ni_tio_generic_clock_src_select(counter);
1018 temp64 = ni_tio_clock_period_ps(counter, *clock_source);
1019 do_div(temp64, pico_per_nano);
1020 *period_ns = temp64;
1021}
1022
1023static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
0a85b6f0 1024 unsigned int gate_source)
cb7859a9
FMH		 1025{
1026 const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
1027 unsigned mode_values = 0;
1028
1029 if (gate_source & CR_INVERT) {
1030 mode_values |= Gi_Gate_Polarity_Bit;
1031 }
1032 if (gate_source & CR_EDGE) {
1033 mode_values |= Gi_Rising_Edge_Gating_Bits;
1034 } else {
1035 mode_values |= Gi_Level_Gating_Bits;
1036 }
1037 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
0a85b6f0 1038 mode_mask, mode_values);
cb7859a9
FMH		 1039}
1040
0a85b6f0
MT		 1041static int ni_660x_set_first_gate(struct ni_gpct *counter,
1042 unsigned int gate_source)
cb7859a9
FMH		 1043{
1044 const unsigned selected_gate = CR_CHAN(gate_source);
1045 /* bits of selected_gate that may be meaningful to input select register */
1046 const unsigned selected_gate_mask = 0x1f;
1047 unsigned ni_660x_gate_select;
1048 unsigned i;
1049
1050 switch (selected_gate) {
1051 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1052 ni_660x_gate_select = NI_660x_Next_SRC_Gate_Select;
1053 break;
1054 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1055 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1056 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1057 case NI_GPCT_GATE_PIN_i_GATE_SELECT:
1058 ni_660x_gate_select = selected_gate & selected_gate_mask;
1059 break;
1060 default:
1061 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1062 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1063 ni_660x_gate_select =
0a85b6f0 1064 selected_gate & selected_gate_mask;
cb7859a9
FMH		 1065 break;
1066 }
1067 }
1068 if (i <= ni_660x_max_rtsi_channel)
1069 break;
1070 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1071 if (selected_gate == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
1072 ni_660x_gate_select =
0a85b6f0 1073 selected_gate & selected_gate_mask;
cb7859a9
FMH		 1074 break;
1075 }
1076 }
1077 if (i <= ni_660x_max_gate_pin)
1078 break;
1079 return -EINVAL;
1080 break;
1081 }
1082 ni_tio_set_bits(counter,
0a85b6f0
MT		 1083 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1084 Gi_Gate_Select_Mask,
1085 Gi_Gate_Select_Bits(ni_660x_gate_select));
cb7859a9
FMH		 1086 return 0;
1087}
1088
1089static int ni_m_series_set_first_gate(struct ni_gpct *counter,
0a85b6f0 1090 unsigned int gate_source)
cb7859a9
FMH		 1091{
1092 const unsigned selected_gate = CR_CHAN(gate_source);
1093 /* bits of selected_gate that may be meaningful to input select register */
1094 const unsigned selected_gate_mask = 0x1f;
1095 unsigned ni_m_series_gate_select;
1096 unsigned i;
1097
1098 switch (selected_gate) {
1099 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
1100 case NI_GPCT_AI_START2_GATE_SELECT:
1101 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
1102 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1103 case NI_GPCT_AI_START1_GATE_SELECT:
1104 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1105 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
1106 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1107 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1108 break;
1109 default:
1110 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1111 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1112 ni_m_series_gate_select =
0a85b6f0 1113 selected_gate & selected_gate_mask;
cb7859a9
FMH		 1114 break;
1115 }
1116 }
1117 if (i <= ni_m_series_max_rtsi_channel)
1118 break;
1119 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1120 if (selected_gate == NI_GPCT_PFI_GATE_SELECT(i)) {
1121 ni_m_series_gate_select =
0a85b6f0 1122 selected_gate & selected_gate_mask;
cb7859a9
FMH		 1123 break;
1124 }
1125 }
1126 if (i <= ni_m_series_max_pfi_channel)
1127 break;
1128 return -EINVAL;
1129 break;
1130 }
1131 ni_tio_set_bits(counter,
0a85b6f0
MT		 1132 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1133 Gi_Gate_Select_Mask,
1134 Gi_Gate_Select_Bits(ni_m_series_gate_select));
cb7859a9
FMH		 1135 return 0;
1136}
1137
1138static int ni_660x_set_second_gate(struct ni_gpct *counter,
0a85b6f0 1139 unsigned int gate_source)
cb7859a9
FMH		 1140{
1141 struct ni_gpct_device *counter_dev = counter->counter_dev;
1142 const unsigned second_gate_reg =
0a85b6f0 1143 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
cb7859a9
FMH		 1144 const unsigned selected_second_gate = CR_CHAN(gate_source);
1145 /* bits of second_gate that may be meaningful to second gate register */
1146 static const unsigned selected_second_gate_mask = 0x1f;
1147 unsigned ni_660x_second_gate_select;
1148 unsigned i;
1149
1150 switch (selected_second_gate) {
1151 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1152 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
1153 case NI_GPCT_SELECTED_GATE_GATE_SELECT:
1154 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1155 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1156 ni_660x_second_gate_select =
0a85b6f0 1157 selected_second_gate & selected_second_gate_mask;
cb7859a9
FMH		 1158 break;
1159 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1160 ni_660x_second_gate_select =
0a85b6f0 1161 NI_660x_Next_SRC_Second_Gate_Select;
cb7859a9
FMH		 1162 break;
1163 default:
1164 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1165 if (selected_second_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1166 ni_660x_second_gate_select =
0a85b6f0
MT		 1167 selected_second_gate &
1168 selected_second_gate_mask;
cb7859a9
FMH		 1169 break;
1170 }
1171 }
1172 if (i <= ni_660x_max_rtsi_channel)
1173 break;
1174 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1175 if (selected_second_gate ==
0a85b6f0 1176 NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
cb7859a9 1177 ni_660x_second_gate_select =
0a85b6f0
MT		 1178 selected_second_gate &
1179 selected_second_gate_mask;
cb7859a9
FMH		 1180 break;
1181 }
1182 }
1183 if (i <= ni_660x_max_up_down_pin)
1184 break;
1185 return -EINVAL;
1186 break;
1187 };
1188 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1189 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1190 counter_dev->regs[second_gate_reg] |=
0a85b6f0 1191 Gi_Second_Gate_Select_Bits(ni_660x_second_gate_select);
cb7859a9 1192 write_register(counter, counter_dev->regs[second_gate_reg],
0a85b6f0 1193 second_gate_reg);
cb7859a9
FMH		 1194 return 0;
1195}
1196
1197static int ni_m_series_set_second_gate(struct ni_gpct *counter,
0a85b6f0 1198 unsigned int gate_source)
cb7859a9
FMH		 1199{
1200 struct ni_gpct_device *counter_dev = counter->counter_dev;
1201 const unsigned second_gate_reg =
0a85b6f0 1202 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
cb7859a9
FMH		 1203 const unsigned selected_second_gate = CR_CHAN(gate_source);
1204 /* bits of second_gate that may be meaningful to second gate register */
1205 static const unsigned selected_second_gate_mask = 0x1f;
1206 unsigned ni_m_series_second_gate_select;
1207
1208 /* FIXME: We don't know what the m-series second gate codes are, so we'll just pass
1209 the bits through for now. */
1210 switch (selected_second_gate) {
1211 default:
1212 ni_m_series_second_gate_select =
0a85b6f0 1213 selected_second_gate & selected_second_gate_mask;
cb7859a9
FMH		 1214 break;
1215 };
1216 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1217 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1218 counter_dev->regs[second_gate_reg] |=
0a85b6f0 1219 Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
cb7859a9 1220 write_register(counter, counter_dev->regs[second_gate_reg],
0a85b6f0 1221 second_gate_reg);
cb7859a9
FMH		 1222 return 0;
1223}
1224
1225int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
0a85b6f0 1226 unsigned int gate_source)
cb7859a9
FMH		 1227{
1228 struct ni_gpct_device *counter_dev = counter->counter_dev;
1229 const unsigned second_gate_reg =
0a85b6f0 1230 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
cb7859a9
FMH		 1231
1232 switch (gate_index) {
1233 case 0:
1234 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1235 ni_tio_set_bits(counter,
0a85b6f0
MT		 1236 NITIO_Gi_Mode_Reg(counter->
1237 counter_index),
1238 Gi_Gating_Mode_Mask,
1239 Gi_Gating_Disabled_Bits);
cb7859a9
FMH		 1240 return 0;
1241 }
1242 ni_tio_set_first_gate_modifiers(counter, gate_source);
1243 switch (counter_dev->variant) {
1244 case ni_gpct_variant_e_series:
1245 case ni_gpct_variant_m_series:
1246 return ni_m_series_set_first_gate(counter, gate_source);
1247 break;
1248 case ni_gpct_variant_660x:
1249 return ni_660x_set_first_gate(counter, gate_source);
1250 break;
1251 default:
1252 BUG();
1253 break;
1254 }
1255 break;
1256 case 1:
1257 if (ni_tio_second_gate_registers_present(counter_dev) == 0)
1258 return -EINVAL;
1259 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1260 counter_dev->regs[second_gate_reg] &=
0a85b6f0 1261 ~Gi_Second_Gate_Mode_Bit;
cb7859a9 1262 write_register(counter,
0a85b6f0
MT		 1263 counter_dev->regs[second_gate_reg],
1264 second_gate_reg);
cb7859a9
FMH		 1265 return 0;
1266 }
1267 if (gate_source & CR_INVERT) {
1268 counter_dev->regs[second_gate_reg] |=
0a85b6f0 1269 Gi_Second_Gate_Polarity_Bit;
cb7859a9
FMH		 1270 } else {
1271 counter_dev->regs[second_gate_reg] &=
0a85b6f0 1272 ~Gi_Second_Gate_Polarity_Bit;
cb7859a9
FMH		 1273 }
1274 switch (counter_dev->variant) {
1275 case ni_gpct_variant_m_series:
1276 return ni_m_series_set_second_gate(counter,
0a85b6f0 1277 gate_source);
cb7859a9
FMH		 1278 break;
1279 case ni_gpct_variant_660x:
1280 return ni_660x_set_second_gate(counter, gate_source);
1281 break;
1282 default:
1283 BUG();
1284 break;
1285 }
1286 break;
1287 default:
1288 return -EINVAL;
1289 break;
1290 }
1291 return 0;
1292}
1293
1294static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
0a85b6f0 1295 unsigned int source)
cb7859a9
FMH		 1296{
1297 struct ni_gpct_device *counter_dev = counter->counter_dev;
1298
1299 if (counter_dev->variant == ni_gpct_variant_m_series) {
1300 unsigned int abz_reg, shift, mask;
1301
1302 abz_reg = NITIO_Gi_ABZ_Reg(counter->counter_index);
1303 switch (index) {
1304 case NI_GPCT_SOURCE_ENCODER_A:
1305 shift = 10;
1306 break;
1307 case NI_GPCT_SOURCE_ENCODER_B:
1308 shift = 5;
1309 break;
1310 case NI_GPCT_SOURCE_ENCODER_Z:
1311 shift = 0;
1312 break;
1313 default:
1314 return -EINVAL;
1315 break;
1316 }
1317 mask = 0x1f << shift;
1318 if (source > 0x1f) {
1319 /* Disable gate */
1320 source = 0x1f;
1321 }
1322 counter_dev->regs[abz_reg] &= ~mask;
1323 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1324 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
5f74ea14 1325/* printk("%s %x %d %d\n", __func__, counter_dev->regs[abz_reg], index, source); */
cb7859a9
FMH		 1326 return 0;
1327 }
1328 return -EINVAL;
1329}
1330
1331static unsigned ni_660x_first_gate_to_generic_gate_source(unsigned
0a85b6f0 1332 ni_660x_gate_select)
cb7859a9
FMH		 1333{
1334 unsigned i;
1335
1336 switch (ni_660x_gate_select) {
1337 case NI_660x_Source_Pin_i_Gate_Select:
1338 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1339 break;
1340 case NI_660x_Gate_Pin_i_Gate_Select:
1341 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1342 break;
1343 case NI_660x_Next_SRC_Gate_Select:
1344 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1345 break;
1346 case NI_660x_Next_Out_Gate_Select:
1347 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1348 break;
1349 case NI_660x_Logic_Low_Gate_Select:
1350 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1351 break;
1352 default:
1353 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1354 if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i)) {
1355 return NI_GPCT_RTSI_GATE_SELECT(i);
1356 break;
1357 }
1358 }
1359 if (i <= ni_660x_max_rtsi_channel)
1360 break;
1361 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1362 if (ni_660x_gate_select ==
0a85b6f0 1363 NI_660x_Gate_Pin_Gate_Select(i)) {
cb7859a9
FMH		 1364 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1365 break;
1366 }
1367 }
1368 if (i <= ni_660x_max_gate_pin)
1369 break;
1370 BUG();
1371 break;
1372 }
1373 return 0;
1374};
1375
1376static unsigned ni_m_series_first_gate_to_generic_gate_source(unsigned
0a85b6f0 1377 ni_m_series_gate_select)
cb7859a9
FMH		 1378{
1379 unsigned i;
1380
1381 switch (ni_m_series_gate_select) {
1382 case NI_M_Series_Timestamp_Mux_Gate_Select:
1383 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1384 break;
1385 case NI_M_Series_AI_START2_Gate_Select:
1386 return NI_GPCT_AI_START2_GATE_SELECT;
1387 break;
1388 case NI_M_Series_PXI_Star_Trigger_Gate_Select:
1389 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1390 break;
1391 case NI_M_Series_Next_Out_Gate_Select:
1392 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1393 break;
1394 case NI_M_Series_AI_START1_Gate_Select:
1395 return NI_GPCT_AI_START1_GATE_SELECT;
1396 break;
1397 case NI_M_Series_Next_SRC_Gate_Select:
1398 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1399 break;
1400 case NI_M_Series_Analog_Trigger_Out_Gate_Select:
1401 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1402 break;
1403 case NI_M_Series_Logic_Low_Gate_Select:
1404 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1405 break;
1406 default:
1407 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1408 if (ni_m_series_gate_select ==
0a85b6f0 1409 NI_M_Series_RTSI_Gate_Select(i)) {
cb7859a9
FMH		 1410 return NI_GPCT_RTSI_GATE_SELECT(i);
1411 break;
1412 }
1413 }
1414 if (i <= ni_m_series_max_rtsi_channel)
1415 break;
1416 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1417 if (ni_m_series_gate_select ==
0a85b6f0 1418 NI_M_Series_PFI_Gate_Select(i)) {
cb7859a9
FMH		 1419 return NI_GPCT_PFI_GATE_SELECT(i);
1420 break;
1421 }
1422 }
1423 if (i <= ni_m_series_max_pfi_channel)
1424 break;
1425 BUG();
1426 break;
1427 }
1428 return 0;
1429};
1430
1431static unsigned ni_660x_second_gate_to_generic_gate_source(unsigned
0a85b6f0 1432 ni_660x_gate_select)
cb7859a9
FMH		 1433{
1434 unsigned i;
1435
1436 switch (ni_660x_gate_select) {
1437 case NI_660x_Source_Pin_i_Second_Gate_Select:
1438 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1439 break;
1440 case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
1441 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1442 break;
1443 case NI_660x_Next_SRC_Second_Gate_Select:
1444 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1445 break;
1446 case NI_660x_Next_Out_Second_Gate_Select:
1447 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1448 break;
1449 case NI_660x_Selected_Gate_Second_Gate_Select:
1450 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1451 break;
1452 case NI_660x_Logic_Low_Second_Gate_Select:
1453 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1454 break;
1455 default:
1456 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1457 if (ni_660x_gate_select ==
0a85b6f0 1458 NI_660x_RTSI_Second_Gate_Select(i)) {
cb7859a9
FMH		 1459 return NI_GPCT_RTSI_GATE_SELECT(i);
1460 break;
1461 }
1462 }
1463 if (i <= ni_660x_max_rtsi_channel)
1464 break;
1465 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1466 if (ni_660x_gate_select ==
0a85b6f0 1467 NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
cb7859a9
FMH		 1468 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1469 break;
1470 }
1471 }
1472 if (i <= ni_660x_max_up_down_pin)
1473 break;
1474 BUG();
1475 break;
1476 }
1477 return 0;
1478};
1479
1480static unsigned ni_m_series_second_gate_to_generic_gate_source(unsigned
0a85b6f0 1481 ni_m_series_gate_select)
cb7859a9
FMH		 1482{
1483 /*FIXME: the second gate sources for the m series are undocumented, so we just return
1484 * the raw bits for now. */
1485 switch (ni_m_series_gate_select) {
1486 default:
1487 return ni_m_series_gate_select;
1488 break;
1489 }
1490 return 0;
1491};
1492
1493static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
0a85b6f0 1494 unsigned int *gate_source)
cb7859a9
FMH		 1495{
1496 struct ni_gpct_device *counter_dev = counter->counter_dev;
1497 const unsigned mode_bits = ni_tio_get_soft_copy(counter,
0a85b6f0
MT		 1498 NITIO_Gi_Mode_Reg
1499 (counter->
1500 counter_index));
cb7859a9 1501 const unsigned second_gate_reg =
0a85b6f0 1502 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
cb7859a9
FMH		 1503 unsigned gate_select_bits;
1504
1505 switch (gate_index) {
1506 case 0:
1507 if ((mode_bits & Gi_Gating_Mode_Mask) ==
0a85b6f0 1508 Gi_Gating_Disabled_Bits) {
cb7859a9
FMH		 1509 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1510 return 0;
1511 } else {
1512 gate_select_bits =
0a85b6f0
MT		 1513 (ni_tio_get_soft_copy(counter,
1514 NITIO_Gi_Input_Select_Reg
1515 (counter->counter_index)) &
1516 Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
cb7859a9
FMH		 1517 }
1518 switch (counter_dev->variant) {
1519 case ni_gpct_variant_e_series:
1520 case ni_gpct_variant_m_series:
1521 *gate_source =
0a85b6f0
MT		 1522 ni_m_series_first_gate_to_generic_gate_source
1523 (gate_select_bits);
cb7859a9
FMH		 1524 break;
1525 case ni_gpct_variant_660x:
1526 *gate_source =
0a85b6f0
MT		 1527 ni_660x_first_gate_to_generic_gate_source
1528 (gate_select_bits);
cb7859a9
FMH		 1529 break;
1530 default:
1531 BUG();
1532 break;
1533 }
1534 if (mode_bits & Gi_Gate_Polarity_Bit) {
1535 *gate_source |= CR_INVERT;
1536 }
1537 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits) {
1538 *gate_source |= CR_EDGE;
1539 }
1540 break;
1541 case 1:
1542 if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
0a85b6f0
MT		 1543 || (counter_dev->regs[second_gate_reg] &
1544 Gi_Second_Gate_Mode_Bit)
1545 == 0) {
cb7859a9
FMH		 1546 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1547 return 0;
1548 } else {
1549 gate_select_bits =
0a85b6f0
MT		 1550 (counter_dev->regs[second_gate_reg] &
1551 Gi_Second_Gate_Select_Mask) >>
1552 Gi_Second_Gate_Select_Shift;
cb7859a9
FMH		 1553 }
1554 switch (counter_dev->variant) {
1555 case ni_gpct_variant_e_series:
1556 case ni_gpct_variant_m_series:
1557 *gate_source =
0a85b6f0
MT		 1558 ni_m_series_second_gate_to_generic_gate_source
1559 (gate_select_bits);
cb7859a9
FMH		 1560 break;
1561 case ni_gpct_variant_660x:
1562 *gate_source =
0a85b6f0
MT		 1563 ni_660x_second_gate_to_generic_gate_source
1564 (gate_select_bits);
cb7859a9
FMH		 1565 break;
1566 default:
1567 BUG();
1568 break;
1569 }
0a85b6f0
MT		 1570 if (counter_dev->regs[second_gate_reg] &
1571 Gi_Second_Gate_Polarity_Bit) {
cb7859a9
FMH		 1572 *gate_source |= CR_INVERT;
1573 }
1574 /* second gate can't have edge/level mode set independently */
1575 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits) {
1576 *gate_source |= CR_EDGE;
1577 }
1578 break;
1579 default:
1580 return -EINVAL;
1581 break;
1582 }
1583 return 0;
1584}
1585
1586int ni_tio_insn_config(struct ni_gpct *counter,
0a85b6f0 1587 struct comedi_insn *insn, unsigned int *data)
cb7859a9
FMH		 1588{
1589 switch (data[0]) {
1590 case INSN_CONFIG_SET_COUNTER_MODE:
1591 return ni_tio_set_counter_mode(counter, data[1]);
1592 break;
1593 case INSN_CONFIG_ARM:
1594 return ni_tio_arm(counter, 1, data[1]);
1595 break;
1596 case INSN_CONFIG_DISARM:
1597 ni_tio_arm(counter, 0, 0);
1598 return 0;
1599 break;
1600 case INSN_CONFIG_GET_COUNTER_STATUS:
1601 data[1] = ni_tio_counter_status(counter);
1602 data[2] = counter_status_mask;
1603 return 0;
1604 break;
1605 case INSN_CONFIG_SET_CLOCK_SRC:
1606 return ni_tio_set_clock_src(counter, data[1], data[2]);
1607 break;
1608 case INSN_CONFIG_GET_CLOCK_SRC:
1609 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1610 return 0;
1611 break;
1612 case INSN_CONFIG_SET_GATE_SRC:
1613 return ni_tio_set_gate_src(counter, data[1], data[2]);
1614 break;
1615 case INSN_CONFIG_GET_GATE_SRC:
1616 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1617 break;
1618 case INSN_CONFIG_SET_OTHER_SRC:
1619 return ni_tio_set_other_src(counter, data[1], data[2]);
1620 break;
1621 case INSN_CONFIG_RESET:
1622 ni_tio_reset_count_and_disarm(counter);
1623 return 0;
1624 break;
1625 default:
1626 break;
1627 }
1628 return -EINVAL;
1629}
1630
0a85b6f0
MT		 1631int ni_tio_rinsn(struct ni_gpct *counter, struct comedi_insn *insn,
1632 unsigned int *data)
cb7859a9
FMH		 1633{
1634 struct ni_gpct_device *counter_dev = counter->counter_dev;
1635 const unsigned channel = CR_CHAN(insn->chanspec);
1636 unsigned first_read;
1637 unsigned second_read;
1638 unsigned correct_read;
1639
1640 if (insn->n < 1)
1641 return 0;
1642 switch (channel) {
1643 case 0:
1644 ni_tio_set_bits(counter,
0a85b6f0
MT		 1645 NITIO_Gi_Command_Reg(counter->counter_index),
1646 Gi_Save_Trace_Bit, 0);
cb7859a9 1647 ni_tio_set_bits(counter,
0a85b6f0
MT		 1648 NITIO_Gi_Command_Reg(counter->counter_index),
1649 Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
cb7859a9
FMH		 1650 /* The count doesn't get latched until the next clock edge, so it is possible the count
1651 may change (once) while we are reading. Since the read of the SW_Save_Reg isn't
1652 atomic (apparently even when it's a 32 bit register according to 660x docs),
1653 we need to read twice and make sure the reading hasn't changed. If it has,
1654 a third read will be correct since the count value will definitely have latched by then. */
1655 first_read =
0a85b6f0
MT		 1656 read_register(counter,
1657 NITIO_Gi_SW_Save_Reg(counter->counter_index));
cb7859a9 1658 second_read =
0a85b6f0
MT		 1659 read_register(counter,
1660 NITIO_Gi_SW_Save_Reg(counter->counter_index));
cb7859a9
FMH		 1661 if (first_read != second_read)
1662 correct_read =
0a85b6f0
MT		 1663 read_register(counter,
1664 NITIO_Gi_SW_Save_Reg(counter->
1665 counter_index));
cb7859a9
FMH		 1666 else
1667 correct_read = first_read;
1668 data[0] = correct_read;
1669 return 0;
1670 break;
1671 case 1:
1672 data[0] =
0a85b6f0
MT		 1673 counter_dev->
1674 regs[NITIO_Gi_LoadA_Reg(counter->counter_index)];
cb7859a9
FMH		 1675 break;
1676 case 2:
1677 data[0] =
0a85b6f0
MT		 1678 counter_dev->
1679 regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
cb7859a9
FMH		 1680 break;
1681 };
1682 return 0;
1683}
1684
1685static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1686{
1687 const unsigned bits = read_register(counter,
0a85b6f0
MT		 1688 NITIO_Gxx_Status_Reg(counter->
1689 counter_index));
cb7859a9
FMH		 1690
1691 if (bits & Gi_Next_Load_Source_Bit(counter->counter_index)) {
1692 return NITIO_Gi_LoadB_Reg(counter->counter_index);
1693 } else {
1694 return NITIO_Gi_LoadA_Reg(counter->counter_index);
1695 }
1696}
1697
0a85b6f0
MT		 1698int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn,
1699 unsigned int *data)
cb7859a9
FMH		 1700{
1701 struct ni_gpct_device *counter_dev = counter->counter_dev;
1702 const unsigned channel = CR_CHAN(insn->chanspec);
1703 unsigned load_reg;
1704
1705 if (insn->n < 1)
1706 return 0;
1707 switch (channel) {
1708 case 0:
1709 /* Unsafe if counter is armed. Should probably check status and return -EBUSY if armed. */
1710 /* Don't disturb load source select, just use whichever load register is already selected. */
1711 load_reg = ni_tio_next_load_register(counter);
1712 write_register(counter, data[0], load_reg);
1713 ni_tio_set_bits_transient(counter,
0a85b6f0
MT		 1714 NITIO_Gi_Command_Reg(counter->
1715 counter_index),
1716 0, 0, Gi_Load_Bit);
cb7859a9
FMH		 1717 /* restore state of load reg to whatever the user set last set it to */
1718 write_register(counter, counter_dev->regs[load_reg], load_reg);
1719 break;
1720 case 1:
1721 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] =
0a85b6f0 1722 data[0];
cb7859a9 1723 write_register(counter, data[0],
0a85b6f0 1724 NITIO_Gi_LoadA_Reg(counter->counter_index));
cb7859a9
FMH		 1725 break;
1726 case 2:
1727 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] =
0a85b6f0 1728 data[0];
cb7859a9 1729 write_register(counter, data[0],
0a85b6f0 1730 NITIO_Gi_LoadB_Reg(counter->counter_index));
cb7859a9
FMH		 1731 break;
1732 default:
1733 return -EINVAL;
1734 break;
1735 }
1736 return 0;
1737}
1738
1739EXPORT_SYMBOL_GPL(ni_tio_rinsn);
1740EXPORT_SYMBOL_GPL(ni_tio_winsn);
1741EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1742EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1743EXPORT_SYMBOL_GPL(ni_tio_arm);
1744EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1745EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1746EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
Linux 6.x block layer and io_uring tree(s)