[linux-2.6-block.git] / drivers / staging / comedi / drivers / ni_6527.c

/*
    comedi/drivers/ni_6527.c
    driver for National Instruments PCI-6527

    COMEDI - Linux Control and Measurement Device Interface
    Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/
/*
Driver: ni_6527
Description: National Instruments 6527
Author: ds
Status: works
Devices: [National Instruments] PCI-6527 (ni6527), PXI-6527
Updated: Sat, 25 Jan 2003 13:24:40 -0800


*/

/*
   Manuals (available from ftp://ftp.natinst.com/support/manuals)

	370106b.pdf	6527 Register Level Programmer Manual

 */

#define DEBUG 1
#define DEBUG_FLAGS

#include <linux/interrupt.h>
#include "../comedidev.h"

#include "comedi_fc.h"
#include "mite.h"

#define DRIVER_NAME "ni_6527"

#define NI6527_DIO_SIZE 4096
#define NI6527_MITE_SIZE 4096

#define Port_Register(x)			(0x00+(x))
#define ID_Register				0x06

#define Clear_Register				0x07
#define ClrEdge				0x08
#define ClrOverflow			0x04
#define ClrFilter			0x02
#define ClrInterval			0x01

#define Filter_Interval(x)			(0x08+(x))
#define Filter_Enable(x)			(0x0c+(x))

#define Change_Status				0x14
#define MasterInterruptStatus		0x04
#define Overflow			0x02
#define EdgeStatus			0x01

#define Master_Interrupt_Control		0x15
#define FallingEdgeIntEnable		0x10
#define RisingEdgeIntEnable		0x08
#define MasterInterruptEnable		0x04
#define OverflowIntEnable		0x02
#define EdgeIntEnable			0x01

#define Rising_Edge_Detection_Enable(x)		(0x018+(x))
#define Falling_Edge_Detection_Enable(x)	(0x020+(x))

struct ni6527_board {

	int dev_id;
	const char *name;
};

static const struct ni6527_board ni6527_boards[] = {
	{
	 .dev_id = 0x2b20,
	 .name = "pci-6527",
	 },
	{
	 .dev_id = 0x2b10,
	 .name = "pxi-6527",
	 },
};

#define this_board ((const struct ni6527_board *)dev->board_ptr)

static DEFINE_PCI_DEVICE_TABLE(ni6527_pci_table) = {
	{PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b10)},
	{PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b20)},
	{0}
};

MODULE_DEVICE_TABLE(pci, ni6527_pci_table);

struct ni6527_private {
	struct mite_struct *mite;
	unsigned int filter_interval;
	unsigned int filter_enable;
};

#define devpriv ((struct ni6527_private *)dev->private)

static int ni6527_di_insn_config(struct comedi_device *dev,
				 struct comedi_subdevice *s,
				 struct comedi_insn *insn, unsigned int *data)
{
	int chan = CR_CHAN(insn->chanspec);
	unsigned int interval;

	if (insn->n != 2)
		return -EINVAL;

	if (data[0] != INSN_CONFIG_FILTER)
		return -EINVAL;

	if (data[1]) {
		interval = (data[1] + 100) / 200;
		data[1] = interval * 200;

		if (interval != devpriv->filter_interval) {
			writeb(interval & 0xff,
			       devpriv->mite->daq_io_addr + Filter_Interval(0));
			writeb((interval >> 8) & 0xff,
			       devpriv->mite->daq_io_addr + Filter_Interval(1));
			writeb((interval >> 16) & 0x0f,
			       devpriv->mite->daq_io_addr + Filter_Interval(2));

			writeb(ClrInterval,
			       devpriv->mite->daq_io_addr + Clear_Register);

			devpriv->filter_interval = interval;
		}

		devpriv->filter_enable |= 1 << chan;
	} else {
		devpriv->filter_enable &= ~(1 << chan);
	}

	writeb(devpriv->filter_enable,
	       devpriv->mite->daq_io_addr + Filter_Enable(0));
	writeb(devpriv->filter_enable >> 8,
	       devpriv->mite->daq_io_addr + Filter_Enable(1));
	writeb(devpriv->filter_enable >> 16,
	       devpriv->mite->daq_io_addr + Filter_Enable(2));

	return 2;
}

static int ni6527_di_insn_bits(struct comedi_device *dev,
			       struct comedi_subdevice *s,
			       struct comedi_insn *insn, unsigned int *data)
{
	data[1] = readb(devpriv->mite->daq_io_addr + Port_Register(0));
	data[1] |= readb(devpriv->mite->daq_io_addr + Port_Register(1)) << 8;
	data[1] |= readb(devpriv->mite->daq_io_addr + Port_Register(2)) << 16;

	return insn->n;
}

static int ni6527_do_insn_bits(struct comedi_device *dev,
			       struct comedi_subdevice *s,
			       struct comedi_insn *insn, unsigned int *data)
{
	if (data[0]) {
		s->state &= ~data[0];
		s->state |= (data[0] & data[1]);

		/* The open relay state on the board cooresponds to 1,
		 * but in Comedi, it is represented by 0. */
		if (data[0] & 0x0000ff) {
			writeb((s->state ^ 0xff),
			       devpriv->mite->daq_io_addr + Port_Register(3));
		}
		if (data[0] & 0x00ff00) {
			writeb((s->state >> 8) ^ 0xff,
			       devpriv->mite->daq_io_addr + Port_Register(4));
		}
		if (data[0] & 0xff0000) {
			writeb((s->state >> 16) ^ 0xff,
			       devpriv->mite->daq_io_addr + Port_Register(5));
		}
	}
	data[1] = s->state;

	return insn->n;
}

static irqreturn_t ni6527_interrupt(int irq, void *d)
{
	struct comedi_device *dev = d;
	struct comedi_subdevice *s = &dev->subdevices[2];
	unsigned int status;

	status = readb(devpriv->mite->daq_io_addr + Change_Status);
	if ((status & MasterInterruptStatus) == 0)
		return IRQ_NONE;
	if ((status & EdgeStatus) == 0)
		return IRQ_NONE;

	writeb(ClrEdge | ClrOverflow,
	       devpriv->mite->daq_io_addr + Clear_Register);

	comedi_buf_put(s->async, 0);
	s->async->events |= COMEDI_CB_EOS;
	comedi_event(dev, s);
	return IRQ_HANDLED;
}

static int ni6527_intr_cmdtest(struct comedi_device *dev,
			       struct comedi_subdevice *s,
			       struct comedi_cmd *cmd)
{
	int err = 0;

	/* Step 1 : check if triggers are trivially valid */

	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);

	if (err)
		return 1;

	/* Step 2a : make sure trigger sources are unique */
	/* Step 2b : and mutually compatible */

	if (err)
		return 2;

	/* step 3: make sure arguments are trivially compatible */

	if (cmd->start_arg != 0) {
		cmd->start_arg = 0;
		err++;
	}
	if (cmd->scan_begin_arg != 0) {
		cmd->scan_begin_arg = 0;
		err++;
	}
	if (cmd->convert_arg != 0) {
		cmd->convert_arg = 0;
		err++;
	}

	if (cmd->scan_end_arg != 1) {
		cmd->scan_end_arg = 1;
		err++;
	}
	if (cmd->stop_arg != 0) {
		cmd->stop_arg = 0;
		err++;
	}

	if (err)
		return 3;

	/* step 4: fix up any arguments */

	if (err)
		return 4;

	return 0;
}

static int ni6527_intr_cmd(struct comedi_device *dev,
			   struct comedi_subdevice *s)
{
	/* struct comedi_cmd *cmd = &s->async->cmd; */

	writeb(ClrEdge | ClrOverflow,
	       devpriv->mite->daq_io_addr + Clear_Register);
	writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
	       MasterInterruptEnable | EdgeIntEnable,
	       devpriv->mite->daq_io_addr + Master_Interrupt_Control);

	return 0;
}

static int ni6527_intr_cancel(struct comedi_device *dev,
			      struct comedi_subdevice *s)
{
	writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);

	return 0;
}

static int ni6527_intr_insn_bits(struct comedi_device *dev,
				 struct comedi_subdevice *s,
				 struct comedi_insn *insn, unsigned int *data)
{
	data[1] = 0;
	return insn->n;
}

static int ni6527_intr_insn_config(struct comedi_device *dev,
				   struct comedi_subdevice *s,
				   struct comedi_insn *insn, unsigned int *data)
{
	if (insn->n < 1)
		return -EINVAL;
	if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
		return -EINVAL;

	writeb(data[1],
	       devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(0));
	writeb(data[1] >> 8,
	       devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(1));
	writeb(data[1] >> 16,
	       devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(2));

	writeb(data[2],
	       devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(0));
	writeb(data[2] >> 8,
	       devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(1));
	writeb(data[2] >> 16,
	       devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(2));

	return 2;
}

static const struct ni6527_board *
ni6527_find_boardinfo(struct pci_dev *pcidev)
{
	unsigned int dev_id = pcidev->device;
	unsigned int n;

	for (n = 0; n < ARRAY_SIZE(ni6527_boards); n++) {
		const struct ni6527_board *board = &ni6527_boards[n];
		if (board->dev_id == dev_id)
			return board;
	}
	return NULL;
}

static int __devinit ni6527_attach_pci(struct comedi_device *dev,
				       struct pci_dev *pcidev)
{
	struct comedi_subdevice *s;
	int ret;

	ret = alloc_private(dev, sizeof(struct ni6527_private));
	if (ret < 0)
		return ret;

	dev->board_ptr = ni6527_find_boardinfo(pcidev);
	if (!dev->board_ptr)
		return -ENODEV;

	devpriv->mite = mite_alloc(pcidev);
	if (!devpriv->mite)
		return -ENOMEM;

	ret = mite_setup(devpriv->mite);
	if (ret < 0) {
		dev_err(dev->class_dev, "error setting up mite\n");
		return ret;
	}

	dev->board_name = this_board->name;
	dev_info(dev->class_dev, "board: %s, ID=0x%02x\n", dev->board_name,
		 readb(devpriv->mite->daq_io_addr + ID_Register));

	ret = comedi_alloc_subdevices(dev, 3);
	if (ret)
		return ret;

	s = &dev->subdevices[0];
	s->type = COMEDI_SUBD_DI;
	s->subdev_flags = SDF_READABLE;
	s->n_chan = 24;
	s->range_table = &range_digital;
	s->maxdata = 1;
	s->insn_config = ni6527_di_insn_config;
	s->insn_bits = ni6527_di_insn_bits;

	s = &dev->subdevices[1];
	s->type = COMEDI_SUBD_DO;
	s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
	s->n_chan = 24;
	s->range_table = &range_unknown;  /* FIXME: actually conductance */
	s->maxdata = 1;
	s->insn_bits = ni6527_do_insn_bits;

	s = &dev->subdevices[2];
	dev->read_subdev = s;
	s->type = COMEDI_SUBD_DI;
	s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
	s->n_chan = 1;
	s->range_table = &range_unknown;
	s->maxdata = 1;
	s->do_cmdtest = ni6527_intr_cmdtest;
	s->do_cmd = ni6527_intr_cmd;
	s->cancel = ni6527_intr_cancel;
	s->insn_bits = ni6527_intr_insn_bits;
	s->insn_config = ni6527_intr_insn_config;

	writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(0));
	writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(1));
	writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(2));

	writeb(ClrEdge | ClrOverflow | ClrFilter | ClrInterval,
	       devpriv->mite->daq_io_addr + Clear_Register);
	writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);

	ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
			  IRQF_SHARED, DRIVER_NAME, dev);
	if (ret < 0)
		dev_warn(dev->class_dev, "irq not available\n");
	else
		dev->irq = mite_irq(devpriv->mite);

	return 0;
}

static void ni6527_detach(struct comedi_device *dev)
{
	if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr)
		writeb(0x00,
		       devpriv->mite->daq_io_addr + Master_Interrupt_Control);
	if (dev->irq)
		free_irq(dev->irq, dev);
	if (devpriv && devpriv->mite) {
		mite_unsetup(devpriv->mite);
		mite_free(devpriv->mite);
	}
}

static struct comedi_driver ni6527_driver = {
	.driver_name = DRIVER_NAME,
	.module = THIS_MODULE,
	.attach_pci = ni6527_attach_pci,
	.detach = ni6527_detach,
};

static int __devinit ni6527_pci_probe(struct pci_dev *dev,
				      const struct pci_device_id *ent)
{
	return comedi_pci_auto_config(dev, &ni6527_driver);
}

static void __devexit ni6527_pci_remove(struct pci_dev *dev)
{
	comedi_pci_auto_unconfig(dev);
}

static struct pci_driver ni6527_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = ni6527_pci_table,
	.probe = ni6527_pci_probe,
	.remove = __devexit_p(ni6527_pci_remove)
};
module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);

MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("Comedi low-level driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ef2ccffb DS	1	/*
	2	comedi/drivers/ni_6527.c
	3	driver for National Instruments PCI-6527
	4
	5	COMEDI - Linux Control and Measurement Device Interface
	6	Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21
	22	*/
	23	/*
	24	Driver: ni_6527
	25	Description: National Instruments 6527
	26	Author: ds
	27	Status: works
	28	Devices: [National Instruments] PCI-6527 (ni6527), PXI-6527
	29	Updated: Sat, 25 Jan 2003 13:24:40 -0800
	30
	31
	32	*/
	33
	34	/*
	35	Manuals (available from ftp://ftp.natinst.com/support/manuals)
	36
	37	370106b.pdf 6527 Register Level Programmer Manual
	38
	39	*/
	40
	41	#define DEBUG 1
	42	#define DEBUG_FLAGS
	43
25436dc9	44	#include <linux/interrupt.h>
ef2ccffb DS	45	#include "../comedidev.h"
ef2ccffb DS	46
27020ffe	47	#include "comedi_fc.h"
ef2ccffb DS	48	#include "mite.h"
ef2ccffb DS	49
38b951f1 IA	50	#define DRIVER_NAME "ni_6527"
38b951f1 IA	51
ef2ccffb DS	52	#define NI6527_DIO_SIZE 4096
	53	#define NI6527_MITE_SIZE 4096
	54
	55	#define Port_Register(x) (0x00+(x))
	56	#define ID_Register 0x06
	57
	58	#define Clear_Register 0x07
	59	#define ClrEdge 0x08
	60	#define ClrOverflow 0x04
	61	#define ClrFilter 0x02
	62	#define ClrInterval 0x01
	63
	64	#define Filter_Interval(x) (0x08+(x))
	65	#define Filter_Enable(x) (0x0c+(x))
	66
	67	#define Change_Status 0x14
	68	#define MasterInterruptStatus 0x04
	69	#define Overflow 0x02
	70	#define EdgeStatus 0x01
	71
	72	#define Master_Interrupt_Control 0x15
	73	#define FallingEdgeIntEnable 0x10
	74	#define RisingEdgeIntEnable 0x08
	75	#define MasterInterruptEnable 0x04
	76	#define OverflowIntEnable 0x02
	77	#define EdgeIntEnable 0x01
	78
	79	#define Rising_Edge_Detection_Enable(x) (0x018+(x))
	80	#define Falling_Edge_Detection_Enable(x) (0x020+(x))
	81
16d38ca3 BP	82	struct ni6527_board {
16d38ca3 BP	83
ef2ccffb DS	84	int dev_id;
ef2ccffb DS	85	const char *name;
16d38ca3 BP	86	};
	87
	88	static const struct ni6527_board ni6527_boards[] = {
ef2ccffb	89	{
0a85b6f0 MT	90	.dev_id = 0x2b20,
	91	.name = "pci-6527",
	92	},
ef2ccffb	93	{
0a85b6f0 MT	94	.dev_id = 0x2b10,
	95	.name = "pxi-6527",
	96	},
ef2ccffb DS	97	};
ef2ccffb DS	98
16d38ca3	99	#define this_board ((const struct ni6527_board *)dev->board_ptr)
ef2ccffb DS	100
ef2ccffb DS	101	static DEFINE_PCI_DEVICE_TABLE(ni6527_pci_table) = {
4e40cee9 GKH	102	{PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b10)},
	103	{PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b20)},
	104	{0}
ef2ccffb DS	105	};
	106
	107	MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
	108
f4c6b319	109	struct ni6527_private {
ef2ccffb DS	110	struct mite_struct *mite;
	111	unsigned int filter_interval;
	112	unsigned int filter_enable;
f4c6b319 BP	113	};
	114
	115	#define devpriv ((struct ni6527_private *)dev->private)
ef2ccffb	116
0a85b6f0 MT	117	static int ni6527_di_insn_config(struct comedi_device *dev,
	118	struct comedi_subdevice *s,
	119	struct comedi_insn insn, unsigned int data)
ef2ccffb DS	120	{
	121	int chan = CR_CHAN(insn->chanspec);
	122	unsigned int interval;
	123
	124	if (insn->n != 2)
	125	return -EINVAL;
	126
	127	if (data[0] != INSN_CONFIG_FILTER)
	128	return -EINVAL;
	129
	130	if (data[1]) {
	131	interval = (data[1] + 100) / 200;
	132	data[1] = interval * 200;
	133
	134	if (interval != devpriv->filter_interval) {
	135	writeb(interval & 0xff,
0a85b6f0	136	devpriv->mite->daq_io_addr + Filter_Interval(0));
ef2ccffb	137	writeb((interval >> 8) & 0xff,
0a85b6f0	138	devpriv->mite->daq_io_addr + Filter_Interval(1));
ef2ccffb	139	writeb((interval >> 16) & 0x0f,
0a85b6f0	140	devpriv->mite->daq_io_addr + Filter_Interval(2));
ef2ccffb DS	141
ef2ccffb DS	142	writeb(ClrInterval,
0a85b6f0	143	devpriv->mite->daq_io_addr + Clear_Register);
ef2ccffb DS	144
	145	devpriv->filter_interval = interval;
	146	}
	147
	148	devpriv->filter_enable \|= 1 << chan;
	149	} else {
	150	devpriv->filter_enable &= ~(1 << chan);
	151	}
	152
	153	writeb(devpriv->filter_enable,
0a85b6f0	154	devpriv->mite->daq_io_addr + Filter_Enable(0));
ef2ccffb	155	writeb(devpriv->filter_enable >> 8,
0a85b6f0	156	devpriv->mite->daq_io_addr + Filter_Enable(1));
ef2ccffb	157	writeb(devpriv->filter_enable >> 16,
0a85b6f0	158	devpriv->mite->daq_io_addr + Filter_Enable(2));
ef2ccffb DS	159
	160	return 2;
	161	}
	162
0a85b6f0 MT	163	static int ni6527_di_insn_bits(struct comedi_device *dev,
	164	struct comedi_subdevice *s,
	165	struct comedi_insn insn, unsigned int data)
ef2ccffb	166	{
ef2ccffb DS	167	data[1] = readb(devpriv->mite->daq_io_addr + Port_Register(0));
	168	data[1] \|= readb(devpriv->mite->daq_io_addr + Port_Register(1)) << 8;
	169	data[1] \|= readb(devpriv->mite->daq_io_addr + Port_Register(2)) << 16;
	170
a2714e3e	171	return insn->n;
ef2ccffb DS	172	}
ef2ccffb DS	173
0a85b6f0 MT	174	static int ni6527_do_insn_bits(struct comedi_device *dev,
	175	struct comedi_subdevice *s,
	176	struct comedi_insn insn, unsigned int data)
ef2ccffb	177	{
ef2ccffb DS	178	if (data[0]) {
	179	s->state &= ~data[0];
	180	s->state \|= (data[0] & data[1]);
	181
	182	/* The open relay state on the board cooresponds to 1,
	183	* but in Comedi, it is represented by 0. */
	184	if (data[0] & 0x0000ff) {
	185	writeb((s->state ^ 0xff),
0a85b6f0	186	devpriv->mite->daq_io_addr + Port_Register(3));
ef2ccffb DS	187	}
	188	if (data[0] & 0x00ff00) {
	189	writeb((s->state >> 8) ^ 0xff,
0a85b6f0	190	devpriv->mite->daq_io_addr + Port_Register(4));
ef2ccffb DS	191	}
	192	if (data[0] & 0xff0000) {
	193	writeb((s->state >> 16) ^ 0xff,
0a85b6f0	194	devpriv->mite->daq_io_addr + Port_Register(5));
ef2ccffb DS	195	}
	196	}
	197	data[1] = s->state;
	198
a2714e3e	199	return insn->n;
ef2ccffb DS	200	}
ef2ccffb DS	201
70265d24	202	static irqreturn_t ni6527_interrupt(int irq, void *d)
ef2ccffb	203	{
71b5f4f1	204	struct comedi_device *dev = d;
3d30dca5	205	struct comedi_subdevice *s = &dev->subdevices[2];
ef2ccffb DS	206	unsigned int status;
	207
	208	status = readb(devpriv->mite->daq_io_addr + Change_Status);
	209	if ((status & MasterInterruptStatus) == 0)
	210	return IRQ_NONE;
	211	if ((status & EdgeStatus) == 0)
	212	return IRQ_NONE;
	213
	214	writeb(ClrEdge \| ClrOverflow,
0a85b6f0	215	devpriv->mite->daq_io_addr + Clear_Register);
ef2ccffb DS	216
	217	comedi_buf_put(s->async, 0);
	218	s->async->events \|= COMEDI_CB_EOS;
	219	comedi_event(dev, s);
	220	return IRQ_HANDLED;
	221	}
	222
0a85b6f0 MT	223	static int ni6527_intr_cmdtest(struct comedi_device *dev,
	224	struct comedi_subdevice *s,
	225	struct comedi_cmd *cmd)
ef2ccffb DS	226	{
ef2ccffb DS	227	int err = 0;
ef2ccffb	228
27020ffe	229	/* Step 1 : check if triggers are trivially valid */
ef2ccffb	230
27020ffe HS	231	err \|= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	232	err \|= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
	233	err \|= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	234	err \|= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	235	err \|= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
ef2ccffb DS	236
	237	if (err)
	238	return 1;
	239
27020ffe HS	240	/* Step 2a : make sure trigger sources are unique */
27020ffe HS	241	/* Step 2b : and mutually compatible */
ef2ccffb DS	242
	243	if (err)
	244	return 2;
	245
	246	/* step 3: make sure arguments are trivially compatible */
	247
	248	if (cmd->start_arg != 0) {
	249	cmd->start_arg = 0;
	250	err++;
	251	}
	252	if (cmd->scan_begin_arg != 0) {
	253	cmd->scan_begin_arg = 0;
	254	err++;
	255	}
	256	if (cmd->convert_arg != 0) {
	257	cmd->convert_arg = 0;
	258	err++;
	259	}
	260
	261	if (cmd->scan_end_arg != 1) {
	262	cmd->scan_end_arg = 1;
	263	err++;
	264	}
	265	if (cmd->stop_arg != 0) {
	266	cmd->stop_arg = 0;
	267	err++;
	268	}
	269
	270	if (err)
	271	return 3;
	272
	273	/* step 4: fix up any arguments */
	274
	275	if (err)
	276	return 4;
	277
	278	return 0;
	279	}
	280
0a85b6f0 MT	281	static int ni6527_intr_cmd(struct comedi_device *dev,
0a85b6f0 MT	282	struct comedi_subdevice *s)
ef2ccffb	283	{
2696fb57	284	/* struct comedi_cmd cmd = &s->async->cmd; /
ef2ccffb DS	285
ef2ccffb DS	286	writeb(ClrEdge \| ClrOverflow,
0a85b6f0	287	devpriv->mite->daq_io_addr + Clear_Register);
ef2ccffb	288	writeb(FallingEdgeIntEnable \| RisingEdgeIntEnable \|
0a85b6f0 MT	289	MasterInterruptEnable \| EdgeIntEnable,
0a85b6f0 MT	290	devpriv->mite->daq_io_addr + Master_Interrupt_Control);
ef2ccffb DS	291
	292	return 0;
	293	}
	294
0a85b6f0 MT	295	static int ni6527_intr_cancel(struct comedi_device *dev,
0a85b6f0 MT	296	struct comedi_subdevice *s)
ef2ccffb DS	297	{
	298	writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
	299
	300	return 0;
	301	}
	302
0a85b6f0 MT	303	static int ni6527_intr_insn_bits(struct comedi_device *dev,
	304	struct comedi_subdevice *s,
	305	struct comedi_insn insn, unsigned int data)
ef2ccffb	306	{
ef2ccffb	307	data[1] = 0;
a2714e3e	308	return insn->n;
ef2ccffb DS	309	}
ef2ccffb DS	310
0a85b6f0 MT	311	static int ni6527_intr_insn_config(struct comedi_device *dev,
	312	struct comedi_subdevice *s,
	313	struct comedi_insn insn, unsigned int data)
ef2ccffb DS	314	{
	315	if (insn->n < 1)
	316	return -EINVAL;
	317	if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
	318	return -EINVAL;
	319
	320	writeb(data[1],
0a85b6f0	321	devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(0));
ef2ccffb	322	writeb(data[1] >> 8,
0a85b6f0	323	devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(1));
ef2ccffb	324	writeb(data[1] >> 16,
0a85b6f0	325	devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(2));
ef2ccffb DS	326
ef2ccffb DS	327	writeb(data[2],
0a85b6f0	328	devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(0));
ef2ccffb	329	writeb(data[2] >> 8,
0a85b6f0	330	devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(1));
ef2ccffb	331	writeb(data[2] >> 16,
0a85b6f0	332	devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(2));
ef2ccffb DS	333
	334	return 2;
	335	}
	336
372959d2 IA	337	static const struct ni6527_board *
	338	ni6527_find_boardinfo(struct pci_dev *pcidev)
	339	{
	340	unsigned int dev_id = pcidev->device;
	341	unsigned int n;
	342
	343	for (n = 0; n < ARRAY_SIZE(ni6527_boards); n++) {
	344	const struct ni6527_board *board = &ni6527_boards[n];
	345	if (board->dev_id == dev_id)
	346	return board;
	347	}
	348	return NULL;
	349	}
	350
	351	static int __devinit ni6527_attach_pci(struct comedi_device *dev,
	352	struct pci_dev *pcidev)
ef2ccffb	353	{
34c43922	354	struct comedi_subdevice *s;
ef2ccffb DS	355	int ret;
ef2ccffb DS	356
c3744138 BP	357	ret = alloc_private(dev, sizeof(struct ni6527_private));
c3744138 BP	358	if (ret < 0)
ef2ccffb DS	359	return ret;
ef2ccffb DS	360
372959d2 IA	361	dev->board_ptr = ni6527_find_boardinfo(pcidev);
	362	if (!dev->board_ptr)
	363	return -ENODEV;
	364
6dc71205	365	devpriv->mite = mite_alloc(pcidev);
372959d2	366	if (!devpriv->mite)
6dc71205	367	return -ENOMEM;
ef2ccffb DS	368
	369	ret = mite_setup(devpriv->mite);
	370	if (ret < 0) {
ca33f4ce	371	dev_err(dev->class_dev, "error setting up mite\n");
ef2ccffb DS	372	return ret;
	373	}
	374
	375	dev->board_name = this_board->name;
ca33f4ce IA	376	dev_info(dev->class_dev, "board: %s, ID=0x%02x\n", dev->board_name,
ca33f4ce IA	377	readb(devpriv->mite->daq_io_addr + ID_Register));
ef2ccffb	378
2f0b9d08	379	ret = comedi_alloc_subdevices(dev, 3);
8b6c5694	380	if (ret)
ef2ccffb DS	381	return ret;
ef2ccffb DS	382
3d30dca5	383	s = &dev->subdevices[0];
ef2ccffb DS	384	s->type = COMEDI_SUBD_DI;
	385	s->subdev_flags = SDF_READABLE;
	386	s->n_chan = 24;
	387	s->range_table = &range_digital;
	388	s->maxdata = 1;
	389	s->insn_config = ni6527_di_insn_config;
	390	s->insn_bits = ni6527_di_insn_bits;
	391
3d30dca5	392	s = &dev->subdevices[1];
ef2ccffb DS	393	s->type = COMEDI_SUBD_DO;
	394	s->subdev_flags = SDF_READABLE \| SDF_WRITABLE;
	395	s->n_chan = 24;
a8c5c198	396	s->range_table = &range_unknown; /* FIXME: actually conductance */
ef2ccffb DS	397	s->maxdata = 1;
	398	s->insn_bits = ni6527_do_insn_bits;
	399
3d30dca5	400	s = &dev->subdevices[2];
ef2ccffb DS	401	dev->read_subdev = s;
	402	s->type = COMEDI_SUBD_DI;
	403	s->subdev_flags = SDF_READABLE \| SDF_CMD_READ;
	404	s->n_chan = 1;
	405	s->range_table = &range_unknown;
	406	s->maxdata = 1;
	407	s->do_cmdtest = ni6527_intr_cmdtest;
	408	s->do_cmd = ni6527_intr_cmd;
	409	s->cancel = ni6527_intr_cancel;
	410	s->insn_bits = ni6527_intr_insn_bits;
	411	s->insn_config = ni6527_intr_insn_config;
	412
	413	writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(0));
	414	writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(1));
	415	writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(2));
	416
	417	writeb(ClrEdge \| ClrOverflow \| ClrFilter \| ClrInterval,
0a85b6f0	418	devpriv->mite->daq_io_addr + Clear_Register);
ef2ccffb DS	419	writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
ef2ccffb DS	420
5f74ea14	421	ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
38b951f1	422	IRQF_SHARED, DRIVER_NAME, dev);
a8c5c198	423	if (ret < 0)
ca33f4ce	424	dev_warn(dev->class_dev, "irq not available\n");
a8c5c198	425	else
ef2ccffb DS	426	dev->irq = mite_irq(devpriv->mite);
ef2ccffb DS	427
ef2ccffb DS	428	return 0;
	429	}
	430
484ecc95	431	static void ni6527_detach(struct comedi_device *dev)
ef2ccffb	432	{
a8c5c198	433	if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr)
ef2ccffb	434	writeb(0x00,
0a85b6f0	435	devpriv->mite->daq_io_addr + Master_Interrupt_Control);
a8c5c198	436	if (dev->irq)
5f74ea14	437	free_irq(dev->irq, dev);
6dc71205	438	if (devpriv && devpriv->mite) {
ef2ccffb	439	mite_unsetup(devpriv->mite);
6dc71205 IA	440	mite_free(devpriv->mite);
6dc71205 IA	441	}
ef2ccffb DS	442	}
ef2ccffb DS	443
fcdd5ecd IA	444	static struct comedi_driver ni6527_driver = {
	445	.driver_name = DRIVER_NAME,
	446	.module = THIS_MODULE,
372959d2	447	.attach_pci = ni6527_attach_pci,
fcdd5ecd IA	448	.detach = ni6527_detach,
	449	};
	450
7ae09413 IA	451	static int __devinit ni6527_pci_probe(struct pci_dev *dev,
7ae09413 IA	452	const struct pci_device_id *ent)
727b286b	453	{
7ae09413	454	return comedi_pci_auto_config(dev, &ni6527_driver);
727b286b AT	455	}
727b286b AT	456
7ae09413	457	static void __devexit ni6527_pci_remove(struct pci_dev *dev)
727b286b AT	458	{
	459	comedi_pci_auto_unconfig(dev);
	460	}
	461
7ae09413 IA	462	static struct pci_driver ni6527_pci_driver = {
7ae09413 IA	463	.name = DRIVER_NAME,
727b286b	464	.id_table = ni6527_pci_table,
7ae09413 IA	465	.probe = ni6527_pci_probe,
7ae09413 IA	466	.remove = __devexit_p(ni6527_pci_remove)
727b286b	467	};
7ae09413	468	module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
3c323c01 IA	469
	470	MODULE_AUTHOR("Comedi http://www.comedi.org");
	471	MODULE_DESCRIPTION("Comedi low-level driver");
	472	MODULE_LICENSE("GPL");