Commit | Line | Data |
---|---|---|
bede7290 | 1 | /* |
65f6fac9 IA |
2 | * comedi/drivers/mite.c |
3 | * Hardware driver for NI Mite PCI interface chip | |
4 | * | |
5 | * COMEDI - Linux Control and Measurement Device Interface | |
6 | * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
bede7290 DS |
18 | |
19 | /* | |
65f6fac9 IA |
20 | * The PCI-MIO E series driver was originally written by |
21 | * Tomasz Motylewski <...>, and ported to comedi by ds. | |
22 | * | |
23 | * References for specifications: | |
24 | * | |
25 | * 321747b.pdf Register Level Programmer Manual (obsolete) | |
26 | * 321747c.pdf Register Level Programmer Manual (new) | |
27 | * DAQ-STC reference manual | |
28 | * | |
29 | * Other possibly relevant info: | |
30 | * | |
31 | * 320517c.pdf User manual (obsolete) | |
32 | * 320517f.pdf User manual (new) | |
33 | * 320889a.pdf delete | |
34 | * 320906c.pdf maximum signal ratings | |
35 | * 321066a.pdf about 16x | |
36 | * 321791a.pdf discontinuation of at-mio-16e-10 rev. c | |
37 | * 321808a.pdf about at-mio-16e-10 rev P | |
38 | * 321837a.pdf discontinuation of at-mio-16de-10 rev d | |
39 | * 321838a.pdf about at-mio-16de-10 rev N | |
40 | * | |
41 | * ISSUES: | |
42 | * | |
43 | */ | |
bede7290 | 44 | |
d799773f IA |
45 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
46 | ||
ce157f80 | 47 | #include <linux/module.h> |
272b1ae5 | 48 | #include <linux/slab.h> |
bede7290 | 49 | |
4953d2c2 | 50 | #include "../comedi_pci.h" |
bede7290 | 51 | |
33782dd5 | 52 | #include "mite.h" |
bede7290 | 53 | |
bede7290 DS |
54 | #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK))) |
55 | ||
ca8eb8d5 IA |
56 | struct mite_struct *mite_alloc(struct pci_dev *pcidev) |
57 | { | |
58 | struct mite_struct *mite; | |
59 | unsigned int i; | |
60 | ||
61 | mite = kzalloc(sizeof(*mite), GFP_KERNEL); | |
62 | if (mite) { | |
63 | spin_lock_init(&mite->lock); | |
64 | mite->pcidev = pcidev; | |
65 | for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) { | |
66 | mite->channels[i].mite = mite; | |
67 | mite->channels[i].channel = i; | |
68 | mite->channels[i].done = 1; | |
69 | } | |
70 | } | |
71 | return mite; | |
72 | } | |
5660e742 | 73 | EXPORT_SYMBOL_GPL(mite_alloc); |
ca8eb8d5 | 74 | |
bede7290 DS |
75 | static void dump_chip_signature(u32 csigr_bits) |
76 | { | |
d799773f IA |
77 | pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n", |
78 | mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits), | |
79 | mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits)); | |
80 | pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n", | |
81 | mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits), | |
82 | mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits)); | |
bede7290 DS |
83 | } |
84 | ||
2ad1d2e1 | 85 | static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel) |
bede7290 | 86 | { |
0a85b6f0 | 87 | unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel)); |
bede7290 DS |
88 | unsigned empty_count = (fcr_bits >> 16) & 0xff; |
89 | unsigned full_count = fcr_bits & 0xff; | |
9a7c5693 | 90 | |
bede7290 DS |
91 | return empty_count + full_count; |
92 | } | |
93 | ||
3bb7c3ab HS |
94 | int mite_setup2(struct comedi_device *dev, |
95 | struct mite_struct *mite, bool use_win1) | |
bede7290 DS |
96 | { |
97 | unsigned long length; | |
bede7290 DS |
98 | int i; |
99 | u32 csigr_bits; | |
100 | unsigned unknown_dma_burst_bits; | |
101 | ||
bede7290 DS |
102 | pci_set_master(mite->pcidev); |
103 | ||
cc375088 | 104 | mite->mite_io_addr = pci_ioremap_bar(mite->pcidev, 0); |
bede7290 | 105 | if (!mite->mite_io_addr) { |
3bb7c3ab | 106 | dev_err(dev->class_dev, |
d799773f | 107 | "Failed to remap mite io memory address\n"); |
bede7290 DS |
108 | return -ENOMEM; |
109 | } | |
cc375088 | 110 | mite->mite_phys_addr = pci_resource_start(mite->pcidev, 0); |
bede7290 | 111 | |
5f8a5f4f HS |
112 | dev->mmio = pci_ioremap_bar(mite->pcidev, 1); |
113 | if (!dev->mmio) { | |
3bb7c3ab | 114 | dev_err(dev->class_dev, |
d799773f | 115 | "Failed to remap daq io memory address\n"); |
bede7290 DS |
116 | return -ENOMEM; |
117 | } | |
cc375088 HS |
118 | mite->daq_phys_addr = pci_resource_start(mite->pcidev, 1); |
119 | length = pci_resource_len(mite->pcidev, 1); | |
bede7290 | 120 | |
3bb7c3ab | 121 | if (use_win1) { |
bede7290 | 122 | writel(0, mite->mite_io_addr + MITE_IODWBSR); |
3bb7c3ab | 123 | dev_info(dev->class_dev, |
d799773f | 124 | "using I/O Window Base Size register 1\n"); |
0a85b6f0 MT |
125 | writel(mite->daq_phys_addr | WENAB | |
126 | MITE_IODWBSR_1_WSIZE_bits(length), | |
127 | mite->mite_io_addr + MITE_IODWBSR_1); | |
bede7290 DS |
128 | writel(0, mite->mite_io_addr + MITE_IODWCR_1); |
129 | } else { | |
130 | writel(mite->daq_phys_addr | WENAB, | |
0a85b6f0 | 131 | mite->mite_io_addr + MITE_IODWBSR); |
bede7290 | 132 | } |
5256fb88 | 133 | /* |
65f6fac9 | 134 | * Make sure dma bursts work. I got this from running a bus analyzer |
5256fb88 | 135 | * on a pxi-6281 and a pxi-6713. 6713 powered up with register value |
136 | * of 0x61f and bursts worked. 6281 powered up with register value of | |
137 | * 0x1f and bursts didn't work. The NI windows driver reads the | |
138 | * register, then does a bitwise-or of 0x600 with it and writes it back. | |
bede7290 DS |
139 | */ |
140 | unknown_dma_burst_bits = | |
0a85b6f0 | 141 | readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); |
bede7290 DS |
142 | unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS; |
143 | writel(unknown_dma_burst_bits, | |
0a85b6f0 | 144 | mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); |
bede7290 DS |
145 | |
146 | csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR); | |
147 | mite->num_channels = mite_csigr_dmac(csigr_bits); | |
148 | if (mite->num_channels > MAX_MITE_DMA_CHANNELS) { | |
3bb7c3ab | 149 | dev_warn(dev->class_dev, |
d799773f IA |
150 | "mite: bug? chip claims to have %i dma channels. Setting to %i.\n", |
151 | mite->num_channels, MAX_MITE_DMA_CHANNELS); | |
bede7290 DS |
152 | mite->num_channels = MAX_MITE_DMA_CHANNELS; |
153 | } | |
154 | dump_chip_signature(csigr_bits); | |
155 | for (i = 0; i < mite->num_channels; i++) { | |
156 | writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); | |
157 | /* disable interrupts */ | |
158 | writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | | |
0a85b6f0 MT |
159 | CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | |
160 | CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, | |
161 | mite->mite_io_addr + MITE_CHCR(i)); | |
bede7290 DS |
162 | } |
163 | mite->fifo_size = mite_fifo_size(mite, 0); | |
3bb7c3ab | 164 | dev_info(dev->class_dev, "fifo size is %i.\n", mite->fifo_size); |
bede7290 DS |
165 | return 0; |
166 | } | |
5660e742 | 167 | EXPORT_SYMBOL_GPL(mite_setup2); |
bede7290 | 168 | |
b876e985 | 169 | void mite_detach(struct mite_struct *mite) |
bede7290 | 170 | { |
bede7290 DS |
171 | if (!mite) |
172 | return; | |
173 | ||
b876e985 | 174 | if (mite->mite_io_addr) |
bede7290 | 175 | iounmap(mite->mite_io_addr); |
b876e985 HS |
176 | |
177 | kfree(mite); | |
bede7290 | 178 | } |
b876e985 | 179 | EXPORT_SYMBOL_GPL(mite_detach); |
bede7290 | 180 | |
7d24e1ac IA |
181 | struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite) |
182 | { | |
183 | struct mite_dma_descriptor_ring *ring = | |
184 | kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL); | |
185 | ||
5effdf70 HS |
186 | if (!ring) |
187 | return NULL; | |
7d24e1ac | 188 | ring->hw_dev = get_device(&mite->pcidev->dev); |
5effdf70 | 189 | if (!ring->hw_dev) { |
7d24e1ac IA |
190 | kfree(ring); |
191 | return NULL; | |
192 | } | |
193 | ring->n_links = 0; | |
194 | ring->descriptors = NULL; | |
195 | ring->descriptors_dma_addr = 0; | |
196 | return ring; | |
197 | }; | |
5660e742 | 198 | EXPORT_SYMBOL_GPL(mite_alloc_ring); |
7d24e1ac IA |
199 | |
200 | void mite_free_ring(struct mite_dma_descriptor_ring *ring) | |
201 | { | |
202 | if (ring) { | |
203 | if (ring->descriptors) { | |
204 | dma_free_coherent(ring->hw_dev, | |
205 | ring->n_links * | |
206 | sizeof(struct mite_dma_descriptor), | |
207 | ring->descriptors, | |
208 | ring->descriptors_dma_addr); | |
209 | } | |
210 | put_device(ring->hw_dev); | |
211 | kfree(ring); | |
212 | } | |
213 | }; | |
5660e742 | 214 | EXPORT_SYMBOL_GPL(mite_free_ring); |
7d24e1ac | 215 | |
bede7290 | 216 | struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite, |
0a85b6f0 MT |
217 | struct |
218 | mite_dma_descriptor_ring | |
219 | *ring, unsigned min_channel, | |
220 | unsigned max_channel) | |
bede7290 DS |
221 | { |
222 | int i; | |
223 | unsigned long flags; | |
224 | struct mite_channel *channel = NULL; | |
225 | ||
65f6fac9 IA |
226 | /* |
227 | * spin lock so mite_release_channel can be called safely | |
5256fb88 | 228 | * from interrupts |
229 | */ | |
5f74ea14 | 230 | spin_lock_irqsave(&mite->lock, flags); |
bede7290 DS |
231 | for (i = min_channel; i <= max_channel; ++i) { |
232 | if (mite->channel_allocated[i] == 0) { | |
233 | mite->channel_allocated[i] = 1; | |
234 | channel = &mite->channels[i]; | |
235 | channel->ring = ring; | |
236 | break; | |
237 | } | |
238 | } | |
5f74ea14 | 239 | spin_unlock_irqrestore(&mite->lock, flags); |
bede7290 DS |
240 | return channel; |
241 | } | |
5660e742 | 242 | EXPORT_SYMBOL_GPL(mite_request_channel_in_range); |
bede7290 DS |
243 | |
244 | void mite_release_channel(struct mite_channel *mite_chan) | |
245 | { | |
246 | struct mite_struct *mite = mite_chan->mite; | |
247 | unsigned long flags; | |
248 | ||
65f6fac9 | 249 | /* spin lock to prevent races with mite_request_channel */ |
5f74ea14 | 250 | spin_lock_irqsave(&mite->lock, flags); |
bede7290 DS |
251 | if (mite->channel_allocated[mite_chan->channel]) { |
252 | mite_dma_disarm(mite_chan); | |
253 | mite_dma_reset(mite_chan); | |
65f6fac9 IA |
254 | /* |
255 | * disable all channel's interrupts (do it after disarm/reset so | |
256 | * MITE_CHCR reg isn't changed while dma is still active!) | |
257 | */ | |
bede7290 | 258 | writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | |
0a85b6f0 MT |
259 | CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | |
260 | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | | |
261 | CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, | |
262 | mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); | |
bede7290 DS |
263 | mite->channel_allocated[mite_chan->channel] = 0; |
264 | mite_chan->ring = NULL; | |
265 | mmiowb(); | |
266 | } | |
5f74ea14 | 267 | spin_unlock_irqrestore(&mite->lock, flags); |
bede7290 | 268 | } |
5660e742 | 269 | EXPORT_SYMBOL_GPL(mite_release_channel); |
bede7290 DS |
270 | |
271 | void mite_dma_arm(struct mite_channel *mite_chan) | |
272 | { | |
273 | struct mite_struct *mite = mite_chan->mite; | |
274 | int chor; | |
275 | unsigned long flags; | |
276 | ||
5256fb88 | 277 | /* |
278 | * memory barrier is intended to insure any twiddling with the buffer | |
279 | * is done before writing to the mite to arm dma transfer | |
280 | */ | |
bede7290 DS |
281 | smp_mb(); |
282 | /* arm */ | |
283 | chor = CHOR_START; | |
5f74ea14 | 284 | spin_lock_irqsave(&mite->lock, flags); |
bede7290 DS |
285 | mite_chan->done = 0; |
286 | writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); | |
287 | mmiowb(); | |
5f74ea14 | 288 | spin_unlock_irqrestore(&mite->lock, flags); |
65f6fac9 | 289 | /* mite_dma_tcr(mite, channel); */ |
bede7290 | 290 | } |
5660e742 | 291 | EXPORT_SYMBOL_GPL(mite_dma_arm); |
bede7290 DS |
292 | |
293 | /**************************************/ | |
294 | ||
0a85b6f0 | 295 | int mite_buf_change(struct mite_dma_descriptor_ring *ring, |
b74e635d | 296 | struct comedi_subdevice *s) |
bede7290 | 297 | { |
b74e635d | 298 | struct comedi_async *async = s->async; |
bede7290 DS |
299 | unsigned int n_links; |
300 | int i; | |
301 | ||
302 | if (ring->descriptors) { | |
303 | dma_free_coherent(ring->hw_dev, | |
0a85b6f0 MT |
304 | ring->n_links * |
305 | sizeof(struct mite_dma_descriptor), | |
306 | ring->descriptors, | |
307 | ring->descriptors_dma_addr); | |
bede7290 DS |
308 | } |
309 | ring->descriptors = NULL; | |
310 | ring->descriptors_dma_addr = 0; | |
311 | ring->n_links = 0; | |
312 | ||
82675f35 | 313 | if (async->prealloc_bufsz == 0) |
bede7290 | 314 | return 0; |
82675f35 | 315 | |
bede7290 DS |
316 | n_links = async->prealloc_bufsz >> PAGE_SHIFT; |
317 | ||
bede7290 | 318 | ring->descriptors = |
0a85b6f0 MT |
319 | dma_alloc_coherent(ring->hw_dev, |
320 | n_links * sizeof(struct mite_dma_descriptor), | |
321 | &ring->descriptors_dma_addr, GFP_KERNEL); | |
bede7290 | 322 | if (!ring->descriptors) { |
b74e635d | 323 | dev_err(s->device->class_dev, |
d799773f | 324 | "mite: ring buffer allocation failed\n"); |
bede7290 DS |
325 | return -ENOMEM; |
326 | } | |
327 | ring->n_links = n_links; | |
328 | ||
329 | for (i = 0; i < n_links; i++) { | |
330 | ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE); | |
331 | ring->descriptors[i].addr = | |
af93da31 | 332 | cpu_to_le32(async->buf_map->page_list[i].dma_addr); |
bede7290 | 333 | ring->descriptors[i].next = |
0a85b6f0 MT |
334 | cpu_to_le32(ring->descriptors_dma_addr + (i + |
335 | 1) * | |
336 | sizeof(struct mite_dma_descriptor)); | |
bede7290 DS |
337 | } |
338 | ring->descriptors[n_links - 1].next = | |
0a85b6f0 | 339 | cpu_to_le32(ring->descriptors_dma_addr); |
5256fb88 | 340 | /* |
341 | * barrier is meant to insure that all the writes to the dma descriptors | |
342 | * have completed before the dma controller is commanded to read them | |
343 | */ | |
bede7290 DS |
344 | smp_wmb(); |
345 | return 0; | |
346 | } | |
5660e742 | 347 | EXPORT_SYMBOL_GPL(mite_buf_change); |
bede7290 DS |
348 | |
349 | void mite_prep_dma(struct mite_channel *mite_chan, | |
0a85b6f0 | 350 | unsigned int num_device_bits, unsigned int num_memory_bits) |
bede7290 DS |
351 | { |
352 | unsigned int chor, chcr, mcr, dcr, lkcr; | |
353 | struct mite_struct *mite = mite_chan->mite; | |
354 | ||
bede7290 DS |
355 | /* reset DMA and FIFO */ |
356 | chor = CHOR_DMARESET | CHOR_FRESET; | |
357 | writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); | |
358 | ||
359 | /* short link chaining mode */ | |
360 | chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE | | |
0a85b6f0 | 361 | CHCR_BURSTEN; |
bede7290 DS |
362 | /* |
363 | * Link Complete Interrupt: interrupt every time a link | |
364 | * in MITE_RING is completed. This can generate a lot of | |
365 | * extra interrupts, but right now we update the values | |
5256fb88 | 366 | * of buf_int_ptr and buf_int_count at each interrupt. A |
bede7290 DS |
367 | * better method is to poll the MITE before each user |
368 | * "read()" to calculate the number of bytes available. | |
369 | */ | |
370 | chcr |= CHCR_SET_LC_IE; | |
371 | if (num_memory_bits == 32 && num_device_bits == 16) { | |
5256fb88 | 372 | /* |
373 | * Doing a combined 32 and 16 bit byteswap gets the 16 bit | |
374 | * samples into the fifo in the right order. Tested doing 32 bit | |
375 | * memory to 16 bit device transfers to the analog out of a | |
376 | * pxi-6281, which has mite version = 1, type = 4. This also | |
377 | * works for dma reads from the counters on e-series boards. | |
378 | */ | |
bede7290 DS |
379 | chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY; |
380 | } | |
82675f35 | 381 | if (mite_chan->dir == COMEDI_INPUT) |
bede7290 | 382 | chcr |= CHCR_DEV_TO_MEM; |
82675f35 | 383 | |
bede7290 DS |
384 | writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); |
385 | ||
386 | /* to/from memory */ | |
387 | mcr = CR_RL(64) | CR_ASEQUP; | |
388 | switch (num_memory_bits) { | |
389 | case 8: | |
390 | mcr |= CR_PSIZE8; | |
391 | break; | |
392 | case 16: | |
393 | mcr |= CR_PSIZE16; | |
394 | break; | |
395 | case 32: | |
396 | mcr |= CR_PSIZE32; | |
397 | break; | |
398 | default: | |
d799773f | 399 | pr_warn("bug! invalid mem bit width for dma transfer\n"); |
bede7290 DS |
400 | break; |
401 | } | |
402 | writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); | |
403 | ||
404 | /* from/to device */ | |
405 | dcr = CR_RL(64) | CR_ASEQUP; | |
406 | dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel); | |
407 | switch (num_device_bits) { | |
408 | case 8: | |
409 | dcr |= CR_PSIZE8; | |
410 | break; | |
411 | case 16: | |
412 | dcr |= CR_PSIZE16; | |
413 | break; | |
414 | case 32: | |
415 | dcr |= CR_PSIZE32; | |
416 | break; | |
417 | default: | |
d799773f | 418 | pr_warn("bug! invalid dev bit width for dma transfer\n"); |
bede7290 DS |
419 | break; |
420 | } | |
421 | writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel)); | |
422 | ||
423 | /* reset the DAR */ | |
424 | writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel)); | |
425 | ||
426 | /* the link is 32bits */ | |
427 | lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32; | |
428 | writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel)); | |
429 | ||
430 | /* starting address for link chaining */ | |
431 | writel(mite_chan->ring->descriptors_dma_addr, | |
0a85b6f0 | 432 | mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); |
bede7290 | 433 | } |
5660e742 | 434 | EXPORT_SYMBOL_GPL(mite_prep_dma); |
bede7290 | 435 | |
ae031801 | 436 | static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan) |
bede7290 DS |
437 | { |
438 | struct mite_struct *mite = mite_chan->mite; | |
9a7c5693 | 439 | |
bede7290 DS |
440 | return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel)); |
441 | } | |
442 | ||
5256fb88 | 443 | u32 mite_bytes_in_transit(struct mite_channel *mite_chan) |
bede7290 DS |
444 | { |
445 | struct mite_struct *mite = mite_chan->mite; | |
9a7c5693 | 446 | |
bede7290 | 447 | return readl(mite->mite_io_addr + |
0a85b6f0 | 448 | MITE_FCR(mite_chan->channel)) & 0x000000FF; |
bede7290 | 449 | } |
5660e742 | 450 | EXPORT_SYMBOL_GPL(mite_bytes_in_transit); |
bede7290 | 451 | |
5256fb88 | 452 | /* returns lower bound for number of bytes transferred from device to memory */ |
453 | u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan) | |
bede7290 DS |
454 | { |
455 | u32 device_byte_count; | |
456 | ||
457 | device_byte_count = mite_device_bytes_transferred(mite_chan); | |
458 | return device_byte_count - mite_bytes_in_transit(mite_chan); | |
459 | } | |
5660e742 | 460 | EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_lb); |
bede7290 | 461 | |
5256fb88 | 462 | /* returns upper bound for number of bytes transferred from device to memory */ |
463 | u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan) | |
bede7290 DS |
464 | { |
465 | u32 in_transit_count; | |
466 | ||
467 | in_transit_count = mite_bytes_in_transit(mite_chan); | |
468 | return mite_device_bytes_transferred(mite_chan) - in_transit_count; | |
469 | } | |
5660e742 | 470 | EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_ub); |
bede7290 | 471 | |
5256fb88 | 472 | /* returns lower bound for number of bytes read from memory to device */ |
473 | u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan) | |
bede7290 DS |
474 | { |
475 | u32 device_byte_count; | |
476 | ||
477 | device_byte_count = mite_device_bytes_transferred(mite_chan); | |
478 | return device_byte_count + mite_bytes_in_transit(mite_chan); | |
479 | } | |
5660e742 | 480 | EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_lb); |
bede7290 | 481 | |
5256fb88 | 482 | /* returns upper bound for number of bytes read from memory to device */ |
483 | u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan) | |
bede7290 DS |
484 | { |
485 | u32 in_transit_count; | |
486 | ||
487 | in_transit_count = mite_bytes_in_transit(mite_chan); | |
488 | return mite_device_bytes_transferred(mite_chan) + in_transit_count; | |
489 | } | |
5660e742 | 490 | EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_ub); |
bede7290 DS |
491 | |
492 | unsigned mite_dma_tcr(struct mite_channel *mite_chan) | |
493 | { | |
494 | struct mite_struct *mite = mite_chan->mite; | |
bede7290 | 495 | |
ea0db9b2 | 496 | return readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel)); |
bede7290 | 497 | } |
5660e742 | 498 | EXPORT_SYMBOL_GPL(mite_dma_tcr); |
bede7290 DS |
499 | |
500 | void mite_dma_disarm(struct mite_channel *mite_chan) | |
501 | { | |
502 | struct mite_struct *mite = mite_chan->mite; | |
503 | unsigned chor; | |
504 | ||
505 | /* disarm */ | |
506 | chor = CHOR_ABORT; | |
507 | writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); | |
508 | } | |
5660e742 | 509 | EXPORT_SYMBOL_GPL(mite_dma_disarm); |
bede7290 | 510 | |
0a85b6f0 | 511 | int mite_sync_input_dma(struct mite_channel *mite_chan, |
74f63db7 | 512 | struct comedi_subdevice *s) |
bede7290 | 513 | { |
74f63db7 | 514 | struct comedi_async *async = s->async; |
bede7290 DS |
515 | int count; |
516 | unsigned int nbytes, old_alloc_count; | |
bede7290 DS |
517 | |
518 | old_alloc_count = async->buf_write_alloc_count; | |
5256fb88 | 519 | /* write alloc as much as we can */ |
24e894bb | 520 | comedi_buf_write_alloc(s, async->prealloc_bufsz); |
bede7290 DS |
521 | |
522 | nbytes = mite_bytes_written_to_memory_lb(mite_chan); | |
523 | if ((int)(mite_bytes_written_to_memory_ub(mite_chan) - | |
0a85b6f0 | 524 | old_alloc_count) > 0) { |
12d6dda6 | 525 | dev_warn(s->device->class_dev, |
d799773f | 526 | "mite: DMA overwrite of free area\n"); |
bede7290 DS |
527 | async->events |= COMEDI_CB_OVERFLOW; |
528 | return -1; | |
529 | } | |
530 | ||
531 | count = nbytes - async->buf_write_count; | |
65f6fac9 IA |
532 | /* |
533 | * it's possible count will be negative due to conservative value | |
534 | * returned by mite_bytes_written_to_memory_lb | |
535 | */ | |
82675f35 | 536 | if (count <= 0) |
bede7290 | 537 | return 0; |
82675f35 | 538 | |
940dd35d | 539 | comedi_buf_write_free(s, count); |
eac783a6 | 540 | comedi_inc_scan_progress(s, count); |
bede7290 DS |
541 | async->events |= COMEDI_CB_BLOCK; |
542 | return 0; | |
543 | } | |
5660e742 | 544 | EXPORT_SYMBOL_GPL(mite_sync_input_dma); |
bede7290 | 545 | |
0a85b6f0 | 546 | int mite_sync_output_dma(struct mite_channel *mite_chan, |
1e575a9c | 547 | struct comedi_subdevice *s) |
bede7290 | 548 | { |
1e575a9c | 549 | struct comedi_async *async = s->async; |
45c9db91 | 550 | struct comedi_cmd *cmd = &async->cmd; |
f4fc1dbe | 551 | u32 stop_count = cmd->stop_arg * comedi_bytes_per_scan(s); |
45c9db91 | 552 | unsigned int old_alloc_count = async->buf_read_alloc_count; |
bede7290 | 553 | u32 nbytes_ub, nbytes_lb; |
45c9db91 | 554 | int count; |
bede7290 | 555 | |
65f6fac9 | 556 | /* read alloc as much as we can */ |
d13be55a | 557 | comedi_buf_read_alloc(s, async->prealloc_bufsz); |
bede7290 | 558 | nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); |
45c9db91 | 559 | if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0) |
bede7290 DS |
560 | nbytes_lb = stop_count; |
561 | nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan); | |
45c9db91 | 562 | if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_ub - stop_count) > 0) |
bede7290 DS |
563 | nbytes_ub = stop_count; |
564 | if ((int)(nbytes_ub - old_alloc_count) > 0) { | |
1e575a9c | 565 | dev_warn(s->device->class_dev, "mite: DMA underrun\n"); |
bede7290 DS |
566 | async->events |= COMEDI_CB_OVERFLOW; |
567 | return -1; | |
568 | } | |
569 | count = nbytes_lb - async->buf_read_count; | |
82675f35 | 570 | if (count <= 0) |
bede7290 | 571 | return 0; |
82675f35 | 572 | |
bede7290 | 573 | if (count) { |
f1df8662 | 574 | comedi_buf_read_free(s, count); |
bede7290 DS |
575 | async->events |= COMEDI_CB_BLOCK; |
576 | } | |
577 | return 0; | |
578 | } | |
5660e742 | 579 | EXPORT_SYMBOL_GPL(mite_sync_output_dma); |
bede7290 DS |
580 | |
581 | unsigned mite_get_status(struct mite_channel *mite_chan) | |
582 | { | |
583 | struct mite_struct *mite = mite_chan->mite; | |
584 | unsigned status; | |
585 | unsigned long flags; | |
586 | ||
5f74ea14 | 587 | spin_lock_irqsave(&mite->lock, flags); |
bede7290 DS |
588 | status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel)); |
589 | if (status & CHSR_DONE) { | |
590 | mite_chan->done = 1; | |
591 | writel(CHOR_CLRDONE, | |
0a85b6f0 | 592 | mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); |
bede7290 DS |
593 | } |
594 | mmiowb(); | |
5f74ea14 | 595 | spin_unlock_irqrestore(&mite->lock, flags); |
bede7290 DS |
596 | return status; |
597 | } | |
5660e742 | 598 | EXPORT_SYMBOL_GPL(mite_get_status); |
bede7290 DS |
599 | |
600 | int mite_done(struct mite_channel *mite_chan) | |
601 | { | |
602 | struct mite_struct *mite = mite_chan->mite; | |
603 | unsigned long flags; | |
604 | int done; | |
605 | ||
606 | mite_get_status(mite_chan); | |
5f74ea14 | 607 | spin_lock_irqsave(&mite->lock, flags); |
bede7290 | 608 | done = mite_chan->done; |
5f74ea14 | 609 | spin_unlock_irqrestore(&mite->lock, flags); |
bede7290 DS |
610 | return done; |
611 | } | |
5660e742 | 612 | EXPORT_SYMBOL_GPL(mite_done); |
bede7290 | 613 | |
a09b0278 | 614 | static int __init mite_module_init(void) |
bede7290 | 615 | { |
bede7290 DS |
616 | return 0; |
617 | } | |
618 | ||
a09b0278 | 619 | static void __exit mite_module_exit(void) |
bede7290 | 620 | { |
bede7290 | 621 | } |
a09b0278 IA |
622 | |
623 | module_init(mite_module_init); | |
624 | module_exit(mite_module_exit); | |
90f703d3 AT |
625 | |
626 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
3ad94703 | 627 | MODULE_DESCRIPTION("Comedi helper for NI Mite PCI interface chip"); |
90f703d3 | 628 | MODULE_LICENSE("GPL"); |