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Staging: comedi: Checkpatch cleanups in adl_pci9111.c
[linux-2.6-block.git] / drivers / staging / comedi / drivers / gsc_hpdi.c
CommitLineData
f26c569b
FMH		 1/*
2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
5
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
8
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25
26************************************************************************/
27
28/*
29
30Driver: gsc_hpdi
31Description: General Standards Corporation High
32 Speed Parallel Digital Interface rs485 boards
33Author: Frank Mori Hess <fmhess@users.sourceforge.net>
34Status: only receive mode works, transmit not supported
35Updated: 2003-02-20
36Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
37 PMC-HPDI32
38
39Configuration options:
40 [0] - PCI bus of device (optional)
41 [1] - PCI slot of device (optional)
42
43There are some additional hpdi models available from GSC for which
44support could be added to this driver.
45
46*/
47
25436dc9 48#include <linux/interrupt.h>
f26c569b
FMH		 49#include "../comedidev.h"
50#include <linux/delay.h>
51
52#include "comedi_pci.h"
53#include "plx9080.h"
54#include "comedi_fc.h"
55
814900c9
BP		 56static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it);
57static int hpdi_detach(struct comedi_device *dev);
64ca6a7e 58static void abort_dma(struct comedi_device *dev, unsigned int channel);
814900c9
BP		 59static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
60static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 61 struct comedi_cmd *cmd);
814900c9 62static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
70265d24 63static irqreturn_t handle_interrupt(int irq, void *d);
814900c9 64static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
f26c569b 65
c52c19c3
BP		 66#undef HPDI_DEBUG /* disable debugging messages */
67/* #define HPDI_DEBUG enable debugging code */
f26c569b
FMH		 68
69#ifdef HPDI_DEBUG
5f74ea14 70#define DEBUG_PRINT(format, args...) printk(format , ## args)
f26c569b
FMH		 71#else
72#define DEBUG_PRINT(format, args...)
73#endif
74
c52c19c3 75#define TIMER_BASE 50 /* 20MHz master clock */
f26c569b
FMH		 76#define DMA_BUFFER_SIZE 0x10000
77#define NUM_DMA_BUFFERS 4
78#define NUM_DMA_DESCRIPTORS 256
79
c52c19c3 80/* indices of base address regions */
f26c569b
FMH		 81enum base_address_regions {
82 PLX9080_BADDRINDEX = 0,
83 HPDI_BADDRINDEX = 2,
84};
85
86enum hpdi_registers {
87 FIRMWARE_REV_REG = 0x0,
88 BOARD_CONTROL_REG = 0x4,
89 BOARD_STATUS_REG = 0x8,
90 TX_PROG_ALMOST_REG = 0xc,
91 RX_PROG_ALMOST_REG = 0x10,
92 FEATURES_REG = 0x14,
93 FIFO_REG = 0x18,
94 TX_STATUS_COUNT_REG = 0x1c,
95 TX_LINE_VALID_COUNT_REG = 0x20,
96 TX_LINE_INVALID_COUNT_REG = 0x24,
97 RX_STATUS_COUNT_REG = 0x28,
98 RX_LINE_COUNT_REG = 0x2c,
99 INTERRUPT_CONTROL_REG = 0x30,
100 INTERRUPT_STATUS_REG = 0x34,
101 TX_CLOCK_DIVIDER_REG = 0x38,
102 TX_FIFO_SIZE_REG = 0x40,
103 RX_FIFO_SIZE_REG = 0x44,
104 TX_FIFO_WORDS_REG = 0x48,
105 RX_FIFO_WORDS_REG = 0x4c,
106 INTERRUPT_EDGE_LEVEL_REG = 0x50,
107 INTERRUPT_POLARITY_REG = 0x54,
108};
109
110int command_channel_valid(unsigned int channel)
111{
112 if (channel == 0 || channel > 6) {
92e462c3
DH		 113 printk(KERN_WARNING
114 "gsc_hpdi: bug! invalid cable command channel\n");
f26c569b
FMH		 115 return 0;
116 }
117 return 1;
118}
119
c52c19c3 120/* bit definitions */
f26c569b
FMH		 121
122enum firmware_revision_bits {
123 FEATURES_REG_PRESENT_BIT = 0x8000,
124};
125int firmware_revision(uint32_t fwr_bits)
126{
127 return fwr_bits & 0xff;
128}
129
130int pcb_revision(uint32_t fwr_bits)
131{
132 return (fwr_bits >> 8) & 0xff;
133}
134
135int hpdi_subid(uint32_t fwr_bits)
136{
137 return (fwr_bits >> 16) & 0xff;
138}
139
140enum board_control_bits {
141 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
142 TX_FIFO_RESET_BIT = 0x2,
143 RX_FIFO_RESET_BIT = 0x4,
144 TX_ENABLE_BIT = 0x10,
145 RX_ENABLE_BIT = 0x20,
95a2572f
DH		 146 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
147 /* for ch 0, ch 1 can only transmit (when present) */
f26c569b
FMH		 148 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
149 START_TX_BIT = 0x10,
150 CABLE_THROTTLE_ENABLE_BIT = 0x20,
151 TEST_MODE_ENABLE_BIT = 0x80000000,
152};
153uint32_t command_discrete_output_bits(unsigned int channel, int output,
0a85b6f0 154 int output_value)
f26c569b
FMH		 155{
156 uint32_t bits = 0;
157
158 if (command_channel_valid(channel) == 0)
159 return 0;
160 if (output) {
161 bits |= 0x1 << (16 + channel);
162 if (output_value)
163 bits |= 0x1 << (24 + channel);
164 } else
165 bits |= 0x1 << (24 + channel);
166
167 return bits;
168}
169
170enum board_status_bits {
171 COMMAND_LINE_STATUS_MASK = 0x7f,
172 TX_IN_PROGRESS_BIT = 0x80,
173 TX_NOT_EMPTY_BIT = 0x100,
174 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
175 TX_NOT_ALMOST_FULL_BIT = 0x400,
176 TX_NOT_FULL_BIT = 0x800,
177 RX_NOT_EMPTY_BIT = 0x1000,
178 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
179 RX_NOT_ALMOST_FULL_BIT = 0x4000,
180 RX_NOT_FULL_BIT = 0x8000,
181 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
182 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
183 TX_OVERRUN_BIT = 0x200000,
184 RX_UNDERRUN_BIT = 0x400000,
185 RX_OVERRUN_BIT = 0x800000,
186};
187
188uint32_t almost_full_bits(unsigned int num_words)
189{
c52c19c3 190/* XXX need to add or subtract one? */
f26c569b
FMH		 191 return (num_words << 16) & 0xff0000;
192}
193
194uint32_t almost_empty_bits(unsigned int num_words)
195{
196 return num_words & 0xffff;
197}
0a85b6f0 198
f26c569b
FMH		 199unsigned int almost_full_num_words(uint32_t bits)
200{
c52c19c3 201/* XXX need to add or subtract one? */
f26c569b
FMH		 202 return (bits >> 16) & 0xffff;
203}
0a85b6f0 204
f26c569b
FMH		 205unsigned int almost_empty_num_words(uint32_t bits)
206{
207 return bits & 0xffff;
208}
209
210enum features_bits {
211 FIFO_SIZE_PRESENT_BIT = 0x1,
212 FIFO_WORDS_PRESENT_BIT = 0x2,
213 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
214 GPIO_SUPPORTED_BIT = 0x8,
215 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
216 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
217};
218
219enum interrupt_sources {
220 FRAME_VALID_START_INTR = 0,
221 FRAME_VALID_END_INTR = 1,
222 TX_FIFO_EMPTY_INTR = 8,
223 TX_FIFO_ALMOST_EMPTY_INTR = 9,
224 TX_FIFO_ALMOST_FULL_INTR = 10,
225 TX_FIFO_FULL_INTR = 11,
226 RX_EMPTY_INTR = 12,
227 RX_ALMOST_EMPTY_INTR = 13,
228 RX_ALMOST_FULL_INTR = 14,
229 RX_FULL_INTR = 15,
230};
231int command_intr_source(unsigned int channel)
232{
233 if (command_channel_valid(channel) == 0)
234 channel = 1;
235 return channel + 1;
236}
237
238uint32_t intr_bit(int interrupt_source)
239{
240 return 0x1 << interrupt_source;
241}
242
243uint32_t tx_clock_divisor_bits(unsigned int divisor)
244{
245 return divisor & 0xff;
246}
247
248unsigned int fifo_size(uint32_t fifo_size_bits)
249{
250 return fifo_size_bits & 0xfffff;
251}
252
253unsigned int fifo_words(uint32_t fifo_words_bits)
254{
255 return fifo_words_bits & 0xfffff;
256}
257
258uint32_t intr_edge_bit(int interrupt_source)
259{
260 return 0x1 << interrupt_source;
261}
262
263uint32_t intr_active_high_bit(int interrupt_source)
264{
265 return 0x1 << interrupt_source;
266}
267
52b3e348
BP		 268struct hpdi_board {
269
f26c569b 270 char *name;
c52c19c3
BP		 271 int device_id; /* pci device id */
272 int subdevice_id; /* pci subdevice id */
52b3e348
BP		 273};
274
52b3e348 275static const struct hpdi_board hpdi_boards[] = {
f26c569b 276 {
0a85b6f0
MT		 277 .name = "pci-hpdi32",
278 .device_id = PCI_DEVICE_ID_PLX_9080,
279 .subdevice_id = 0x2400,
280 },
f26c569b
FMH		 281#if 0
282 {
0a85b6f0
MT		 283 .name = "pxi-hpdi32",
284 .device_id = 0x9656,
285 .subdevice_id = 0x2705,
286 },
f26c569b
FMH		 287#endif
288};
289
f26c569b 290static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = {
0a85b6f0
MT		 291 {
292 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
293 0x2400, 0, 0, 0}, {
294 0}
f26c569b
FMH		 295};
296
297MODULE_DEVICE_TABLE(pci, hpdi_pci_table);
298
0a85b6f0 299static inline struct hpdi_board *board(const struct comedi_device *dev)
f26c569b 300{
0a85b6f0 301 return (struct hpdi_board *)dev->board_ptr;
f26c569b
FMH		 302}
303
352dec62
BP		 304struct hpdi_private {
305
c52c19c3
BP		 306 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
307 /* base addresses (physical) */
f26c569b
FMH		 308 resource_size_t plx9080_phys_iobase;
309 resource_size_t hpdi_phys_iobase;
c52c19c3 310 /* base addresses (ioremapped) */
f26c569b
FMH		 311 void *plx9080_iobase;
312 void *hpdi_iobase;
c52c19c3
BP		 313 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
314 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS]; /* physical addresses of dma buffers */
315 struct plx_dma_desc *dma_desc; /* array of dma descriptors read by plx9080, allocated to get proper alignment */
316 dma_addr_t dma_desc_phys_addr; /* physical address of dma descriptor array */
f26c569b 317 unsigned int num_dma_descriptors;
c52c19c3
BP		 318 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS]; /* pointer to start of buffers indexed by descriptor */
319 volatile unsigned int dma_desc_index; /* index of the dma descriptor that is currently being used */
f26c569b
FMH		 320 unsigned int tx_fifo_size;
321 unsigned int rx_fifo_size;
322 volatile unsigned long dio_count;
c52c19c3
BP		 323 volatile uint32_t bits[24]; /* software copies of values written to hpdi registers */
324 volatile unsigned int block_size; /* number of bytes at which to generate COMEDI_CB_BLOCK events */
f26c569b 325 unsigned dio_config_output:1;
352dec62
BP		 326};
327
0a85b6f0 328static inline struct hpdi_private *priv(struct comedi_device *dev)
f26c569b
FMH		 329{
330 return dev->private;
331}
332
139dfbdf 333static struct comedi_driver driver_hpdi = {
68c3dbff
BP		 334 .driver_name = "gsc_hpdi",
335 .module = THIS_MODULE,
336 .attach = hpdi_attach,
337 .detach = hpdi_detach,
f26c569b
FMH		 338};
339
340COMEDI_PCI_INITCLEANUP(driver_hpdi, hpdi_pci_table);
341
0a85b6f0
MT		 342static int dio_config_insn(struct comedi_device *dev,
343 struct comedi_subdevice *s, struct comedi_insn *insn,
344 unsigned int *data)
f26c569b
FMH		 345{
346 switch (data[0]) {
347 case INSN_CONFIG_DIO_OUTPUT:
348 priv(dev)->dio_config_output = 1;
349 return insn->n;
350 break;
351 case INSN_CONFIG_DIO_INPUT:
352 priv(dev)->dio_config_output = 0;
353 return insn->n;
354 break;
355 case INSN_CONFIG_DIO_QUERY:
356 data[1] =
0a85b6f0 357 priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
f26c569b
FMH		 358 return insn->n;
359 break;
360 case INSN_CONFIG_BLOCK_SIZE:
361 return dio_config_block_size(dev, data);
362 break;
363 default:
364 break;
365 }
366
367 return -EINVAL;
368}
369
da91b269 370static void disable_plx_interrupts(struct comedi_device *dev)
f26c569b
FMH		 371{
372 writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
373}
374
c52c19c3 375/* initialize plx9080 chip */
da91b269 376static void init_plx9080(struct comedi_device *dev)
f26c569b
FMH		 377{
378 uint32_t bits;
379 void *plx_iobase = priv(dev)->plx9080_iobase;
380
c52c19c3 381 /* plx9080 dump */
f26c569b 382 DEBUG_PRINT(" plx interrupt status 0x%x\n",
0a85b6f0 383 readl(plx_iobase + PLX_INTRCS_REG));
f26c569b
FMH		 384 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
385 DEBUG_PRINT(" plx control reg 0x%x\n",
0a85b6f0 386 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
f26c569b
FMH		 387
388 DEBUG_PRINT(" plx revision 0x%x\n",
0a85b6f0 389 readl(plx_iobase + PLX_REVISION_REG));
f26c569b 390 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
0a85b6f0 391 readl(plx_iobase + PLX_DMA0_MODE_REG));
f26c569b 392 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
0a85b6f0 393 readl(plx_iobase + PLX_DMA1_MODE_REG));
f26c569b 394 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
0a85b6f0 395 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
f26c569b 396 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
0a85b6f0 397 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
f26c569b 398 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
0a85b6f0 399 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
f26c569b 400 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
0a85b6f0 401 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
f26c569b 402 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
0a85b6f0 403 readb(plx_iobase + PLX_DMA0_CS_REG));
f26c569b 404 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
0a85b6f0 405 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
f26c569b
FMH		 406 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
407#ifdef __BIG_ENDIAN
408 bits = BIGEND_DMA0 | BIGEND_DMA1;
409#else
410 bits = 0;
411#endif
412 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
413
414 disable_plx_interrupts(dev);
415
416 abort_dma(dev, 0);
417 abort_dma(dev, 1);
418
c52c19c3 419 /* configure dma0 mode */
f26c569b 420 bits = 0;
c52c19c3 421 /* enable ready input */
f26c569b 422 bits |= PLX_DMA_EN_READYIN_BIT;
c52c19c3 423 /* enable dma chaining */
f26c569b 424 bits |= PLX_EN_CHAIN_BIT;
95a2572f
DH		 425 /* enable interrupt on dma done
426 * (probably don't need this, since chain never finishes) */
f26c569b 427 bits |= PLX_EN_DMA_DONE_INTR_BIT;
95a2572f
DH		 428 /* don't increment local address during transfers
429 * (we are transferring from a fixed fifo register) */
f26c569b 430 bits |= PLX_LOCAL_ADDR_CONST_BIT;
c52c19c3 431 /* route dma interrupt to pci bus */
f26c569b 432 bits |= PLX_DMA_INTR_PCI_BIT;
c52c19c3 433 /* enable demand mode */
f26c569b 434 bits |= PLX_DEMAND_MODE_BIT;
c52c19c3 435 /* enable local burst mode */
f26c569b
FMH		 436 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
437 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
438 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
439}
440
441/* Allocate and initialize the subdevice structures.
442 */
da91b269 443static int setup_subdevices(struct comedi_device *dev)
f26c569b 444{
34c43922 445 struct comedi_subdevice *s;
f26c569b
FMH		 446
447 if (alloc_subdevices(dev, 1) < 0)
448 return -ENOMEM;
449
450 s = dev->subdevices + 0;
451 /* analog input subdevice */
452 dev->read_subdev = s;
453/* dev->write_subdev = s; */
454 s->type = COMEDI_SUBD_DIO;
455 s->subdev_flags =
0a85b6f0 456 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
f26c569b
FMH		 457 s->n_chan = 32;
458 s->len_chanlist = 32;
459 s->maxdata = 1;
460 s->range_table = &range_digital;
461 s->insn_config = dio_config_insn;
462 s->do_cmd = hpdi_cmd;
463 s->do_cmdtest = hpdi_cmd_test;
464 s->cancel = hpdi_cancel;
465
466 return 0;
467}
468
da91b269 469static int init_hpdi(struct comedi_device *dev)
f26c569b
FMH		 470{
471 uint32_t plx_intcsr_bits;
472
473 writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
5f74ea14 474 udelay(10);
f26c569b
FMH		 475
476 writel(almost_empty_bits(32) | almost_full_bits(32),
0a85b6f0 477 priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
f26c569b 478 writel(almost_empty_bits(32) | almost_full_bits(32),
0a85b6f0 479 priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
f26c569b
FMH		 480
481 priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
0a85b6f0 482 TX_FIFO_SIZE_REG));
f26c569b 483 priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
0a85b6f0 484 RX_FIFO_SIZE_REG));
f26c569b
FMH		 485
486 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
487
c52c19c3 488 /* enable interrupts */
f26c569b 489 plx_intcsr_bits =
0a85b6f0
MT		 490 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
491 ICS_DMA0_E;
f26c569b
FMH		 492 writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
493
494 return 0;
495}
496
c52c19c3 497/* setup dma descriptors so a link completes every 'transfer_size' bytes */
da91b269 498static int setup_dma_descriptors(struct comedi_device *dev,
0a85b6f0 499 unsigned int transfer_size)
f26c569b
FMH		 500{
501 unsigned int buffer_index, buffer_offset;
502 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
0a85b6f0 503 PLX_XFER_LOCAL_TO_PCI;
f26c569b
FMH		 504 unsigned int i;
505
506 if (transfer_size > DMA_BUFFER_SIZE)
507 transfer_size = DMA_BUFFER_SIZE;
508 transfer_size -= transfer_size % sizeof(uint32_t);
509 if (transfer_size == 0)
510 return -1;
511
512 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
513 DEBUG_PRINT(" descriptors at 0x%lx\n",
0a85b6f0 514 (unsigned long)priv(dev)->dma_desc_phys_addr);
f26c569b
FMH		 515
516 buffer_offset = 0;
517 buffer_index = 0;
518 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
0a85b6f0 519 buffer_index < NUM_DMA_BUFFERS; i++) {
f26c569b 520 priv(dev)->dma_desc[i].pci_start_addr =
0a85b6f0
MT		 521 cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] +
522 buffer_offset);
f26c569b
FMH		 523 priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
524 priv(dev)->dma_desc[i].transfer_size =
0a85b6f0 525 cpu_to_le32(transfer_size);
f26c569b 526 priv(dev)->dma_desc[i].next =
0a85b6f0
MT		 527 cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
528 1) *
529 sizeof(priv(dev)->dma_desc[0])) | next_bits);
f26c569b
FMH		 530
531 priv(dev)->desc_dio_buffer[i] =
0a85b6f0
MT		 532 priv(dev)->dio_buffer[buffer_index] +
533 (buffer_offset / sizeof(uint32_t));
f26c569b
FMH		 534
535 buffer_offset += transfer_size;
536 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
537 buffer_offset = 0;
538 buffer_index++;
539 }
540
541 DEBUG_PRINT(" desc %i\n", i);
542 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
0a85b6f0
MT		 543 priv(dev)->desc_dio_buffer[i],
544 (unsigned long)priv(dev)->dma_desc[i].
545 pci_start_addr);
f26c569b 546 DEBUG_PRINT(" next 0x%lx\n",
0a85b6f0 547 (unsigned long)priv(dev)->dma_desc[i].next);
f26c569b
FMH		 548 }
549 priv(dev)->num_dma_descriptors = i;
c52c19c3 550 /* fix last descriptor to point back to first */
f26c569b 551 priv(dev)->dma_desc[i - 1].next =
0a85b6f0 552 cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
f26c569b 553 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
0a85b6f0 554 (unsigned long)priv(dev)->dma_desc[i - 1].next);
f26c569b
FMH		 555
556 priv(dev)->block_size = transfer_size;
557
558 return transfer_size;
559}
560
da91b269 561static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it)
f26c569b
FMH		 562{
563 struct pci_dev *pcidev;
564 int i;
565 int retval;
566
92e462c3 567 printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor);
f26c569b 568
352dec62 569 if (alloc_private(dev, sizeof(struct hpdi_private)) < 0)
f26c569b
FMH		 570 return -ENOMEM;
571
572 pcidev = NULL;
8629efa4 573 for (i = 0; i < ARRAY_SIZE(hpdi_boards) && dev->board_ptr == NULL; i++) {
f26c569b
FMH		 574 do {
575 pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
0a85b6f0
MT		 576 hpdi_boards[i].device_id,
577 PCI_VENDOR_ID_PLX,
578 hpdi_boards[i].subdevice_id,
579 pcidev);
c52c19c3 580 /* was a particular bus/slot requested? */
f26c569b 581 if (it->options[0] || it->options[1]) {
c52c19c3 582 /* are we on the wrong bus/slot? */
f26c569b 583 if (pcidev->bus->number != it->options[0] ||
0a85b6f0 584 PCI_SLOT(pcidev->devfn) != it->options[1])
f26c569b
FMH		 585 continue;
586 }
587 if (pcidev) {
588 priv(dev)->hw_dev = pcidev;
589 dev->board_ptr = hpdi_boards + i;
590 break;
591 }
592 } while (pcidev != NULL);
593 }
594 if (dev->board_ptr == NULL) {
92e462c3 595 printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n");
f26c569b
FMH		 596 return -EIO;
597 }
598
92e462c3
DH		 599 printk(KERN_WARNING
600 "gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
0a85b6f0 601 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
f26c569b
FMH		 602
603 if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) {
604 printk(KERN_WARNING
0a85b6f0 605 " failed enable PCI device and request regions\n");
f26c569b
FMH		 606 return -EIO;
607 }
608 pci_set_master(pcidev);
609
c52c19c3 610 /* Initialize dev->board_name */
f26c569b
FMH		 611 dev->board_name = board(dev)->name;
612
613 priv(dev)->plx9080_phys_iobase =
0a85b6f0 614 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
f26c569b 615 priv(dev)->hpdi_phys_iobase =
0a85b6f0 616 pci_resource_start(pcidev, HPDI_BADDRINDEX);
f26c569b 617
c52c19c3 618 /* remap, won't work with 2.0 kernels but who cares */
f26c569b 619 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
0a85b6f0
MT		 620 pci_resource_len(pcidev,
621 PLX9080_BADDRINDEX));
622 priv(dev)->hpdi_iobase =
623 ioremap(priv(dev)->hpdi_phys_iobase,
624 pci_resource_len(pcidev, HPDI_BADDRINDEX));
f26c569b 625 if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
92e462c3 626 printk(KERN_WARNING " failed to remap io memory\n");
f26c569b
FMH		 627 return -ENOMEM;
628 }
629
630 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
631 DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
632
633 init_plx9080(dev);
634
c52c19c3 635 /* get irq */
5f74ea14 636 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
f26c569b 637 driver_hpdi.driver_name, dev)) {
92e462c3
DH		 638 printk(KERN_WARNING
639 " unable to allocate irq %u\n", pcidev->irq);
f26c569b
FMH		 640 return -EINVAL;
641 }
642 dev->irq = pcidev->irq;
643
92e462c3 644 printk(KERN_WARNING " irq %u\n", dev->irq);
f26c569b 645
c52c19c3 646 /* alocate pci dma buffers */
f26c569b
FMH		 647 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
648 priv(dev)->dio_buffer[i] =
0a85b6f0
MT		 649 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
650 &priv(dev)->dio_buffer_phys_addr[i]);
f26c569b 651 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
0a85b6f0
MT		 652 priv(dev)->dio_buffer[i],
653 (unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
f26c569b 654 }
c52c19c3 655 /* allocate dma descriptors */
f26c569b 656 priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
0a85b6f0
MT		 657 sizeof(struct plx_dma_desc) *
658 NUM_DMA_DESCRIPTORS,
659 &priv(dev)->
660 dma_desc_phys_addr);
f26c569b 661 if (priv(dev)->dma_desc_phys_addr & 0xf) {
92e462c3
DH		 662 printk(KERN_WARNING
663 " dma descriptors not quad-word aligned (bug)\n");
f26c569b
FMH		 664 return -EIO;
665 }
666
667 retval = setup_dma_descriptors(dev, 0x1000);
668 if (retval < 0)
669 return retval;
670
671 retval = setup_subdevices(dev);
672 if (retval < 0)
673 return retval;
674
675 return init_hpdi(dev);
676}
677
da91b269 678static int hpdi_detach(struct comedi_device *dev)
f26c569b
FMH		 679{
680 unsigned int i;
681
92e462c3 682 printk(KERN_WARNING "comedi%d: gsc_hpdi: remove\n", dev->minor);
f26c569b
FMH		 683
684 if (dev->irq)
5f74ea14 685 free_irq(dev->irq, dev);
95a2572f
DH		 686 if ((priv(dev)) && (priv(dev)->hw_dev)) {
687 if (priv(dev)->plx9080_iobase) {
688 disable_plx_interrupts(dev);
689 iounmap((void *)priv(dev)->plx9080_iobase);
690 }
691 if (priv(dev)->hpdi_iobase)
692 iounmap((void *)priv(dev)->hpdi_iobase);
693 /* free pci dma buffers */
694 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
695 if (priv(dev)->dio_buffer[i])
f26c569b 696 pci_free_consistent(priv(dev)->hw_dev,
95a2572f 697 DMA_BUFFER_SIZE,
0a85b6f0 698 priv(dev)->
95a2572f
DH		 699 dio_buffer[i],
700 priv
701 (dev)->dio_buffer_phys_addr
702 [i]);
f26c569b 703 }
95a2572f
DH		 704 /* free dma descriptors */
705 if (priv(dev)->dma_desc)
706 pci_free_consistent(priv(dev)->hw_dev,
707 sizeof(struct plx_dma_desc)
708 * NUM_DMA_DESCRIPTORS,
709 priv(dev)->dma_desc,
710 priv(dev)->
711 dma_desc_phys_addr);
712 if (priv(dev)->hpdi_phys_iobase)
713 comedi_pci_disable(priv(dev)->hw_dev);
714 pci_dev_put(priv(dev)->hw_dev);
f26c569b
FMH		 715 }
716 return 0;
717}
718
da91b269 719static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
f26c569b
FMH		 720{
721 unsigned int requested_block_size;
722 int retval;
723
724 requested_block_size = data[1];
725
726 retval = setup_dma_descriptors(dev, requested_block_size);
727 if (retval < 0)
728 return retval;
729
730 data[1] = retval;
731
732 return 2;
733}
734
da91b269 735static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 736 struct comedi_cmd *cmd)
f26c569b
FMH		 737{
738 int err = 0;
739 int tmp;
740 int i;
741
742 /* step 1: make sure trigger sources are trivially valid */
743
744 tmp = cmd->start_src;
745 cmd->start_src &= TRIG_NOW;
746 if (!cmd->start_src || tmp != cmd->start_src)
747 err++;
748
749 tmp = cmd->scan_begin_src;
750 cmd->scan_begin_src &= TRIG_EXT;
751 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
752 err++;
753
754 tmp = cmd->convert_src;
755 cmd->convert_src &= TRIG_NOW;
756 if (!cmd->convert_src || tmp != cmd->convert_src)
757 err++;
758
759 tmp = cmd->scan_end_src;
760 cmd->scan_end_src &= TRIG_COUNT;
761 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
762 err++;
763
764 tmp = cmd->stop_src;
765 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
766 if (!cmd->stop_src || tmp != cmd->stop_src)
767 err++;
768
769 if (err)
770 return 1;
771
772 /* step 2: make sure trigger sources are unique and mutually compatible */
773
c52c19c3 774 /* uniqueness check */
f26c569b
FMH		 775 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
776 err++;
777
778 if (err)
779 return 2;
780
781 /* step 3: make sure arguments are trivially compatible */
782
783 if (!cmd->chanlist_len) {
784 cmd->chanlist_len = 32;
785 err++;
786 }
787 if (cmd->scan_end_arg != cmd->chanlist_len) {
788 cmd->scan_end_arg = cmd->chanlist_len;
789 err++;
790 }
791
792 switch (cmd->stop_src) {
793 case TRIG_COUNT:
794 if (!cmd->stop_arg) {
795 cmd->stop_arg = 1;
796 err++;
797 }
798 break;
799 case TRIG_NONE:
800 if (cmd->stop_arg != 0) {
801 cmd->stop_arg = 0;
802 err++;
803 }
804 break;
805 default:
806 break;
807 }
808
809 if (err)
810 return 3;
811
812 /* step 4: fix up any arguments */
813
814 if (err)
815 return 4;
816
95a2572f
DH		 817 if (!cmd->chanlist)
818 return 0;
819
820 for (i = 1; i < cmd->chanlist_len; i++) {
821 if (CR_CHAN(cmd->chanlist[i]) != i) {
822 /* XXX could support 8 or 16 channels */
823 comedi_error(dev,
824 "chanlist must be ch 0 to 31 in order");
825 err++;
826 break;
f26c569b
FMH		 827 }
828 }
829
830 if (err)
831 return 5;
832
833 return 0;
834}
835
da91b269 836static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 837 struct comedi_cmd *cmd)
f26c569b 838{
95a2572f 839 if (priv(dev)->dio_config_output)
f26c569b 840 return -EINVAL;
95a2572f 841 else
f26c569b
FMH		 842 return di_cmd_test(dev, s, cmd);
843}
844
da91b269 845static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
0a85b6f0 846 unsigned int offset)
f26c569b
FMH		 847{
848 writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
0a85b6f0 849 priv(dev)->hpdi_iobase + offset);
f26c569b
FMH		 850}
851
da91b269 852static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
f26c569b
FMH		 853{
854 uint32_t bits;
855 unsigned long flags;
d163679c 856 struct comedi_async *async = s->async;
ea6d0d4c 857 struct comedi_cmd *cmd = &async->cmd;
f26c569b
FMH		 858
859 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
860
861 DEBUG_PRINT("hpdi: in di_cmd\n");
862
863 abort_dma(dev, 0);
864
865 priv(dev)->dma_desc_index = 0;
866
867 /* These register are supposedly unused during chained dma,
868 * but I have found that left over values from last operation
869 * occasionally cause problems with transfer of first dma
870 * block. Initializing them to zero seems to fix the problem. */
871 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
872 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
873 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
c52c19c3 874 /* give location of first dma descriptor */
0a85b6f0
MT		 875 bits =
876 priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
877 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
f26c569b
FMH		 878 writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
879
c52c19c3 880 /* spinlock for plx dma control/status reg */
5f74ea14 881 spin_lock_irqsave(&dev->spinlock, flags);
c52c19c3 882 /* enable dma transfer */
f26c569b 883 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
0a85b6f0 884 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
5f74ea14 885 spin_unlock_irqrestore(&dev->spinlock, flags);
f26c569b
FMH		 886
887 if (cmd->stop_src == TRIG_COUNT)
888 priv(dev)->dio_count = cmd->stop_arg;
889 else
890 priv(dev)->dio_count = 1;
891
c52c19c3 892 /* clear over/under run status flags */
f26c569b 893 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
0a85b6f0 894 priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
c52c19c3 895 /* enable interrupts */
f26c569b 896 writel(intr_bit(RX_FULL_INTR),
0a85b6f0 897 priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
f26c569b
FMH		 898
899 DEBUG_PRINT("hpdi: starting rx\n");
900 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
901
902 return 0;
903}
904
da91b269 905static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
f26c569b 906{
95a2572f 907 if (priv(dev)->dio_config_output)
f26c569b 908 return -EINVAL;
95a2572f 909 else
f26c569b
FMH		 910 return di_cmd(dev, s);
911}
912
da91b269 913static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
f26c569b 914{
d163679c 915 struct comedi_async *async = dev->read_subdev->async;
f26c569b
FMH		 916 uint32_t next_transfer_addr;
917 int j;
918 int num_samples = 0;
919 void *pci_addr_reg;
920
921 if (channel)
922 pci_addr_reg =
0a85b6f0 923 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
f26c569b
FMH		 924 else
925 pci_addr_reg =
0a85b6f0 926 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
f26c569b 927
c52c19c3 928 /* loop until we have read all the full buffers */
f26c569b
FMH		 929 j = 0;
930 for (next_transfer_addr = readl(pci_addr_reg);
0a85b6f0
MT		 931 (next_transfer_addr <
932 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
933 pci_start_addr)
934 || next_transfer_addr >=
935 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
936 pci_start_addr) + priv(dev)->block_size)
937 && j < priv(dev)->num_dma_descriptors; j++) {
c52c19c3 938 /* transfer data from dma buffer to comedi buffer */
f26c569b
FMH		 939 num_samples = priv(dev)->block_size / sizeof(uint32_t);
940 if (async->cmd.stop_src == TRIG_COUNT) {
941 if (num_samples > priv(dev)->dio_count)
942 num_samples = priv(dev)->dio_count;
943 priv(dev)->dio_count -= num_samples;
944 }
945 cfc_write_array_to_buffer(dev->read_subdev,
0a85b6f0
MT		 946 priv(dev)->desc_dio_buffer[priv(dev)->
947 dma_desc_index],
948 num_samples * sizeof(uint32_t));
f26c569b
FMH		 949 priv(dev)->dma_desc_index++;
950 priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
951
952 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
0a85b6f0
MT		 953 priv(dev)->dma_desc[priv(dev)->dma_desc_index].
954 next);
f26c569b
FMH		 955 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
956 }
c52c19c3 957 /* XXX check for buffer overrun somehow */
f26c569b
FMH		 958}
959
70265d24 960static irqreturn_t handle_interrupt(int irq, void *d)
f26c569b 961{
71b5f4f1 962 struct comedi_device *dev = d;
34c43922 963 struct comedi_subdevice *s = dev->read_subdev;
d163679c 964 struct comedi_async *async = s->async;
f26c569b
FMH		 965 uint32_t hpdi_intr_status, hpdi_board_status;
966 uint32_t plx_status;
967 uint32_t plx_bits;
968 uint8_t dma0_status, dma1_status;
969 unsigned long flags;
970
95a2572f 971 if (!dev->attached)
f26c569b 972 return IRQ_NONE;
f26c569b
FMH		 973
974 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
95a2572f 975 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
f26c569b 976 return IRQ_NONE;
f26c569b
FMH		 977
978 hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
979 hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
980
981 async->events = 0;
982
983 if (hpdi_intr_status) {
984 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
985 writel(hpdi_intr_status,
0a85b6f0 986 priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
f26c569b 987 }
c52c19c3 988 /* spin lock makes sure noone else changes plx dma control reg */
5f74ea14 989 spin_lock_irqsave(&dev->spinlock, flags);
f26c569b 990 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
c52c19c3 991 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
f26c569b 992 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
0a85b6f0 993 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
f26c569b
FMH		 994
995 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
95a2572f 996 if (dma0_status & PLX_DMA_EN_BIT)
f26c569b 997 drain_dma_buffers(dev, 0);
f26c569b
FMH		 998 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
999 }
5f74ea14 1000 spin_unlock_irqrestore(&dev->spinlock, flags);
f26c569b 1001
c52c19c3 1002 /* spin lock makes sure noone else changes plx dma control reg */
5f74ea14 1003 spin_lock_irqsave(&dev->spinlock, flags);
f26c569b 1004 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
0a85b6f0 1005 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
f26c569b 1006 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
0a85b6f0 1007 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
f26c569b
FMH		 1008 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
1009
1010 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
1011 }
5f74ea14 1012 spin_unlock_irqrestore(&dev->spinlock, flags);
f26c569b 1013
c52c19c3
BP		 1014 /* clear possible plx9080 interrupt sources */
1015 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
f26c569b
FMH		 1016 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1017 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1018 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
1019 }
1020
1021 if (hpdi_board_status & RX_OVERRUN_BIT) {
1022 comedi_error(dev, "rx fifo overrun");
1023 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1024 DEBUG_PRINT("dma0_status 0x%x\n",
0a85b6f0
MT		 1025 (int)readb(priv(dev)->plx9080_iobase +
1026 PLX_DMA0_CS_REG));
f26c569b
FMH		 1027 }
1028
1029 if (hpdi_board_status & RX_UNDERRUN_BIT) {
1030 comedi_error(dev, "rx fifo underrun");
1031 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1032 }
1033
1034 if (priv(dev)->dio_count == 0)
1035 async->events |= COMEDI_CB_EOA;
1036
1037 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
1038 DEBUG_PRINT("plx status 0x%x\n", plx_status);
1039 if (async->events)
1040 DEBUG_PRINT(" events 0x%x\n", async->events);
1041
1042 cfc_handle_events(dev, s);
1043
1044 return IRQ_HANDLED;
1045}
1046
64ca6a7e 1047static void abort_dma(struct comedi_device *dev, unsigned int channel)
f26c569b
FMH		 1048{
1049 unsigned long flags;
1050
c52c19c3 1051 /* spinlock for plx dma control/status reg */
5f74ea14 1052 spin_lock_irqsave(&dev->spinlock, flags);
f26c569b
FMH		 1053
1054 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
1055
5f74ea14 1056 spin_unlock_irqrestore(&dev->spinlock, flags);
f26c569b
FMH		 1057}
1058
da91b269 1059static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
f26c569b
FMH		 1060{
1061 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
1062
1063 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
1064
1065 abort_dma(dev, 0);
1066
1067 return 0;
1068}
Linux 6.x block layer and io_uring tree(s)