Commit | Line | Data |
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f26c569b FMH |
1 | /* |
2 | comedi/drivers/gsc_hpdi.c | |
3 | This is a driver for the General Standards Corporation High | |
4 | Speed Parallel Digital Interface rs485 boards. | |
5 | ||
6 | Author: Frank Mori Hess <fmhess@users.sourceforge.net> | |
7 | Copyright (C) 2003 Coherent Imaging Systems | |
8 | ||
9 | COMEDI - Linux Control and Measurement Device Interface | |
10 | Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> | |
11 | ||
12 | This program is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
16 | ||
17 | This program is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | ||
26 | ************************************************************************/ | |
27 | ||
28 | /* | |
29 | ||
30 | Driver: gsc_hpdi | |
31 | Description: General Standards Corporation High | |
32 | Speed Parallel Digital Interface rs485 boards | |
33 | Author: Frank Mori Hess <fmhess@users.sourceforge.net> | |
34 | Status: only receive mode works, transmit not supported | |
35 | Updated: 2003-02-20 | |
36 | Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi), | |
37 | PMC-HPDI32 | |
38 | ||
39 | Configuration options: | |
40 | [0] - PCI bus of device (optional) | |
41 | [1] - PCI slot of device (optional) | |
42 | ||
43 | There are some additional hpdi models available from GSC for which | |
44 | support could be added to this driver. | |
45 | ||
46 | */ | |
47 | ||
25436dc9 | 48 | #include <linux/interrupt.h> |
f26c569b FMH |
49 | #include "../comedidev.h" |
50 | #include <linux/delay.h> | |
51 | ||
52 | #include "comedi_pci.h" | |
53 | #include "plx9080.h" | |
54 | #include "comedi_fc.h" | |
55 | ||
814900c9 BP |
56 | static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it); |
57 | static int hpdi_detach(struct comedi_device *dev); | |
64ca6a7e | 58 | static void abort_dma(struct comedi_device *dev, unsigned int channel); |
814900c9 BP |
59 | static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s); |
60 | static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s, | |
0a85b6f0 | 61 | struct comedi_cmd *cmd); |
814900c9 | 62 | static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s); |
70265d24 | 63 | static irqreturn_t handle_interrupt(int irq, void *d); |
814900c9 | 64 | static int dio_config_block_size(struct comedi_device *dev, unsigned int *data); |
f26c569b | 65 | |
c52c19c3 BP |
66 | #undef HPDI_DEBUG /* disable debugging messages */ |
67 | /* #define HPDI_DEBUG enable debugging code */ | |
f26c569b FMH |
68 | |
69 | #ifdef HPDI_DEBUG | |
5f74ea14 | 70 | #define DEBUG_PRINT(format, args...) printk(format , ## args) |
f26c569b FMH |
71 | #else |
72 | #define DEBUG_PRINT(format, args...) | |
73 | #endif | |
74 | ||
c52c19c3 | 75 | #define TIMER_BASE 50 /* 20MHz master clock */ |
f26c569b FMH |
76 | #define DMA_BUFFER_SIZE 0x10000 |
77 | #define NUM_DMA_BUFFERS 4 | |
78 | #define NUM_DMA_DESCRIPTORS 256 | |
79 | ||
c52c19c3 | 80 | /* indices of base address regions */ |
f26c569b FMH |
81 | enum base_address_regions { |
82 | PLX9080_BADDRINDEX = 0, | |
83 | HPDI_BADDRINDEX = 2, | |
84 | }; | |
85 | ||
86 | enum hpdi_registers { | |
87 | FIRMWARE_REV_REG = 0x0, | |
88 | BOARD_CONTROL_REG = 0x4, | |
89 | BOARD_STATUS_REG = 0x8, | |
90 | TX_PROG_ALMOST_REG = 0xc, | |
91 | RX_PROG_ALMOST_REG = 0x10, | |
92 | FEATURES_REG = 0x14, | |
93 | FIFO_REG = 0x18, | |
94 | TX_STATUS_COUNT_REG = 0x1c, | |
95 | TX_LINE_VALID_COUNT_REG = 0x20, | |
96 | TX_LINE_INVALID_COUNT_REG = 0x24, | |
97 | RX_STATUS_COUNT_REG = 0x28, | |
98 | RX_LINE_COUNT_REG = 0x2c, | |
99 | INTERRUPT_CONTROL_REG = 0x30, | |
100 | INTERRUPT_STATUS_REG = 0x34, | |
101 | TX_CLOCK_DIVIDER_REG = 0x38, | |
102 | TX_FIFO_SIZE_REG = 0x40, | |
103 | RX_FIFO_SIZE_REG = 0x44, | |
104 | TX_FIFO_WORDS_REG = 0x48, | |
105 | RX_FIFO_WORDS_REG = 0x4c, | |
106 | INTERRUPT_EDGE_LEVEL_REG = 0x50, | |
107 | INTERRUPT_POLARITY_REG = 0x54, | |
108 | }; | |
109 | ||
110 | int command_channel_valid(unsigned int channel) | |
111 | { | |
112 | if (channel == 0 || channel > 6) { | |
92e462c3 DH |
113 | printk(KERN_WARNING |
114 | "gsc_hpdi: bug! invalid cable command channel\n"); | |
f26c569b FMH |
115 | return 0; |
116 | } | |
117 | return 1; | |
118 | } | |
119 | ||
c52c19c3 | 120 | /* bit definitions */ |
f26c569b FMH |
121 | |
122 | enum firmware_revision_bits { | |
123 | FEATURES_REG_PRESENT_BIT = 0x8000, | |
124 | }; | |
125 | int firmware_revision(uint32_t fwr_bits) | |
126 | { | |
127 | return fwr_bits & 0xff; | |
128 | } | |
129 | ||
130 | int pcb_revision(uint32_t fwr_bits) | |
131 | { | |
132 | return (fwr_bits >> 8) & 0xff; | |
133 | } | |
134 | ||
135 | int hpdi_subid(uint32_t fwr_bits) | |
136 | { | |
137 | return (fwr_bits >> 16) & 0xff; | |
138 | } | |
139 | ||
140 | enum board_control_bits { | |
141 | BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */ | |
142 | TX_FIFO_RESET_BIT = 0x2, | |
143 | RX_FIFO_RESET_BIT = 0x4, | |
144 | TX_ENABLE_BIT = 0x10, | |
145 | RX_ENABLE_BIT = 0x20, | |
95a2572f DH |
146 | DEMAND_DMA_DIRECTION_TX_BIT = 0x40, |
147 | /* for ch 0, ch 1 can only transmit (when present) */ | |
f26c569b FMH |
148 | LINE_VALID_ON_STATUS_VALID_BIT = 0x80, |
149 | START_TX_BIT = 0x10, | |
150 | CABLE_THROTTLE_ENABLE_BIT = 0x20, | |
151 | TEST_MODE_ENABLE_BIT = 0x80000000, | |
152 | }; | |
153 | uint32_t command_discrete_output_bits(unsigned int channel, int output, | |
0a85b6f0 | 154 | int output_value) |
f26c569b FMH |
155 | { |
156 | uint32_t bits = 0; | |
157 | ||
158 | if (command_channel_valid(channel) == 0) | |
159 | return 0; | |
160 | if (output) { | |
161 | bits |= 0x1 << (16 + channel); | |
162 | if (output_value) | |
163 | bits |= 0x1 << (24 + channel); | |
164 | } else | |
165 | bits |= 0x1 << (24 + channel); | |
166 | ||
167 | return bits; | |
168 | } | |
169 | ||
170 | enum board_status_bits { | |
171 | COMMAND_LINE_STATUS_MASK = 0x7f, | |
172 | TX_IN_PROGRESS_BIT = 0x80, | |
173 | TX_NOT_EMPTY_BIT = 0x100, | |
174 | TX_NOT_ALMOST_EMPTY_BIT = 0x200, | |
175 | TX_NOT_ALMOST_FULL_BIT = 0x400, | |
176 | TX_NOT_FULL_BIT = 0x800, | |
177 | RX_NOT_EMPTY_BIT = 0x1000, | |
178 | RX_NOT_ALMOST_EMPTY_BIT = 0x2000, | |
179 | RX_NOT_ALMOST_FULL_BIT = 0x4000, | |
180 | RX_NOT_FULL_BIT = 0x8000, | |
181 | BOARD_JUMPER0_INSTALLED_BIT = 0x10000, | |
182 | BOARD_JUMPER1_INSTALLED_BIT = 0x20000, | |
183 | TX_OVERRUN_BIT = 0x200000, | |
184 | RX_UNDERRUN_BIT = 0x400000, | |
185 | RX_OVERRUN_BIT = 0x800000, | |
186 | }; | |
187 | ||
188 | uint32_t almost_full_bits(unsigned int num_words) | |
189 | { | |
c52c19c3 | 190 | /* XXX need to add or subtract one? */ |
f26c569b FMH |
191 | return (num_words << 16) & 0xff0000; |
192 | } | |
193 | ||
194 | uint32_t almost_empty_bits(unsigned int num_words) | |
195 | { | |
196 | return num_words & 0xffff; | |
197 | } | |
0a85b6f0 | 198 | |
f26c569b FMH |
199 | unsigned int almost_full_num_words(uint32_t bits) |
200 | { | |
c52c19c3 | 201 | /* XXX need to add or subtract one? */ |
f26c569b FMH |
202 | return (bits >> 16) & 0xffff; |
203 | } | |
0a85b6f0 | 204 | |
f26c569b FMH |
205 | unsigned int almost_empty_num_words(uint32_t bits) |
206 | { | |
207 | return bits & 0xffff; | |
208 | } | |
209 | ||
210 | enum features_bits { | |
211 | FIFO_SIZE_PRESENT_BIT = 0x1, | |
212 | FIFO_WORDS_PRESENT_BIT = 0x2, | |
213 | LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4, | |
214 | GPIO_SUPPORTED_BIT = 0x8, | |
215 | PLX_DMA_CH1_SUPPORTED_BIT = 0x10, | |
216 | OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20, | |
217 | }; | |
218 | ||
219 | enum interrupt_sources { | |
220 | FRAME_VALID_START_INTR = 0, | |
221 | FRAME_VALID_END_INTR = 1, | |
222 | TX_FIFO_EMPTY_INTR = 8, | |
223 | TX_FIFO_ALMOST_EMPTY_INTR = 9, | |
224 | TX_FIFO_ALMOST_FULL_INTR = 10, | |
225 | TX_FIFO_FULL_INTR = 11, | |
226 | RX_EMPTY_INTR = 12, | |
227 | RX_ALMOST_EMPTY_INTR = 13, | |
228 | RX_ALMOST_FULL_INTR = 14, | |
229 | RX_FULL_INTR = 15, | |
230 | }; | |
231 | int command_intr_source(unsigned int channel) | |
232 | { | |
233 | if (command_channel_valid(channel) == 0) | |
234 | channel = 1; | |
235 | return channel + 1; | |
236 | } | |
237 | ||
238 | uint32_t intr_bit(int interrupt_source) | |
239 | { | |
240 | return 0x1 << interrupt_source; | |
241 | } | |
242 | ||
243 | uint32_t tx_clock_divisor_bits(unsigned int divisor) | |
244 | { | |
245 | return divisor & 0xff; | |
246 | } | |
247 | ||
248 | unsigned int fifo_size(uint32_t fifo_size_bits) | |
249 | { | |
250 | return fifo_size_bits & 0xfffff; | |
251 | } | |
252 | ||
253 | unsigned int fifo_words(uint32_t fifo_words_bits) | |
254 | { | |
255 | return fifo_words_bits & 0xfffff; | |
256 | } | |
257 | ||
258 | uint32_t intr_edge_bit(int interrupt_source) | |
259 | { | |
260 | return 0x1 << interrupt_source; | |
261 | } | |
262 | ||
263 | uint32_t intr_active_high_bit(int interrupt_source) | |
264 | { | |
265 | return 0x1 << interrupt_source; | |
266 | } | |
267 | ||
52b3e348 BP |
268 | struct hpdi_board { |
269 | ||
f26c569b | 270 | char *name; |
c52c19c3 BP |
271 | int device_id; /* pci device id */ |
272 | int subdevice_id; /* pci subdevice id */ | |
52b3e348 BP |
273 | }; |
274 | ||
52b3e348 | 275 | static const struct hpdi_board hpdi_boards[] = { |
f26c569b | 276 | { |
0a85b6f0 MT |
277 | .name = "pci-hpdi32", |
278 | .device_id = PCI_DEVICE_ID_PLX_9080, | |
279 | .subdevice_id = 0x2400, | |
280 | }, | |
f26c569b FMH |
281 | #if 0 |
282 | { | |
0a85b6f0 MT |
283 | .name = "pxi-hpdi32", |
284 | .device_id = 0x9656, | |
285 | .subdevice_id = 0x2705, | |
286 | }, | |
f26c569b FMH |
287 | #endif |
288 | }; | |
289 | ||
f26c569b | 290 | static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = { |
0a85b6f0 MT |
291 | { |
292 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX, | |
293 | 0x2400, 0, 0, 0}, { | |
294 | 0} | |
f26c569b FMH |
295 | }; |
296 | ||
297 | MODULE_DEVICE_TABLE(pci, hpdi_pci_table); | |
298 | ||
0a85b6f0 | 299 | static inline struct hpdi_board *board(const struct comedi_device *dev) |
f26c569b | 300 | { |
0a85b6f0 | 301 | return (struct hpdi_board *)dev->board_ptr; |
f26c569b FMH |
302 | } |
303 | ||
352dec62 BP |
304 | struct hpdi_private { |
305 | ||
c52c19c3 BP |
306 | struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */ |
307 | /* base addresses (physical) */ | |
f26c569b FMH |
308 | resource_size_t plx9080_phys_iobase; |
309 | resource_size_t hpdi_phys_iobase; | |
c52c19c3 | 310 | /* base addresses (ioremapped) */ |
f26c569b FMH |
311 | void *plx9080_iobase; |
312 | void *hpdi_iobase; | |
c52c19c3 | 313 | uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */ |
4c67da06 MR |
314 | /* physical addresses of dma buffers */ |
315 | dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS]; | |
316 | /* array of dma descriptors read by plx9080, allocated to get proper | |
317 | * alignment */ | |
318 | struct plx_dma_desc *dma_desc; | |
319 | /* physical address of dma descriptor array */ | |
320 | dma_addr_t dma_desc_phys_addr; | |
f26c569b | 321 | unsigned int num_dma_descriptors; |
4c67da06 MR |
322 | /* pointer to start of buffers indexed by descriptor */ |
323 | uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS]; | |
324 | /* index of the dma descriptor that is currently being used */ | |
325 | volatile unsigned int dma_desc_index; | |
f26c569b FMH |
326 | unsigned int tx_fifo_size; |
327 | unsigned int rx_fifo_size; | |
328 | volatile unsigned long dio_count; | |
4c67da06 MR |
329 | /* software copies of values written to hpdi registers */ |
330 | volatile uint32_t bits[24]; | |
331 | /* number of bytes at which to generate COMEDI_CB_BLOCK events */ | |
332 | volatile unsigned int block_size; | |
f26c569b | 333 | unsigned dio_config_output:1; |
352dec62 BP |
334 | }; |
335 | ||
0a85b6f0 | 336 | static inline struct hpdi_private *priv(struct comedi_device *dev) |
f26c569b FMH |
337 | { |
338 | return dev->private; | |
339 | } | |
340 | ||
139dfbdf | 341 | static struct comedi_driver driver_hpdi = { |
68c3dbff BP |
342 | .driver_name = "gsc_hpdi", |
343 | .module = THIS_MODULE, | |
344 | .attach = hpdi_attach, | |
345 | .detach = hpdi_detach, | |
f26c569b FMH |
346 | }; |
347 | ||
727b286b AT |
348 | static int __devinit driver_hpdi_pci_probe(struct pci_dev *dev, |
349 | const struct pci_device_id *ent) | |
350 | { | |
351 | return comedi_pci_auto_config(dev, driver_hpdi.driver_name); | |
352 | } | |
353 | ||
354 | static void __devexit driver_hpdi_pci_remove(struct pci_dev *dev) | |
355 | { | |
356 | comedi_pci_auto_unconfig(dev); | |
357 | } | |
358 | ||
359 | static struct pci_driver driver_hpdi_pci_driver = { | |
360 | .id_table = hpdi_pci_table, | |
361 | .probe = &driver_hpdi_pci_probe, | |
362 | .remove = __devexit_p(&driver_hpdi_pci_remove) | |
363 | }; | |
364 | ||
365 | static int __init driver_hpdi_init_module(void) | |
366 | { | |
367 | int retval; | |
368 | ||
369 | retval = comedi_driver_register(&driver_hpdi); | |
370 | if (retval < 0) | |
371 | return retval; | |
372 | ||
373 | driver_hpdi_pci_driver.name = (char *)driver_hpdi.driver_name; | |
374 | return pci_register_driver(&driver_hpdi_pci_driver); | |
375 | } | |
376 | ||
377 | static void __exit driver_hpdi_cleanup_module(void) | |
378 | { | |
379 | pci_unregister_driver(&driver_hpdi_pci_driver); | |
380 | comedi_driver_unregister(&driver_hpdi); | |
381 | } | |
382 | ||
383 | module_init(driver_hpdi_init_module); | |
384 | module_exit(driver_hpdi_cleanup_module); | |
f26c569b | 385 | |
0a85b6f0 MT |
386 | static int dio_config_insn(struct comedi_device *dev, |
387 | struct comedi_subdevice *s, struct comedi_insn *insn, | |
388 | unsigned int *data) | |
f26c569b FMH |
389 | { |
390 | switch (data[0]) { | |
391 | case INSN_CONFIG_DIO_OUTPUT: | |
392 | priv(dev)->dio_config_output = 1; | |
393 | return insn->n; | |
394 | break; | |
395 | case INSN_CONFIG_DIO_INPUT: | |
396 | priv(dev)->dio_config_output = 0; | |
397 | return insn->n; | |
398 | break; | |
399 | case INSN_CONFIG_DIO_QUERY: | |
400 | data[1] = | |
0a85b6f0 | 401 | priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT; |
f26c569b FMH |
402 | return insn->n; |
403 | break; | |
404 | case INSN_CONFIG_BLOCK_SIZE: | |
405 | return dio_config_block_size(dev, data); | |
406 | break; | |
407 | default: | |
408 | break; | |
409 | } | |
410 | ||
411 | return -EINVAL; | |
412 | } | |
413 | ||
da91b269 | 414 | static void disable_plx_interrupts(struct comedi_device *dev) |
f26c569b FMH |
415 | { |
416 | writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG); | |
417 | } | |
418 | ||
c52c19c3 | 419 | /* initialize plx9080 chip */ |
da91b269 | 420 | static void init_plx9080(struct comedi_device *dev) |
f26c569b FMH |
421 | { |
422 | uint32_t bits; | |
423 | void *plx_iobase = priv(dev)->plx9080_iobase; | |
424 | ||
c52c19c3 | 425 | /* plx9080 dump */ |
f26c569b | 426 | DEBUG_PRINT(" plx interrupt status 0x%x\n", |
0a85b6f0 | 427 | readl(plx_iobase + PLX_INTRCS_REG)); |
f26c569b FMH |
428 | DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG)); |
429 | DEBUG_PRINT(" plx control reg 0x%x\n", | |
0a85b6f0 | 430 | readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG)); |
f26c569b FMH |
431 | |
432 | DEBUG_PRINT(" plx revision 0x%x\n", | |
0a85b6f0 | 433 | readl(plx_iobase + PLX_REVISION_REG)); |
f26c569b | 434 | DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n", |
0a85b6f0 | 435 | readl(plx_iobase + PLX_DMA0_MODE_REG)); |
f26c569b | 436 | DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n", |
0a85b6f0 | 437 | readl(plx_iobase + PLX_DMA1_MODE_REG)); |
f26c569b | 438 | DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n", |
0a85b6f0 | 439 | readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG)); |
f26c569b | 440 | DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n", |
0a85b6f0 | 441 | readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG)); |
f26c569b | 442 | DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n", |
0a85b6f0 | 443 | readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG)); |
f26c569b | 444 | DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n", |
0a85b6f0 | 445 | readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG)); |
f26c569b | 446 | DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n", |
0a85b6f0 | 447 | readb(plx_iobase + PLX_DMA0_CS_REG)); |
f26c569b | 448 | DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n", |
0a85b6f0 | 449 | readl(plx_iobase + PLX_DMA0_THRESHOLD_REG)); |
f26c569b FMH |
450 | DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG)); |
451 | #ifdef __BIG_ENDIAN | |
452 | bits = BIGEND_DMA0 | BIGEND_DMA1; | |
453 | #else | |
454 | bits = 0; | |
455 | #endif | |
456 | writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG); | |
457 | ||
458 | disable_plx_interrupts(dev); | |
459 | ||
460 | abort_dma(dev, 0); | |
461 | abort_dma(dev, 1); | |
462 | ||
c52c19c3 | 463 | /* configure dma0 mode */ |
f26c569b | 464 | bits = 0; |
c52c19c3 | 465 | /* enable ready input */ |
f26c569b | 466 | bits |= PLX_DMA_EN_READYIN_BIT; |
c52c19c3 | 467 | /* enable dma chaining */ |
f26c569b | 468 | bits |= PLX_EN_CHAIN_BIT; |
95a2572f DH |
469 | /* enable interrupt on dma done |
470 | * (probably don't need this, since chain never finishes) */ | |
f26c569b | 471 | bits |= PLX_EN_DMA_DONE_INTR_BIT; |
95a2572f DH |
472 | /* don't increment local address during transfers |
473 | * (we are transferring from a fixed fifo register) */ | |
f26c569b | 474 | bits |= PLX_LOCAL_ADDR_CONST_BIT; |
c52c19c3 | 475 | /* route dma interrupt to pci bus */ |
f26c569b | 476 | bits |= PLX_DMA_INTR_PCI_BIT; |
c52c19c3 | 477 | /* enable demand mode */ |
f26c569b | 478 | bits |= PLX_DEMAND_MODE_BIT; |
c52c19c3 | 479 | /* enable local burst mode */ |
f26c569b FMH |
480 | bits |= PLX_DMA_LOCAL_BURST_EN_BIT; |
481 | bits |= PLX_LOCAL_BUS_32_WIDE_BITS; | |
482 | writel(bits, plx_iobase + PLX_DMA0_MODE_REG); | |
483 | } | |
484 | ||
485 | /* Allocate and initialize the subdevice structures. | |
486 | */ | |
da91b269 | 487 | static int setup_subdevices(struct comedi_device *dev) |
f26c569b | 488 | { |
34c43922 | 489 | struct comedi_subdevice *s; |
f26c569b FMH |
490 | |
491 | if (alloc_subdevices(dev, 1) < 0) | |
492 | return -ENOMEM; | |
493 | ||
494 | s = dev->subdevices + 0; | |
495 | /* analog input subdevice */ | |
496 | dev->read_subdev = s; | |
497 | /* dev->write_subdev = s; */ | |
498 | s->type = COMEDI_SUBD_DIO; | |
499 | s->subdev_flags = | |
0a85b6f0 | 500 | SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ; |
f26c569b FMH |
501 | s->n_chan = 32; |
502 | s->len_chanlist = 32; | |
503 | s->maxdata = 1; | |
504 | s->range_table = &range_digital; | |
505 | s->insn_config = dio_config_insn; | |
506 | s->do_cmd = hpdi_cmd; | |
507 | s->do_cmdtest = hpdi_cmd_test; | |
508 | s->cancel = hpdi_cancel; | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
da91b269 | 513 | static int init_hpdi(struct comedi_device *dev) |
f26c569b FMH |
514 | { |
515 | uint32_t plx_intcsr_bits; | |
516 | ||
517 | writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG); | |
5f74ea14 | 518 | udelay(10); |
f26c569b FMH |
519 | |
520 | writel(almost_empty_bits(32) | almost_full_bits(32), | |
0a85b6f0 | 521 | priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG); |
f26c569b | 522 | writel(almost_empty_bits(32) | almost_full_bits(32), |
0a85b6f0 | 523 | priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG); |
f26c569b FMH |
524 | |
525 | priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase + | |
0a85b6f0 | 526 | TX_FIFO_SIZE_REG)); |
f26c569b | 527 | priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase + |
0a85b6f0 | 528 | RX_FIFO_SIZE_REG)); |
f26c569b FMH |
529 | |
530 | writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG); | |
531 | ||
c52c19c3 | 532 | /* enable interrupts */ |
f26c569b | 533 | plx_intcsr_bits = |
0a85b6f0 MT |
534 | ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE | |
535 | ICS_DMA0_E; | |
f26c569b FMH |
536 | writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG); |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
c52c19c3 | 541 | /* setup dma descriptors so a link completes every 'transfer_size' bytes */ |
da91b269 | 542 | static int setup_dma_descriptors(struct comedi_device *dev, |
0a85b6f0 | 543 | unsigned int transfer_size) |
f26c569b FMH |
544 | { |
545 | unsigned int buffer_index, buffer_offset; | |
546 | uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | | |
0a85b6f0 | 547 | PLX_XFER_LOCAL_TO_PCI; |
f26c569b FMH |
548 | unsigned int i; |
549 | ||
550 | if (transfer_size > DMA_BUFFER_SIZE) | |
551 | transfer_size = DMA_BUFFER_SIZE; | |
552 | transfer_size -= transfer_size % sizeof(uint32_t); | |
553 | if (transfer_size == 0) | |
554 | return -1; | |
555 | ||
556 | DEBUG_PRINT(" transfer_size %i\n", transfer_size); | |
557 | DEBUG_PRINT(" descriptors at 0x%lx\n", | |
0a85b6f0 | 558 | (unsigned long)priv(dev)->dma_desc_phys_addr); |
f26c569b FMH |
559 | |
560 | buffer_offset = 0; | |
561 | buffer_index = 0; | |
562 | for (i = 0; i < NUM_DMA_DESCRIPTORS && | |
0a85b6f0 | 563 | buffer_index < NUM_DMA_BUFFERS; i++) { |
f26c569b | 564 | priv(dev)->dma_desc[i].pci_start_addr = |
0a85b6f0 MT |
565 | cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] + |
566 | buffer_offset); | |
f26c569b FMH |
567 | priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG); |
568 | priv(dev)->dma_desc[i].transfer_size = | |
0a85b6f0 | 569 | cpu_to_le32(transfer_size); |
f26c569b | 570 | priv(dev)->dma_desc[i].next = |
0a85b6f0 MT |
571 | cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i + |
572 | 1) * | |
573 | sizeof(priv(dev)->dma_desc[0])) | next_bits); | |
f26c569b FMH |
574 | |
575 | priv(dev)->desc_dio_buffer[i] = | |
0a85b6f0 MT |
576 | priv(dev)->dio_buffer[buffer_index] + |
577 | (buffer_offset / sizeof(uint32_t)); | |
f26c569b FMH |
578 | |
579 | buffer_offset += transfer_size; | |
580 | if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) { | |
581 | buffer_offset = 0; | |
582 | buffer_index++; | |
583 | } | |
584 | ||
585 | DEBUG_PRINT(" desc %i\n", i); | |
586 | DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n", | |
0a85b6f0 MT |
587 | priv(dev)->desc_dio_buffer[i], |
588 | (unsigned long)priv(dev)->dma_desc[i]. | |
589 | pci_start_addr); | |
f26c569b | 590 | DEBUG_PRINT(" next 0x%lx\n", |
0a85b6f0 | 591 | (unsigned long)priv(dev)->dma_desc[i].next); |
f26c569b FMH |
592 | } |
593 | priv(dev)->num_dma_descriptors = i; | |
c52c19c3 | 594 | /* fix last descriptor to point back to first */ |
f26c569b | 595 | priv(dev)->dma_desc[i - 1].next = |
0a85b6f0 | 596 | cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits); |
f26c569b | 597 | DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1, |
0a85b6f0 | 598 | (unsigned long)priv(dev)->dma_desc[i - 1].next); |
f26c569b FMH |
599 | |
600 | priv(dev)->block_size = transfer_size; | |
601 | ||
602 | return transfer_size; | |
603 | } | |
604 | ||
da91b269 | 605 | static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
f26c569b FMH |
606 | { |
607 | struct pci_dev *pcidev; | |
608 | int i; | |
609 | int retval; | |
610 | ||
92e462c3 | 611 | printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor); |
f26c569b | 612 | |
352dec62 | 613 | if (alloc_private(dev, sizeof(struct hpdi_private)) < 0) |
f26c569b FMH |
614 | return -ENOMEM; |
615 | ||
616 | pcidev = NULL; | |
4c67da06 MR |
617 | for (i = 0; i < ARRAY_SIZE(hpdi_boards) && |
618 | dev->board_ptr == NULL; i++) { | |
f26c569b FMH |
619 | do { |
620 | pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX, | |
0a85b6f0 MT |
621 | hpdi_boards[i].device_id, |
622 | PCI_VENDOR_ID_PLX, | |
623 | hpdi_boards[i].subdevice_id, | |
624 | pcidev); | |
c52c19c3 | 625 | /* was a particular bus/slot requested? */ |
f26c569b | 626 | if (it->options[0] || it->options[1]) { |
c52c19c3 | 627 | /* are we on the wrong bus/slot? */ |
f26c569b | 628 | if (pcidev->bus->number != it->options[0] || |
0a85b6f0 | 629 | PCI_SLOT(pcidev->devfn) != it->options[1]) |
f26c569b FMH |
630 | continue; |
631 | } | |
632 | if (pcidev) { | |
633 | priv(dev)->hw_dev = pcidev; | |
634 | dev->board_ptr = hpdi_boards + i; | |
635 | break; | |
636 | } | |
637 | } while (pcidev != NULL); | |
638 | } | |
639 | if (dev->board_ptr == NULL) { | |
92e462c3 | 640 | printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n"); |
f26c569b FMH |
641 | return -EIO; |
642 | } | |
643 | ||
92e462c3 DH |
644 | printk(KERN_WARNING |
645 | "gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name, | |
0a85b6f0 | 646 | pcidev->bus->number, PCI_SLOT(pcidev->devfn)); |
f26c569b FMH |
647 | |
648 | if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) { | |
649 | printk(KERN_WARNING | |
0a85b6f0 | 650 | " failed enable PCI device and request regions\n"); |
f26c569b FMH |
651 | return -EIO; |
652 | } | |
653 | pci_set_master(pcidev); | |
654 | ||
c52c19c3 | 655 | /* Initialize dev->board_name */ |
f26c569b FMH |
656 | dev->board_name = board(dev)->name; |
657 | ||
658 | priv(dev)->plx9080_phys_iobase = | |
0a85b6f0 | 659 | pci_resource_start(pcidev, PLX9080_BADDRINDEX); |
f26c569b | 660 | priv(dev)->hpdi_phys_iobase = |
0a85b6f0 | 661 | pci_resource_start(pcidev, HPDI_BADDRINDEX); |
f26c569b | 662 | |
c52c19c3 | 663 | /* remap, won't work with 2.0 kernels but who cares */ |
f26c569b | 664 | priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase, |
0a85b6f0 | 665 | pci_resource_len(pcidev, |
4c67da06 | 666 | PLX9080_BADDRINDEX)); |
0a85b6f0 MT |
667 | priv(dev)->hpdi_iobase = |
668 | ioremap(priv(dev)->hpdi_phys_iobase, | |
669 | pci_resource_len(pcidev, HPDI_BADDRINDEX)); | |
f26c569b | 670 | if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) { |
92e462c3 | 671 | printk(KERN_WARNING " failed to remap io memory\n"); |
f26c569b FMH |
672 | return -ENOMEM; |
673 | } | |
674 | ||
675 | DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase); | |
676 | DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase); | |
677 | ||
678 | init_plx9080(dev); | |
679 | ||
c52c19c3 | 680 | /* get irq */ |
5f74ea14 | 681 | if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED, |
f26c569b | 682 | driver_hpdi.driver_name, dev)) { |
92e462c3 DH |
683 | printk(KERN_WARNING |
684 | " unable to allocate irq %u\n", pcidev->irq); | |
f26c569b FMH |
685 | return -EINVAL; |
686 | } | |
687 | dev->irq = pcidev->irq; | |
688 | ||
92e462c3 | 689 | printk(KERN_WARNING " irq %u\n", dev->irq); |
f26c569b | 690 | |
c52c19c3 | 691 | /* alocate pci dma buffers */ |
f26c569b FMH |
692 | for (i = 0; i < NUM_DMA_BUFFERS; i++) { |
693 | priv(dev)->dio_buffer[i] = | |
0a85b6f0 MT |
694 | pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE, |
695 | &priv(dev)->dio_buffer_phys_addr[i]); | |
f26c569b | 696 | DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n", |
0a85b6f0 MT |
697 | priv(dev)->dio_buffer[i], |
698 | (unsigned long)priv(dev)->dio_buffer_phys_addr[i]); | |
f26c569b | 699 | } |
c52c19c3 | 700 | /* allocate dma descriptors */ |
f26c569b | 701 | priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev, |
0a85b6f0 MT |
702 | sizeof(struct plx_dma_desc) * |
703 | NUM_DMA_DESCRIPTORS, | |
704 | &priv(dev)-> | |
705 | dma_desc_phys_addr); | |
f26c569b | 706 | if (priv(dev)->dma_desc_phys_addr & 0xf) { |
92e462c3 DH |
707 | printk(KERN_WARNING |
708 | " dma descriptors not quad-word aligned (bug)\n"); | |
f26c569b FMH |
709 | return -EIO; |
710 | } | |
711 | ||
712 | retval = setup_dma_descriptors(dev, 0x1000); | |
713 | if (retval < 0) | |
714 | return retval; | |
715 | ||
716 | retval = setup_subdevices(dev); | |
717 | if (retval < 0) | |
718 | return retval; | |
719 | ||
720 | return init_hpdi(dev); | |
721 | } | |
722 | ||
da91b269 | 723 | static int hpdi_detach(struct comedi_device *dev) |
f26c569b FMH |
724 | { |
725 | unsigned int i; | |
726 | ||
92e462c3 | 727 | printk(KERN_WARNING "comedi%d: gsc_hpdi: remove\n", dev->minor); |
f26c569b FMH |
728 | |
729 | if (dev->irq) | |
5f74ea14 | 730 | free_irq(dev->irq, dev); |
95a2572f DH |
731 | if ((priv(dev)) && (priv(dev)->hw_dev)) { |
732 | if (priv(dev)->plx9080_iobase) { | |
733 | disable_plx_interrupts(dev); | |
734 | iounmap((void *)priv(dev)->plx9080_iobase); | |
735 | } | |
736 | if (priv(dev)->hpdi_iobase) | |
737 | iounmap((void *)priv(dev)->hpdi_iobase); | |
738 | /* free pci dma buffers */ | |
739 | for (i = 0; i < NUM_DMA_BUFFERS; i++) { | |
740 | if (priv(dev)->dio_buffer[i]) | |
f26c569b | 741 | pci_free_consistent(priv(dev)->hw_dev, |
95a2572f | 742 | DMA_BUFFER_SIZE, |
0a85b6f0 | 743 | priv(dev)-> |
95a2572f DH |
744 | dio_buffer[i], |
745 | priv | |
746 | (dev)->dio_buffer_phys_addr | |
747 | [i]); | |
f26c569b | 748 | } |
95a2572f DH |
749 | /* free dma descriptors */ |
750 | if (priv(dev)->dma_desc) | |
751 | pci_free_consistent(priv(dev)->hw_dev, | |
752 | sizeof(struct plx_dma_desc) | |
753 | * NUM_DMA_DESCRIPTORS, | |
754 | priv(dev)->dma_desc, | |
755 | priv(dev)-> | |
756 | dma_desc_phys_addr); | |
757 | if (priv(dev)->hpdi_phys_iobase) | |
758 | comedi_pci_disable(priv(dev)->hw_dev); | |
759 | pci_dev_put(priv(dev)->hw_dev); | |
f26c569b FMH |
760 | } |
761 | return 0; | |
762 | } | |
763 | ||
da91b269 | 764 | static int dio_config_block_size(struct comedi_device *dev, unsigned int *data) |
f26c569b FMH |
765 | { |
766 | unsigned int requested_block_size; | |
767 | int retval; | |
768 | ||
769 | requested_block_size = data[1]; | |
770 | ||
771 | retval = setup_dma_descriptors(dev, requested_block_size); | |
772 | if (retval < 0) | |
773 | return retval; | |
774 | ||
775 | data[1] = retval; | |
776 | ||
777 | return 2; | |
778 | } | |
779 | ||
da91b269 | 780 | static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 781 | struct comedi_cmd *cmd) |
f26c569b FMH |
782 | { |
783 | int err = 0; | |
784 | int tmp; | |
785 | int i; | |
786 | ||
787 | /* step 1: make sure trigger sources are trivially valid */ | |
788 | ||
789 | tmp = cmd->start_src; | |
790 | cmd->start_src &= TRIG_NOW; | |
791 | if (!cmd->start_src || tmp != cmd->start_src) | |
792 | err++; | |
793 | ||
794 | tmp = cmd->scan_begin_src; | |
795 | cmd->scan_begin_src &= TRIG_EXT; | |
796 | if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) | |
797 | err++; | |
798 | ||
799 | tmp = cmd->convert_src; | |
800 | cmd->convert_src &= TRIG_NOW; | |
801 | if (!cmd->convert_src || tmp != cmd->convert_src) | |
802 | err++; | |
803 | ||
804 | tmp = cmd->scan_end_src; | |
805 | cmd->scan_end_src &= TRIG_COUNT; | |
806 | if (!cmd->scan_end_src || tmp != cmd->scan_end_src) | |
807 | err++; | |
808 | ||
809 | tmp = cmd->stop_src; | |
810 | cmd->stop_src &= TRIG_COUNT | TRIG_NONE; | |
811 | if (!cmd->stop_src || tmp != cmd->stop_src) | |
812 | err++; | |
813 | ||
814 | if (err) | |
815 | return 1; | |
816 | ||
4c67da06 MR |
817 | /* step 2: make sure trigger sources are unique and mutually |
818 | * compatible */ | |
f26c569b | 819 | |
c52c19c3 | 820 | /* uniqueness check */ |
f26c569b FMH |
821 | if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) |
822 | err++; | |
823 | ||
824 | if (err) | |
825 | return 2; | |
826 | ||
827 | /* step 3: make sure arguments are trivially compatible */ | |
828 | ||
829 | if (!cmd->chanlist_len) { | |
830 | cmd->chanlist_len = 32; | |
831 | err++; | |
832 | } | |
833 | if (cmd->scan_end_arg != cmd->chanlist_len) { | |
834 | cmd->scan_end_arg = cmd->chanlist_len; | |
835 | err++; | |
836 | } | |
837 | ||
838 | switch (cmd->stop_src) { | |
839 | case TRIG_COUNT: | |
840 | if (!cmd->stop_arg) { | |
841 | cmd->stop_arg = 1; | |
842 | err++; | |
843 | } | |
844 | break; | |
845 | case TRIG_NONE: | |
846 | if (cmd->stop_arg != 0) { | |
847 | cmd->stop_arg = 0; | |
848 | err++; | |
849 | } | |
850 | break; | |
851 | default: | |
852 | break; | |
853 | } | |
854 | ||
855 | if (err) | |
856 | return 3; | |
857 | ||
858 | /* step 4: fix up any arguments */ | |
859 | ||
860 | if (err) | |
861 | return 4; | |
862 | ||
95a2572f DH |
863 | if (!cmd->chanlist) |
864 | return 0; | |
865 | ||
866 | for (i = 1; i < cmd->chanlist_len; i++) { | |
867 | if (CR_CHAN(cmd->chanlist[i]) != i) { | |
868 | /* XXX could support 8 or 16 channels */ | |
869 | comedi_error(dev, | |
870 | "chanlist must be ch 0 to 31 in order"); | |
871 | err++; | |
872 | break; | |
f26c569b FMH |
873 | } |
874 | } | |
875 | ||
876 | if (err) | |
877 | return 5; | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
da91b269 | 882 | static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 883 | struct comedi_cmd *cmd) |
f26c569b | 884 | { |
95a2572f | 885 | if (priv(dev)->dio_config_output) |
f26c569b | 886 | return -EINVAL; |
95a2572f | 887 | else |
f26c569b FMH |
888 | return di_cmd_test(dev, s, cmd); |
889 | } | |
890 | ||
da91b269 | 891 | static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits, |
0a85b6f0 | 892 | unsigned int offset) |
f26c569b FMH |
893 | { |
894 | writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)], | |
0a85b6f0 | 895 | priv(dev)->hpdi_iobase + offset); |
f26c569b FMH |
896 | } |
897 | ||
da91b269 | 898 | static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
f26c569b FMH |
899 | { |
900 | uint32_t bits; | |
901 | unsigned long flags; | |
d163679c | 902 | struct comedi_async *async = s->async; |
ea6d0d4c | 903 | struct comedi_cmd *cmd = &async->cmd; |
f26c569b FMH |
904 | |
905 | hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG); | |
906 | ||
907 | DEBUG_PRINT("hpdi: in di_cmd\n"); | |
908 | ||
909 | abort_dma(dev, 0); | |
910 | ||
911 | priv(dev)->dma_desc_index = 0; | |
912 | ||
913 | /* These register are supposedly unused during chained dma, | |
914 | * but I have found that left over values from last operation | |
915 | * occasionally cause problems with transfer of first dma | |
916 | * block. Initializing them to zero seems to fix the problem. */ | |
917 | writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG); | |
918 | writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); | |
919 | writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG); | |
c52c19c3 | 920 | /* give location of first dma descriptor */ |
0a85b6f0 MT |
921 | bits = |
922 | priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT | | |
923 | PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI; | |
f26c569b FMH |
924 | writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); |
925 | ||
c52c19c3 | 926 | /* spinlock for plx dma control/status reg */ |
5f74ea14 | 927 | spin_lock_irqsave(&dev->spinlock, flags); |
c52c19c3 | 928 | /* enable dma transfer */ |
f26c569b | 929 | writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT, |
0a85b6f0 | 930 | priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); |
5f74ea14 | 931 | spin_unlock_irqrestore(&dev->spinlock, flags); |
f26c569b FMH |
932 | |
933 | if (cmd->stop_src == TRIG_COUNT) | |
934 | priv(dev)->dio_count = cmd->stop_arg; | |
935 | else | |
936 | priv(dev)->dio_count = 1; | |
937 | ||
c52c19c3 | 938 | /* clear over/under run status flags */ |
f26c569b | 939 | writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, |
0a85b6f0 | 940 | priv(dev)->hpdi_iobase + BOARD_STATUS_REG); |
c52c19c3 | 941 | /* enable interrupts */ |
f26c569b | 942 | writel(intr_bit(RX_FULL_INTR), |
0a85b6f0 | 943 | priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG); |
f26c569b FMH |
944 | |
945 | DEBUG_PRINT("hpdi: starting rx\n"); | |
946 | hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG); | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
da91b269 | 951 | static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
f26c569b | 952 | { |
95a2572f | 953 | if (priv(dev)->dio_config_output) |
f26c569b | 954 | return -EINVAL; |
95a2572f | 955 | else |
f26c569b FMH |
956 | return di_cmd(dev, s); |
957 | } | |
958 | ||
da91b269 | 959 | static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) |
f26c569b | 960 | { |
d163679c | 961 | struct comedi_async *async = dev->read_subdev->async; |
f26c569b FMH |
962 | uint32_t next_transfer_addr; |
963 | int j; | |
964 | int num_samples = 0; | |
965 | void *pci_addr_reg; | |
966 | ||
967 | if (channel) | |
968 | pci_addr_reg = | |
0a85b6f0 | 969 | priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG; |
f26c569b FMH |
970 | else |
971 | pci_addr_reg = | |
0a85b6f0 | 972 | priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; |
f26c569b | 973 | |
c52c19c3 | 974 | /* loop until we have read all the full buffers */ |
f26c569b FMH |
975 | j = 0; |
976 | for (next_transfer_addr = readl(pci_addr_reg); | |
0a85b6f0 MT |
977 | (next_transfer_addr < |
978 | le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index]. | |
979 | pci_start_addr) | |
980 | || next_transfer_addr >= | |
981 | le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index]. | |
982 | pci_start_addr) + priv(dev)->block_size) | |
983 | && j < priv(dev)->num_dma_descriptors; j++) { | |
c52c19c3 | 984 | /* transfer data from dma buffer to comedi buffer */ |
f26c569b FMH |
985 | num_samples = priv(dev)->block_size / sizeof(uint32_t); |
986 | if (async->cmd.stop_src == TRIG_COUNT) { | |
987 | if (num_samples > priv(dev)->dio_count) | |
988 | num_samples = priv(dev)->dio_count; | |
989 | priv(dev)->dio_count -= num_samples; | |
990 | } | |
991 | cfc_write_array_to_buffer(dev->read_subdev, | |
0a85b6f0 MT |
992 | priv(dev)->desc_dio_buffer[priv(dev)-> |
993 | dma_desc_index], | |
994 | num_samples * sizeof(uint32_t)); | |
f26c569b FMH |
995 | priv(dev)->dma_desc_index++; |
996 | priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors; | |
997 | ||
998 | DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long) | |
0a85b6f0 MT |
999 | priv(dev)->dma_desc[priv(dev)->dma_desc_index]. |
1000 | next); | |
f26c569b FMH |
1001 | DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr); |
1002 | } | |
c52c19c3 | 1003 | /* XXX check for buffer overrun somehow */ |
f26c569b FMH |
1004 | } |
1005 | ||
70265d24 | 1006 | static irqreturn_t handle_interrupt(int irq, void *d) |
f26c569b | 1007 | { |
71b5f4f1 | 1008 | struct comedi_device *dev = d; |
34c43922 | 1009 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 1010 | struct comedi_async *async = s->async; |
f26c569b FMH |
1011 | uint32_t hpdi_intr_status, hpdi_board_status; |
1012 | uint32_t plx_status; | |
1013 | uint32_t plx_bits; | |
1014 | uint8_t dma0_status, dma1_status; | |
1015 | unsigned long flags; | |
1016 | ||
95a2572f | 1017 | if (!dev->attached) |
f26c569b | 1018 | return IRQ_NONE; |
f26c569b FMH |
1019 | |
1020 | plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG); | |
95a2572f | 1021 | if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0) |
f26c569b | 1022 | return IRQ_NONE; |
f26c569b FMH |
1023 | |
1024 | hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG); | |
1025 | hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG); | |
1026 | ||
1027 | async->events = 0; | |
1028 | ||
1029 | if (hpdi_intr_status) { | |
1030 | DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status); | |
1031 | writel(hpdi_intr_status, | |
0a85b6f0 | 1032 | priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG); |
f26c569b | 1033 | } |
25985edc | 1034 | /* spin lock makes sure no one else changes plx dma control reg */ |
5f74ea14 | 1035 | spin_lock_irqsave(&dev->spinlock, flags); |
f26c569b | 1036 | dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); |
c52c19c3 | 1037 | if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */ |
f26c569b | 1038 | writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, |
0a85b6f0 | 1039 | priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); |
f26c569b FMH |
1040 | |
1041 | DEBUG_PRINT("dma0 status 0x%x\n", dma0_status); | |
95a2572f | 1042 | if (dma0_status & PLX_DMA_EN_BIT) |
f26c569b | 1043 | drain_dma_buffers(dev, 0); |
f26c569b FMH |
1044 | DEBUG_PRINT(" cleared dma ch0 interrupt\n"); |
1045 | } | |
5f74ea14 | 1046 | spin_unlock_irqrestore(&dev->spinlock, flags); |
f26c569b | 1047 | |
25985edc | 1048 | /* spin lock makes sure no one else changes plx dma control reg */ |
5f74ea14 | 1049 | spin_lock_irqsave(&dev->spinlock, flags); |
f26c569b | 1050 | dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); |
0a85b6f0 | 1051 | if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */ |
f26c569b | 1052 | writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, |
0a85b6f0 | 1053 | priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); |
f26c569b FMH |
1054 | DEBUG_PRINT("dma1 status 0x%x\n", dma1_status); |
1055 | ||
1056 | DEBUG_PRINT(" cleared dma ch1 interrupt\n"); | |
1057 | } | |
5f74ea14 | 1058 | spin_unlock_irqrestore(&dev->spinlock, flags); |
f26c569b | 1059 | |
c52c19c3 BP |
1060 | /* clear possible plx9080 interrupt sources */ |
1061 | if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */ | |
f26c569b FMH |
1062 | plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); |
1063 | writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); | |
1064 | DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits); | |
1065 | } | |
1066 | ||
1067 | if (hpdi_board_status & RX_OVERRUN_BIT) { | |
1068 | comedi_error(dev, "rx fifo overrun"); | |
1069 | async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; | |
1070 | DEBUG_PRINT("dma0_status 0x%x\n", | |
0a85b6f0 MT |
1071 | (int)readb(priv(dev)->plx9080_iobase + |
1072 | PLX_DMA0_CS_REG)); | |
f26c569b FMH |
1073 | } |
1074 | ||
1075 | if (hpdi_board_status & RX_UNDERRUN_BIT) { | |
1076 | comedi_error(dev, "rx fifo underrun"); | |
1077 | async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; | |
1078 | } | |
1079 | ||
1080 | if (priv(dev)->dio_count == 0) | |
1081 | async->events |= COMEDI_CB_EOA; | |
1082 | ||
1083 | DEBUG_PRINT("board status 0x%x, ", hpdi_board_status); | |
1084 | DEBUG_PRINT("plx status 0x%x\n", plx_status); | |
1085 | if (async->events) | |
1086 | DEBUG_PRINT(" events 0x%x\n", async->events); | |
1087 | ||
1088 | cfc_handle_events(dev, s); | |
1089 | ||
1090 | return IRQ_HANDLED; | |
1091 | } | |
1092 | ||
64ca6a7e | 1093 | static void abort_dma(struct comedi_device *dev, unsigned int channel) |
f26c569b FMH |
1094 | { |
1095 | unsigned long flags; | |
1096 | ||
c52c19c3 | 1097 | /* spinlock for plx dma control/status reg */ |
5f74ea14 | 1098 | spin_lock_irqsave(&dev->spinlock, flags); |
f26c569b FMH |
1099 | |
1100 | plx9080_abort_dma(priv(dev)->plx9080_iobase, channel); | |
1101 | ||
5f74ea14 | 1102 | spin_unlock_irqrestore(&dev->spinlock, flags); |
f26c569b FMH |
1103 | } |
1104 | ||
da91b269 | 1105 | static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
f26c569b FMH |
1106 | { |
1107 | hpdi_writel(dev, 0, BOARD_CONTROL_REG); | |
1108 | ||
1109 | writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG); | |
1110 | ||
1111 | abort_dma(dev, 0); | |
1112 | ||
1113 | return 0; | |
1114 | } | |
90f703d3 AT |
1115 | |
1116 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
1117 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
1118 | MODULE_LICENSE("GPL"); |