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7ff7e4c2 IA |
1 | /* comedi/drivers/amplc_dio200_pci.c |
2 | ||
3 | Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296. | |
4 | ||
5 | Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/> | |
6 | ||
7 | COMEDI - Linux Control and Measurement Device Interface | |
8 | Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org> | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
7ff7e4c2 IA |
19 | */ |
20 | /* | |
21 | * Driver: amplc_dio200_pci | |
22 | * Description: Amplicon 200 Series PCI Digital I/O | |
23 | * Author: Ian Abbott <abbotti@mev.co.uk> | |
24 | * Devices: [Amplicon] PCI215 (amplc_dio200_pci), PCIe215, PCIe236, | |
25 | * PCI272, PCIe296 | |
26 | * Updated: Mon, 18 Mar 2013 15:03:50 +0000 | |
27 | * Status: works | |
28 | * | |
29 | * Configuration options: | |
30 | * none | |
31 | * | |
32 | * Manual configuration of PCI(e) cards is not supported; they are configured | |
33 | * automatically. | |
34 | * | |
35 | * SUBDEVICES | |
36 | * | |
37 | * PCI215 PCIe215 PCIe236 | |
38 | * ------------- ------------- ------------- | |
39 | * Subdevices 5 8 8 | |
40 | * 0 PPI-X PPI-X PPI-X | |
41 | * 1 PPI-Y UNUSED UNUSED | |
42 | * 2 CTR-Z1 PPI-Y UNUSED | |
43 | * 3 CTR-Z2 UNUSED UNUSED | |
44 | * 4 INTERRUPT CTR-Z1 CTR-Z1 | |
45 | * 5 CTR-Z2 CTR-Z2 | |
46 | * 6 TIMER TIMER | |
47 | * 7 INTERRUPT INTERRUPT | |
48 | * | |
49 | * | |
50 | * PCI272 PCIe296 | |
51 | * ------------- ------------- | |
52 | * Subdevices 4 8 | |
53 | * 0 PPI-X PPI-X1 | |
54 | * 1 PPI-Y PPI-X2 | |
55 | * 2 PPI-Z PPI-Y1 | |
56 | * 3 INTERRUPT PPI-Y2 | |
57 | * 4 CTR-Z1 | |
58 | * 5 CTR-Z2 | |
59 | * 6 TIMER | |
60 | * 7 INTERRUPT | |
61 | * | |
62 | * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels | |
63 | * are configurable as inputs or outputs in four groups: | |
64 | * | |
65 | * Port A - channels 0 to 7 | |
66 | * Port B - channels 8 to 15 | |
67 | * Port CL - channels 16 to 19 | |
68 | * Port CH - channels 20 to 23 | |
69 | * | |
70 | * Only mode 0 of the 8255 chips is supported. | |
71 | * | |
72 | * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each | |
73 | * channel is configured individually with INSN_CONFIG instructions. The | |
74 | * specific type of configuration instruction is specified in data[0]. | |
75 | * Some configuration instructions expect an additional parameter in | |
76 | * data[1]; others return a value in data[1]. The following configuration | |
77 | * instructions are supported: | |
78 | * | |
79 | * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and | |
80 | * BCD/binary setting specified in data[1]. | |
81 | * | |
82 | * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the | |
83 | * counter channel into data[1]. | |
84 | * | |
85 | * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as | |
86 | * specified in data[1] (this is a hardware-specific value). Not | |
87 | * supported on PC214E. For the other boards, valid clock sources are | |
88 | * 0 to 7 as follows: | |
89 | * | |
90 | * 0. CLK n, the counter channel's dedicated CLK input from the SK1 | |
91 | * connector. (N.B. for other values, the counter channel's CLKn | |
92 | * pin on the SK1 connector is an output!) | |
93 | * 1. Internal 10 MHz clock. | |
94 | * 2. Internal 1 MHz clock. | |
95 | * 3. Internal 100 kHz clock. | |
96 | * 4. Internal 10 kHz clock. | |
97 | * 5. Internal 1 kHz clock. | |
98 | * 6. OUT n-1, the output of counter channel n-1 (see note 1 below). | |
99 | * 7. Ext Clock, the counter chip's dedicated Ext Clock input from | |
100 | * the SK1 connector. This pin is shared by all three counter | |
101 | * channels on the chip. | |
102 | * | |
103 | * For the PCIe boards, clock sources in the range 0 to 31 are allowed | |
104 | * and the following additional clock sources are defined: | |
105 | * | |
106 | * 8. HIGH logic level. | |
107 | * 9. LOW logic level. | |
108 | * 10. "Pattern present" signal. | |
109 | * 11. Internal 20 MHz clock. | |
110 | * | |
111 | * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current | |
112 | * clock source in data[1]. For internal clock sources, data[2] is set | |
113 | * to the period in ns. | |
114 | * | |
115 | * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as | |
116 | * specified in data[2] (this is a hardware-specific value). Not | |
117 | * supported on PC214E. For the other boards, valid gate sources are 0 | |
118 | * to 7 as follows: | |
119 | * | |
120 | * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled. | |
121 | * 1. GND (internal 0V d.c.), i.e. gate permanently disabled. | |
122 | * 2. GAT n, the counter channel's dedicated GAT input from the SK1 | |
123 | * connector. (N.B. for other values, the counter channel's GATn | |
124 | * pin on the SK1 connector is an output!) | |
125 | * 3. /OUT n-2, the inverted output of counter channel n-2 (see note | |
126 | * 2 below). | |
127 | * 4. Reserved. | |
128 | * 5. Reserved. | |
129 | * 6. Reserved. | |
130 | * 7. Reserved. | |
131 | * | |
132 | * For the PCIe boards, gate sources in the range 0 to 31 are allowed; | |
133 | * the following additional clock sources and clock sources 6 and 7 are | |
134 | * (re)defined: | |
135 | * | |
136 | * 6. /GAT n, negated version of the counter channel's dedicated | |
137 | * GAT input (negated version of gate source 2). | |
138 | * 7. OUT n-2, the non-inverted output of counter channel n-2 | |
139 | * (negated version of gate source 3). | |
140 | * 8. "Pattern present" signal, HIGH while pattern present. | |
141 | * 9. "Pattern occurred" latched signal, latches HIGH when pattern | |
142 | * occurs. | |
143 | * 10. "Pattern gone away" latched signal, latches LOW when pattern | |
144 | * goes away after it occurred. | |
145 | * 11. Negated "pattern present" signal, LOW while pattern present | |
146 | * (negated version of gate source 8). | |
147 | * 12. Negated "pattern occurred" latched signal, latches LOW when | |
148 | * pattern occurs (negated version of gate source 9). | |
149 | * 13. Negated "pattern gone away" latched signal, latches LOW when | |
150 | * pattern goes away after it occurred (negated version of gate | |
151 | * source 10). | |
152 | * | |
153 | * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate | |
154 | * source in data[2]. | |
155 | * | |
156 | * Clock and gate interconnection notes: | |
157 | * | |
158 | * 1. Clock source OUT n-1 is the output of the preceding channel on the | |
159 | * same counter subdevice if n > 0, or the output of channel 2 on the | |
160 | * preceding counter subdevice (see note 3) if n = 0. | |
161 | * | |
162 | * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the | |
163 | * same counter subdevice if n = 2, or the inverted output of channel n+1 | |
164 | * on the preceding counter subdevice (see note 3) if n < 2. | |
165 | * | |
166 | * 3. The counter subdevices are connected in a ring, so the highest | |
167 | * counter subdevice precedes the lowest. | |
168 | * | |
169 | * The 'TIMER' subdevice is a free-running 32-bit timer subdevice. | |
170 | * | |
171 | * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The | |
172 | * digital inputs come from the interrupt status register. The number of | |
173 | * channels matches the number of interrupt sources. The PC214E does not | |
174 | * have an interrupt status register; see notes on 'INTERRUPT SOURCES' | |
175 | * below. | |
176 | * | |
177 | * INTERRUPT SOURCES | |
178 | * | |
179 | * PCI215 PCIe215 PCIe236 | |
180 | * ------------- ------------- ------------- | |
181 | * Sources 6 6 6 | |
182 | * 0 PPI-X-C0 PPI-X-C0 PPI-X-C0 | |
183 | * 1 PPI-X-C3 PPI-X-C3 PPI-X-C3 | |
184 | * 2 PPI-Y-C0 PPI-Y-C0 unused | |
185 | * 3 PPI-Y-C3 PPI-Y-C3 unused | |
186 | * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1 | |
187 | * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1 | |
188 | * | |
189 | * PCI272 PCIe296 | |
190 | * ------------- ------------- | |
191 | * Sources 6 6 | |
192 | * 0 PPI-X-C0 PPI-X1-C0 | |
193 | * 1 PPI-X-C3 PPI-X1-C3 | |
194 | * 2 PPI-Y-C0 PPI-Y1-C0 | |
195 | * 3 PPI-Y-C3 PPI-Y1-C3 | |
196 | * 4 PPI-Z-C0 CTR-Z1-OUT1 | |
197 | * 5 PPI-Z-C3 CTR-Z2-OUT1 | |
198 | * | |
199 | * When an interrupt source is enabled in the interrupt source enable | |
200 | * register, a rising edge on the source signal latches the corresponding | |
201 | * bit to 1 in the interrupt status register. | |
202 | * | |
203 | * When the interrupt status register value as a whole (actually, just the | |
204 | * 6 least significant bits) goes from zero to non-zero, the board will | |
205 | * generate an interrupt. The interrupt will remain asserted until the | |
206 | * interrupt status register is cleared to zero. To clear a bit to zero in | |
207 | * the interrupt status register, the corresponding interrupt source must | |
208 | * be disabled in the interrupt source enable register (there is no | |
209 | * separate interrupt clear register). | |
210 | * | |
211 | * COMMANDS | |
212 | * | |
213 | * The driver supports a read streaming acquisition command on the | |
214 | * 'INTERRUPT' subdevice. The channel list selects the interrupt sources | |
215 | * to be enabled. All channels will be sampled together (convert_src == | |
216 | * TRIG_NOW). The scan begins a short time after the hardware interrupt | |
217 | * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT, | |
218 | * scan_begin_arg == 0). The value read from the interrupt status register | |
219 | * is packed into a short value, one bit per requested channel, in the | |
220 | * order they appear in the channel list. | |
221 | */ | |
222 | ||
ce157f80 | 223 | #include <linux/module.h> |
7ff7e4c2 IA |
224 | #include <linux/pci.h> |
225 | #include <linux/interrupt.h> | |
7ff7e4c2 IA |
226 | |
227 | #include "../comedidev.h" | |
228 | ||
229 | #include "amplc_dio200.h" | |
230 | ||
7ff7e4c2 IA |
231 | /* |
232 | * Board descriptions. | |
233 | */ | |
234 | ||
235 | enum dio200_pci_model { | |
236 | pci215_model, | |
237 | pci272_model, | |
238 | pcie215_model, | |
239 | pcie236_model, | |
240 | pcie296_model | |
241 | }; | |
242 | ||
243 | static const struct dio200_board dio200_pci_boards[] = { | |
698f57f4 | 244 | [pci215_model] = { |
f6ce0950 HS |
245 | .name = "pci215", |
246 | .mainbar = 2, | |
247 | .n_subdevs = 5, | |
248 | .sdtype = { | |
249 | sd_8255, sd_8255, sd_8254, sd_8254, sd_intr | |
7ff7e4c2 | 250 | }, |
f6ce0950 HS |
251 | .sdinfo = { 0x00, 0x08, 0x10, 0x14, 0x3f }, |
252 | .has_int_sce = true, | |
253 | .has_clk_gat_sce = true, | |
7ff7e4c2 | 254 | }, |
698f57f4 | 255 | [pci272_model] = { |
f6ce0950 HS |
256 | .name = "pci272", |
257 | .mainbar = 2, | |
258 | .n_subdevs = 4, | |
259 | .sdtype = { | |
260 | sd_8255, sd_8255, sd_8255, sd_intr | |
7ff7e4c2 | 261 | }, |
f6ce0950 HS |
262 | .sdinfo = { 0x00, 0x08, 0x10, 0x3f }, |
263 | .has_int_sce = true, | |
7ff7e4c2 | 264 | }, |
698f57f4 | 265 | [pcie215_model] = { |
f6ce0950 HS |
266 | .name = "pcie215", |
267 | .mainbar = 1, | |
f6ce0950 HS |
268 | .n_subdevs = 8, |
269 | .sdtype = { | |
270 | sd_8255, sd_none, sd_8255, sd_none, | |
271 | sd_8254, sd_8254, sd_timer, sd_intr | |
7ff7e4c2 | 272 | }, |
f6ce0950 HS |
273 | .sdinfo = { |
274 | 0x00, 0x00, 0x08, 0x00, 0x10, 0x14, 0x00, 0x3f | |
275 | }, | |
276 | .has_int_sce = true, | |
277 | .has_clk_gat_sce = true, | |
c1b0cccc | 278 | .is_pcie = true, |
7ff7e4c2 | 279 | }, |
698f57f4 | 280 | [pcie236_model] = { |
f6ce0950 HS |
281 | .name = "pcie236", |
282 | .mainbar = 1, | |
f6ce0950 HS |
283 | .n_subdevs = 8, |
284 | .sdtype = { | |
285 | sd_8255, sd_none, sd_none, sd_none, | |
286 | sd_8254, sd_8254, sd_timer, sd_intr | |
287 | }, | |
288 | .sdinfo = { | |
289 | 0x00, 0x00, 0x00, 0x00, 0x10, 0x14, 0x00, 0x3f | |
7ff7e4c2 | 290 | }, |
f6ce0950 HS |
291 | .has_int_sce = true, |
292 | .has_clk_gat_sce = true, | |
c1b0cccc | 293 | .is_pcie = true, |
7ff7e4c2 | 294 | }, |
698f57f4 | 295 | [pcie296_model] = { |
f6ce0950 HS |
296 | .name = "pcie296", |
297 | .mainbar = 1, | |
f6ce0950 HS |
298 | .n_subdevs = 8, |
299 | .sdtype = { | |
300 | sd_8255, sd_8255, sd_8255, sd_8255, | |
301 | sd_8254, sd_8254, sd_timer, sd_intr | |
302 | }, | |
303 | .sdinfo = { | |
304 | 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x00, 0x3f | |
7ff7e4c2 | 305 | }, |
f6ce0950 HS |
306 | .has_int_sce = true, |
307 | .has_clk_gat_sce = true, | |
c1b0cccc | 308 | .is_pcie = true, |
7ff7e4c2 IA |
309 | }, |
310 | }; | |
311 | ||
312 | /* | |
313 | * This function does some special set-up for the PCIe boards | |
314 | * PCIe215, PCIe236, PCIe296. | |
315 | */ | |
316 | static int dio200_pcie_board_setup(struct comedi_device *dev) | |
317 | { | |
318 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); | |
319 | void __iomem *brbase; | |
7ff7e4c2 IA |
320 | |
321 | /* | |
322 | * The board uses Altera Cyclone IV with PCI-Express hard IP. | |
323 | * The FPGA configuration has the PCI-Express Avalon-MM Bridge | |
324 | * Control registers in PCI BAR 0, offset 0, and the length of | |
325 | * these registers is 0x4000. | |
326 | * | |
327 | * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt | |
328 | * Enable" register at offset 0x50 to allow generation of PCIe | |
329 | * interrupts when RXmlrq_i is asserted in the SOPC Builder system. | |
330 | */ | |
c400c1e1 | 331 | if (pci_resource_len(pcidev, 0) < 0x4000) { |
7ff7e4c2 IA |
332 | dev_err(dev->class_dev, "error! bad PCI region!\n"); |
333 | return -EINVAL; | |
334 | } | |
c400c1e1 | 335 | brbase = pci_ioremap_bar(pcidev, 0); |
7ff7e4c2 IA |
336 | if (!brbase) { |
337 | dev_err(dev->class_dev, "error! failed to map registers!\n"); | |
338 | return -ENOMEM; | |
339 | } | |
340 | writel(0x80, brbase + 0x50); | |
341 | iounmap(brbase); | |
342 | /* Enable "enhanced" features of board. */ | |
343 | amplc_dio200_set_enhance(dev, 1); | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static int dio200_pci_auto_attach(struct comedi_device *dev, | |
348 | unsigned long context_model) | |
349 | { | |
350 | struct pci_dev *pci_dev = comedi_to_pci_dev(dev); | |
c1b0cccc | 351 | const struct dio200_board *board = NULL; |
7ff7e4c2 IA |
352 | unsigned int bar; |
353 | int ret; | |
354 | ||
355 | if (context_model < ARRAY_SIZE(dio200_pci_boards)) | |
c1b0cccc HS |
356 | board = &dio200_pci_boards[context_model]; |
357 | if (!board) | |
7ff7e4c2 | 358 | return -EINVAL; |
c1b0cccc HS |
359 | dev->board_ptr = board; |
360 | dev->board_name = board->name; | |
7ff7e4c2 IA |
361 | |
362 | dev_info(dev->class_dev, "%s: attach pci %s (%s)\n", | |
363 | dev->driver->driver_name, pci_name(pci_dev), dev->board_name); | |
364 | ||
7ff7e4c2 IA |
365 | ret = comedi_pci_enable(dev); |
366 | if (ret) | |
367 | return ret; | |
368 | ||
c1b0cccc | 369 | bar = board->mainbar; |
7ff7e4c2 | 370 | if (pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) { |
0c3dfdc2 HS |
371 | dev->mmio = pci_ioremap_bar(pci_dev, bar); |
372 | if (!dev->mmio) { | |
7ff7e4c2 IA |
373 | dev_err(dev->class_dev, |
374 | "error! cannot remap registers\n"); | |
375 | return -ENOMEM; | |
376 | } | |
7ff7e4c2 | 377 | } else { |
0c3dfdc2 | 378 | dev->iobase = pci_resource_start(pci_dev, bar); |
7ff7e4c2 | 379 | } |
c1b0cccc HS |
380 | |
381 | if (board->is_pcie) { | |
7ff7e4c2 IA |
382 | ret = dio200_pcie_board_setup(dev); |
383 | if (ret < 0) | |
384 | return ret; | |
7ff7e4c2 | 385 | } |
c1b0cccc | 386 | |
7ff7e4c2 IA |
387 | return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED); |
388 | } | |
389 | ||
7ff7e4c2 | 390 | static struct comedi_driver dio200_pci_comedi_driver = { |
593d11c5 HS |
391 | .driver_name = "amplc_dio200_pci", |
392 | .module = THIS_MODULE, | |
393 | .auto_attach = dio200_pci_auto_attach, | |
aac307f9 | 394 | .detach = comedi_pci_detach, |
7ff7e4c2 IA |
395 | }; |
396 | ||
41e043fc | 397 | static const struct pci_device_id dio200_pci_table[] = { |
472cd3db HS |
398 | { PCI_VDEVICE(AMPLICON, 0x000b), pci215_model }, |
399 | { PCI_VDEVICE(AMPLICON, 0x000a), pci272_model }, | |
400 | { PCI_VDEVICE(AMPLICON, 0x0011), pcie236_model }, | |
401 | { PCI_VDEVICE(AMPLICON, 0x0012), pcie215_model }, | |
402 | { PCI_VDEVICE(AMPLICON, 0x0014), pcie296_model }, | |
7ff7e4c2 IA |
403 | {0} |
404 | }; | |
405 | ||
406 | MODULE_DEVICE_TABLE(pci, dio200_pci_table); | |
407 | ||
408 | static int dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
409 | { | |
410 | return comedi_pci_auto_config(dev, &dio200_pci_comedi_driver, | |
411 | id->driver_data); | |
412 | } | |
413 | ||
414 | static struct pci_driver dio200_pci_pci_driver = { | |
593d11c5 HS |
415 | .name = "amplc_dio200_pci", |
416 | .id_table = dio200_pci_table, | |
417 | .probe = dio200_pci_probe, | |
418 | .remove = comedi_pci_auto_unconfig, | |
7ff7e4c2 IA |
419 | }; |
420 | module_comedi_pci_driver(dio200_pci_comedi_driver, dio200_pci_pci_driver); | |
421 | ||
422 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
423 | MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series PCI(e) DIO boards"); | |
424 | MODULE_LICENSE("GPL"); |