Commit | Line | Data |
---|---|---|
8cb9b9fb EP |
1 | /* |
2 | ||
842ec6ba | 3 | comedi/drivers/adl_pci9111.c |
8cb9b9fb | 4 | |
842ec6ba | 5 | Hardware driver for PCI9111 ADLink cards: |
8cb9b9fb | 6 | |
842ec6ba | 7 | PCI-9111HR |
8cb9b9fb | 8 | |
842ec6ba | 9 | Copyright (C) 2002-2005 Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr> |
8cb9b9fb | 10 | |
842ec6ba MD |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
8cb9b9fb | 15 | |
842ec6ba MD |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
8cb9b9fb | 20 | |
842ec6ba MD |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
8cb9b9fb EP |
24 | */ |
25 | ||
26 | /* | |
27 | Driver: adl_pci9111 | |
28 | Description: Adlink PCI-9111HR | |
29 | Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr> | |
30 | Devices: [ADLink] PCI-9111HR (adl_pci9111) | |
31 | Status: experimental | |
32 | ||
33 | Supports: | |
34 | ||
842ec6ba MD |
35 | - ai_insn read |
36 | - ao_insn read/write | |
37 | - di_insn read | |
38 | - do_insn read/write | |
39 | - ai_do_cmd mode with the following sources: | |
8cb9b9fb | 40 | |
842ec6ba MD |
41 | - start_src TRIG_NOW |
42 | - scan_begin_src TRIG_FOLLOW TRIG_TIMER TRIG_EXT | |
43 | - convert_src TRIG_TIMER TRIG_EXT | |
44 | - scan_end_src TRIG_COUNT | |
45 | - stop_src TRIG_COUNT TRIG_NONE | |
8cb9b9fb | 46 | |
842ec6ba MD |
47 | The scanned channels must be consecutive and start from 0. They must |
48 | all have the same range and aref. | |
8cb9b9fb | 49 | |
3e5a0ba0 | 50 | Configuration options: not applicable, uses PCI auto config |
8cb9b9fb EP |
51 | */ |
52 | ||
53 | /* | |
54 | CHANGELOG: | |
55 | ||
842ec6ba MD |
56 | 2005/02/17 Extend AI streaming capabilities. Now, scan_begin_arg can be |
57 | a multiple of chanlist_len*convert_arg. | |
58 | 2002/02/19 Fixed the two's complement conversion in pci9111_(hr_)ai_get_data. | |
59 | 2002/02/18 Added external trigger support for analog input. | |
8cb9b9fb EP |
60 | |
61 | TODO: | |
62 | ||
842ec6ba MD |
63 | - Really test implemented functionality. |
64 | - Add support for the PCI-9111DG with a probe routine to identify | |
65 | the card type (perhaps with the help of the channel number readback | |
66 | of the A/D Data register). | |
67 | - Add external multiplexer support. | |
8cb9b9fb EP |
68 | |
69 | */ | |
70 | ||
71 | #include "../comedidev.h" | |
72 | ||
73 | #include <linux/delay.h> | |
70265d24 | 74 | #include <linux/interrupt.h> |
8cb9b9fb EP |
75 | |
76 | #include "8253.h" | |
8cb9b9fb EP |
77 | #include "comedi_fc.h" |
78 | ||
2f6df34c MR |
79 | #define PCI9111_DRIVER_NAME "adl_pci9111" |
80 | #define PCI9111_HR_DEVICE_ID 0x9111 | |
8cb9b9fb | 81 | |
8cb9b9fb EP |
82 | #define PCI9111_FIFO_HALF_SIZE 512 |
83 | ||
8cb9b9fb | 84 | #define PCI9111_AI_ACQUISITION_PERIOD_MIN_NS 10000 |
8cb9b9fb EP |
85 | |
86 | #define PCI9111_RANGE_SETTING_DELAY 10 | |
87 | #define PCI9111_AI_INSTANT_READ_UDELAY_US 2 | |
88 | #define PCI9111_AI_INSTANT_READ_TIMEOUT 100 | |
89 | ||
90 | #define PCI9111_8254_CLOCK_PERIOD_NS 500 | |
91 | ||
8c7524e6 HS |
92 | /* |
93 | * IO address map and bit defines | |
94 | */ | |
95 | #define PCI9111_AI_FIFO_REG 0x00 | |
96 | #define PCI9111_AO_REG 0x00 | |
97 | #define PCI9111_DIO_REG 0x02 | |
98 | #define PCI9111_EDIO_REG 0x04 | |
99 | #define PCI9111_AI_CHANNEL_REG 0x06 | |
100 | #define PCI9111_AI_RANGE_STAT_REG 0x08 | |
101 | #define PCI9111_AI_STAT_AD_BUSY (1 << 7) | |
102 | #define PCI9111_AI_STAT_FF_FF (1 << 6) | |
103 | #define PCI9111_AI_STAT_FF_HF (1 << 5) | |
104 | #define PCI9111_AI_STAT_FF_EF (1 << 4) | |
105 | #define PCI9111_AI_RANGE_MASK (7 << 0) | |
106 | #define PCI9111_AI_TRIG_CTRL_REG 0x0a | |
107 | #define PCI9111_AI_TRIG_CTRL_TRGEVENT (1 << 5) | |
108 | #define PCI9111_AI_TRIG_CTRL_POTRG (1 << 4) | |
109 | #define PCI9111_AI_TRIG_CTRL_PTRG (1 << 3) | |
110 | #define PCI9111_AI_TRIG_CTRL_ETIS (1 << 2) | |
111 | #define PCI9111_AI_TRIG_CTRL_TPST (1 << 1) | |
112 | #define PCI9111_AI_TRIG_CTRL_ASCAN (1 << 0) | |
113 | #define PCI9111_INT_CTRL_REG 0x0c | |
114 | #define PCI9111_INT_CTRL_ISC2 (1 << 3) | |
115 | #define PCI9111_INT_CTRL_FFEN (1 << 2) | |
116 | #define PCI9111_INT_CTRL_ISC1 (1 << 1) | |
117 | #define PCI9111_INT_CTRL_ISC0 (1 << 0) | |
118 | #define PCI9111_SOFT_TRIG_REG 0x0e | |
119 | #define PCI9111_8254_BASE_REG 0x40 | |
120 | #define PCI9111_INT_CLR_REG 0x48 | |
8cb9b9fb | 121 | |
afa6ac4a | 122 | static const struct comedi_lrange pci9111_ai_range = { |
8cb9b9fb EP |
123 | 5, |
124 | { | |
afa6ac4a HS |
125 | BIP_RANGE(10), |
126 | BIP_RANGE(5), | |
127 | BIP_RANGE(2.5), | |
128 | BIP_RANGE(1.25), | |
129 | BIP_RANGE(0.625) | |
130 | } | |
8cb9b9fb EP |
131 | }; |
132 | ||
c350fa19 | 133 | struct pci9111_private_data { |
293b048a | 134 | unsigned long lcr_io_base; |
8cb9b9fb EP |
135 | |
136 | int stop_counter; | |
137 | int stop_is_none; | |
138 | ||
139 | unsigned int scan_delay; | |
140 | unsigned int chanlist_len; | |
141 | unsigned int chunk_counter; | |
142 | unsigned int chunk_num_samples; | |
143 | ||
293b048a | 144 | int ao_readback; |
8cb9b9fb | 145 | |
eba16272 HS |
146 | unsigned int div1; |
147 | unsigned int div2; | |
8cb9b9fb | 148 | |
790c5541 | 149 | short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE]; |
c350fa19 | 150 | }; |
8cb9b9fb | 151 | |
8cb9b9fb EP |
152 | #define PLX9050_REGISTER_INTERRUPT_CONTROL 0x4c |
153 | ||
154 | #define PLX9050_LINTI1_ENABLE (1 << 0) | |
155 | #define PLX9050_LINTI1_ACTIVE_HIGH (1 << 1) | |
156 | #define PLX9050_LINTI1_STATUS (1 << 2) | |
157 | #define PLX9050_LINTI2_ENABLE (1 << 3) | |
158 | #define PLX9050_LINTI2_ACTIVE_HIGH (1 << 4) | |
159 | #define PLX9050_LINTI2_STATUS (1 << 5) | |
160 | #define PLX9050_PCI_INTERRUPT_ENABLE (1 << 6) | |
161 | #define PLX9050_SOFTWARE_INTERRUPT (1 << 7) | |
162 | ||
163 | static void plx9050_interrupt_control(unsigned long io_base, | |
0a85b6f0 MT |
164 | bool LINTi1_enable, |
165 | bool LINTi1_active_high, | |
166 | bool LINTi2_enable, | |
167 | bool LINTi2_active_high, | |
168 | bool interrupt_enable) | |
8cb9b9fb EP |
169 | { |
170 | int flags = 0; | |
171 | ||
172 | if (LINTi1_enable) | |
173 | flags |= PLX9050_LINTI1_ENABLE; | |
174 | if (LINTi1_active_high) | |
175 | flags |= PLX9050_LINTI1_ACTIVE_HIGH; | |
176 | if (LINTi2_enable) | |
177 | flags |= PLX9050_LINTI2_ENABLE; | |
178 | if (LINTi2_active_high) | |
179 | flags |= PLX9050_LINTI2_ACTIVE_HIGH; | |
180 | ||
181 | if (interrupt_enable) | |
182 | flags |= PLX9050_PCI_INTERRUPT_ENABLE; | |
183 | ||
184 | outb(flags, io_base + PLX9050_REGISTER_INTERRUPT_CONTROL); | |
185 | } | |
186 | ||
da91b269 | 187 | static void pci9111_timer_set(struct comedi_device *dev) |
8cb9b9fb | 188 | { |
98943079 | 189 | struct pci9111_private_data *dev_private = dev->private; |
9d093151 | 190 | unsigned long timer_base = dev->iobase + PCI9111_8254_BASE_REG; |
98943079 | 191 | |
9d093151 HS |
192 | i8254_set_mode(timer_base, 1, 0, I8254_MODE0 | I8254_BINARY); |
193 | i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY); | |
194 | i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY); | |
8cb9b9fb | 195 | |
5f74ea14 | 196 | udelay(1); |
8cb9b9fb | 197 | |
eba16272 HS |
198 | i8254_write(timer_base, 1, 2, dev_private->div2); |
199 | i8254_write(timer_base, 1, 1, dev_private->div1); | |
8cb9b9fb EP |
200 | } |
201 | ||
655f78f6 | 202 | enum pci9111_trigger_sources { |
8cb9b9fb EP |
203 | software, |
204 | timer_pacer, | |
205 | external | |
655f78f6 | 206 | }; |
8cb9b9fb | 207 | |
da91b269 | 208 | static void pci9111_trigger_source_set(struct comedi_device *dev, |
0a85b6f0 | 209 | enum pci9111_trigger_sources source) |
8cb9b9fb EP |
210 | { |
211 | int flags; | |
212 | ||
20614d96 | 213 | /* Read the current trigger mode control bits */ |
8c7524e6 | 214 | flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
20614d96 HS |
215 | /* Mask off the EITS and TPST bits */ |
216 | flags &= 0x9; | |
8cb9b9fb EP |
217 | |
218 | switch (source) { | |
219 | case software: | |
8cb9b9fb EP |
220 | break; |
221 | ||
222 | case timer_pacer: | |
8c7524e6 | 223 | flags |= PCI9111_AI_TRIG_CTRL_TPST; |
8cb9b9fb EP |
224 | break; |
225 | ||
226 | case external: | |
8c7524e6 | 227 | flags |= PCI9111_AI_TRIG_CTRL_ETIS; |
8cb9b9fb EP |
228 | break; |
229 | } | |
230 | ||
8c7524e6 | 231 | outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
8cb9b9fb EP |
232 | } |
233 | ||
da91b269 | 234 | static void pci9111_pretrigger_set(struct comedi_device *dev, bool pretrigger) |
8cb9b9fb EP |
235 | { |
236 | int flags; | |
237 | ||
20614d96 | 238 | /* Read the current trigger mode control bits */ |
8c7524e6 | 239 | flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
20614d96 HS |
240 | /* Mask off the PTRG bit */ |
241 | flags &= 0x7; | |
8cb9b9fb EP |
242 | |
243 | if (pretrigger) | |
8c7524e6 | 244 | flags |= PCI9111_AI_TRIG_CTRL_PTRG; |
8cb9b9fb | 245 | |
8c7524e6 | 246 | outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
8cb9b9fb EP |
247 | } |
248 | ||
da91b269 | 249 | static void pci9111_autoscan_set(struct comedi_device *dev, bool autoscan) |
8cb9b9fb EP |
250 | { |
251 | int flags; | |
252 | ||
20614d96 | 253 | /* Read the current trigger mode control bits */ |
8c7524e6 | 254 | flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
20614d96 HS |
255 | /* Mask off the ASCAN bit */ |
256 | flags &= 0xe; | |
8cb9b9fb EP |
257 | |
258 | if (autoscan) | |
8c7524e6 | 259 | flags |= PCI9111_AI_TRIG_CTRL_ASCAN; |
8cb9b9fb | 260 | |
8c7524e6 | 261 | outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
8cb9b9fb EP |
262 | } |
263 | ||
3ba97b3c | 264 | enum pci9111_ISC0_sources { |
8cb9b9fb EP |
265 | irq_on_eoc, |
266 | irq_on_fifo_half_full | |
3ba97b3c | 267 | }; |
8cb9b9fb | 268 | |
52f8ac98 | 269 | enum pci9111_ISC1_sources { |
8cb9b9fb EP |
270 | irq_on_timer_tick, |
271 | irq_on_external_trigger | |
52f8ac98 | 272 | }; |
8cb9b9fb | 273 | |
da91b269 | 274 | static void pci9111_interrupt_source_set(struct comedi_device *dev, |
0a85b6f0 MT |
275 | enum pci9111_ISC0_sources irq_0_source, |
276 | enum pci9111_ISC1_sources irq_1_source) | |
8cb9b9fb EP |
277 | { |
278 | int flags; | |
279 | ||
2959bc21 | 280 | /* Read the current interrupt control bits */ |
8c7524e6 | 281 | flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG); |
2959bc21 HS |
282 | /* Shift the bits so they are compatible with the write register */ |
283 | flags >>= 4; | |
284 | /* Mask off the ISCx bits */ | |
285 | flags &= 0xc0; | |
8cb9b9fb | 286 | |
2959bc21 | 287 | /* Now set the new ISCx bits */ |
8cb9b9fb | 288 | if (irq_0_source == irq_on_fifo_half_full) |
8c7524e6 | 289 | flags |= PCI9111_INT_CTRL_ISC0; |
8cb9b9fb EP |
290 | |
291 | if (irq_1_source == irq_on_external_trigger) | |
8c7524e6 | 292 | flags |= PCI9111_INT_CTRL_ISC1; |
8cb9b9fb | 293 | |
2959bc21 | 294 | outb(flags, dev->iobase + PCI9111_INT_CTRL_REG); |
8cb9b9fb EP |
295 | } |
296 | ||
6b228d8a HS |
297 | static void pci9111_fifo_reset(struct comedi_device *dev) |
298 | { | |
299 | unsigned long int_ctrl_reg = dev->iobase + PCI9111_INT_CTRL_REG; | |
300 | ||
301 | /* To reset the FIFO, set FFEN sequence as 0 -> 1 -> 0 */ | |
8c7524e6 HS |
302 | outb(0, int_ctrl_reg); |
303 | outb(PCI9111_INT_CTRL_FFEN, int_ctrl_reg); | |
304 | outb(0, int_ctrl_reg); | |
6b228d8a HS |
305 | } |
306 | ||
0a85b6f0 MT |
307 | static int pci9111_ai_cancel(struct comedi_device *dev, |
308 | struct comedi_subdevice *s) | |
8cb9b9fb | 309 | { |
98943079 HS |
310 | struct pci9111_private_data *dev_private = dev->private; |
311 | ||
52f8ac98 | 312 | /* Disable interrupts */ |
8cb9b9fb | 313 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true, |
0a85b6f0 | 314 | true, false); |
8cb9b9fb EP |
315 | |
316 | pci9111_trigger_source_set(dev, software); | |
317 | ||
318 | pci9111_autoscan_set(dev, false); | |
319 | ||
6b228d8a | 320 | pci9111_fifo_reset(dev); |
8cb9b9fb | 321 | |
8cb9b9fb EP |
322 | return 0; |
323 | } | |
324 | ||
97e01bb1 HS |
325 | static int pci9111_ai_do_cmd_test(struct comedi_device *dev, |
326 | struct comedi_subdevice *s, | |
327 | struct comedi_cmd *cmd) | |
8cb9b9fb | 328 | { |
98943079 | 329 | struct pci9111_private_data *dev_private = dev->private; |
8cb9b9fb EP |
330 | int tmp; |
331 | int error = 0; | |
332 | int range, reference; | |
333 | int i; | |
8cb9b9fb | 334 | |
27020ffe | 335 | /* Step 1 : check if triggers are trivially valid */ |
8cb9b9fb | 336 | |
97e01bb1 HS |
337 | error |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW); |
338 | error |= cfc_check_trigger_src(&cmd->scan_begin_src, | |
339 | TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); | |
340 | error |= cfc_check_trigger_src(&cmd->convert_src, | |
341 | TRIG_TIMER | TRIG_EXT); | |
342 | error |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
343 | error |= cfc_check_trigger_src(&cmd->stop_src, | |
344 | TRIG_COUNT | TRIG_NONE); | |
8cb9b9fb EP |
345 | |
346 | if (error) | |
347 | return 1; | |
348 | ||
e990333d | 349 | /* Step 2a : make sure trigger sources are unique */ |
8cb9b9fb | 350 | |
e990333d HS |
351 | error |= cfc_check_trigger_is_unique(cmd->scan_begin_src); |
352 | error |= cfc_check_trigger_is_unique(cmd->convert_src); | |
353 | error |= cfc_check_trigger_is_unique(cmd->stop_src); | |
354 | ||
355 | /* Step 2b : and mutually compatible */ | |
8cb9b9fb | 356 | |
8cb9b9fb | 357 | if ((cmd->convert_src == TRIG_TIMER) && |
0a85b6f0 | 358 | !((cmd->scan_begin_src == TRIG_TIMER) || |
2306d9b1 | 359 | (cmd->scan_begin_src == TRIG_FOLLOW))) |
e990333d | 360 | error |= -EINVAL; |
8cb9b9fb | 361 | if ((cmd->convert_src == TRIG_EXT) && |
0a85b6f0 | 362 | !((cmd->scan_begin_src == TRIG_EXT) || |
2306d9b1 | 363 | (cmd->scan_begin_src == TRIG_FOLLOW))) |
e990333d | 364 | error |= -EINVAL; |
8cb9b9fb EP |
365 | |
366 | if (error) | |
367 | return 2; | |
368 | ||
430f87da | 369 | /* Step 3: check if arguments are trivially valid */ |
8cb9b9fb | 370 | |
430f87da | 371 | error |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); |
8cb9b9fb | 372 | |
430f87da HS |
373 | if (cmd->convert_src == TRIG_TIMER) |
374 | error |= cfc_check_trigger_arg_min(&cmd->convert_arg, | |
375 | PCI9111_AI_ACQUISITION_PERIOD_MIN_NS); | |
376 | else /* TRIG_EXT */ | |
377 | error |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); | |
8cb9b9fb | 378 | |
430f87da HS |
379 | if (cmd->scan_begin_src == TRIG_TIMER) |
380 | error |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, | |
381 | PCI9111_AI_ACQUISITION_PERIOD_MIN_NS); | |
382 | else /* TRIG_FOLLOW || TRIG_EXT */ | |
383 | error |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0); | |
8cb9b9fb | 384 | |
430f87da HS |
385 | error |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, |
386 | cmd->chanlist_len); | |
8cb9b9fb | 387 | |
430f87da HS |
388 | if (cmd->stop_src == TRIG_COUNT) |
389 | error |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); | |
390 | else /* TRIG_NONE */ | |
391 | error |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); | |
8cb9b9fb EP |
392 | |
393 | if (error) | |
394 | return 3; | |
395 | ||
52f8ac98 | 396 | /* Step 4 : fix up any arguments */ |
8cb9b9fb EP |
397 | |
398 | if (cmd->convert_src == TRIG_TIMER) { | |
399 | tmp = cmd->convert_arg; | |
400 | i8253_cascade_ns_to_timer_2div(PCI9111_8254_CLOCK_PERIOD_NS, | |
eba16272 HS |
401 | &dev_private->div1, |
402 | &dev_private->div2, | |
499a76dc | 403 | &cmd->convert_arg, |
0a85b6f0 | 404 | cmd->flags & TRIG_ROUND_MASK); |
8cb9b9fb EP |
405 | if (tmp != cmd->convert_arg) |
406 | error++; | |
407 | } | |
52f8ac98 BP |
408 | /* There's only one timer on this card, so the scan_begin timer must */ |
409 | /* be a multiple of chanlist_len*convert_arg */ | |
8cb9b9fb EP |
410 | |
411 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
412 | ||
413 | unsigned int scan_begin_min; | |
414 | unsigned int scan_begin_arg; | |
415 | unsigned int scan_factor; | |
416 | ||
417 | scan_begin_min = cmd->chanlist_len * cmd->convert_arg; | |
418 | ||
419 | if (cmd->scan_begin_arg != scan_begin_min) { | |
420 | if (scan_begin_min < cmd->scan_begin_arg) { | |
421 | scan_factor = | |
0a85b6f0 | 422 | cmd->scan_begin_arg / scan_begin_min; |
8cb9b9fb EP |
423 | scan_begin_arg = scan_factor * scan_begin_min; |
424 | if (cmd->scan_begin_arg != scan_begin_arg) { | |
425 | cmd->scan_begin_arg = scan_begin_arg; | |
426 | error++; | |
427 | } | |
428 | } else { | |
429 | cmd->scan_begin_arg = scan_begin_min; | |
430 | error++; | |
431 | } | |
432 | } | |
433 | } | |
434 | ||
435 | if (error) | |
436 | return 4; | |
437 | ||
52f8ac98 | 438 | /* Step 5 : check channel list */ |
8cb9b9fb EP |
439 | |
440 | if (cmd->chanlist) { | |
441 | ||
442 | range = CR_RANGE(cmd->chanlist[0]); | |
443 | reference = CR_AREF(cmd->chanlist[0]); | |
444 | ||
445 | if (cmd->chanlist_len > 1) { | |
446 | for (i = 0; i < cmd->chanlist_len; i++) { | |
447 | if (CR_CHAN(cmd->chanlist[i]) != i) { | |
448 | comedi_error(dev, | |
0a85b6f0 MT |
449 | "entries in chanlist must be consecutive " |
450 | "channels,counting upwards from 0\n"); | |
8cb9b9fb EP |
451 | error++; |
452 | } | |
453 | if (CR_RANGE(cmd->chanlist[i]) != range) { | |
454 | comedi_error(dev, | |
0a85b6f0 | 455 | "entries in chanlist must all have the same gain\n"); |
8cb9b9fb EP |
456 | error++; |
457 | } | |
458 | if (CR_AREF(cmd->chanlist[i]) != reference) { | |
459 | comedi_error(dev, | |
0a85b6f0 | 460 | "entries in chanlist must all have the same reference\n"); |
8cb9b9fb EP |
461 | error++; |
462 | } | |
463 | } | |
8cb9b9fb EP |
464 | } |
465 | } | |
466 | ||
467 | if (error) | |
468 | return 5; | |
469 | ||
470 | return 0; | |
471 | ||
472 | } | |
473 | ||
0a85b6f0 | 474 | static int pci9111_ai_do_cmd(struct comedi_device *dev, |
d1d7b20d | 475 | struct comedi_subdevice *s) |
8cb9b9fb | 476 | { |
98943079 | 477 | struct pci9111_private_data *dev_private = dev->private; |
d1d7b20d | 478 | struct comedi_cmd *async_cmd = &s->async->cmd; |
8cb9b9fb EP |
479 | |
480 | if (!dev->irq) { | |
481 | comedi_error(dev, | |
0a85b6f0 | 482 | "no irq assigned for PCI9111, cannot do hardware conversion"); |
8cb9b9fb EP |
483 | return -1; |
484 | } | |
52f8ac98 BP |
485 | /* Set channel scan limit */ |
486 | /* PCI9111 allows only scanning from channel 0 to channel n */ | |
487 | /* TODO: handle the case of an external multiplexer */ | |
8cb9b9fb EP |
488 | |
489 | if (async_cmd->chanlist_len > 1) { | |
0f0bde92 HS |
490 | outb(async_cmd->chanlist_len - 1, |
491 | dev->iobase + PCI9111_AI_CHANNEL_REG); | |
8cb9b9fb EP |
492 | pci9111_autoscan_set(dev, true); |
493 | } else { | |
0f0bde92 HS |
494 | outb(CR_CHAN(async_cmd->chanlist[0]), |
495 | dev->iobase + PCI9111_AI_CHANNEL_REG); | |
8cb9b9fb EP |
496 | pci9111_autoscan_set(dev, false); |
497 | } | |
498 | ||
52f8ac98 BP |
499 | /* Set gain */ |
500 | /* This is the same gain on every channel */ | |
8cb9b9fb | 501 | |
8c7524e6 HS |
502 | outb(CR_RANGE(async_cmd->chanlist[0]) & PCI9111_AI_RANGE_MASK, |
503 | dev->iobase + PCI9111_AI_RANGE_STAT_REG); | |
8cb9b9fb EP |
504 | |
505 | /* Set counter */ | |
506 | ||
507 | switch (async_cmd->stop_src) { | |
508 | case TRIG_COUNT: | |
509 | dev_private->stop_counter = | |
0a85b6f0 | 510 | async_cmd->stop_arg * async_cmd->chanlist_len; |
8cb9b9fb EP |
511 | dev_private->stop_is_none = 0; |
512 | break; | |
513 | ||
514 | case TRIG_NONE: | |
515 | dev_private->stop_counter = 0; | |
516 | dev_private->stop_is_none = 1; | |
517 | break; | |
518 | ||
519 | default: | |
520 | comedi_error(dev, "Invalid stop trigger"); | |
521 | return -1; | |
522 | } | |
523 | ||
52f8ac98 | 524 | /* Set timer pacer */ |
8cb9b9fb EP |
525 | |
526 | dev_private->scan_delay = 0; | |
527 | switch (async_cmd->convert_src) { | |
528 | case TRIG_TIMER: | |
8cb9b9fb EP |
529 | pci9111_trigger_source_set(dev, software); |
530 | pci9111_timer_set(dev); | |
6b228d8a | 531 | pci9111_fifo_reset(dev); |
8cb9b9fb | 532 | pci9111_interrupt_source_set(dev, irq_on_fifo_half_full, |
0a85b6f0 | 533 | irq_on_timer_tick); |
8cb9b9fb EP |
534 | pci9111_trigger_source_set(dev, timer_pacer); |
535 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, | |
0a85b6f0 | 536 | false, true, true); |
8cb9b9fb | 537 | |
6c2fd308 IA |
538 | if (async_cmd->scan_begin_src == TRIG_TIMER) { |
539 | dev_private->scan_delay = | |
540 | (async_cmd->scan_begin_arg / | |
541 | (async_cmd->convert_arg * | |
542 | async_cmd->chanlist_len)) - 1; | |
543 | } | |
8cb9b9fb EP |
544 | |
545 | break; | |
546 | ||
547 | case TRIG_EXT: | |
548 | ||
549 | pci9111_trigger_source_set(dev, external); | |
6b228d8a | 550 | pci9111_fifo_reset(dev); |
8cb9b9fb | 551 | pci9111_interrupt_source_set(dev, irq_on_fifo_half_full, |
0a85b6f0 | 552 | irq_on_timer_tick); |
8cb9b9fb | 553 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, |
0a85b6f0 | 554 | false, true, true); |
8cb9b9fb EP |
555 | |
556 | break; | |
557 | ||
558 | default: | |
559 | comedi_error(dev, "Invalid convert trigger"); | |
560 | return -1; | |
561 | } | |
562 | ||
563 | dev_private->stop_counter *= (1 + dev_private->scan_delay); | |
564 | dev_private->chanlist_len = async_cmd->chanlist_len; | |
565 | dev_private->chunk_counter = 0; | |
566 | dev_private->chunk_num_samples = | |
0a85b6f0 | 567 | dev_private->chanlist_len * (1 + dev_private->scan_delay); |
8cb9b9fb | 568 | |
8cb9b9fb EP |
569 | return 0; |
570 | } | |
571 | ||
0a85b6f0 MT |
572 | static void pci9111_ai_munge(struct comedi_device *dev, |
573 | struct comedi_subdevice *s, void *data, | |
574 | unsigned int num_bytes, | |
575 | unsigned int start_chan_index) | |
8cb9b9fb | 576 | { |
790c5541 | 577 | short *array = data; |
af031edf HS |
578 | unsigned int maxdata = s->maxdata; |
579 | unsigned int invert = (maxdata + 1) >> 1; | |
580 | unsigned int shift = (maxdata == 0xffff) ? 0 : 4; | |
581 | unsigned int num_samples = num_bytes / sizeof(short); | |
582 | unsigned int i; | |
583 | ||
584 | for (i = 0; i < num_samples; i++) | |
585 | array[i] = ((array[i] >> shift) & maxdata) ^ invert; | |
8cb9b9fb EP |
586 | } |
587 | ||
70265d24 | 588 | static irqreturn_t pci9111_interrupt(int irq, void *p_device) |
8cb9b9fb | 589 | { |
71b5f4f1 | 590 | struct comedi_device *dev = p_device; |
98943079 | 591 | struct pci9111_private_data *dev_private = dev->private; |
d1d7b20d | 592 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 593 | struct comedi_async *async; |
96764373 | 594 | unsigned int status; |
8cb9b9fb EP |
595 | unsigned long irq_flags; |
596 | unsigned char intcsr; | |
597 | ||
598 | if (!dev->attached) { | |
52f8ac98 BP |
599 | /* Ignore interrupt before device fully attached. */ |
600 | /* Might not even have allocated subdevices yet! */ | |
8cb9b9fb EP |
601 | return IRQ_NONE; |
602 | } | |
603 | ||
d1d7b20d | 604 | async = s->async; |
8cb9b9fb | 605 | |
5f74ea14 | 606 | spin_lock_irqsave(&dev->spinlock, irq_flags); |
8cb9b9fb | 607 | |
52f8ac98 | 608 | /* Check if we are source of interrupt */ |
8cb9b9fb | 609 | intcsr = inb(dev_private->lcr_io_base + |
0a85b6f0 | 610 | PLX9050_REGISTER_INTERRUPT_CONTROL); |
8cb9b9fb | 611 | if (!(((intcsr & PLX9050_PCI_INTERRUPT_ENABLE) != 0) |
0a85b6f0 MT |
612 | && (((intcsr & (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) |
613 | == (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) | |
614 | || ((intcsr & (PLX9050_LINTI2_ENABLE | PLX9050_LINTI2_STATUS)) | |
615 | == (PLX9050_LINTI2_ENABLE | PLX9050_LINTI2_STATUS))))) { | |
52f8ac98 BP |
616 | /* Not the source of the interrupt. */ |
617 | /* (N.B. not using PLX9050_SOFTWARE_INTERRUPT) */ | |
5f74ea14 | 618 | spin_unlock_irqrestore(&dev->spinlock, irq_flags); |
8cb9b9fb EP |
619 | return IRQ_NONE; |
620 | } | |
621 | ||
622 | if ((intcsr & (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) == | |
0a85b6f0 | 623 | (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) { |
52f8ac98 | 624 | /* Interrupt comes from fifo_half-full signal */ |
8cb9b9fb | 625 | |
8c7524e6 | 626 | status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); |
96764373 HS |
627 | |
628 | /* '0' means FIFO is full, data may have been lost */ | |
8c7524e6 | 629 | if (!(status & PCI9111_AI_STAT_FF_FF)) { |
0a85b6f0 | 630 | spin_unlock_irqrestore(&dev->spinlock, irq_flags); |
8cb9b9fb | 631 | comedi_error(dev, PCI9111_DRIVER_NAME " fifo overflow"); |
f123f287 | 632 | outb(0, dev->iobase + PCI9111_INT_CLR_REG); |
d1d7b20d | 633 | pci9111_ai_cancel(dev, s); |
8cb9b9fb | 634 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
d1d7b20d | 635 | comedi_event(dev, s); |
8cb9b9fb EP |
636 | |
637 | return IRQ_HANDLED; | |
638 | } | |
639 | ||
96764373 | 640 | /* '0' means FIFO is half-full */ |
8c7524e6 | 641 | if (!(status & PCI9111_AI_STAT_FF_HF)) { |
8cb9b9fb EP |
642 | unsigned int num_samples; |
643 | unsigned int bytes_written = 0; | |
644 | ||
8cb9b9fb | 645 | num_samples = |
0a85b6f0 MT |
646 | PCI9111_FIFO_HALF_SIZE > |
647 | dev_private->stop_counter | |
648 | && !dev_private-> | |
649 | stop_is_none ? dev_private->stop_counter : | |
650 | PCI9111_FIFO_HALF_SIZE; | |
b5d8d119 | 651 | insw(dev->iobase + PCI9111_AI_FIFO_REG, |
0a85b6f0 | 652 | dev_private->ai_bounce_buffer, num_samples); |
8cb9b9fb EP |
653 | |
654 | if (dev_private->scan_delay < 1) { | |
655 | bytes_written = | |
d1d7b20d | 656 | cfc_write_array_to_buffer(s, |
0a85b6f0 MT |
657 | dev_private-> |
658 | ai_bounce_buffer, | |
659 | num_samples * | |
660 | sizeof(short)); | |
8cb9b9fb EP |
661 | } else { |
662 | int position = 0; | |
663 | int to_read; | |
664 | ||
665 | while (position < num_samples) { | |
666 | if (dev_private->chunk_counter < | |
0a85b6f0 | 667 | dev_private->chanlist_len) { |
8cb9b9fb | 668 | to_read = |
0a85b6f0 MT |
669 | dev_private->chanlist_len - |
670 | dev_private->chunk_counter; | |
8cb9b9fb EP |
671 | |
672 | if (to_read > | |
0a85b6f0 | 673 | num_samples - position) |
8cb9b9fb | 674 | to_read = |
0a85b6f0 MT |
675 | num_samples - |
676 | position; | |
8cb9b9fb EP |
677 | |
678 | bytes_written += | |
0a85b6f0 | 679 | cfc_write_array_to_buffer |
d1d7b20d | 680 | (s, |
0a85b6f0 MT |
681 | dev_private->ai_bounce_buffer |
682 | + position, | |
683 | to_read * sizeof(short)); | |
8cb9b9fb EP |
684 | } else { |
685 | to_read = | |
0a85b6f0 MT |
686 | dev_private->chunk_num_samples |
687 | - | |
688 | dev_private->chunk_counter; | |
8cb9b9fb | 689 | if (to_read > |
0a85b6f0 | 690 | num_samples - position) |
8cb9b9fb | 691 | to_read = |
0a85b6f0 MT |
692 | num_samples - |
693 | position; | |
8cb9b9fb EP |
694 | |
695 | bytes_written += | |
0a85b6f0 | 696 | sizeof(short) * to_read; |
8cb9b9fb EP |
697 | } |
698 | ||
699 | position += to_read; | |
700 | dev_private->chunk_counter += to_read; | |
701 | ||
702 | if (dev_private->chunk_counter >= | |
0a85b6f0 | 703 | dev_private->chunk_num_samples) |
8cb9b9fb EP |
704 | dev_private->chunk_counter = 0; |
705 | } | |
706 | } | |
707 | ||
708 | dev_private->stop_counter -= | |
0a85b6f0 | 709 | bytes_written / sizeof(short); |
8cb9b9fb EP |
710 | } |
711 | } | |
712 | ||
713 | if ((dev_private->stop_counter == 0) && (!dev_private->stop_is_none)) { | |
714 | async->events |= COMEDI_CB_EOA; | |
d1d7b20d | 715 | pci9111_ai_cancel(dev, s); |
8cb9b9fb EP |
716 | } |
717 | ||
f123f287 | 718 | outb(0, dev->iobase + PCI9111_INT_CLR_REG); |
8cb9b9fb | 719 | |
5f74ea14 | 720 | spin_unlock_irqrestore(&dev->spinlock, irq_flags); |
8cb9b9fb | 721 | |
d1d7b20d | 722 | comedi_event(dev, s); |
8cb9b9fb EP |
723 | |
724 | return IRQ_HANDLED; | |
725 | } | |
726 | ||
da91b269 | 727 | static int pci9111_ai_insn_read(struct comedi_device *dev, |
d1d7b20d | 728 | struct comedi_subdevice *s, |
0a85b6f0 | 729 | struct comedi_insn *insn, unsigned int *data) |
8cb9b9fb | 730 | { |
ae479ee5 HS |
731 | unsigned int chan = CR_CHAN(insn->chanspec); |
732 | unsigned int range = CR_RANGE(insn->chanspec); | |
2f002cc9 HS |
733 | unsigned int maxdata = s->maxdata; |
734 | unsigned int invert = (maxdata + 1) >> 1; | |
735 | unsigned int shift = (maxdata == 0xffff) ? 0 : 4; | |
96764373 | 736 | unsigned int status; |
2f002cc9 HS |
737 | int timeout; |
738 | int i; | |
8cb9b9fb | 739 | |
0f0bde92 | 740 | outb(chan, dev->iobase + PCI9111_AI_CHANNEL_REG); |
8cb9b9fb | 741 | |
8c7524e6 HS |
742 | status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); |
743 | if ((status & PCI9111_AI_RANGE_MASK) != range) { | |
744 | outb(range & PCI9111_AI_RANGE_MASK, | |
745 | dev->iobase + PCI9111_AI_RANGE_STAT_REG); | |
c514bab7 | 746 | } |
8cb9b9fb | 747 | |
6b228d8a | 748 | pci9111_fifo_reset(dev); |
8cb9b9fb EP |
749 | |
750 | for (i = 0; i < insn->n; i++) { | |
3eb60d73 | 751 | /* Generate a software trigger */ |
8c7524e6 | 752 | outb(0, dev->iobase + PCI9111_SOFT_TRIG_REG); |
8cb9b9fb EP |
753 | |
754 | timeout = PCI9111_AI_INSTANT_READ_TIMEOUT; | |
755 | ||
756 | while (timeout--) { | |
8c7524e6 | 757 | status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); |
96764373 | 758 | /* '1' means FIFO is not empty */ |
8c7524e6 | 759 | if (status & PCI9111_AI_STAT_FF_EF) |
8cb9b9fb EP |
760 | goto conversion_done; |
761 | } | |
762 | ||
763 | comedi_error(dev, "A/D read timeout"); | |
764 | data[i] = 0; | |
6b228d8a | 765 | pci9111_fifo_reset(dev); |
8cb9b9fb EP |
766 | return -ETIME; |
767 | ||
0a85b6f0 | 768 | conversion_done: |
8cb9b9fb | 769 | |
2f002cc9 HS |
770 | data[i] = inw(dev->iobase + PCI9111_AI_FIFO_REG); |
771 | data[i] = ((data[i] >> shift) & maxdata) ^ invert; | |
8cb9b9fb EP |
772 | } |
773 | ||
8cb9b9fb EP |
774 | return i; |
775 | } | |
776 | ||
2084fd19 HS |
777 | static int pci9111_ao_insn_write(struct comedi_device *dev, |
778 | struct comedi_subdevice *s, | |
779 | struct comedi_insn *insn, | |
780 | unsigned int *data) | |
8cb9b9fb | 781 | { |
98943079 | 782 | struct pci9111_private_data *dev_private = dev->private; |
2084fd19 | 783 | unsigned int val = 0; |
8cb9b9fb EP |
784 | int i; |
785 | ||
786 | for (i = 0; i < insn->n; i++) { | |
2084fd19 HS |
787 | val = data[i]; |
788 | outw(val, dev->iobase + PCI9111_AO_REG); | |
8cb9b9fb | 789 | } |
2084fd19 | 790 | dev_private->ao_readback = val; |
8cb9b9fb | 791 | |
2084fd19 | 792 | return insn->n; |
8cb9b9fb EP |
793 | } |
794 | ||
da91b269 | 795 | static int pci9111_ao_insn_read(struct comedi_device *dev, |
0a85b6f0 | 796 | struct comedi_subdevice *s, |
b3450faf HS |
797 | struct comedi_insn *insn, |
798 | unsigned int *data) | |
8cb9b9fb | 799 | { |
98943079 | 800 | struct pci9111_private_data *dev_private = dev->private; |
8cb9b9fb EP |
801 | int i; |
802 | ||
2306d9b1 | 803 | for (i = 0; i < insn->n; i++) |
b3450faf | 804 | data[i] = dev_private->ao_readback; |
8cb9b9fb | 805 | |
b3450faf | 806 | return insn->n; |
8cb9b9fb EP |
807 | } |
808 | ||
da91b269 | 809 | static int pci9111_di_insn_bits(struct comedi_device *dev, |
d1d7b20d | 810 | struct comedi_subdevice *s, |
bfa6d3b8 HS |
811 | struct comedi_insn *insn, |
812 | unsigned int *data) | |
8cb9b9fb | 813 | { |
bfa6d3b8 | 814 | data[1] = inw(dev->iobase + PCI9111_DIO_REG); |
8cb9b9fb | 815 | |
a2714e3e | 816 | return insn->n; |
8cb9b9fb EP |
817 | } |
818 | ||
da91b269 | 819 | static int pci9111_do_insn_bits(struct comedi_device *dev, |
d1d7b20d | 820 | struct comedi_subdevice *s, |
83dcfee0 HS |
821 | struct comedi_insn *insn, |
822 | unsigned int *data) | |
8cb9b9fb | 823 | { |
83dcfee0 HS |
824 | unsigned int mask = data[0]; |
825 | unsigned int bits = data[1]; | |
8cb9b9fb | 826 | |
83dcfee0 HS |
827 | if (mask) { |
828 | s->state &= ~mask; | |
829 | s->state |= (bits & mask); | |
8cb9b9fb | 830 | |
83dcfee0 HS |
831 | outw(s->state, dev->iobase + PCI9111_DIO_REG); |
832 | } | |
8cb9b9fb | 833 | |
83dcfee0 | 834 | data[1] = s->state; |
8cb9b9fb | 835 | |
a2714e3e | 836 | return insn->n; |
8cb9b9fb EP |
837 | } |
838 | ||
da91b269 | 839 | static int pci9111_reset(struct comedi_device *dev) |
8cb9b9fb | 840 | { |
98943079 HS |
841 | struct pci9111_private_data *dev_private = dev->private; |
842 | ||
52f8ac98 | 843 | /* Set trigger source to software */ |
8cb9b9fb | 844 | plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true, |
0a85b6f0 | 845 | true, false); |
8cb9b9fb EP |
846 | |
847 | pci9111_trigger_source_set(dev, software); | |
848 | pci9111_pretrigger_set(dev, false); | |
849 | pci9111_autoscan_set(dev, false); | |
850 | ||
eba16272 HS |
851 | /* Reset 8254 chip */ |
852 | dev_private->div1 = 0; | |
853 | dev_private->div2 = 0; | |
8cb9b9fb EP |
854 | pci9111_timer_set(dev); |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
a690b7e5 | 859 | static int pci9111_auto_attach(struct comedi_device *dev, |
750af5e5 | 860 | unsigned long context_unused) |
8cb9b9fb | 861 | { |
750af5e5 | 862 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
98943079 | 863 | struct pci9111_private_data *dev_private; |
d1d7b20d | 864 | struct comedi_subdevice *s; |
98943079 | 865 | int ret; |
3e5a0ba0 | 866 | |
3e5a0ba0 | 867 | dev->board_name = dev->driver->driver_name; |
8cb9b9fb | 868 | |
c34fa261 HS |
869 | dev_private = kzalloc(sizeof(*dev_private), GFP_KERNEL); |
870 | if (!dev_private) | |
871 | return -ENOMEM; | |
872 | dev->private = dev_private; | |
98943079 | 873 | |
3e5a0ba0 HS |
874 | ret = comedi_pci_enable(pcidev, dev->board_name); |
875 | if (ret) | |
876 | return ret; | |
877 | dev_private->lcr_io_base = pci_resource_start(pcidev, 1); | |
878 | dev->iobase = pci_resource_start(pcidev, 2); | |
8cb9b9fb EP |
879 | |
880 | pci9111_reset(dev); | |
881 | ||
6a7b1b0c | 882 | if (pcidev->irq > 0) { |
3e5a0ba0 HS |
883 | ret = request_irq(dev->irq, pci9111_interrupt, |
884 | IRQF_SHARED, dev->board_name, dev); | |
885 | if (ret) | |
886 | return ret; | |
6a7b1b0c | 887 | dev->irq = pcidev->irq; |
8cb9b9fb | 888 | } |
8cb9b9fb | 889 | |
98943079 HS |
890 | ret = comedi_alloc_subdevices(dev, 4); |
891 | if (ret) | |
892 | return ret; | |
8cb9b9fb | 893 | |
573e31af | 894 | s = &dev->subdevices[0]; |
d1d7b20d | 895 | dev->read_subdev = s; |
02baee8c HS |
896 | s->type = COMEDI_SUBD_AI; |
897 | s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ; | |
898 | s->n_chan = 16; | |
899 | s->maxdata = 0xffff; | |
900 | s->len_chanlist = 16; | |
afa6ac4a | 901 | s->range_table = &pci9111_ai_range; |
02baee8c HS |
902 | s->cancel = pci9111_ai_cancel; |
903 | s->insn_read = pci9111_ai_insn_read; | |
904 | s->do_cmdtest = pci9111_ai_do_cmd_test; | |
905 | s->do_cmd = pci9111_ai_do_cmd; | |
906 | s->munge = pci9111_ai_munge; | |
d1d7b20d | 907 | |
573e31af | 908 | s = &dev->subdevices[1]; |
05841b36 HS |
909 | s->type = COMEDI_SUBD_AO; |
910 | s->subdev_flags = SDF_WRITABLE | SDF_COMMON; | |
911 | s->n_chan = 1; | |
912 | s->maxdata = 0x0fff; | |
913 | s->len_chanlist = 1; | |
914 | s->range_table = &range_bipolar10; | |
915 | s->insn_write = pci9111_ao_insn_write; | |
916 | s->insn_read = pci9111_ao_insn_read; | |
d1d7b20d | 917 | |
573e31af | 918 | s = &dev->subdevices[2]; |
3acf3176 HS |
919 | s->type = COMEDI_SUBD_DI; |
920 | s->subdev_flags = SDF_READABLE; | |
921 | s->n_chan = 16; | |
922 | s->maxdata = 1; | |
923 | s->range_table = &range_digital; | |
924 | s->insn_bits = pci9111_di_insn_bits; | |
d1d7b20d | 925 | |
573e31af | 926 | s = &dev->subdevices[3]; |
3acf3176 HS |
927 | s->type = COMEDI_SUBD_DO; |
928 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE; | |
929 | s->n_chan = 16; | |
930 | s->maxdata = 1; | |
931 | s->range_table = &range_digital; | |
932 | s->insn_bits = pci9111_do_insn_bits; | |
8cb9b9fb | 933 | |
034f8734 HS |
934 | dev_info(dev->class_dev, "%s attached\n", dev->board_name); |
935 | ||
8cb9b9fb EP |
936 | return 0; |
937 | } | |
938 | ||
484ecc95 | 939 | static void pci9111_detach(struct comedi_device *dev) |
8cb9b9fb | 940 | { |
6a7b1b0c HS |
941 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
942 | ||
893be483 HS |
943 | if (dev->iobase) |
944 | pci9111_reset(dev); | |
2306d9b1 | 945 | if (dev->irq != 0) |
5f74ea14 | 946 | free_irq(dev->irq, dev); |
6a7b1b0c | 947 | if (pcidev) { |
2306d9b1 | 948 | if (dev->iobase) |
6a7b1b0c | 949 | comedi_pci_disable(pcidev); |
8cb9b9fb | 950 | } |
8cb9b9fb | 951 | } |
90f703d3 | 952 | |
75e6301b HS |
953 | static struct comedi_driver adl_pci9111_driver = { |
954 | .driver_name = "adl_pci9111", | |
e68a83fe | 955 | .module = THIS_MODULE, |
750af5e5 | 956 | .auto_attach = pci9111_auto_attach, |
e68a83fe HS |
957 | .detach = pci9111_detach, |
958 | }; | |
959 | ||
a690b7e5 | 960 | static int pci9111_pci_probe(struct pci_dev *dev, |
75e6301b | 961 | const struct pci_device_id *ent) |
e68a83fe | 962 | { |
75e6301b | 963 | return comedi_pci_auto_config(dev, &adl_pci9111_driver); |
e68a83fe HS |
964 | } |
965 | ||
e68a83fe HS |
966 | static DEFINE_PCI_DEVICE_TABLE(pci9111_pci_table) = { |
967 | { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HR_DEVICE_ID) }, | |
968 | /* { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HG_DEVICE_ID) }, */ | |
969 | { 0 } | |
970 | }; | |
971 | MODULE_DEVICE_TABLE(pci, pci9111_pci_table); | |
972 | ||
75e6301b HS |
973 | static struct pci_driver adl_pci9111_pci_driver = { |
974 | .name = "adl_pci9111", | |
e68a83fe | 975 | .id_table = pci9111_pci_table, |
75e6301b | 976 | .probe = pci9111_pci_probe, |
9901a4d7 | 977 | .remove = comedi_pci_auto_unconfig, |
e68a83fe | 978 | }; |
75e6301b | 979 | module_comedi_pci_driver(adl_pci9111_driver, adl_pci9111_pci_driver); |
e68a83fe | 980 | |
90f703d3 AT |
981 | MODULE_AUTHOR("Comedi http://www.comedi.org"); |
982 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
983 | MODULE_LICENSE("GPL"); |