[linux-2.6-block.git] / drivers / staging / comedi / drivers / addi_apci_1032.c

/*
 * addi_apci_1032.c
 * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
 * Project manager: Eric Stolz
 *
 *	ADDI-DATA GmbH
 *	Dieselstrasse 3
 *	D-77833 Ottersweier
 *	Tel: +19(0)7223/9493-0
 *	Fax: +49(0)7223/9493-92
 *	http://www.addi-data.com
 *	info@addi-data.com
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * You should also find the complete GPL in the COPYING file accompanying this
 * source code.
 */

#include "../comedidev.h"
#include "comedi_fc.h"
#include "amcc_s5933.h"

/*
 * I/O Register Map
 */
#define APCI1032_DI_REG			0x00
#define APCI1032_MODE1_REG		0x04
#define APCI1032_MODE2_REG		0x08
#define APCI1032_STATUS_REG		0x0c
#define APCI1032_CTRL_REG		0x10
#define APCI1032_CTRL_INT_OR		(0 << 1)
#define APCI1032_CTRL_INT_AND		(1 << 1)
#define APCI1032_CTRL_INT_ENA		(1 << 2)

struct apci1032_private {
	unsigned long amcc_iobase;	/* base of AMCC I/O registers */
	unsigned int mode1;	/* rising-edge/high level channels */
	unsigned int mode2;	/* falling-edge/low level channels */
	unsigned int ctrl;	/* interrupt mode OR (edge) . AND (level) */
};

static int apci1032_reset(struct comedi_device *dev)
{
	/* disable the interrupts */
	outl(0x0, dev->iobase + APCI1032_CTRL_REG);
	/* Reset the interrupt status register */
	inl(dev->iobase + APCI1032_STATUS_REG);
	/* Disable the and/or interrupt */
	outl(0x0, dev->iobase + APCI1032_MODE1_REG);
	outl(0x0, dev->iobase + APCI1032_MODE2_REG);

	return 0;
}

/*
 * Change-Of-State (COS) interrupt configuration
 *
 * Channels 0 to 15 are interruptible. These channels can be configured
 * to generate interrupts based on AND/OR logic for the desired channels.
 *
 *	OR logic
 *		- reacts to rising or falling edges
 *		- interrupt is generated when any enabled channel
 *		  meet the desired interrupt condition
 *
 *	AND logic
 *		- reacts to changes in level of the selected inputs
 *		- interrupt is generated when all enabled channels
 *		  meet the desired interrupt condition
 *		- after an interrupt, a change in level must occur on
 *		  the selected inputs to release the IRQ logic
 *
 * The COS interrupt must be configured before it can be enabled.
 *
 *	data[0] : INSN_CONFIG_DIGITAL_TRIG
 *	data[1] : trigger number (= 0)
 *	data[2] : configuration operation:
 *	          COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
 *	          COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
 *	          COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
 *	data[3] : left-shift for data[4] and data[5]
 *	data[4] : rising-edge/high level channels
 *	data[5] : falling-edge/low level channels
 */
static int apci1032_cos_insn_config(struct comedi_device *dev,
				    struct comedi_subdevice *s,
				    struct comedi_insn *insn,
				    unsigned int *data)
{
	struct apci1032_private *devpriv = dev->private;
	unsigned int shift, oldmask;

	switch (data[0]) {
	case INSN_CONFIG_DIGITAL_TRIG:
		if (data[1] != 0)
			return -EINVAL;
		shift = data[3];
		oldmask = (1U << shift) - 1;
		switch (data[2]) {
		case COMEDI_DIGITAL_TRIG_DISABLE:
			devpriv->ctrl = 0;
			devpriv->mode1 = 0;
			devpriv->mode2 = 0;
			apci1032_reset(dev);
			break;
		case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
			if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA |
					      APCI1032_CTRL_INT_OR)) {
				/* switching to 'OR' mode */
				devpriv->ctrl = APCI1032_CTRL_INT_ENA |
						APCI1032_CTRL_INT_OR;
				/* wipe old channels */
				devpriv->mode1 = 0;
				devpriv->mode2 = 0;
			} else {
				/* preserve unspecified channels */
				devpriv->mode1 &= oldmask;
				devpriv->mode2 &= oldmask;
			}
			/* configure specified channels */
			devpriv->mode1 |= data[4] << shift;
			devpriv->mode2 |= data[5] << shift;
			break;
		case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
			if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA |
					      APCI1032_CTRL_INT_AND)) {
				/* switching to 'AND' mode */
				devpriv->ctrl = APCI1032_CTRL_INT_ENA |
						APCI1032_CTRL_INT_AND;
				/* wipe old channels */
				devpriv->mode1 = 0;
				devpriv->mode2 = 0;
			} else {
				/* preserve unspecified channels */
				devpriv->mode1 &= oldmask;
				devpriv->mode2 &= oldmask;
			}
			/* configure specified channels */
			devpriv->mode1 |= data[4] << shift;
			devpriv->mode2 |= data[5] << shift;
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
	}

	return insn->n;
}

static int apci1032_cos_insn_bits(struct comedi_device *dev,
				  struct comedi_subdevice *s,
				  struct comedi_insn *insn,
				  unsigned int *data)
{
	data[1] = s->state;

	return 0;
}

static int apci1032_cos_cmdtest(struct comedi_device *dev,
				struct comedi_subdevice *s,
				struct comedi_cmd *cmd)
{
	int err = 0;

	/* Step 1 : check if triggers are trivially valid */

	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);

	if (err)
		return 1;

	/* Step 2a : make sure trigger sources are unique */
	/* Step 2b : and mutually compatible */

	if (err)
		return 2;

	/* Step 3: check if arguments are trivially valid */

	err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
	err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);

	if (err)
		return 3;

	/* step 4: ignored */

	if (err)
		return 4;

	return 0;
}

/*
 * Change-Of-State (COS) 'do_cmd' operation
 *
 * Enable the COS interrupt as configured by apci1032_cos_insn_config().
 */
static int apci1032_cos_cmd(struct comedi_device *dev,
			    struct comedi_subdevice *s)
{
	struct apci1032_private *devpriv = dev->private;

	if (!devpriv->ctrl) {
		dev_warn(dev->class_dev,
			"Interrupts disabled due to mode configuration!\n");
		return -EINVAL;
	}

	outl(devpriv->mode1, dev->iobase + APCI1032_MODE1_REG);
	outl(devpriv->mode2, dev->iobase + APCI1032_MODE2_REG);
	outl(devpriv->ctrl, dev->iobase + APCI1032_CTRL_REG);

	return 0;
}

static int apci1032_cos_cancel(struct comedi_device *dev,
			       struct comedi_subdevice *s)
{
	return apci1032_reset(dev);
}

static irqreturn_t apci1032_interrupt(int irq, void *d)
{
	struct comedi_device *dev = d;
	struct apci1032_private *devpriv = dev->private;
	struct comedi_subdevice *s = dev->read_subdev;
	unsigned int ctrl;

	/* check interrupt is from this device */
	if ((inl(devpriv->amcc_iobase + AMCC_OP_REG_INTCSR) &
	     INTCSR_INTR_ASSERTED) == 0)
		return IRQ_NONE;

	/* check interrupt is enabled */
	ctrl = inl(dev->iobase + APCI1032_CTRL_REG);
	if ((ctrl & APCI1032_CTRL_INT_ENA) == 0)
		return IRQ_HANDLED;

	/* disable the interrupt */
	outl(ctrl & ~APCI1032_CTRL_INT_ENA, dev->iobase + APCI1032_CTRL_REG);

	s->state = inl(dev->iobase + APCI1032_STATUS_REG) & 0xffff;
	comedi_buf_put(s->async, s->state);
	s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
	comedi_event(dev, s);

	/* enable the interrupt */
	outl(ctrl, dev->iobase + APCI1032_CTRL_REG);

	return IRQ_HANDLED;
}

static int apci1032_di_insn_bits(struct comedi_device *dev,
				 struct comedi_subdevice *s,
				 struct comedi_insn *insn,
				 unsigned int *data)
{
	data[1] = inl(dev->iobase + APCI1032_DI_REG);

	return insn->n;
}

static int apci1032_auto_attach(struct comedi_device *dev,
					  unsigned long context_unused)
{
	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
	struct apci1032_private *devpriv;
	struct comedi_subdevice *s;
	int ret;

	dev->board_name = dev->driver->driver_name;

	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	if (!devpriv)
		return -ENOMEM;
	dev->private = devpriv;

	ret = comedi_pci_enable(pcidev, dev->board_name);
	if (ret)
		return ret;

	devpriv->amcc_iobase = pci_resource_start(pcidev, 0);
	dev->iobase = pci_resource_start(pcidev, 1);
	apci1032_reset(dev);
	if (pcidev->irq > 0) {
		ret = request_irq(pcidev->irq, apci1032_interrupt, IRQF_SHARED,
				  dev->board_name, dev);
		if (ret == 0)
			dev->irq = pcidev->irq;
	}

	ret = comedi_alloc_subdevices(dev, 2);
	if (ret)
		return ret;

	/*  Allocate and Initialise DI Subdevice Structures */
	s = &dev->subdevices[0];
	s->type		= COMEDI_SUBD_DI;
	s->subdev_flags	= SDF_READABLE;
	s->n_chan	= 32;
	s->maxdata	= 1;
	s->range_table	= &range_digital;
	s->insn_bits	= apci1032_di_insn_bits;

	/* Change-Of-State (COS) interrupt subdevice */
	s = &dev->subdevices[1];
	if (dev->irq) {
		dev->read_subdev = s;
		s->type		= COMEDI_SUBD_DI | SDF_CMD_READ;
		s->subdev_flags	= SDF_READABLE;
		s->n_chan	= 1;
		s->maxdata	= 1;
		s->range_table	= &range_digital;
		s->insn_config	= apci1032_cos_insn_config;
		s->insn_bits	= apci1032_cos_insn_bits;
		s->do_cmdtest	= apci1032_cos_cmdtest;
		s->do_cmd	= apci1032_cos_cmd;
		s->cancel	= apci1032_cos_cancel;
	} else {
		s->type		= COMEDI_SUBD_UNUSED;
	}

	return 0;
}

static void apci1032_detach(struct comedi_device *dev)
{
	struct pci_dev *pcidev = comedi_to_pci_dev(dev);

	if (dev->iobase)
		apci1032_reset(dev);
	if (dev->irq)
		free_irq(dev->irq, dev);
	if (pcidev) {
		if (dev->iobase)
			comedi_pci_disable(pcidev);
	}
}

static struct comedi_driver apci1032_driver = {
	.driver_name	= "addi_apci_1032",
	.module		= THIS_MODULE,
	.auto_attach	= apci1032_auto_attach,
	.detach		= apci1032_detach,
};

static int apci1032_pci_probe(struct pci_dev *dev,
					const struct pci_device_id *ent)
{
	return comedi_pci_auto_config(dev, &apci1032_driver);
}

static DEFINE_PCI_DEVICE_TABLE(apci1032_pci_table) = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1003) },
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, apci1032_pci_table);

static struct pci_driver apci1032_pci_driver = {
	.name		= "addi_apci_1032",
	.id_table	= apci1032_pci_table,
	.probe		= apci1032_pci_probe,
	.remove		= comedi_pci_auto_unconfig,
};
module_comedi_pci_driver(apci1032_driver, apci1032_pci_driver);

MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("Comedi low-level driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
6a3734af HS	1	/*
	2	* addi_apci_1032.c
	3	* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
	4	* Project manager: Eric Stolz
	5	*
	6	* ADDI-DATA GmbH
	7	* Dieselstrasse 3
	8	* D-77833 Ottersweier
	9	* Tel: +19(0)7223/9493-0
	10	* Fax: +49(0)7223/9493-92
	11	* http://www.addi-data.com
	12	* info@addi-data.com
	13	*
	14	* This program is free software; you can redistribute it and/or modify it
	15	* under the terms of the GNU General Public License as published by the
	16	* Free Software Foundation; either version 2 of the License, or (at your
	17	* option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
	23	*
	24	* You should have received a copy of the GNU General Public License along with
	25	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	26	* Place, Suite 330, Boston, MA 02111-1307 USA
	27	*
	28	* You should also find the complete GPL in the COPYING file accompanying this
	29	* source code.
	30	*/
	31
3d41c443 HS	32	#include "../comedidev.h"
3d41c443 HS	33	#include "comedi_fc.h"
792660d5	34	#include "amcc_s5933.h"
3d41c443	35
6a3734af HS	36	/*
	37	* I/O Register Map
	38	*/
	39	#define APCI1032_DI_REG 0x00
	40	#define APCI1032_MODE1_REG 0x04
	41	#define APCI1032_MODE2_REG 0x08
	42	#define APCI1032_STATUS_REG 0x0c
	43	#define APCI1032_CTRL_REG 0x10
	44	#define APCI1032_CTRL_INT_OR (0 << 1)
	45	#define APCI1032_CTRL_INT_AND (1 << 1)
	46	#define APCI1032_CTRL_INT_ENA (1 << 2)
	47
4cde0a6d	48	struct apci1032_private {
792660d5	49	unsigned long amcc_iobase; /* base of AMCC I/O registers */
4cde0a6d HS	50	unsigned int mode1; /* rising-edge/high level channels */
	51	unsigned int mode2; /* falling-edge/low level channels */
	52	unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
	53	};
6a3734af	54
4cde0a6d HS	55	static int apci1032_reset(struct comedi_device *dev)
	56	{
	57	/* disable the interrupts */
	58	outl(0x0, dev->iobase + APCI1032_CTRL_REG);
	59	/* Reset the interrupt status register */
	60	inl(dev->iobase + APCI1032_STATUS_REG);
	61	/* Disable the and/or interrupt */
	62	outl(0x0, dev->iobase + APCI1032_MODE1_REG);
	63	outl(0x0, dev->iobase + APCI1032_MODE2_REG);
	64
	65	return 0;
	66	}
6a3734af HS	67
6a3734af HS	68	/*
4cde0a6d HS	69	* Change-Of-State (COS) interrupt configuration
	70	*
	71	* Channels 0 to 15 are interruptible. These channels can be configured
	72	* to generate interrupts based on AND/OR logic for the desired channels.
	73	*
	74	* OR logic
	75	* - reacts to rising or falling edges
	76	* - interrupt is generated when any enabled channel
	77	* meet the desired interrupt condition
	78	*
	79	* AND logic
	80	* - reacts to changes in level of the selected inputs
	81	* - interrupt is generated when all enabled channels
	82	* meet the desired interrupt condition
	83	* - after an interrupt, a change in level must occur on
	84	* the selected inputs to release the IRQ logic
	85	*
	86	* The COS interrupt must be configured before it can be enabled.
	87	*
	88	* data[0] : INSN_CONFIG_DIGITAL_TRIG
33cdce62 IA	89	* data[1] : trigger number (= 0)
	90	* data[2] : configuration operation:
	91	* COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
	92	* COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
	93	* COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
	94	* data[3] : left-shift for data[4] and data[5]
	95	* data[4] : rising-edge/high level channels
	96	* data[5] : falling-edge/low level channels
6a3734af	97	*/
4cde0a6d HS	98	static int apci1032_cos_insn_config(struct comedi_device *dev,
	99	struct comedi_subdevice *s,
	100	struct comedi_insn *insn,
	101	unsigned int *data)
6a3734af	102	{
4cde0a6d	103	struct apci1032_private *devpriv = dev->private;
33cdce62	104	unsigned int shift, oldmask;
4cde0a6d HS	105
	106	switch (data[0]) {
	107	case INSN_CONFIG_DIGITAL_TRIG:
33cdce62 IA	108	if (data[1] != 0)
	109	return -EINVAL;
	110	shift = data[3];
	111	oldmask = (1U << shift) - 1;
	112	switch (data[2]) {
	113	case COMEDI_DIGITAL_TRIG_DISABLE:
4cde0a6d	114	devpriv->ctrl = 0;
33cdce62 IA	115	devpriv->mode1 = 0;
33cdce62 IA	116	devpriv->mode2 = 0;
4cde0a6d	117	apci1032_reset(dev);
33cdce62 IA	118	break;
	119	case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
	120	if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA \|
	121	APCI1032_CTRL_INT_OR)) {
	122	/* switching to 'OR' mode */
	123	devpriv->ctrl = APCI1032_CTRL_INT_ENA \|
	124	APCI1032_CTRL_INT_OR;
	125	/* wipe old channels */
	126	devpriv->mode1 = 0;
	127	devpriv->mode2 = 0;
	128	} else {
	129	/* preserve unspecified channels */
	130	devpriv->mode1 &= oldmask;
	131	devpriv->mode2 &= oldmask;
	132	}
	133	/* configure specified channels */
	134	devpriv->mode1 \|= data[4] << shift;
	135	devpriv->mode2 \|= data[5] << shift;
	136	break;
	137	case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
	138	if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA \|
	139	APCI1032_CTRL_INT_AND)) {
	140	/* switching to 'AND' mode */
	141	devpriv->ctrl = APCI1032_CTRL_INT_ENA \|
	142	APCI1032_CTRL_INT_AND;
	143	/* wipe old channels */
	144	devpriv->mode1 = 0;
	145	devpriv->mode2 = 0;
	146	} else {
	147	/* preserve unspecified channels */
	148	devpriv->mode1 &= oldmask;
	149	devpriv->mode2 &= oldmask;
	150	}
	151	/* configure specified channels */
	152	devpriv->mode1 \|= data[4] << shift;
	153	devpriv->mode2 \|= data[5] << shift;
	154	break;
	155	default:
	156	return -EINVAL;
4cde0a6d HS	157	}
	158	break;
	159	default:
	160	return -EINVAL;
	161	}
6a3734af HS	162
	163	return insn->n;
	164	}
2bb8b1df	165
4cde0a6d HS	166	static int apci1032_cos_insn_bits(struct comedi_device *dev,
	167	struct comedi_subdevice *s,
	168	struct comedi_insn *insn,
	169	unsigned int *data)
	170	{
	171	data[1] = s->state;
	172
	173	return 0;
	174	}
	175
	176	static int apci1032_cos_cmdtest(struct comedi_device *dev,
	177	struct comedi_subdevice *s,
	178	struct comedi_cmd *cmd)
	179	{
	180	int err = 0;
	181
	182	/* Step 1 : check if triggers are trivially valid */
	183
	184	err \|= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	185	err \|= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
	186	err \|= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	187	err \|= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	188	err \|= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
	189
	190	if (err)
	191	return 1;
	192
	193	/* Step 2a : make sure trigger sources are unique */
	194	/* Step 2b : and mutually compatible */
	195
	196	if (err)
	197	return 2;
	198
58bed93e	199	/* Step 3: check if arguments are trivially valid */
4cde0a6d	200
58bed93e HS	201	err \|= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
	202	err \|= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
	203	err \|= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
	204	err \|= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
	205	err \|= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
4cde0a6d HS	206
	207	if (err)
	208	return 3;
	209
	210	/* step 4: ignored */
	211
	212	if (err)
	213	return 4;
	214
	215	return 0;
	216	}
	217
	218	/*
	219	* Change-Of-State (COS) 'do_cmd' operation
	220	*
	221	* Enable the COS interrupt as configured by apci1032_cos_insn_config().
	222	*/
	223	static int apci1032_cos_cmd(struct comedi_device *dev,
	224	struct comedi_subdevice *s)
	225	{
	226	struct apci1032_private *devpriv = dev->private;
	227
	228	if (!devpriv->ctrl) {
	229	dev_warn(dev->class_dev,
	230	"Interrupts disabled due to mode configuration!\n");
	231	return -EINVAL;
	232	}
	233
	234	outl(devpriv->mode1, dev->iobase + APCI1032_MODE1_REG);
	235	outl(devpriv->mode2, dev->iobase + APCI1032_MODE2_REG);
	236	outl(devpriv->ctrl, dev->iobase + APCI1032_CTRL_REG);
	237
	238	return 0;
	239	}
	240
	241	static int apci1032_cos_cancel(struct comedi_device *dev,
	242	struct comedi_subdevice *s)
	243	{
	244	return apci1032_reset(dev);
	245	}
	246
12d606f7	247	static irqreturn_t apci1032_interrupt(int irq, void *d)
2bb8b1df	248	{
12d606f7	249	struct comedi_device *dev = d;
792660d5	250	struct apci1032_private *devpriv = dev->private;
4cde0a6d	251	struct comedi_subdevice *s = dev->read_subdev;
12d606f7 HS	252	unsigned int ctrl;
12d606f7 HS	253
792660d5 IA	254	/* check interrupt is from this device */
	255	if ((inl(devpriv->amcc_iobase + AMCC_OP_REG_INTCSR) &
	256	INTCSR_INTR_ASSERTED) == 0)
	257	return IRQ_NONE;
	258
	259	/* check interrupt is enabled */
12d606f7	260	ctrl = inl(dev->iobase + APCI1032_CTRL_REG);
792660d5 IA	261	if ((ctrl & APCI1032_CTRL_INT_ENA) == 0)
	262	return IRQ_HANDLED;
	263
	264	/* disable the interrupt */
12d606f7 HS	265	outl(ctrl & ~APCI1032_CTRL_INT_ENA, dev->iobase + APCI1032_CTRL_REG);
12d606f7 HS	266
4cde0a6d HS	267	s->state = inl(dev->iobase + APCI1032_STATUS_REG) & 0xffff;
	268	comedi_buf_put(s->async, s->state);
	269	s->async->events \|= COMEDI_CB_BLOCK \| COMEDI_CB_EOS;
	270	comedi_event(dev, s);
12d606f7 HS	271
	272	/* enable the interrupt */
	273	outl(ctrl, dev->iobase + APCI1032_CTRL_REG);
	274
	275	return IRQ_HANDLED;
2bb8b1df HS	276	}
2bb8b1df HS	277
a3de4cd3 HS	278	static int apci1032_di_insn_bits(struct comedi_device *dev,
	279	struct comedi_subdevice *s,
	280	struct comedi_insn *insn,
	281	unsigned int *data)
	282	{
	283	data[1] = inl(dev->iobase + APCI1032_DI_REG);
	284
	285	return insn->n;
	286	}
	287
a690b7e5	288	static int apci1032_auto_attach(struct comedi_device *dev,
891e62c3	289	unsigned long context_unused)
2bb8b1df	290	{
891e62c3	291	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4cde0a6d	292	struct apci1032_private *devpriv;
2bb8b1df	293	struct comedi_subdevice *s;
b37f84d5	294	int ret;
2bb8b1df	295
ac467b5e	296	dev->board_name = dev->driver->driver_name;
2bb8b1df	297
4cde0a6d HS	298	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	299	if (!devpriv)
	300	return -ENOMEM;
	301	dev->private = devpriv;
	302
2bb8b1df HS	303	ret = comedi_pci_enable(pcidev, dev->board_name);
	304	if (ret)
	305	return ret;
	306
792660d5	307	devpriv->amcc_iobase = pci_resource_start(pcidev, 0);
c965c8b7	308	dev->iobase = pci_resource_start(pcidev, 1);
792660d5	309	apci1032_reset(dev);
2bb8b1df	310	if (pcidev->irq > 0) {
12d606f7	311	ret = request_irq(pcidev->irq, apci1032_interrupt, IRQF_SHARED,
2bb8b1df HS	312	dev->board_name, dev);
	313	if (ret == 0)
	314	dev->irq = pcidev->irq;
	315	}
	316
6835a17a	317	ret = comedi_alloc_subdevices(dev, 2);
2bb8b1df HS	318	if (ret)
	319	return ret;
	320
2bb8b1df	321	/* Allocate and Initialise DI Subdevice Structures */
b37f84d5	322	s = &dev->subdevices[0];
4c2c1488 HS	323	s->type = COMEDI_SUBD_DI;
	324	s->subdev_flags = SDF_READABLE;
	325	s->n_chan = 32;
	326	s->maxdata = 1;
4c2c1488	327	s->range_table = &range_digital;
a3de4cd3	328	s->insn_bits = apci1032_di_insn_bits;
5dbdbf67	329
4cde0a6d HS	330	/* Change-Of-State (COS) interrupt subdevice */
4cde0a6d HS	331	s = &dev->subdevices[1];
6835a17a	332	if (dev->irq) {
4cde0a6d HS	333	dev->read_subdev = s;
4cde0a6d HS	334	s->type = COMEDI_SUBD_DI \| SDF_CMD_READ;
6835a17a HS	335	s->subdev_flags = SDF_READABLE;
	336	s->n_chan = 1;
	337	s->maxdata = 1;
	338	s->range_table = &range_digital;
4cde0a6d HS	339	s->insn_config = apci1032_cos_insn_config;
	340	s->insn_bits = apci1032_cos_insn_bits;
	341	s->do_cmdtest = apci1032_cos_cmdtest;
	342	s->do_cmd = apci1032_cos_cmd;
	343	s->cancel = apci1032_cos_cancel;
	344	} else {
	345	s->type = COMEDI_SUBD_UNUSED;
6835a17a HS	346	}
6835a17a HS	347
2bb8b1df HS	348	return 0;
	349	}
	350
	351	static void apci1032_detach(struct comedi_device *dev)
	352	{
	353	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2bb8b1df	354
14696bbe HS	355	if (dev->iobase)
	356	apci1032_reset(dev);
	357	if (dev->irq)
	358	free_irq(dev->irq, dev);
2bb8b1df HS	359	if (pcidev) {
	360	if (dev->iobase)
	361	comedi_pci_disable(pcidev);
	362	}
	363	}
	364
20a22b70 HS	365	static struct comedi_driver apci1032_driver = {
	366	.driver_name = "addi_apci_1032",
	367	.module = THIS_MODULE,
891e62c3	368	.auto_attach = apci1032_auto_attach,
2bb8b1df	369	.detach = apci1032_detach,
20a22b70 HS	370	};
20a22b70 HS	371
a690b7e5	372	static int apci1032_pci_probe(struct pci_dev *dev,
20a22b70 HS	373	const struct pci_device_id *ent)
	374	{
	375	return comedi_pci_auto_config(dev, &apci1032_driver);
	376	}
	377
20a22b70	378	static DEFINE_PCI_DEVICE_TABLE(apci1032_pci_table) = {
317285d7 HS	379	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1003) },
	380	{ 0 }
	381	};
20a22b70	382	MODULE_DEVICE_TABLE(pci, apci1032_pci_table);
317285d7	383
20a22b70 HS	384	static struct pci_driver apci1032_pci_driver = {
	385	.name = "addi_apci_1032",
	386	.id_table = apci1032_pci_table,
	387	.probe = apci1032_pci_probe,
9901a4d7	388	.remove = comedi_pci_auto_unconfig,
20a22b70 HS	389	};
20a22b70 HS	390	module_comedi_pci_driver(apci1032_driver, apci1032_pci_driver);
90f703d3 AT	391
	392	MODULE_AUTHOR("Comedi http://www.comedi.org");
	393	MODULE_DESCRIPTION("Comedi low-level driver");
	394	MODULE_LICENSE("GPL");