[linux-2.6-block.git] / drivers / staging / comedi / drivers / addi_apci_1032.c

/*
 * addi_apci_1032.c
 * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
 * Project manager: Eric Stolz
 *
 *	ADDI-DATA GmbH
 *	Dieselstrasse 3
 *	D-77833 Ottersweier
 *	Tel: +19(0)7223/9493-0
 *	Fax: +49(0)7223/9493-92
 *	http://www.addi-data.com
 *	info@addi-data.com
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/interrupt.h>

#include "../comedidev.h"
#include "comedi_fc.h"
#include "amcc_s5933.h"

/*
 * I/O Register Map
 */
#define APCI1032_DI_REG			0x00
#define APCI1032_MODE1_REG		0x04
#define APCI1032_MODE2_REG		0x08
#define APCI1032_STATUS_REG		0x0c
#define APCI1032_CTRL_REG		0x10
#define APCI1032_CTRL_INT_OR		(0 << 1)
#define APCI1032_CTRL_INT_AND		(1 << 1)
#define APCI1032_CTRL_INT_ENA		(1 << 2)

struct apci1032_private {
	unsigned long amcc_iobase;	/* base of AMCC I/O registers */
	unsigned int mode1;	/* rising-edge/high level channels */
	unsigned int mode2;	/* falling-edge/low level channels */
	unsigned int ctrl;	/* interrupt mode OR (edge) . AND (level) */
};

static int apci1032_reset(struct comedi_device *dev)
{
	/* disable the interrupts */
	outl(0x0, dev->iobase + APCI1032_CTRL_REG);
	/* Reset the interrupt status register */
	inl(dev->iobase + APCI1032_STATUS_REG);
	/* Disable the and/or interrupt */
	outl(0x0, dev->iobase + APCI1032_MODE1_REG);
	outl(0x0, dev->iobase + APCI1032_MODE2_REG);

	return 0;
}

/*
 * Change-Of-State (COS) interrupt configuration
 *
 * Channels 0 to 15 are interruptible. These channels can be configured
 * to generate interrupts based on AND/OR logic for the desired channels.
 *
 *	OR logic
 *		- reacts to rising or falling edges
 *		- interrupt is generated when any enabled channel
 *		  meet the desired interrupt condition
 *
 *	AND logic
 *		- reacts to changes in level of the selected inputs
 *		- interrupt is generated when all enabled channels
 *		  meet the desired interrupt condition
 *		- after an interrupt, a change in level must occur on
 *		  the selected inputs to release the IRQ logic
 *
 * The COS interrupt must be configured before it can be enabled.
 *
 *	data[0] : INSN_CONFIG_DIGITAL_TRIG
 *	data[1] : trigger number (= 0)
 *	data[2] : configuration operation:
 *	          COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
 *	          COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
 *	          COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
 *	data[3] : left-shift for data[4] and data[5]
 *	data[4] : rising-edge/high level channels
 *	data[5] : falling-edge/low level channels
 */
static int apci1032_cos_insn_config(struct comedi_device *dev,
				    struct comedi_subdevice *s,
				    struct comedi_insn *insn,
				    unsigned int *data)
{
	struct apci1032_private *devpriv = dev->private;
	unsigned int shift, oldmask;

	switch (data[0]) {
	case INSN_CONFIG_DIGITAL_TRIG:
		if (data[1] != 0)
			return -EINVAL;
		shift = data[3];
		oldmask = (1U << shift) - 1;
		switch (data[2]) {
		case COMEDI_DIGITAL_TRIG_DISABLE:
			devpriv->ctrl = 0;
			devpriv->mode1 = 0;
			devpriv->mode2 = 0;
			apci1032_reset(dev);
			break;
		case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
			if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA |
					      APCI1032_CTRL_INT_OR)) {
				/* switching to 'OR' mode */
				devpriv->ctrl = APCI1032_CTRL_INT_ENA |
						APCI1032_CTRL_INT_OR;
				/* wipe old channels */
				devpriv->mode1 = 0;
				devpriv->mode2 = 0;
			} else {
				/* preserve unspecified channels */
				devpriv->mode1 &= oldmask;
				devpriv->mode2 &= oldmask;
			}
			/* configure specified channels */
			devpriv->mode1 |= data[4] << shift;
			devpriv->mode2 |= data[5] << shift;
			break;
		case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
			if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA |
					      APCI1032_CTRL_INT_AND)) {
				/* switching to 'AND' mode */
				devpriv->ctrl = APCI1032_CTRL_INT_ENA |
						APCI1032_CTRL_INT_AND;
				/* wipe old channels */
				devpriv->mode1 = 0;
				devpriv->mode2 = 0;
			} else {
				/* preserve unspecified channels */
				devpriv->mode1 &= oldmask;
				devpriv->mode2 &= oldmask;
			}
			/* configure specified channels */
			devpriv->mode1 |= data[4] << shift;
			devpriv->mode2 |= data[5] << shift;
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
	}

	return insn->n;
}

static int apci1032_cos_insn_bits(struct comedi_device *dev,
				  struct comedi_subdevice *s,
				  struct comedi_insn *insn,
				  unsigned int *data)
{
	data[1] = s->state;

	return 0;
}

static int apci1032_cos_cmdtest(struct comedi_device *dev,
				struct comedi_subdevice *s,
				struct comedi_cmd *cmd)
{
	int err = 0;

	/* Step 1 : check if triggers are trivially valid */

	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);

	if (err)
		return 1;

	/* Step 2a : make sure trigger sources are unique */
	/* Step 2b : and mutually compatible */

	if (err)
		return 2;

	/* Step 3: check if arguments are trivially valid */

	err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
	err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);

	if (err)
		return 3;

	/* step 4: ignored */

	if (err)
		return 4;

	return 0;
}

/*
 * Change-Of-State (COS) 'do_cmd' operation
 *
 * Enable the COS interrupt as configured by apci1032_cos_insn_config().
 */
static int apci1032_cos_cmd(struct comedi_device *dev,
			    struct comedi_subdevice *s)
{
	struct apci1032_private *devpriv = dev->private;

	if (!devpriv->ctrl) {
		dev_warn(dev->class_dev,
			"Interrupts disabled due to mode configuration!\n");
		return -EINVAL;
	}

	outl(devpriv->mode1, dev->iobase + APCI1032_MODE1_REG);
	outl(devpriv->mode2, dev->iobase + APCI1032_MODE2_REG);
	outl(devpriv->ctrl, dev->iobase + APCI1032_CTRL_REG);

	return 0;
}

static int apci1032_cos_cancel(struct comedi_device *dev,
			       struct comedi_subdevice *s)
{
	return apci1032_reset(dev);
}

static irqreturn_t apci1032_interrupt(int irq, void *d)
{
	struct comedi_device *dev = d;
	struct apci1032_private *devpriv = dev->private;
	struct comedi_subdevice *s = dev->read_subdev;
	unsigned int ctrl;

	/* check interrupt is from this device */
	if ((inl(devpriv->amcc_iobase + AMCC_OP_REG_INTCSR) &
	     INTCSR_INTR_ASSERTED) == 0)
		return IRQ_NONE;

	/* check interrupt is enabled */
	ctrl = inl(dev->iobase + APCI1032_CTRL_REG);
	if ((ctrl & APCI1032_CTRL_INT_ENA) == 0)
		return IRQ_HANDLED;

	/* disable the interrupt */
	outl(ctrl & ~APCI1032_CTRL_INT_ENA, dev->iobase + APCI1032_CTRL_REG);

	s->state = inl(dev->iobase + APCI1032_STATUS_REG) & 0xffff;
	comedi_buf_put(s->async, s->state);
	s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
	comedi_event(dev, s);

	/* enable the interrupt */
	outl(ctrl, dev->iobase + APCI1032_CTRL_REG);

	return IRQ_HANDLED;
}

static int apci1032_di_insn_bits(struct comedi_device *dev,
				 struct comedi_subdevice *s,
				 struct comedi_insn *insn,
				 unsigned int *data)
{
	data[1] = inl(dev->iobase + APCI1032_DI_REG);

	return insn->n;
}

static int apci1032_auto_attach(struct comedi_device *dev,
					  unsigned long context_unused)
{
	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
	struct apci1032_private *devpriv;
	struct comedi_subdevice *s;
	int ret;

	devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
	if (!devpriv)
		return -ENOMEM;

	ret = comedi_pci_enable(dev);
	if (ret)
		return ret;

	devpriv->amcc_iobase = pci_resource_start(pcidev, 0);
	dev->iobase = pci_resource_start(pcidev, 1);
	apci1032_reset(dev);
	if (pcidev->irq > 0) {
		ret = request_irq(pcidev->irq, apci1032_interrupt, IRQF_SHARED,
				  dev->board_name, dev);
		if (ret == 0)
			dev->irq = pcidev->irq;
	}

	ret = comedi_alloc_subdevices(dev, 2);
	if (ret)
		return ret;

	/*  Allocate and Initialise DI Subdevice Structures */
	s = &dev->subdevices[0];
	s->type		= COMEDI_SUBD_DI;
	s->subdev_flags	= SDF_READABLE;
	s->n_chan	= 32;
	s->maxdata	= 1;
	s->range_table	= &range_digital;
	s->insn_bits	= apci1032_di_insn_bits;

	/* Change-Of-State (COS) interrupt subdevice */
	s = &dev->subdevices[1];
	if (dev->irq) {
		dev->read_subdev = s;
		s->type		= COMEDI_SUBD_DI;
		s->subdev_flags	= SDF_READABLE | SDF_CMD_READ;
		s->n_chan	= 1;
		s->maxdata	= 1;
		s->range_table	= &range_digital;
		s->insn_config	= apci1032_cos_insn_config;
		s->insn_bits	= apci1032_cos_insn_bits;
		s->do_cmdtest	= apci1032_cos_cmdtest;
		s->do_cmd	= apci1032_cos_cmd;
		s->cancel	= apci1032_cos_cancel;
	} else {
		s->type		= COMEDI_SUBD_UNUSED;
	}

	return 0;
}

static void apci1032_detach(struct comedi_device *dev)
{
	if (dev->iobase)
		apci1032_reset(dev);
	if (dev->irq)
		free_irq(dev->irq, dev);
	comedi_pci_disable(dev);
}

static struct comedi_driver apci1032_driver = {
	.driver_name	= "addi_apci_1032",
	.module		= THIS_MODULE,
	.auto_attach	= apci1032_auto_attach,
	.detach		= apci1032_detach,
};

static int apci1032_pci_probe(struct pci_dev *dev,
			      const struct pci_device_id *id)
{
	return comedi_pci_auto_config(dev, &apci1032_driver, id->driver_data);
}

static const struct pci_device_id apci1032_pci_table[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1003) },
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, apci1032_pci_table);

static struct pci_driver apci1032_pci_driver = {
	.name		= "addi_apci_1032",
	.id_table	= apci1032_pci_table,
	.probe		= apci1032_pci_probe,
	.remove		= comedi_pci_auto_unconfig,
};
module_comedi_pci_driver(apci1032_driver, apci1032_pci_driver);

MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("ADDI-DATA APCI-1032, 32 channel DI boards");
MODULE_LICENSE("GPL");
Commit	Line	Data
6a3734af HS	1	/*
	2	* addi_apci_1032.c
	3	* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
	4	* Project manager: Eric Stolz
	5	*
	6	* ADDI-DATA GmbH
	7	* Dieselstrasse 3
	8	* D-77833 Ottersweier
	9	* Tel: +19(0)7223/9493-0
	10	* Fax: +49(0)7223/9493-92
	11	* http://www.addi-data.com
	12	* info@addi-data.com
	13	*
	14	* This program is free software; you can redistribute it and/or modify it
	15	* under the terms of the GNU General Public License as published by the
	16	* Free Software Foundation; either version 2 of the License, or (at your
	17	* option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
6a3734af HS	23	*/
6a3734af HS	24
ce157f80	25	#include <linux/module.h>
33782dd5	26	#include <linux/pci.h>
abac8b54 HS	27	#include <linux/interrupt.h>
abac8b54 HS	28
3d41c443 HS	29	#include "../comedidev.h"
3d41c443 HS	30	#include "comedi_fc.h"
792660d5	31	#include "amcc_s5933.h"
3d41c443	32
6a3734af HS	33	/*
	34	* I/O Register Map
	35	*/
	36	#define APCI1032_DI_REG 0x00
	37	#define APCI1032_MODE1_REG 0x04
	38	#define APCI1032_MODE2_REG 0x08
	39	#define APCI1032_STATUS_REG 0x0c
	40	#define APCI1032_CTRL_REG 0x10
	41	#define APCI1032_CTRL_INT_OR (0 << 1)
	42	#define APCI1032_CTRL_INT_AND (1 << 1)
	43	#define APCI1032_CTRL_INT_ENA (1 << 2)
	44
4cde0a6d	45	struct apci1032_private {
792660d5	46	unsigned long amcc_iobase; /* base of AMCC I/O registers */
4cde0a6d HS	47	unsigned int mode1; /* rising-edge/high level channels */
	48	unsigned int mode2; /* falling-edge/low level channels */
	49	unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
	50	};
6a3734af	51
4cde0a6d HS	52	static int apci1032_reset(struct comedi_device *dev)
	53	{
	54	/* disable the interrupts */
	55	outl(0x0, dev->iobase + APCI1032_CTRL_REG);
	56	/* Reset the interrupt status register */
	57	inl(dev->iobase + APCI1032_STATUS_REG);
	58	/* Disable the and/or interrupt */
	59	outl(0x0, dev->iobase + APCI1032_MODE1_REG);
	60	outl(0x0, dev->iobase + APCI1032_MODE2_REG);
	61
	62	return 0;
	63	}
6a3734af HS	64
6a3734af HS	65	/*
4cde0a6d HS	66	* Change-Of-State (COS) interrupt configuration
	67	*
	68	* Channels 0 to 15 are interruptible. These channels can be configured
	69	* to generate interrupts based on AND/OR logic for the desired channels.
	70	*
	71	* OR logic
	72	* - reacts to rising or falling edges
	73	* - interrupt is generated when any enabled channel
	74	* meet the desired interrupt condition
	75	*
	76	* AND logic
	77	* - reacts to changes in level of the selected inputs
	78	* - interrupt is generated when all enabled channels
	79	* meet the desired interrupt condition
	80	* - after an interrupt, a change in level must occur on
	81	* the selected inputs to release the IRQ logic
	82	*
	83	* The COS interrupt must be configured before it can be enabled.
	84	*
	85	* data[0] : INSN_CONFIG_DIGITAL_TRIG
33cdce62 IA	86	* data[1] : trigger number (= 0)
	87	* data[2] : configuration operation:
	88	* COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
	89	* COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
	90	* COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
	91	* data[3] : left-shift for data[4] and data[5]
	92	* data[4] : rising-edge/high level channels
	93	* data[5] : falling-edge/low level channels
6a3734af	94	*/
4cde0a6d HS	95	static int apci1032_cos_insn_config(struct comedi_device *dev,
	96	struct comedi_subdevice *s,
	97	struct comedi_insn *insn,
	98	unsigned int *data)
6a3734af	99	{
4cde0a6d	100	struct apci1032_private *devpriv = dev->private;
33cdce62	101	unsigned int shift, oldmask;
4cde0a6d HS	102
	103	switch (data[0]) {
	104	case INSN_CONFIG_DIGITAL_TRIG:
33cdce62 IA	105	if (data[1] != 0)
	106	return -EINVAL;
	107	shift = data[3];
	108	oldmask = (1U << shift) - 1;
	109	switch (data[2]) {
	110	case COMEDI_DIGITAL_TRIG_DISABLE:
4cde0a6d	111	devpriv->ctrl = 0;
33cdce62 IA	112	devpriv->mode1 = 0;
33cdce62 IA	113	devpriv->mode2 = 0;
4cde0a6d	114	apci1032_reset(dev);
33cdce62 IA	115	break;
	116	case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
	117	if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA \|
	118	APCI1032_CTRL_INT_OR)) {
	119	/* switching to 'OR' mode */
	120	devpriv->ctrl = APCI1032_CTRL_INT_ENA \|
	121	APCI1032_CTRL_INT_OR;
	122	/* wipe old channels */
	123	devpriv->mode1 = 0;
	124	devpriv->mode2 = 0;
	125	} else {
	126	/* preserve unspecified channels */
	127	devpriv->mode1 &= oldmask;
	128	devpriv->mode2 &= oldmask;
	129	}
	130	/* configure specified channels */
	131	devpriv->mode1 \|= data[4] << shift;
	132	devpriv->mode2 \|= data[5] << shift;
	133	break;
	134	case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
	135	if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA \|
	136	APCI1032_CTRL_INT_AND)) {
	137	/* switching to 'AND' mode */
	138	devpriv->ctrl = APCI1032_CTRL_INT_ENA \|
	139	APCI1032_CTRL_INT_AND;
	140	/* wipe old channels */
	141	devpriv->mode1 = 0;
	142	devpriv->mode2 = 0;
	143	} else {
	144	/* preserve unspecified channels */
	145	devpriv->mode1 &= oldmask;
	146	devpriv->mode2 &= oldmask;
	147	}
	148	/* configure specified channels */
	149	devpriv->mode1 \|= data[4] << shift;
	150	devpriv->mode2 \|= data[5] << shift;
	151	break;
	152	default:
	153	return -EINVAL;
4cde0a6d HS	154	}
	155	break;
	156	default:
	157	return -EINVAL;
	158	}
6a3734af HS	159
	160	return insn->n;
	161	}
2bb8b1df	162
4cde0a6d HS	163	static int apci1032_cos_insn_bits(struct comedi_device *dev,
	164	struct comedi_subdevice *s,
	165	struct comedi_insn *insn,
	166	unsigned int *data)
	167	{
	168	data[1] = s->state;
	169
	170	return 0;
	171	}
	172
	173	static int apci1032_cos_cmdtest(struct comedi_device *dev,
	174	struct comedi_subdevice *s,
	175	struct comedi_cmd *cmd)
	176	{
	177	int err = 0;
	178
	179	/* Step 1 : check if triggers are trivially valid */
	180
	181	err \|= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	182	err \|= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
	183	err \|= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	184	err \|= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	185	err \|= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
	186
	187	if (err)
	188	return 1;
	189
	190	/* Step 2a : make sure trigger sources are unique */
	191	/* Step 2b : and mutually compatible */
	192
	193	if (err)
	194	return 2;
	195
58bed93e	196	/* Step 3: check if arguments are trivially valid */
4cde0a6d	197
58bed93e HS	198	err \|= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
	199	err \|= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
	200	err \|= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
	201	err \|= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
	202	err \|= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
4cde0a6d HS	203
	204	if (err)
	205	return 3;
	206
	207	/* step 4: ignored */
	208
	209	if (err)
	210	return 4;
	211
	212	return 0;
	213	}
	214
	215	/*
	216	* Change-Of-State (COS) 'do_cmd' operation
	217	*
	218	* Enable the COS interrupt as configured by apci1032_cos_insn_config().
	219	*/
	220	static int apci1032_cos_cmd(struct comedi_device *dev,
	221	struct comedi_subdevice *s)
	222	{
	223	struct apci1032_private *devpriv = dev->private;
	224
	225	if (!devpriv->ctrl) {
	226	dev_warn(dev->class_dev,
	227	"Interrupts disabled due to mode configuration!\n");
	228	return -EINVAL;
	229	}
	230
	231	outl(devpriv->mode1, dev->iobase + APCI1032_MODE1_REG);
	232	outl(devpriv->mode2, dev->iobase + APCI1032_MODE2_REG);
	233	outl(devpriv->ctrl, dev->iobase + APCI1032_CTRL_REG);
	234
	235	return 0;
	236	}
	237
	238	static int apci1032_cos_cancel(struct comedi_device *dev,
	239	struct comedi_subdevice *s)
	240	{
	241	return apci1032_reset(dev);
	242	}
	243
12d606f7	244	static irqreturn_t apci1032_interrupt(int irq, void *d)
2bb8b1df	245	{
12d606f7	246	struct comedi_device *dev = d;
792660d5	247	struct apci1032_private *devpriv = dev->private;
4cde0a6d	248	struct comedi_subdevice *s = dev->read_subdev;
12d606f7 HS	249	unsigned int ctrl;
12d606f7 HS	250
792660d5 IA	251	/* check interrupt is from this device */
	252	if ((inl(devpriv->amcc_iobase + AMCC_OP_REG_INTCSR) &
	253	INTCSR_INTR_ASSERTED) == 0)
	254	return IRQ_NONE;
	255
	256	/* check interrupt is enabled */
12d606f7	257	ctrl = inl(dev->iobase + APCI1032_CTRL_REG);
792660d5 IA	258	if ((ctrl & APCI1032_CTRL_INT_ENA) == 0)
	259	return IRQ_HANDLED;
	260
	261	/* disable the interrupt */
12d606f7 HS	262	outl(ctrl & ~APCI1032_CTRL_INT_ENA, dev->iobase + APCI1032_CTRL_REG);
12d606f7 HS	263
4cde0a6d HS	264	s->state = inl(dev->iobase + APCI1032_STATUS_REG) & 0xffff;
	265	comedi_buf_put(s->async, s->state);
	266	s->async->events \|= COMEDI_CB_BLOCK \| COMEDI_CB_EOS;
	267	comedi_event(dev, s);
12d606f7 HS	268
	269	/* enable the interrupt */
	270	outl(ctrl, dev->iobase + APCI1032_CTRL_REG);
	271
	272	return IRQ_HANDLED;
2bb8b1df HS	273	}
2bb8b1df HS	274
a3de4cd3 HS	275	static int apci1032_di_insn_bits(struct comedi_device *dev,
	276	struct comedi_subdevice *s,
	277	struct comedi_insn *insn,
	278	unsigned int *data)
	279	{
	280	data[1] = inl(dev->iobase + APCI1032_DI_REG);
	281
	282	return insn->n;
	283	}
	284
a690b7e5	285	static int apci1032_auto_attach(struct comedi_device *dev,
891e62c3	286	unsigned long context_unused)
2bb8b1df	287	{
891e62c3	288	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4cde0a6d	289	struct apci1032_private *devpriv;
2bb8b1df	290	struct comedi_subdevice *s;
b37f84d5	291	int ret;
2bb8b1df	292
0bdab509	293	devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4cde0a6d HS	294	if (!devpriv)
4cde0a6d HS	295	return -ENOMEM;
4cde0a6d	296
818f569f	297	ret = comedi_pci_enable(dev);
2bb8b1df HS	298	if (ret)
	299	return ret;
	300
792660d5	301	devpriv->amcc_iobase = pci_resource_start(pcidev, 0);
c965c8b7	302	dev->iobase = pci_resource_start(pcidev, 1);
792660d5	303	apci1032_reset(dev);
2bb8b1df	304	if (pcidev->irq > 0) {
12d606f7	305	ret = request_irq(pcidev->irq, apci1032_interrupt, IRQF_SHARED,
2bb8b1df HS	306	dev->board_name, dev);
	307	if (ret == 0)
	308	dev->irq = pcidev->irq;
	309	}
	310
6835a17a	311	ret = comedi_alloc_subdevices(dev, 2);
2bb8b1df HS	312	if (ret)
	313	return ret;
	314
2bb8b1df	315	/* Allocate and Initialise DI Subdevice Structures */
b37f84d5	316	s = &dev->subdevices[0];
4c2c1488 HS	317	s->type = COMEDI_SUBD_DI;
	318	s->subdev_flags = SDF_READABLE;
	319	s->n_chan = 32;
	320	s->maxdata = 1;
4c2c1488	321	s->range_table = &range_digital;
a3de4cd3	322	s->insn_bits = apci1032_di_insn_bits;
5dbdbf67	323
4cde0a6d HS	324	/* Change-Of-State (COS) interrupt subdevice */
4cde0a6d HS	325	s = &dev->subdevices[1];
6835a17a	326	if (dev->irq) {
4cde0a6d	327	dev->read_subdev = s;
90daf69a HS	328	s->type = COMEDI_SUBD_DI;
90daf69a HS	329	s->subdev_flags = SDF_READABLE \| SDF_CMD_READ;
6835a17a HS	330	s->n_chan = 1;
	331	s->maxdata = 1;
	332	s->range_table = &range_digital;
4cde0a6d HS	333	s->insn_config = apci1032_cos_insn_config;
	334	s->insn_bits = apci1032_cos_insn_bits;
	335	s->do_cmdtest = apci1032_cos_cmdtest;
	336	s->do_cmd = apci1032_cos_cmd;
	337	s->cancel = apci1032_cos_cancel;
	338	} else {
	339	s->type = COMEDI_SUBD_UNUSED;
6835a17a HS	340	}
6835a17a HS	341
2bb8b1df HS	342	return 0;
	343	}
	344
	345	static void apci1032_detach(struct comedi_device *dev)
	346	{
14696bbe HS	347	if (dev->iobase)
	348	apci1032_reset(dev);
	349	if (dev->irq)
	350	free_irq(dev->irq, dev);
7f072f54	351	comedi_pci_disable(dev);
2bb8b1df HS	352	}
2bb8b1df HS	353
20a22b70 HS	354	static struct comedi_driver apci1032_driver = {
	355	.driver_name = "addi_apci_1032",
	356	.module = THIS_MODULE,
891e62c3	357	.auto_attach = apci1032_auto_attach,
2bb8b1df	358	.detach = apci1032_detach,
20a22b70 HS	359	};
20a22b70 HS	360
a690b7e5	361	static int apci1032_pci_probe(struct pci_dev *dev,
b8f4ac23	362	const struct pci_device_id *id)
20a22b70	363	{
b8f4ac23	364	return comedi_pci_auto_config(dev, &apci1032_driver, id->driver_data);
20a22b70 HS	365	}
20a22b70 HS	366
41e043fc	367	static const struct pci_device_id apci1032_pci_table[] = {
317285d7 HS	368	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1003) },
	369	{ 0 }
	370	};
20a22b70	371	MODULE_DEVICE_TABLE(pci, apci1032_pci_table);
317285d7	372
20a22b70 HS	373	static struct pci_driver apci1032_pci_driver = {
	374	.name = "addi_apci_1032",
	375	.id_table = apci1032_pci_table,
	376	.probe = apci1032_pci_probe,
9901a4d7	377	.remove = comedi_pci_auto_unconfig,
20a22b70 HS	378	};
20a22b70 HS	379	module_comedi_pci_driver(apci1032_driver, apci1032_pci_driver);
90f703d3 AT	380
90f703d3 AT	381	MODULE_AUTHOR("Comedi http://www.comedi.org");
b5ebcaa8	382	MODULE_DESCRIPTION("ADDI-DATA APCI-1032, 32 channel DI boards");
90f703d3	383	MODULE_LICENSE("GPL");