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a9533e7e HP |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef _SBPCMCIA_H | |
18 | #define _SBPCMCIA_H | |
19 | ||
20 | /* All the addresses that are offsets in attribute space are divided | |
21 | * by two to account for the fact that odd bytes are invalid in | |
22 | * attribute space and our read/write routines make the space appear | |
23 | * as if they didn't exist. Still we want to show the original numbers | |
24 | * as documented in the hnd_pcmcia core manual. | |
25 | */ | |
26 | ||
27 | /* PCMCIA Function Configuration Registers */ | |
28 | #define PCMCIA_FCR (0x700 / 2) | |
29 | ||
30 | #define FCR0_OFF 0 | |
31 | #define FCR1_OFF (0x40 / 2) | |
32 | #define FCR2_OFF (0x80 / 2) | |
33 | #define FCR3_OFF (0xc0 / 2) | |
34 | ||
35 | #define PCMCIA_FCR0 (0x700 / 2) | |
36 | #define PCMCIA_FCR1 (0x740 / 2) | |
37 | #define PCMCIA_FCR2 (0x780 / 2) | |
38 | #define PCMCIA_FCR3 (0x7c0 / 2) | |
39 | ||
40 | /* Standard PCMCIA FCR registers */ | |
41 | ||
42 | #define PCMCIA_COR 0 | |
43 | ||
44 | #define COR_RST 0x80 | |
45 | #define COR_LEV 0x40 | |
46 | #define COR_IRQEN 0x04 | |
47 | #define COR_BLREN 0x01 | |
48 | #define COR_FUNEN 0x01 | |
49 | ||
50 | #define PCICIA_FCSR (2 / 2) | |
51 | #define PCICIA_PRR (4 / 2) | |
52 | #define PCICIA_SCR (6 / 2) | |
53 | #define PCICIA_ESR (8 / 2) | |
54 | ||
55 | #define PCM_MEMOFF 0x0000 | |
56 | #define F0_MEMOFF 0x1000 | |
57 | #define F1_MEMOFF 0x2000 | |
58 | #define F2_MEMOFF 0x3000 | |
59 | #define F3_MEMOFF 0x4000 | |
60 | ||
61 | /* Memory base in the function fcr's */ | |
62 | #define MEM_ADDR0 (0x728 / 2) | |
63 | #define MEM_ADDR1 (0x72a / 2) | |
64 | #define MEM_ADDR2 (0x72c / 2) | |
65 | ||
66 | /* PCMCIA base plus Srom access in fcr0: */ | |
67 | #define PCMCIA_ADDR0 (0x072e / 2) | |
68 | #define PCMCIA_ADDR1 (0x0730 / 2) | |
69 | #define PCMCIA_ADDR2 (0x0732 / 2) | |
70 | ||
71 | #define MEM_SEG (0x0734 / 2) | |
72 | #define SROM_CS (0x0736 / 2) | |
73 | #define SROM_DATAL (0x0738 / 2) | |
74 | #define SROM_DATAH (0x073a / 2) | |
75 | #define SROM_ADDRL (0x073c / 2) | |
76 | #define SROM_ADDRH (0x073e / 2) | |
77 | #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ | |
78 | #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ | |
79 | ||
80 | /* Values for srom_cs: */ | |
81 | #define SROM_IDLE 0 | |
82 | #define SROM_WRITE 1 | |
83 | #define SROM_READ 2 | |
84 | #define SROM_WEN 4 | |
85 | #define SROM_WDS 7 | |
86 | #define SROM_DONE 8 | |
87 | ||
88 | /* Fields in srom_info: */ | |
89 | #define SRI_SZ_MASK 0x03 | |
90 | #define SRI_BLANK 0x04 | |
91 | #define SRI_OTP 0x80 | |
92 | ||
93 | #if !defined(ESTA_POSTMOGRIFY_REMOVAL) | |
94 | /* CIS stuff */ | |
95 | ||
96 | /* The CIS stops where the FCRs start */ | |
97 | #define CIS_SIZE PCMCIA_FCR | |
98 | ||
99 | /* CIS tuple length field max */ | |
100 | #define CIS_TUPLE_LEN_MAX 0xff | |
101 | ||
102 | /* Standard tuples we know about */ | |
103 | ||
104 | #define CISTPL_NULL 0x00 | |
105 | #define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */ | |
106 | #define CISTPL_MANFID 0x20 /* Manufacturer and device id */ | |
107 | #define CISTPL_FUNCID 0x21 /* Function identification */ | |
108 | #define CISTPL_FUNCE 0x22 /* Function extensions */ | |
109 | #define CISTPL_CFTABLE 0x1b /* Config table entry */ | |
110 | #define CISTPL_END 0xff /* End of the CIS tuple chain */ | |
111 | ||
25985edc | 112 | /* Function identifier provides context for the function extensions tuple */ |
a9533e7e HP |
113 | #define CISTPL_FID_SDIO 0x0c /* Extensions defined by SDIO spec */ |
114 | ||
115 | /* Function extensions for LANs (assumed for extensions other than SDIO) */ | |
116 | #define LAN_TECH 1 /* Technology type */ | |
117 | #define LAN_SPEED 2 /* Raw bit rate */ | |
118 | #define LAN_MEDIA 3 /* Transmission media */ | |
119 | #define LAN_NID 4 /* Node identification (aka MAC addr) */ | |
120 | #define LAN_CONN 5 /* Connector standard */ | |
121 | ||
122 | /* CFTable */ | |
123 | #define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */ | |
124 | #define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */ | |
125 | #define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */ | |
126 | ||
127 | /* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll | |
128 | * take one for HNBU, and use "extensions" (a la FUNCE) within it. | |
129 | */ | |
130 | ||
131 | #define CISTPL_BRCM_HNBU 0x80 | |
132 | ||
133 | /* Subtypes of BRCM_HNBU: */ | |
134 | ||
135 | #define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */ | |
136 | #define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */ | |
137 | #define HNBU_BOARDREV 0x02 /* One byte board revision */ | |
138 | #define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1) | |
139 | * or 9 (sromrev > 1) bytes | |
140 | */ | |
141 | #define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */ | |
142 | #define HNBU_CC 0x05 /* Default country code (sromrev == 1) */ | |
143 | #define HNBU_AA 0x06 /* Antennas available */ | |
144 | #define HNBU_AG 0x07 /* Antenna gain */ | |
145 | #define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */ | |
146 | #define HNBU_LEDS 0x09 /* LED set */ | |
147 | #define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl) | |
148 | * in rev 2 | |
149 | */ | |
150 | #define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */ | |
151 | #define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */ | |
152 | #define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */ | |
153 | #define HNBU_PAPARMS5G 0x0e /* 5G PA params */ | |
154 | #define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */ | |
155 | #define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */ | |
156 | #define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch, | |
157 | * 2 bytes, rev 3. | |
158 | */ | |
159 | #define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch, | |
160 | * 2 bytes, rev 3. | |
161 | */ | |
162 | #define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */ | |
163 | #define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */ | |
164 | #define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */ | |
165 | #define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */ | |
166 | #define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */ | |
167 | #define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */ | |
168 | #define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */ | |
169 | #define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */ | |
170 | #define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ | |
171 | #define HNBU_LEDDC 0x1c /* 2 bytes; LED duty cycle */ | |
172 | #define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */ | |
173 | #define HNBU_PAPARMS_SSLPNPHY 0x1e /* SSLPNPHY PA params */ | |
174 | #define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */ | |
175 | #define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */ | |
176 | #define HNBU_CHAINSWITCH 0x21 /* 2 byte; txchain, rxchain */ | |
177 | #define HNBU_REGREV 0x22 /* 1 byte; */ | |
178 | #define HNBU_FEM 0x23 /* 2 or 4 byte: 11n frontend specification */ | |
179 | #define HNBU_PAPARMS_C0 0x24 /* 8 or 30 bytes: 11n pa paramater for chain 0 */ | |
180 | #define HNBU_PAPARMS_C1 0x25 /* 8 or 30 bytes: 11n pa paramater for chain 1 */ | |
181 | #define HNBU_PAPARMS_C2 0x26 /* 8 or 30 bytes: 11n pa paramater for chain 2 */ | |
182 | #define HNBU_PAPARMS_C3 0x27 /* 8 or 30 bytes: 11n pa paramater for chain 3 */ | |
183 | #define HNBU_PO_CCKOFDM 0x28 /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */ | |
184 | #define HNBU_PO_MCS2G 0x29 /* 8 bytes: mcs2g power offset */ | |
185 | #define HNBU_PO_MCS5GM 0x2a /* 8 bytes: mcs5g mid band power offset */ | |
186 | #define HNBU_PO_MCS5GLH 0x2b /* 16 bytes: mcs5g low-high band power offset */ | |
187 | #define HNBU_PO_CDD 0x2c /* 2 bytes: cdd2g/5g power offset */ | |
188 | #define HNBU_PO_STBC 0x2d /* 2 bytes: stbc2g/5g power offset */ | |
189 | #define HNBU_PO_40M 0x2e /* 2 bytes: 40Mhz channel 2g/5g power offset */ | |
190 | #define HNBU_PO_40MDUP 0x2f /* 2 bytes: 40Mhz channel dup 2g/5g power offset */ | |
191 | ||
192 | #define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */ | |
193 | #define HNBU_WPS 0x31 /* 1 byte; GPIO pin for WPS button */ | |
194 | #define HNBU_USBFS 0x32 /* 1 byte; 1 = USB advertises FS mode only */ | |
195 | #define HNBU_BRMIN 0x33 /* 4 byte bootloader min resource mask */ | |
196 | #define HNBU_BRMAX 0x34 /* 4 byte bootloader max resource mask */ | |
197 | #define HNBU_PATCH 0x35 /* bootloader patch addr(2b) & data(4b) pair */ | |
198 | #define HNBU_CCKFILTTYPE 0x36 /* CCK digital filter selection options */ | |
199 | #define HNBU_OFDMPO5G 0x37 /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */ | |
200 | ||
201 | #define HNBU_USBEPNUM 0x40 /* USB endpoint numbers */ | |
202 | #define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8 | |
203 | * plus extra info appended. | |
204 | */ | |
205 | #define HNBU_RESERVED 0x81 /* Reserved for non-BRCM post-mfg additions */ | |
206 | #define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */ | |
207 | #define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */ | |
208 | #endif /* !defined(ESTA_POSTMOGRIFY_REMOVAL) */ | |
209 | ||
210 | /* sbtmstatelow */ | |
211 | #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ | |
212 | #define SBTML_INT_EN 0x20000 /* enable sb interrupt */ | |
213 | ||
214 | /* sbtmstatehigh */ | |
215 | #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ | |
216 | ||
217 | #endif /* _SBPCMCIA_H */ |