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61e115a5 MB |
1 | /* |
2 | * Sonics Silicon Backplane | |
3 | * Broadcom PCI-core driver | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
6 | * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> | |
7 | * | |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
11 | #include <linux/ssb/ssb.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/delay.h> | |
7cb44615 | 14 | #include <linux/ssb/ssb_embedded.h> |
61e115a5 MB |
15 | |
16 | #include "ssb_private.h" | |
17 | ||
18 | ||
19 | static inline | |
20 | u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) | |
21 | { | |
22 | return ssb_read32(pc->dev, offset); | |
23 | } | |
24 | ||
25 | static inline | |
26 | void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) | |
27 | { | |
28 | ssb_write32(pc->dev, offset, value); | |
29 | } | |
30 | ||
7cb44615 MB |
31 | static inline |
32 | u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset) | |
33 | { | |
34 | return ssb_read16(pc->dev, offset); | |
35 | } | |
36 | ||
37 | static inline | |
38 | void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value) | |
39 | { | |
40 | ssb_write16(pc->dev, offset, value); | |
41 | } | |
42 | ||
61e115a5 MB |
43 | /************************************************** |
44 | * Code for hostmode operation. | |
45 | **************************************************/ | |
46 | ||
47 | #ifdef CONFIG_SSB_PCICORE_HOSTMODE | |
48 | ||
49 | #include <asm/paccess.h> | |
50 | /* Probe a 32bit value on the bus and catch bus exceptions. | |
51 | * Returns nonzero on a bus exception. | |
52 | * This is MIPS specific */ | |
53 | #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) | |
54 | ||
55 | /* Assume one-hot slot wiring */ | |
56 | #define SSB_PCI_SLOT_MAX 16 | |
57 | ||
58 | /* Global lock is OK, as we won't have more than one extpci anyway. */ | |
59 | static DEFINE_SPINLOCK(cfgspace_lock); | |
60 | /* Core to access the external PCI config space. Can only have one. */ | |
61 | static struct ssb_pcicore *extpci_core; | |
62 | ||
63 | static u32 ssb_pcicore_pcibus_iobase = 0x100; | |
64 | static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA; | |
65 | ||
66 | int pcibios_plat_dev_init(struct pci_dev *d) | |
67 | { | |
68 | struct resource *res; | |
69 | int pos, size; | |
70 | u32 *base; | |
71 | ||
72 | ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", | |
73 | pci_name(d)); | |
74 | ||
75 | /* Fix up resource bases */ | |
76 | for (pos = 0; pos < 6; pos++) { | |
77 | res = &d->resource[pos]; | |
78 | if (res->flags & IORESOURCE_IO) | |
79 | base = &ssb_pcicore_pcibus_iobase; | |
80 | else | |
81 | base = &ssb_pcicore_pcibus_membase; | |
82 | if (res->end) { | |
83 | size = res->end - res->start + 1; | |
84 | if (*base & (size - 1)) | |
85 | *base = (*base + size) & ~(size - 1); | |
86 | res->start = *base; | |
87 | res->end = res->start + size - 1; | |
88 | *base += size; | |
89 | pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); | |
90 | } | |
91 | /* Fix up PCI bridge BAR0 only */ | |
92 | if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0) | |
93 | break; | |
94 | } | |
95 | /* Fix up interrupt lines */ | |
96 | d->irq = ssb_mips_irq(extpci_core->dev) + 2; | |
97 | pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
102 | static void __init ssb_fixup_pcibridge(struct pci_dev *dev) | |
103 | { | |
104 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) | |
105 | return; | |
106 | ||
107 | ssb_printk(KERN_INFO "PCI: fixing up bridge\n"); | |
108 | ||
109 | /* Enable PCI bridge bus mastering and memory space */ | |
110 | pci_set_master(dev); | |
111 | pcibios_enable_device(dev, ~0); | |
112 | ||
113 | /* Enable PCI bridge BAR1 prefetch and burst */ | |
114 | pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); | |
115 | ||
116 | /* Make sure our latency is high enough to handle the devices behind us */ | |
117 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8); | |
118 | } | |
119 | DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge); | |
120 | ||
121 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
122 | { | |
123 | return ssb_mips_irq(extpci_core->dev) + 2; | |
124 | } | |
125 | ||
126 | static u32 get_cfgspace_addr(struct ssb_pcicore *pc, | |
127 | unsigned int bus, unsigned int dev, | |
128 | unsigned int func, unsigned int off) | |
129 | { | |
130 | u32 addr = 0; | |
131 | u32 tmp; | |
132 | ||
7cb44615 MB |
133 | /* We do only have one cardbus device behind the bridge. */ |
134 | if (pc->cardbusmode && (dev >= 1)) | |
61e115a5 | 135 | goto out; |
7cb44615 | 136 | |
61e115a5 MB |
137 | if (bus == 0) { |
138 | /* Type 0 transaction */ | |
139 | if (unlikely(dev >= SSB_PCI_SLOT_MAX)) | |
140 | goto out; | |
141 | /* Slide the window */ | |
142 | tmp = SSB_PCICORE_SBTOPCI_CFG0; | |
143 | tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK); | |
144 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); | |
145 | /* Calculate the address */ | |
146 | addr = SSB_PCI_CFG; | |
147 | addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK); | |
148 | addr |= (func << 8); | |
149 | addr |= (off & ~3); | |
150 | } else { | |
151 | /* Type 1 transaction */ | |
152 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, | |
153 | SSB_PCICORE_SBTOPCI_CFG1); | |
154 | /* Calculate the address */ | |
155 | addr = SSB_PCI_CFG; | |
156 | addr |= (bus << 16); | |
157 | addr |= (dev << 11); | |
158 | addr |= (func << 8); | |
159 | addr |= (off & ~3); | |
160 | } | |
161 | out: | |
162 | return addr; | |
163 | } | |
164 | ||
165 | static int ssb_extpci_read_config(struct ssb_pcicore *pc, | |
166 | unsigned int bus, unsigned int dev, | |
167 | unsigned int func, unsigned int off, | |
168 | void *buf, int len) | |
169 | { | |
170 | int err = -EINVAL; | |
171 | u32 addr, val; | |
172 | void __iomem *mmio; | |
173 | ||
174 | SSB_WARN_ON(!pc->hostmode); | |
175 | if (unlikely(len != 1 && len != 2 && len != 4)) | |
176 | goto out; | |
177 | addr = get_cfgspace_addr(pc, bus, dev, func, off); | |
178 | if (unlikely(!addr)) | |
179 | goto out; | |
180 | err = -ENOMEM; | |
181 | mmio = ioremap_nocache(addr, len); | |
182 | if (!mmio) | |
183 | goto out; | |
184 | ||
185 | if (mips_busprobe32(val, mmio)) { | |
186 | val = 0xffffffff; | |
187 | goto unmap; | |
188 | } | |
189 | ||
190 | val = readl(mmio); | |
191 | val >>= (8 * (off & 3)); | |
192 | ||
193 | switch (len) { | |
194 | case 1: | |
195 | *((u8 *)buf) = (u8)val; | |
196 | break; | |
197 | case 2: | |
198 | *((u16 *)buf) = (u16)val; | |
199 | break; | |
200 | case 4: | |
201 | *((u32 *)buf) = (u32)val; | |
202 | break; | |
203 | } | |
204 | err = 0; | |
205 | unmap: | |
206 | iounmap(mmio); | |
207 | out: | |
208 | return err; | |
209 | } | |
210 | ||
211 | static int ssb_extpci_write_config(struct ssb_pcicore *pc, | |
212 | unsigned int bus, unsigned int dev, | |
213 | unsigned int func, unsigned int off, | |
214 | const void *buf, int len) | |
215 | { | |
216 | int err = -EINVAL; | |
217 | u32 addr, val = 0; | |
218 | void __iomem *mmio; | |
219 | ||
220 | SSB_WARN_ON(!pc->hostmode); | |
221 | if (unlikely(len != 1 && len != 2 && len != 4)) | |
222 | goto out; | |
223 | addr = get_cfgspace_addr(pc, bus, dev, func, off); | |
224 | if (unlikely(!addr)) | |
225 | goto out; | |
226 | err = -ENOMEM; | |
227 | mmio = ioremap_nocache(addr, len); | |
228 | if (!mmio) | |
229 | goto out; | |
230 | ||
231 | if (mips_busprobe32(val, mmio)) { | |
232 | val = 0xffffffff; | |
233 | goto unmap; | |
234 | } | |
235 | ||
236 | switch (len) { | |
237 | case 1: | |
238 | val = readl(mmio); | |
239 | val &= ~(0xFF << (8 * (off & 3))); | |
240 | val |= *((const u8 *)buf) << (8 * (off & 3)); | |
241 | break; | |
242 | case 2: | |
243 | val = readl(mmio); | |
244 | val &= ~(0xFFFF << (8 * (off & 3))); | |
245 | val |= *((const u16 *)buf) << (8 * (off & 3)); | |
246 | break; | |
247 | case 4: | |
248 | val = *((const u32 *)buf); | |
249 | break; | |
250 | } | |
251 | writel(val, mmio); | |
252 | ||
253 | err = 0; | |
254 | unmap: | |
255 | iounmap(mmio); | |
256 | out: | |
257 | return err; | |
258 | } | |
259 | ||
260 | static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn, | |
261 | int reg, int size, u32 *val) | |
262 | { | |
263 | unsigned long flags; | |
264 | int err; | |
265 | ||
266 | spin_lock_irqsave(&cfgspace_lock, flags); | |
267 | err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn), | |
268 | PCI_FUNC(devfn), reg, val, size); | |
269 | spin_unlock_irqrestore(&cfgspace_lock, flags); | |
270 | ||
271 | return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; | |
272 | } | |
273 | ||
274 | static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn, | |
275 | int reg, int size, u32 val) | |
276 | { | |
277 | unsigned long flags; | |
278 | int err; | |
279 | ||
280 | spin_lock_irqsave(&cfgspace_lock, flags); | |
281 | err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn), | |
282 | PCI_FUNC(devfn), reg, &val, size); | |
283 | spin_unlock_irqrestore(&cfgspace_lock, flags); | |
284 | ||
285 | return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; | |
286 | } | |
287 | ||
288 | static struct pci_ops ssb_pcicore_pciops = { | |
289 | .read = ssb_pcicore_read_config, | |
290 | .write = ssb_pcicore_write_config, | |
291 | }; | |
292 | ||
293 | static struct resource ssb_pcicore_mem_resource = { | |
294 | .name = "SSB PCIcore external memory", | |
295 | .start = SSB_PCI_DMA, | |
296 | .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1, | |
297 | .flags = IORESOURCE_MEM, | |
298 | }; | |
299 | ||
300 | static struct resource ssb_pcicore_io_resource = { | |
301 | .name = "SSB PCIcore external I/O", | |
302 | .start = 0x100, | |
303 | .end = 0x7FF, | |
304 | .flags = IORESOURCE_IO, | |
305 | }; | |
306 | ||
307 | static struct pci_controller ssb_pcicore_controller = { | |
308 | .pci_ops = &ssb_pcicore_pciops, | |
309 | .io_resource = &ssb_pcicore_io_resource, | |
310 | .mem_resource = &ssb_pcicore_mem_resource, | |
311 | .mem_offset = 0x24000000, | |
312 | }; | |
313 | ||
314 | static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) | |
315 | { | |
316 | u32 val; | |
317 | ||
318 | if (WARN_ON(extpci_core)) | |
319 | return; | |
320 | extpci_core = pc; | |
321 | ||
322 | ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); | |
323 | /* Reset devices on the external PCI bus */ | |
324 | val = SSB_PCICORE_CTL_RST_OE; | |
325 | val |= SSB_PCICORE_CTL_CLK_OE; | |
326 | pcicore_write32(pc, SSB_PCICORE_CTL, val); | |
327 | val |= SSB_PCICORE_CTL_CLK; /* Clock on */ | |
328 | pcicore_write32(pc, SSB_PCICORE_CTL, val); | |
329 | udelay(150); /* Assertion time demanded by the PCI standard */ | |
330 | val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ | |
331 | pcicore_write32(pc, SSB_PCICORE_CTL, val); | |
332 | val = SSB_PCICORE_ARBCTL_INTERN; | |
333 | pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); | |
334 | udelay(1); /* Assertion time demanded by the PCI standard */ | |
335 | ||
7cb44615 MB |
336 | if (pc->dev->bus->has_cardbus_slot) { |
337 | ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); | |
338 | pc->cardbusmode = 1; | |
339 | /* GPIO 1 resets the bridge */ | |
340 | ssb_gpio_out(pc->dev->bus, 1, 1); | |
341 | ssb_gpio_outen(pc->dev->bus, 1, 1); | |
342 | pcicore_write16(pc, SSB_PCICORE_SPROM(0), | |
343 | pcicore_read16(pc, SSB_PCICORE_SPROM(0)) | |
344 | | 0x0400); | |
345 | } | |
61e115a5 MB |
346 | |
347 | /* 64MB I/O window */ | |
348 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, | |
349 | SSB_PCICORE_SBTOPCI_IO); | |
350 | /* 64MB config space */ | |
351 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, | |
352 | SSB_PCICORE_SBTOPCI_CFG0); | |
353 | /* 1GB memory window */ | |
354 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, | |
355 | SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); | |
356 | ||
357 | /* Enable PCI bridge BAR0 prefetch and burst */ | |
358 | val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | |
359 | ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); | |
360 | /* Clear error conditions */ | |
361 | val = 0; | |
362 | ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); | |
363 | ||
364 | /* Enable PCI interrupts */ | |
365 | pcicore_write32(pc, SSB_PCICORE_IMASK, | |
366 | SSB_PCICORE_IMASK_INTA); | |
367 | ||
368 | /* Ok, ready to run, register it to the system. | |
369 | * The following needs change, if we want to port hostmode | |
370 | * to non-MIPS platform. */ | |
371 | set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000)); | |
372 | /* Give some time to the PCI controller to configure itself with the new | |
373 | * values. Not waiting at this point causes crashes of the machine. */ | |
374 | mdelay(10); | |
375 | register_pci_controller(&ssb_pcicore_controller); | |
376 | } | |
377 | ||
378 | static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) | |
379 | { | |
380 | struct ssb_bus *bus = pc->dev->bus; | |
381 | u16 chipid_top; | |
382 | u32 tmp; | |
383 | ||
384 | chipid_top = (bus->chip_id & 0xFF00); | |
385 | if (chipid_top != 0x4700 && | |
386 | chipid_top != 0x5300) | |
387 | return 0; | |
388 | ||
389 | if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI) | |
390 | return 0; | |
391 | ||
392 | /* The 200-pin BCM4712 package does not bond out PCI. Even when | |
393 | * PCI is bonded out, some boards may leave the pins floating. */ | |
394 | if (bus->chip_id == 0x4712) { | |
395 | if (bus->chip_package == SSB_CHIPPACK_BCM4712S) | |
396 | return 0; | |
397 | if (bus->chip_package == SSB_CHIPPACK_BCM4712M) | |
398 | return 0; | |
399 | } | |
400 | if (bus->chip_id == 0x5350) | |
401 | return 0; | |
402 | ||
403 | return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); | |
404 | } | |
405 | #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ | |
406 | ||
407 | ||
408 | /************************************************** | |
409 | * Generic and Clientmode operation code. | |
410 | **************************************************/ | |
411 | ||
412 | static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) | |
413 | { | |
414 | /* Disable PCI interrupts. */ | |
415 | ssb_write32(pc->dev, SSB_INTVEC, 0); | |
416 | } | |
417 | ||
418 | void ssb_pcicore_init(struct ssb_pcicore *pc) | |
419 | { | |
420 | struct ssb_device *dev = pc->dev; | |
421 | struct ssb_bus *bus; | |
422 | ||
423 | if (!dev) | |
424 | return; | |
425 | bus = dev->bus; | |
426 | if (!ssb_device_is_enabled(dev)) | |
427 | ssb_device_enable(dev, 0); | |
428 | ||
429 | #ifdef CONFIG_SSB_PCICORE_HOSTMODE | |
430 | pc->hostmode = pcicore_is_in_hostmode(pc); | |
431 | if (pc->hostmode) | |
432 | ssb_pcicore_init_hostmode(pc); | |
433 | #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ | |
434 | if (!pc->hostmode) | |
435 | ssb_pcicore_init_clientmode(pc); | |
436 | } | |
437 | ||
438 | static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) | |
439 | { | |
440 | pcicore_write32(pc, 0x130, address); | |
441 | return pcicore_read32(pc, 0x134); | |
442 | } | |
443 | ||
444 | static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) | |
445 | { | |
446 | pcicore_write32(pc, 0x130, address); | |
447 | pcicore_write32(pc, 0x134, data); | |
448 | } | |
449 | ||
450 | static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, | |
451 | u8 address, u16 data) | |
452 | { | |
453 | const u16 mdio_control = 0x128; | |
454 | const u16 mdio_data = 0x12C; | |
455 | u32 v; | |
456 | int i; | |
457 | ||
458 | v = 0x80; /* Enable Preamble Sequence */ | |
459 | v |= 0x2; /* MDIO Clock Divisor */ | |
460 | pcicore_write32(pc, mdio_control, v); | |
461 | ||
462 | v = (1 << 30); /* Start of Transaction */ | |
463 | v |= (1 << 28); /* Write Transaction */ | |
464 | v |= (1 << 17); /* Turnaround */ | |
465 | v |= (u32)device << 22; | |
466 | v |= (u32)address << 18; | |
467 | v |= data; | |
468 | pcicore_write32(pc, mdio_data, v); | |
469 | /* Wait for the device to complete the transaction */ | |
470 | udelay(10); | |
471 | for (i = 0; i < 10; i++) { | |
472 | v = pcicore_read32(pc, mdio_control); | |
473 | if (v & 0x100 /* Trans complete */) | |
474 | break; | |
475 | msleep(1); | |
476 | } | |
477 | pcicore_write32(pc, mdio_control, 0); | |
478 | } | |
479 | ||
480 | static void ssb_broadcast_value(struct ssb_device *dev, | |
481 | u32 address, u32 data) | |
482 | { | |
483 | /* This is used for both, PCI and ChipCommon core, so be careful. */ | |
484 | BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); | |
485 | BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); | |
486 | ||
487 | ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); | |
488 | ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ | |
489 | ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); | |
490 | ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ | |
491 | } | |
492 | ||
493 | static void ssb_commit_settings(struct ssb_bus *bus) | |
494 | { | |
495 | struct ssb_device *dev; | |
496 | ||
497 | dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; | |
498 | if (WARN_ON(!dev)) | |
499 | return; | |
500 | /* This forces an update of the cached registers. */ | |
501 | ssb_broadcast_value(dev, 0xFD8, 0); | |
502 | } | |
503 | ||
504 | int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, | |
505 | struct ssb_device *dev) | |
506 | { | |
507 | struct ssb_device *pdev = pc->dev; | |
508 | struct ssb_bus *bus; | |
509 | int err = 0; | |
510 | u32 tmp; | |
511 | ||
512 | might_sleep(); | |
513 | ||
514 | if (!pdev) | |
515 | goto out; | |
516 | bus = pdev->bus; | |
517 | ||
518 | /* Enable interrupts for this device. */ | |
519 | if (bus->host_pci && | |
520 | ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) { | |
521 | u32 coremask; | |
522 | ||
523 | /* Calculate the "coremask" for the device. */ | |
524 | coremask = (1 << dev->core_index); | |
525 | ||
526 | err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); | |
527 | if (err) | |
528 | goto out; | |
529 | tmp |= coremask << 8; | |
530 | err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp); | |
531 | if (err) | |
532 | goto out; | |
533 | } else { | |
534 | u32 intvec; | |
535 | ||
536 | intvec = ssb_read32(pdev, SSB_INTVEC); | |
537 | if ((bus->chip_id & 0xFF00) == 0x4400) { | |
538 | /* Workaround: On the BCM44XX the BPFLAG routing | |
539 | * bit is wrong. Use a hardcoded constant. */ | |
540 | intvec |= 0x00000002; | |
541 | } else { | |
542 | tmp = ssb_read32(dev, SSB_TPSFLAG); | |
543 | tmp &= SSB_TPSFLAG_BPFLAG; | |
544 | intvec |= tmp; | |
545 | } | |
546 | ssb_write32(pdev, SSB_INTVEC, intvec); | |
547 | } | |
548 | ||
549 | /* Setup PCIcore operation. */ | |
550 | if (pc->setup_done) | |
551 | goto out; | |
552 | if (pdev->id.coreid == SSB_DEV_PCI) { | |
553 | tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); | |
554 | tmp |= SSB_PCICORE_SBTOPCI_PREF; | |
555 | tmp |= SSB_PCICORE_SBTOPCI_BURST; | |
556 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); | |
557 | ||
558 | if (pdev->id.revision < 5) { | |
559 | tmp = ssb_read32(pdev, SSB_IMCFGLO); | |
560 | tmp &= ~SSB_IMCFGLO_SERTO; | |
561 | tmp |= 2; | |
562 | tmp &= ~SSB_IMCFGLO_REQTO; | |
563 | tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; | |
564 | ssb_write32(pdev, SSB_IMCFGLO, tmp); | |
565 | ssb_commit_settings(bus); | |
566 | } else if (pdev->id.revision >= 11) { | |
567 | tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); | |
568 | tmp |= SSB_PCICORE_SBTOPCI_MRM; | |
569 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); | |
570 | } | |
571 | } else { | |
572 | WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); | |
573 | //TODO: Better make defines for all these magic PCIE values. | |
574 | if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) { | |
575 | /* TLP Workaround register. */ | |
576 | tmp = ssb_pcie_read(pc, 0x4); | |
577 | tmp |= 0x8; | |
578 | ssb_pcie_write(pc, 0x4, tmp); | |
579 | } | |
580 | if (pdev->id.revision == 0) { | |
581 | const u8 serdes_rx_device = 0x1F; | |
582 | ||
583 | ssb_pcie_mdio_write(pc, serdes_rx_device, | |
584 | 2 /* Timer */, 0x8128); | |
585 | ssb_pcie_mdio_write(pc, serdes_rx_device, | |
586 | 6 /* CDR */, 0x0100); | |
587 | ssb_pcie_mdio_write(pc, serdes_rx_device, | |
588 | 7 /* CDR BW */, 0x1466); | |
589 | } else if (pdev->id.revision == 1) { | |
590 | /* DLLP Link Control register. */ | |
591 | tmp = ssb_pcie_read(pc, 0x100); | |
592 | tmp |= 0x40; | |
593 | ssb_pcie_write(pc, 0x100, tmp); | |
594 | } | |
595 | } | |
596 | pc->setup_done = 1; | |
597 | out: | |
598 | return err; | |
599 | } | |
600 | EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable); |