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ae918c02 AK |
1 | /* |
2 | * xilinx_spi.c | |
3 | * | |
4 | * Xilinx SPI controller driver (master mode only) | |
5 | * | |
6 | * Author: MontaVista Software, Inc. | |
7 | * source@mvista.com | |
8 | * | |
9 | * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is licensed | |
11 | * "as is" without any warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
ff82c587 | 17 | |
ae918c02 AK |
18 | #include <linux/spi/spi.h> |
19 | #include <linux/spi/spi_bitbang.h> | |
20 | #include <linux/io.h> | |
21 | ||
d5af91a1 RR |
22 | #include "xilinx_spi.h" |
23 | #include <linux/spi/xilinx_spi.h> | |
24 | ||
fc3ba952 | 25 | #define XILINX_SPI_NAME "xilinx_spi" |
ae918c02 AK |
26 | |
27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | |
28 | * Product Specification", DS464 | |
29 | */ | |
c9da2e12 | 30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
ae918c02 AK |
31 | |
32 | #define XSPI_CR_ENABLE 0x02 | |
33 | #define XSPI_CR_MASTER_MODE 0x04 | |
34 | #define XSPI_CR_CPOL 0x08 | |
35 | #define XSPI_CR_CPHA 0x10 | |
36 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) | |
37 | #define XSPI_CR_TXFIFO_RESET 0x20 | |
38 | #define XSPI_CR_RXFIFO_RESET 0x40 | |
39 | #define XSPI_CR_MANUAL_SSELECT 0x80 | |
40 | #define XSPI_CR_TRANS_INHIBIT 0x100 | |
c9da2e12 | 41 | #define XSPI_CR_LSB_FIRST 0x200 |
ae918c02 | 42 | |
c9da2e12 | 43 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
ae918c02 AK |
44 | |
45 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | |
46 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | |
47 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ | |
48 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | |
49 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | |
50 | ||
c9da2e12 RR |
51 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
52 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ | |
ae918c02 AK |
53 | |
54 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | |
55 | ||
56 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 | |
57 | * IPIF registers are 32 bit | |
58 | */ | |
59 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ | |
60 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 | |
61 | ||
62 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ | |
63 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ | |
64 | ||
65 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ | |
66 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while | |
67 | * disabled */ | |
68 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ | |
69 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | |
70 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | |
71 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | |
c9da2e12 | 72 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
ae918c02 AK |
73 | |
74 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | |
75 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | |
76 | ||
77 | struct xilinx_spi { | |
78 | /* bitbang has to be first */ | |
79 | struct spi_bitbang bitbang; | |
80 | struct completion done; | |
d5af91a1 | 81 | struct resource mem; /* phys mem */ |
ae918c02 AK |
82 | void __iomem *regs; /* virt. address of the control registers */ |
83 | ||
84 | u32 irq; | |
85 | ||
ae918c02 AK |
86 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
87 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | |
88 | int remaining_bytes; /* the number of bytes left to transfer */ | |
c9da2e12 | 89 | u8 bits_per_word; |
86fc5935 RR |
90 | unsigned int (*read_fn) (void __iomem *); |
91 | void (*write_fn) (u32, void __iomem *); | |
c9da2e12 RR |
92 | void (*tx_fn) (struct xilinx_spi *); |
93 | void (*rx_fn) (struct xilinx_spi *); | |
ae918c02 AK |
94 | }; |
95 | ||
97782149 PM |
96 | static void xspi_write32(u32 val, void __iomem *addr) |
97 | { | |
98 | iowrite32(val, addr); | |
99 | } | |
100 | ||
101 | static unsigned int xspi_read32(void __iomem *addr) | |
102 | { | |
103 | return ioread32(addr); | |
104 | } | |
105 | ||
106 | static void xspi_write32_be(u32 val, void __iomem *addr) | |
107 | { | |
108 | iowrite32be(val, addr); | |
109 | } | |
110 | ||
111 | static unsigned int xspi_read32_be(void __iomem *addr) | |
112 | { | |
113 | return ioread32be(addr); | |
114 | } | |
115 | ||
c9da2e12 RR |
116 | static void xspi_tx8(struct xilinx_spi *xspi) |
117 | { | |
118 | xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); | |
119 | xspi->tx_ptr++; | |
120 | } | |
121 | ||
122 | static void xspi_tx16(struct xilinx_spi *xspi) | |
123 | { | |
124 | xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
125 | xspi->tx_ptr += 2; | |
126 | } | |
127 | ||
128 | static void xspi_tx32(struct xilinx_spi *xspi) | |
129 | { | |
130 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
131 | xspi->tx_ptr += 4; | |
132 | } | |
133 | ||
134 | static void xspi_rx8(struct xilinx_spi *xspi) | |
135 | { | |
136 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
137 | if (xspi->rx_ptr) { | |
138 | *xspi->rx_ptr = data & 0xff; | |
139 | xspi->rx_ptr++; | |
140 | } | |
141 | } | |
142 | ||
143 | static void xspi_rx16(struct xilinx_spi *xspi) | |
144 | { | |
145 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
146 | if (xspi->rx_ptr) { | |
147 | *(u16 *)(xspi->rx_ptr) = data & 0xffff; | |
148 | xspi->rx_ptr += 2; | |
149 | } | |
150 | } | |
151 | ||
152 | static void xspi_rx32(struct xilinx_spi *xspi) | |
153 | { | |
154 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
155 | if (xspi->rx_ptr) { | |
156 | *(u32 *)(xspi->rx_ptr) = data; | |
157 | xspi->rx_ptr += 4; | |
158 | } | |
159 | } | |
160 | ||
86fc5935 | 161 | static void xspi_init_hw(struct xilinx_spi *xspi) |
ae918c02 | 162 | { |
86fc5935 RR |
163 | void __iomem *regs_base = xspi->regs; |
164 | ||
ae918c02 | 165 | /* Reset the SPI device */ |
86fc5935 RR |
166 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
167 | regs_base + XIPIF_V123B_RESETR_OFFSET); | |
ae918c02 | 168 | /* Disable all the interrupts just in case */ |
86fc5935 | 169 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); |
ae918c02 | 170 | /* Enable the global IPIF interrupt */ |
86fc5935 RR |
171 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, |
172 | regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ae918c02 | 173 | /* Deselect the slave on the SPI bus */ |
86fc5935 | 174 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
ae918c02 AK |
175 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
176 | * put SPI controller into master mode, and enable it */ | |
86fc5935 | 177 | xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | |
c9da2e12 RR |
178 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | |
179 | XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); | |
ae918c02 AK |
180 | } |
181 | ||
182 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |
183 | { | |
184 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
185 | ||
186 | if (is_on == BITBANG_CS_INACTIVE) { | |
187 | /* Deselect the slave on the SPI bus */ | |
86fc5935 | 188 | xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); |
ae918c02 AK |
189 | } else if (is_on == BITBANG_CS_ACTIVE) { |
190 | /* Set the SPI clock phase and polarity */ | |
86fc5935 | 191 | u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) |
ae918c02 AK |
192 | & ~XSPI_CR_MODE_MASK; |
193 | if (spi->mode & SPI_CPHA) | |
194 | cr |= XSPI_CR_CPHA; | |
195 | if (spi->mode & SPI_CPOL) | |
196 | cr |= XSPI_CR_CPOL; | |
86fc5935 | 197 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
ae918c02 AK |
198 | |
199 | /* We do not check spi->max_speed_hz here as the SPI clock | |
200 | * frequency is not software programmable (the IP block design | |
201 | * parameter) | |
202 | */ | |
203 | ||
204 | /* Activate the chip select */ | |
86fc5935 RR |
205 | xspi->write_fn(~(0x0001 << spi->chip_select), |
206 | xspi->regs + XSPI_SSR_OFFSET); | |
ae918c02 AK |
207 | } |
208 | } | |
209 | ||
210 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | |
211 | * custom txrx_bufs(). We have nothing to setup here as the SPI IP block | |
c9da2e12 RR |
212 | * supports 8 or 16 bits per word which cannot be changed in software. |
213 | * SPI clock can't be changed in software either. | |
214 | * Check for correct bits per word. Chip select delay calculations could be | |
ae918c02 AK |
215 | * added here as soon as bitbang_work() can be made aware of the delay value. |
216 | */ | |
217 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | |
218 | struct spi_transfer *t) | |
219 | { | |
c9da2e12 | 220 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
ae918c02 | 221 | u8 bits_per_word; |
ae918c02 | 222 | |
1a8d3b77 JL |
223 | bits_per_word = (t && t->bits_per_word) |
224 | ? t->bits_per_word : spi->bits_per_word; | |
c9da2e12 | 225 | if (bits_per_word != xspi->bits_per_word) { |
ae918c02 | 226 | dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", |
b687d2a8 | 227 | __func__, bits_per_word); |
ae918c02 AK |
228 | return -EINVAL; |
229 | } | |
230 | ||
ae918c02 AK |
231 | return 0; |
232 | } | |
233 | ||
ae918c02 AK |
234 | static int xilinx_spi_setup(struct spi_device *spi) |
235 | { | |
c9da2e12 RR |
236 | /* always return 0, we can not check the number of bits. |
237 | * There are cases when SPI setup is called before any driver is | |
238 | * there, in that case the SPI core defaults to 8 bits, which we | |
239 | * do not support in some cases. But if we return an error, the | |
240 | * SPI device would not be registered and no driver can get hold of it | |
241 | * When the driver is there, it will call SPI setup again with the | |
242 | * correct number of bits per transfer. | |
243 | * If a driver setups with the wrong bit number, it will fail when | |
244 | * it tries to do a transfer | |
245 | */ | |
ae918c02 AK |
246 | return 0; |
247 | } | |
248 | ||
249 | static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) | |
250 | { | |
251 | u8 sr; | |
252 | ||
253 | /* Fill the Tx FIFO with as many bytes as possible */ | |
86fc5935 | 254 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 | 255 | while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { |
86fc5935 | 256 | if (xspi->tx_ptr) |
c9da2e12 | 257 | xspi->tx_fn(xspi); |
86fc5935 RR |
258 | else |
259 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
c9da2e12 | 260 | xspi->remaining_bytes -= xspi->bits_per_word / 8; |
86fc5935 | 261 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 AK |
262 | } |
263 | } | |
264 | ||
265 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | |
266 | { | |
267 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
268 | u32 ipif_ier; | |
269 | u16 cr; | |
270 | ||
271 | /* We get here with transmitter inhibited */ | |
272 | ||
273 | xspi->tx_ptr = t->tx_buf; | |
274 | xspi->rx_ptr = t->rx_buf; | |
275 | xspi->remaining_bytes = t->len; | |
276 | INIT_COMPLETION(xspi->done); | |
277 | ||
278 | xilinx_spi_fill_tx_fifo(xspi); | |
279 | ||
280 | /* Enable the transmit empty interrupt, which we use to determine | |
281 | * progress on the transmission. | |
282 | */ | |
86fc5935 RR |
283 | ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); |
284 | xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, | |
285 | xspi->regs + XIPIF_V123B_IIER_OFFSET); | |
ae918c02 AK |
286 | |
287 | /* Start the transfer by not inhibiting the transmitter any longer */ | |
86fc5935 RR |
288 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & |
289 | ~XSPI_CR_TRANS_INHIBIT; | |
290 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
ae918c02 AK |
291 | |
292 | wait_for_completion(&xspi->done); | |
293 | ||
294 | /* Disable the transmit empty interrupt */ | |
86fc5935 | 295 | xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); |
ae918c02 AK |
296 | |
297 | return t->len - xspi->remaining_bytes; | |
298 | } | |
299 | ||
300 | ||
301 | /* This driver supports single master mode only. Hence Tx FIFO Empty | |
302 | * is the only interrupt we care about. | |
303 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode | |
304 | * Fault are not to happen. | |
305 | */ | |
306 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |
307 | { | |
308 | struct xilinx_spi *xspi = dev_id; | |
309 | u32 ipif_isr; | |
310 | ||
311 | /* Get the IPIF interrupts, and clear them immediately */ | |
86fc5935 RR |
312 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
313 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
ae918c02 AK |
314 | |
315 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ | |
316 | u16 cr; | |
317 | u8 sr; | |
318 | ||
319 | /* A transmit has just completed. Process received data and | |
320 | * check for more data to transmit. Always inhibit the | |
321 | * transmitter while the Isr refills the transmit register/FIFO, | |
322 | * or make sure it is stopped if we're done. | |
323 | */ | |
86fc5935 RR |
324 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); |
325 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | |
326 | xspi->regs + XSPI_CR_OFFSET); | |
ae918c02 AK |
327 | |
328 | /* Read out all the data from the Rx FIFO */ | |
86fc5935 | 329 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 | 330 | while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { |
c9da2e12 | 331 | xspi->rx_fn(xspi); |
86fc5935 | 332 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 AK |
333 | } |
334 | ||
335 | /* See if there is more data to send */ | |
336 | if (xspi->remaining_bytes > 0) { | |
337 | xilinx_spi_fill_tx_fifo(xspi); | |
338 | /* Start the transfer by not inhibiting the | |
339 | * transmitter any longer | |
340 | */ | |
86fc5935 | 341 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
ae918c02 AK |
342 | } else { |
343 | /* No more data to send. | |
344 | * Indicate the transfer is completed. | |
345 | */ | |
346 | complete(&xspi->done); | |
347 | } | |
348 | } | |
349 | ||
350 | return IRQ_HANDLED; | |
351 | } | |
352 | ||
d5af91a1 RR |
353 | struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem, |
354 | u32 irq, s16 bus_num) | |
ae918c02 | 355 | { |
ae918c02 AK |
356 | struct spi_master *master; |
357 | struct xilinx_spi *xspi; | |
d5af91a1 RR |
358 | struct xspi_platform_data *pdata = dev->platform_data; |
359 | int ret; | |
ae918c02 | 360 | |
d5af91a1 RR |
361 | if (!pdata) { |
362 | dev_err(dev, "No platform data attached\n"); | |
363 | return NULL; | |
ae918c02 AK |
364 | } |
365 | ||
d5af91a1 RR |
366 | master = spi_alloc_master(dev, sizeof(struct xilinx_spi)); |
367 | if (!master) | |
368 | return NULL; | |
ae918c02 | 369 | |
e7db06b5 DB |
370 | /* the spi->mode bits understood by this driver: */ |
371 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
372 | ||
ae918c02 AK |
373 | xspi = spi_master_get_devdata(master); |
374 | xspi->bitbang.master = spi_master_get(master); | |
375 | xspi->bitbang.chipselect = xilinx_spi_chipselect; | |
376 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | |
377 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; | |
378 | xspi->bitbang.master->setup = xilinx_spi_setup; | |
379 | init_completion(&xspi->done); | |
380 | ||
d5af91a1 RR |
381 | if (!request_mem_region(mem->start, resource_size(mem), |
382 | XILINX_SPI_NAME)) | |
ae918c02 | 383 | goto put_master; |
ae918c02 | 384 | |
d5af91a1 | 385 | xspi->regs = ioremap(mem->start, resource_size(mem)); |
ae918c02 | 386 | if (xspi->regs == NULL) { |
d5af91a1 RR |
387 | dev_warn(dev, "ioremap failure\n"); |
388 | goto map_failed; | |
ae918c02 AK |
389 | } |
390 | ||
d5af91a1 RR |
391 | master->bus_num = bus_num; |
392 | master->num_chipselect = pdata->num_chipselect; | |
12b15e83 AG |
393 | #ifdef CONFIG_OF |
394 | master->dev.of_node = dev->of_node; | |
395 | #endif | |
ae918c02 | 396 | |
d5af91a1 RR |
397 | xspi->mem = *mem; |
398 | xspi->irq = irq; | |
86fc5935 | 399 | if (pdata->little_endian) { |
97782149 PM |
400 | xspi->read_fn = xspi_read32; |
401 | xspi->write_fn = xspi_write32; | |
86fc5935 | 402 | } else { |
97782149 PM |
403 | xspi->read_fn = xspi_read32_be; |
404 | xspi->write_fn = xspi_write32_be; | |
86fc5935 | 405 | } |
c9da2e12 RR |
406 | xspi->bits_per_word = pdata->bits_per_word; |
407 | if (xspi->bits_per_word == 8) { | |
408 | xspi->tx_fn = xspi_tx8; | |
409 | xspi->rx_fn = xspi_rx8; | |
410 | } else if (xspi->bits_per_word == 16) { | |
411 | xspi->tx_fn = xspi_tx16; | |
412 | xspi->rx_fn = xspi_rx16; | |
413 | } else if (xspi->bits_per_word == 32) { | |
414 | xspi->tx_fn = xspi_tx32; | |
415 | xspi->rx_fn = xspi_rx32; | |
416 | } else | |
417 | goto unmap_io; | |
418 | ||
ae918c02 AK |
419 | |
420 | /* SPI controller initializations */ | |
86fc5935 | 421 | xspi_init_hw(xspi); |
ae918c02 AK |
422 | |
423 | /* Register for SPI Interrupt */ | |
d5af91a1 RR |
424 | ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); |
425 | if (ret) | |
ae918c02 AK |
426 | goto unmap_io; |
427 | ||
d5af91a1 RR |
428 | ret = spi_bitbang_start(&xspi->bitbang); |
429 | if (ret) { | |
430 | dev_err(dev, "spi_bitbang_start FAILED\n"); | |
ae918c02 AK |
431 | goto free_irq; |
432 | } | |
433 | ||
920712af GL |
434 | dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", |
435 | (unsigned long long)mem->start, xspi->regs, xspi->irq); | |
d5af91a1 | 436 | return master; |
ae918c02 AK |
437 | |
438 | free_irq: | |
439 | free_irq(xspi->irq, xspi); | |
440 | unmap_io: | |
441 | iounmap(xspi->regs); | |
d5af91a1 RR |
442 | map_failed: |
443 | release_mem_region(mem->start, resource_size(mem)); | |
ae918c02 AK |
444 | put_master: |
445 | spi_master_put(master); | |
d5af91a1 | 446 | return NULL; |
ae918c02 | 447 | } |
d5af91a1 | 448 | EXPORT_SYMBOL(xilinx_spi_init); |
ae918c02 | 449 | |
d5af91a1 | 450 | void xilinx_spi_deinit(struct spi_master *master) |
ae918c02 AK |
451 | { |
452 | struct xilinx_spi *xspi; | |
ae918c02 | 453 | |
ae918c02 AK |
454 | xspi = spi_master_get_devdata(master); |
455 | ||
456 | spi_bitbang_stop(&xspi->bitbang); | |
457 | free_irq(xspi->irq, xspi); | |
458 | iounmap(xspi->regs); | |
ff82c587 | 459 | |
d5af91a1 RR |
460 | release_mem_region(xspi->mem.start, resource_size(&xspi->mem)); |
461 | spi_master_put(xspi->bitbang.master); | |
ae918c02 | 462 | } |
d5af91a1 | 463 | EXPORT_SYMBOL(xilinx_spi_deinit); |
ae918c02 | 464 | |
ae918c02 AK |
465 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
466 | MODULE_DESCRIPTION("Xilinx SPI driver"); | |
467 | MODULE_LICENSE("GPL"); |