[linux-2.6-block.git] / drivers / spi / spi_mpc83xx.c

/*
 * MPC83xx SPI controller driver.
 *
 * Maintainer: Kumar Gala
 *
 * Copyright (C) 2006 Polycom, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>

#include <asm/irq.h>
#include <asm/io.h>

/* SPI Controller registers */
struct mpc83xx_spi_reg {
	u8 res1[0x20];
	__be32 mode;
	__be32 event;
	__be32 mask;
	__be32 command;
	__be32 transmit;
	__be32 receive;
};

/* SPI Controller mode register definitions */
#define	SPMODE_LOOP		(1 << 30)
#define	SPMODE_CI_INACTIVEHIGH	(1 << 29)
#define	SPMODE_CP_BEGIN_EDGECLK	(1 << 28)
#define	SPMODE_DIV16		(1 << 27)
#define	SPMODE_REV		(1 << 26)
#define	SPMODE_MS		(1 << 25)
#define	SPMODE_ENABLE		(1 << 24)
#define	SPMODE_LEN(x)		((x) << 20)
#define	SPMODE_PM(x)		((x) << 16)
#define	SPMODE_OP		(1 << 14)
#define	SPMODE_CG(x)		((x) << 7)

/*
 * Default for SPI Mode:
 * 	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
 */
#define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))

/* SPIE register values */
#define	SPIE_NE		0x00000200	/* Not empty */
#define	SPIE_NF		0x00000100	/* Not full */

/* SPIM register values */
#define	SPIM_NE		0x00000200	/* Not empty */
#define	SPIM_NF		0x00000100	/* Not full */

/* SPI Controller driver's private data. */
struct mpc83xx_spi {
	struct mpc83xx_spi_reg __iomem *base;

	/* rx & tx bufs from the spi_transfer */
	const void *tx;
	void *rx;

	/* functions to deal with different sized buffers */
	void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
	u32(*get_tx) (struct mpc83xx_spi *);

	unsigned int count;
	int irq;

	unsigned nsecs;		/* (clock cycle time)/2 */

	u32 spibrg;		/* SPIBRG input clock */
	u32 rx_shift;		/* RX data reg shift when in qe mode */
	u32 tx_shift;		/* TX data reg shift when in qe mode */

	bool qe_mode;

	void (*activate_cs) (u8 cs, u8 polarity);
	void (*deactivate_cs) (u8 cs, u8 polarity);

	u8 busy;

	struct workqueue_struct *workqueue;
	struct work_struct work;

	struct list_head queue;
	spinlock_t lock;

	struct completion done;
};

struct spi_mpc83xx_cs {
	/* functions to deal with different sized buffers */
	void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
	u32 (*get_tx) (struct mpc83xx_spi *);
	u32 rx_shift;		/* RX data reg shift when in qe mode */
	u32 tx_shift;		/* TX data reg shift when in qe mode */
	u32 hw_mode;		/* Holds HW mode register settings */
};

static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
{
	out_be32(reg, val);
}

static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
{
	return in_be32(reg);
}

#define MPC83XX_SPI_RX_BUF(type) 					  \
static									  \
void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
{									  \
	type * rx = mpc83xx_spi->rx;					  \
	*rx++ = (type)(data >> mpc83xx_spi->rx_shift);			  \
	mpc83xx_spi->rx = rx;						  \
}

#define MPC83XX_SPI_TX_BUF(type)				\
static								\
u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)	\
{								\
	u32 data;						\
	const type * tx = mpc83xx_spi->tx;			\
	if (!tx)						\
		return 0;					\
	data = *tx++ << mpc83xx_spi->tx_shift;			\
	mpc83xx_spi->tx = tx;					\
	return data;						\
}

MPC83XX_SPI_RX_BUF(u8)
MPC83XX_SPI_RX_BUF(u16)
MPC83XX_SPI_RX_BUF(u32)
MPC83XX_SPI_TX_BUF(u8)
MPC83XX_SPI_TX_BUF(u16)
MPC83XX_SPI_TX_BUF(u32)

static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
	struct spi_mpc83xx_cs	*cs = spi->controller_state;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (value == BITBANG_CS_INACTIVE) {
		if (mpc83xx_spi->deactivate_cs)
			mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
	}

	if (value == BITBANG_CS_ACTIVE) {
		u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);

		mpc83xx_spi->rx_shift = cs->rx_shift;
		mpc83xx_spi->tx_shift = cs->tx_shift;
		mpc83xx_spi->get_rx = cs->get_rx;
		mpc83xx_spi->get_tx = cs->get_tx;

		if (cs->hw_mode != regval) {
			unsigned long flags;
			__be32 __iomem *mode = &mpc83xx_spi->base->mode;

			regval = cs->hw_mode;
			/* Turn off IRQs locally to minimize time that
			 * SPI is disabled
			 */
			local_irq_save(flags);
			/* Turn off SPI unit prior changing mode */
			mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
			mpc83xx_spi_write_reg(mode, regval);
			local_irq_restore(flags);
		}
		if (mpc83xx_spi->activate_cs)
			mpc83xx_spi->activate_cs(spi->chip_select, pol);
	}
}

static
int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u32 regval;
	u8 bits_per_word, pm;
	u32 hz;
	struct spi_mpc83xx_cs	*cs = spi->controller_state;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	/* Make sure its a bit width we support [4..16, 32] */
	if ((bits_per_word < 4)
	    || ((bits_per_word > 16) && (bits_per_word != 32)))
		return -EINVAL;

	if (!hz)
		hz = spi->max_speed_hz;

	cs->rx_shift = 0;
	cs->tx_shift = 0;
	if (bits_per_word <= 8) {
		cs->get_rx = mpc83xx_spi_rx_buf_u8;
		cs->get_tx = mpc83xx_spi_tx_buf_u8;
		if (mpc83xx_spi->qe_mode) {
			cs->rx_shift = 16;
			cs->tx_shift = 24;
		}
	} else if (bits_per_word <= 16) {
		cs->get_rx = mpc83xx_spi_rx_buf_u16;
		cs->get_tx = mpc83xx_spi_tx_buf_u16;
		if (mpc83xx_spi->qe_mode) {
			cs->rx_shift = 16;
			cs->tx_shift = 16;
		}
	} else if (bits_per_word <= 32) {
		cs->get_rx = mpc83xx_spi_rx_buf_u32;
		cs->get_tx = mpc83xx_spi_tx_buf_u32;
	} else
		return -EINVAL;

	if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
		cs->tx_shift = 0;
		if (bits_per_word <= 8)
			cs->rx_shift = 8;
		else
			cs->rx_shift = 0;
	}

	mpc83xx_spi->rx_shift = cs->rx_shift;
	mpc83xx_spi->tx_shift = cs->tx_shift;
	mpc83xx_spi->get_rx = cs->get_rx;
	mpc83xx_spi->get_tx = cs->get_tx;

	if (bits_per_word == 32)
		bits_per_word = 0;
	else
		bits_per_word = bits_per_word - 1;

	/* mask out bits we are going to set */
	cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
				  | SPMODE_PM(0xF));

	cs->hw_mode |= SPMODE_LEN(bits_per_word);

	if ((mpc83xx_spi->spibrg / hz) > 64) {
		cs->hw_mode |= SPMODE_DIV16;
		pm = mpc83xx_spi->spibrg / (hz * 64);
		if (pm > 16) {
			dev_err(&spi->dev, "Requested speed is too "
				"low: %d Hz. Will use %d Hz instead.\n",
				hz, mpc83xx_spi->spibrg / 1024);
			pm = 16;
		}
	} else
		pm = mpc83xx_spi->spibrg / (hz * 4);
	if (pm)
		pm--;

	cs->hw_mode |= SPMODE_PM(pm);
	regval =  mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	if (cs->hw_mode != regval) {
		unsigned long flags;
		__be32 __iomem *mode = &mpc83xx_spi->base->mode;

		regval = cs->hw_mode;
		/* Turn off IRQs locally to minimize time
		 * that SPI is disabled
		 */
		local_irq_save(flags);
		/* Turn off SPI unit prior changing mode */
		mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
		mpc83xx_spi_write_reg(mode, regval);
		local_irq_restore(flags);
	}
	return 0;
}

static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u32 word, len, bits_per_word;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	mpc83xx_spi->tx = t->tx_buf;
	mpc83xx_spi->rx = t->rx_buf;
	bits_per_word = spi->bits_per_word;
	if (t->bits_per_word)
		bits_per_word = t->bits_per_word;
	len = t->len;
	if (bits_per_word > 8) {
		/* invalid length? */
		if (len & 1)
			return -EINVAL;
		len /= 2;
	}
	if (bits_per_word > 16) {
		/* invalid length? */
		if (len & 1)
			return -EINVAL;
		len /= 2;
	}
	mpc83xx_spi->count = len;

	INIT_COMPLETION(mpc83xx_spi->done);

	/* enable rx ints */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);

	/* transmit word */
	word = mpc83xx_spi->get_tx(mpc83xx_spi);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);

	wait_for_completion(&mpc83xx_spi->done);

	/* disable rx ints */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);

	return mpc83xx_spi->count;
}

static void mpc83xx_spi_work(struct work_struct *work)
{
	struct mpc83xx_spi *mpc83xx_spi =
		container_of(work, struct mpc83xx_spi, work);

	spin_lock_irq(&mpc83xx_spi->lock);
	mpc83xx_spi->busy = 1;
	while (!list_empty(&mpc83xx_spi->queue)) {
		struct spi_message *m;
		struct spi_device *spi;
		struct spi_transfer *t = NULL;
		unsigned cs_change;
		int status, nsecs = 50;

		m = container_of(mpc83xx_spi->queue.next,
				struct spi_message, queue);
		list_del_init(&m->queue);
		spin_unlock_irq(&mpc83xx_spi->lock);

		spi = m->spi;
		cs_change = 1;
		status = 0;
		list_for_each_entry(t, &m->transfers, transfer_list) {
			if (t->bits_per_word || t->speed_hz) {
				/* Don't allow changes if CS is active */
				status = -EINVAL;

				if (cs_change)
					status = mpc83xx_spi_setup_transfer(spi, t);
				if (status < 0)
					break;
			}

			if (cs_change)
				mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
			cs_change = t->cs_change;
			if (t->len)
				status = mpc83xx_spi_bufs(spi, t);
			if (status) {
				status = -EMSGSIZE;
				break;
			}
			m->actual_length += t->len;

			if (t->delay_usecs)
				udelay(t->delay_usecs);

			if (cs_change) {
				ndelay(nsecs);
				mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
				ndelay(nsecs);
			}
		}

		m->status = status;
		m->complete(m->context);

		if (status || !cs_change) {
			ndelay(nsecs);
			mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
		}

		mpc83xx_spi_setup_transfer(spi, NULL);

		spin_lock_irq(&mpc83xx_spi->lock);
	}
	mpc83xx_spi->busy = 0;
	spin_unlock_irq(&mpc83xx_spi->lock);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS	(SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
			| SPI_LSB_FIRST | SPI_LOOP)

static int mpc83xx_spi_setup(struct spi_device *spi)
{
	struct mpc83xx_spi *mpc83xx_spi;
	int retval;
	u32 hw_mode;
	struct spi_mpc83xx_cs	*cs = spi->controller_state;

	if (spi->mode & ~MODEBITS) {
		dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
			spi->mode & ~MODEBITS);
		return -EINVAL;
	}

	if (!spi->max_speed_hz)
		return -EINVAL;

	if (!cs) {
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}
	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	hw_mode = cs->hw_mode; /* Save orginal settings */
	cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	/* mask out bits we are going to set */
	cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
			 | SPMODE_REV | SPMODE_LOOP);

	if (spi->mode & SPI_CPHA)
		cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
	if (spi->mode & SPI_CPOL)
		cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
	if (!(spi->mode & SPI_LSB_FIRST))
		cs->hw_mode |= SPMODE_REV;
	if (spi->mode & SPI_LOOP)
		cs->hw_mode |= SPMODE_LOOP;

	retval = mpc83xx_spi_setup_transfer(spi, NULL);
	if (retval < 0) {
		cs->hw_mode = hw_mode; /* Restore settings */
		return retval;
	}

	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
		__func__, spi->mode & (SPI_CPOL | SPI_CPHA),
		spi->bits_per_word, spi->max_speed_hz);
#if 0 /* Don't think this is needed */
	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	 * setup, unless the hardware defaults cooperate to avoid confusion
	 * between normal (active low) and inverted chipselects.
	 */

	/* deselect chip (low or high) */
	spin_lock(&mpc83xx_spi->lock);
	if (!mpc83xx_spi->busy)
		mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
	spin_unlock(&mpc83xx_spi->lock);
#endif
	return 0;
}

static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
{
	struct mpc83xx_spi *mpc83xx_spi = context_data;
	u32 event;
	irqreturn_t ret = IRQ_NONE;

	/* Get interrupt events(tx/rx) */
	event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);

	/* We need handle RX first */
	if (event & SPIE_NE) {
		u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);

		if (mpc83xx_spi->rx)
			mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);

		ret = IRQ_HANDLED;
	}

	if ((event & SPIE_NF) == 0)
		/* spin until TX is done */
		while (((event =
			 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
						SPIE_NF) == 0)
			 cpu_relax();

	mpc83xx_spi->count -= 1;
	if (mpc83xx_spi->count) {
		u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
		mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
	} else {
		complete(&mpc83xx_spi->done);
	}

	/* Clear the events */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);

	return ret;
}
static int mpc83xx_spi_transfer(struct spi_device *spi,
				struct spi_message *m)
{
	struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
	unsigned long flags;

	m->actual_length = 0;
	m->status = -EINPROGRESS;

	spin_lock_irqsave(&mpc83xx_spi->lock, flags);
	list_add_tail(&m->queue, &mpc83xx_spi->queue);
	queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
	spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);

	return 0;
}


static void mpc83xx_spi_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static int __init mpc83xx_spi_probe(struct platform_device *dev)
{
	struct spi_master *master;
	struct mpc83xx_spi *mpc83xx_spi;
	struct fsl_spi_platform_data *pdata;
	struct resource *r;
	u32 regval;
	int ret = 0;

	/* Get resources(memory, IRQ) associated with the device */
	master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));

	if (master == NULL) {
		ret = -ENOMEM;
		goto err;
	}

	platform_set_drvdata(dev, master);
	pdata = dev->dev.platform_data;

	if (pdata == NULL) {
		ret = -ENODEV;
		goto free_master;
	}

	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENODEV;
		goto free_master;
	}
	master->setup = mpc83xx_spi_setup;
	master->transfer = mpc83xx_spi_transfer;
	master->cleanup = mpc83xx_spi_cleanup;

	mpc83xx_spi = spi_master_get_devdata(master);
	mpc83xx_spi->activate_cs = pdata->activate_cs;
	mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
	mpc83xx_spi->qe_mode = pdata->qe_mode;
	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
	mpc83xx_spi->spibrg = pdata->sysclk;

	mpc83xx_spi->rx_shift = 0;
	mpc83xx_spi->tx_shift = 0;
	if (mpc83xx_spi->qe_mode) {
		mpc83xx_spi->rx_shift = 16;
		mpc83xx_spi->tx_shift = 24;
	}

	init_completion(&mpc83xx_spi->done);

	mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
	if (mpc83xx_spi->base == NULL) {
		ret = -ENOMEM;
		goto put_master;
	}

	mpc83xx_spi->irq = platform_get_irq(dev, 0);

	if (mpc83xx_spi->irq < 0) {
		ret = -ENXIO;
		goto unmap_io;
	}

	/* Register for SPI Interrupt */
	ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
			  0, "mpc83xx_spi", mpc83xx_spi);

	if (ret != 0)
		goto unmap_io;

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->max_chipselect;

	/* SPI controller initializations */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);

	/* Enable SPI interface */
	regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
	if (pdata->qe_mode)
		regval |= SPMODE_OP;

	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
	spin_lock_init(&mpc83xx_spi->lock);
	init_completion(&mpc83xx_spi->done);
	INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
	INIT_LIST_HEAD(&mpc83xx_spi->queue);

	mpc83xx_spi->workqueue = create_singlethread_workqueue(
		dev_name(master->dev.parent));
	if (mpc83xx_spi->workqueue == NULL) {
		ret = -EBUSY;
		goto free_irq;
	}

	ret = spi_register_master(master);
	if (ret < 0)
		goto unreg_master;

	printk(KERN_INFO
	       "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
	       dev_name(&dev->dev), mpc83xx_spi->base, mpc83xx_spi->irq);

	return ret;

unreg_master:
	destroy_workqueue(mpc83xx_spi->workqueue);
free_irq:
	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
unmap_io:
	iounmap(mpc83xx_spi->base);
put_master:
	spi_master_put(master);
free_master:
	kfree(master);
err:
	return ret;
}

static int __exit mpc83xx_spi_remove(struct platform_device *dev)
{
	struct mpc83xx_spi *mpc83xx_spi;
	struct spi_master *master;

	master = platform_get_drvdata(dev);
	mpc83xx_spi = spi_master_get_devdata(master);

	flush_workqueue(mpc83xx_spi->workqueue);
	destroy_workqueue(mpc83xx_spi->workqueue);
	spi_unregister_master(master);

	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
	iounmap(mpc83xx_spi->base);

	return 0;
}

MODULE_ALIAS("platform:mpc83xx_spi");
static struct platform_driver mpc83xx_spi_driver = {
	.remove = __exit_p(mpc83xx_spi_remove),
	.driver = {
		.name = "mpc83xx_spi",
		.owner = THIS_MODULE,
	},
};

static int __init mpc83xx_spi_init(void)
{
	return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
}

static void __exit mpc83xx_spi_exit(void)
{
	platform_driver_unregister(&mpc83xx_spi_driver);
}

module_init(mpc83xx_spi_init);
module_exit(mpc83xx_spi_exit);

MODULE_AUTHOR("Kumar Gala");
MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ccf06998 KG	1	/*
	2	* MPC83xx SPI controller driver.
	3	*
	4	* Maintainer: Kumar Gala
	5	*
	6	* Copyright (C) 2006 Polycom, Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/types.h>
	16	#include <linux/kernel.h>
	17	#include <linux/completion.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/delay.h>
	20	#include <linux/irq.h>
	21	#include <linux/device.h>
	22	#include <linux/spi/spi.h>
	23	#include <linux/spi/spi_bitbang.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/fsl_devices.h>
	26
	27	#include <asm/irq.h>
	28	#include <asm/io.h>
	29
	30	/* SPI Controller registers */
	31	struct mpc83xx_spi_reg {
	32	u8 res1[0x20];
	33	__be32 mode;
	34	__be32 event;
	35	__be32 mask;
	36	__be32 command;
	37	__be32 transmit;
	38	__be32 receive;
	39	};
	40
	41	/* SPI Controller mode register definitions */
2a485d7a	42	#define SPMODE_LOOP (1 << 30)
ccf06998 KG	43	#define SPMODE_CI_INACTIVEHIGH (1 << 29)
	44	#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
	45	#define SPMODE_DIV16 (1 << 27)
	46	#define SPMODE_REV (1 << 26)
	47	#define SPMODE_MS (1 << 25)
	48	#define SPMODE_ENABLE (1 << 24)
	49	#define SPMODE_LEN(x) ((x) << 20)
	50	#define SPMODE_PM(x) ((x) << 16)
f29ba280	51	#define SPMODE_OP (1 << 14)
c9bfcb31	52	#define SPMODE_CG(x) ((x) << 7)
ccf06998 KG	53
	54	/*
	55	* Default for SPI Mode:
	56	* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
	57	*/
	58	#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH \| SPMODE_DIV16 \| SPMODE_REV \| \
	59	SPMODE_MS \| SPMODE_LEN(7) \| SPMODE_PM(0xf))
	60
	61	/* SPIE register values */
	62	#define SPIE_NE 0x00000200 /* Not empty */
	63	#define SPIE_NF 0x00000100 /* Not full */
	64
	65	/* SPIM register values */
	66	#define SPIM_NE 0x00000200 /* Not empty */
	67	#define SPIM_NF 0x00000100 /* Not full */
	68
	69	/* SPI Controller driver's private data. */
	70	struct mpc83xx_spi {
ccf06998 KG	71	struct mpc83xx_spi_reg __iomem *base;
	72
	73	/* rx & tx bufs from the spi_transfer */
	74	const void *tx;
	75	void *rx;
	76
	77	/* functions to deal with different sized buffers */
	78	void (get_rx) (u32 rx_data, struct mpc83xx_spi );
	79	u32(get_tx) (struct mpc83xx_spi );
	80
	81	unsigned int count;
c9bfcb31	82	int irq;
ccf06998 KG	83
	84	unsigned nsecs; /* (clock cycle time)/2 */
	85
e24a4d1e	86	u32 spibrg; /* SPIBRG input clock */
f29ba280 JT	87	u32 rx_shift; /* RX data reg shift when in qe mode */
	88	u32 tx_shift; /* TX data reg shift when in qe mode */
	89
	90	bool qe_mode;
	91
ccf06998 KG	92	void (*activate_cs) (u8 cs, u8 polarity);
ccf06998 KG	93	void (*deactivate_cs) (u8 cs, u8 polarity);
c9bfcb31 JT	94
	95	u8 busy;
	96
	97	struct workqueue_struct *workqueue;
	98	struct work_struct work;
	99
	100	struct list_head queue;
	101	spinlock_t lock;
	102
	103	struct completion done;
	104	};
	105
	106	struct spi_mpc83xx_cs {
	107	/* functions to deal with different sized buffers */
	108	void (get_rx) (u32 rx_data, struct mpc83xx_spi );
	109	u32 (get_tx) (struct mpc83xx_spi );
	110	u32 rx_shift; /* RX data reg shift when in qe mode */
	111	u32 tx_shift; /* TX data reg shift when in qe mode */
	112	u32 hw_mode; /* Holds HW mode register settings */
ccf06998 KG	113	};
	114
	115	static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
	116	{
	117	out_be32(reg, val);
	118	}
	119
	120	static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
	121	{
	122	return in_be32(reg);
	123	}
	124
	125	#define MPC83XX_SPI_RX_BUF(type) \
34c8a20c	126	static \
ccf06998 KG	127	void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
	128	{ \
	129	type * rx = mpc83xx_spi->rx; \
f29ba280	130	*rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
ccf06998 KG	131	mpc83xx_spi->rx = rx; \
	132	}
	133
	134	#define MPC83XX_SPI_TX_BUF(type) \
34c8a20c	135	static \
ccf06998 KG	136	u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
	137	{ \
	138	u32 data; \
	139	const type * tx = mpc83xx_spi->tx; \
4b1badf5 DB	140	if (!tx) \
4b1badf5 DB	141	return 0; \
f29ba280	142	data = *tx++ << mpc83xx_spi->tx_shift; \
ccf06998 KG	143	mpc83xx_spi->tx = tx; \
	144	return data; \
	145	}
	146
	147	MPC83XX_SPI_RX_BUF(u8)
	148	MPC83XX_SPI_RX_BUF(u16)
	149	MPC83XX_SPI_RX_BUF(u32)
	150	MPC83XX_SPI_TX_BUF(u8)
	151	MPC83XX_SPI_TX_BUF(u16)
	152	MPC83XX_SPI_TX_BUF(u32)
	153
	154	static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
	155	{
	156	struct mpc83xx_spi *mpc83xx_spi;
	157	u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
c9bfcb31	158	struct spi_mpc83xx_cs *cs = spi->controller_state;
ccf06998 KG	159
	160	mpc83xx_spi = spi_master_get_devdata(spi->master);
	161
	162	if (value == BITBANG_CS_INACTIVE) {
	163	if (mpc83xx_spi->deactivate_cs)
	164	mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
	165	}
	166
	167	if (value == BITBANG_CS_ACTIVE) {
	168	u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
a44648b0	169
c9bfcb31 JT	170	mpc83xx_spi->rx_shift = cs->rx_shift;
	171	mpc83xx_spi->tx_shift = cs->tx_shift;
	172	mpc83xx_spi->get_rx = cs->get_rx;
	173	mpc83xx_spi->get_tx = cs->get_tx;
	174
	175	if (cs->hw_mode != regval) {
	176	unsigned long flags;
34c8a20c	177	__be32 __iomem *mode = &mpc83xx_spi->base->mode;
c9bfcb31 JT	178
	179	regval = cs->hw_mode;
	180	/* Turn off IRQs locally to minimize time that
	181	* SPI is disabled
	182	*/
	183	local_irq_save(flags);
	184	/* Turn off SPI unit prior changing mode */
34c8a20c AV	185	mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
34c8a20c AV	186	mpc83xx_spi_write_reg(mode, regval);
c9bfcb31	187	local_irq_restore(flags);
ccf06998	188	}
ccf06998 KG	189	if (mpc83xx_spi->activate_cs)
	190	mpc83xx_spi->activate_cs(spi->chip_select, pol);
	191	}
	192	}
	193
	194	static
	195	int mpc83xx_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	196	{
	197	struct mpc83xx_spi *mpc83xx_spi;
	198	u32 regval;
c9bfcb31	199	u8 bits_per_word, pm;
ccf06998	200	u32 hz;
c9bfcb31	201	struct spi_mpc83xx_cs *cs = spi->controller_state;
ccf06998 KG	202
	203	mpc83xx_spi = spi_master_get_devdata(spi->master);
	204
	205	if (t) {
	206	bits_per_word = t->bits_per_word;
	207	hz = t->speed_hz;
	208	} else {
	209	bits_per_word = 0;
	210	hz = 0;
	211	}
	212
	213	/* spi_transfer level calls that work per-word */
	214	if (!bits_per_word)
	215	bits_per_word = spi->bits_per_word;
	216
	217	/* Make sure its a bit width we support [4..16, 32] */
	218	if ((bits_per_word < 4)
	219	\|\| ((bits_per_word > 16) && (bits_per_word != 32)))
	220	return -EINVAL;
	221
c9bfcb31 JT	222	if (!hz)
	223	hz = spi->max_speed_hz;
	224
	225	cs->rx_shift = 0;
	226	cs->tx_shift = 0;
ccf06998	227	if (bits_per_word <= 8) {
c9bfcb31 JT	228	cs->get_rx = mpc83xx_spi_rx_buf_u8;
c9bfcb31 JT	229	cs->get_tx = mpc83xx_spi_tx_buf_u8;
f29ba280	230	if (mpc83xx_spi->qe_mode) {
c9bfcb31 JT	231	cs->rx_shift = 16;
c9bfcb31 JT	232	cs->tx_shift = 24;
f29ba280	233	}
ccf06998	234	} else if (bits_per_word <= 16) {
c9bfcb31 JT	235	cs->get_rx = mpc83xx_spi_rx_buf_u16;
c9bfcb31 JT	236	cs->get_tx = mpc83xx_spi_tx_buf_u16;
f29ba280	237	if (mpc83xx_spi->qe_mode) {
c9bfcb31 JT	238	cs->rx_shift = 16;
c9bfcb31 JT	239	cs->tx_shift = 16;
f29ba280	240	}
ccf06998	241	} else if (bits_per_word <= 32) {
c9bfcb31 JT	242	cs->get_rx = mpc83xx_spi_rx_buf_u32;
c9bfcb31 JT	243	cs->get_tx = mpc83xx_spi_tx_buf_u32;
ccf06998 KG	244	} else
	245	return -EINVAL;
	246
35cc0b97	247	if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
c9bfcb31	248	cs->tx_shift = 0;
35cc0b97	249	if (bits_per_word <= 8)
c9bfcb31	250	cs->rx_shift = 8;
35cc0b97	251	else
c9bfcb31	252	cs->rx_shift = 0;
35cc0b97 AV	253	}
35cc0b97 AV	254
c9bfcb31 JT	255	mpc83xx_spi->rx_shift = cs->rx_shift;
	256	mpc83xx_spi->tx_shift = cs->tx_shift;
	257	mpc83xx_spi->get_rx = cs->get_rx;
	258	mpc83xx_spi->get_tx = cs->get_tx;
ccf06998 KG	259
	260	if (bits_per_word == 32)
	261	bits_per_word = 0;
	262	else
	263	bits_per_word = bits_per_word - 1;
	264
32421daa	265	/* mask out bits we are going to set */
c9bfcb31 JT	266	cs->hw_mode &= ~(SPMODE_LEN(0xF) \| SPMODE_DIV16
	267	\| SPMODE_PM(0xF));
	268
	269	cs->hw_mode \|= SPMODE_LEN(bits_per_word);
	270
a61f5345	271	if ((mpc83xx_spi->spibrg / hz) > 64) {
53604dbe	272	cs->hw_mode \|= SPMODE_DIV16;
a61f5345 CG	273	pm = mpc83xx_spi->spibrg / (hz * 64);
a61f5345 CG	274	if (pm > 16) {
53604dbe PK	275	dev_err(&spi->dev, "Requested speed is too "
	276	"low: %d Hz. Will use %d Hz instead.\n",
	277	hz, mpc83xx_spi->spibrg / 1024);
	278	pm = 16;
c9bfcb31	279	}
a61f5345	280	} else
c9bfcb31	281	pm = mpc83xx_spi->spibrg / (hz * 4);
a61f5345 CG	282	if (pm)
	283	pm--;
	284
	285	cs->hw_mode \|= SPMODE_PM(pm);
c9bfcb31 JT	286	regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	287	if (cs->hw_mode != regval) {
	288	unsigned long flags;
34c8a20c	289	__be32 __iomem *mode = &mpc83xx_spi->base->mode;
c9bfcb31 JT	290
	291	regval = cs->hw_mode;
	292	/* Turn off IRQs locally to minimize time
	293	* that SPI is disabled
	294	*/
	295	local_irq_save(flags);
	296	/* Turn off SPI unit prior changing mode */
34c8a20c AV	297	mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
34c8a20c AV	298	mpc83xx_spi_write_reg(mode, regval);
c9bfcb31 JT	299	local_irq_restore(flags);
	300	}
	301	return 0;
	302	}
ccf06998	303
c9bfcb31 JT	304	static int mpc83xx_spi_bufs(struct spi_device spi, struct spi_transfer t)
	305	{
	306	struct mpc83xx_spi *mpc83xx_spi;
	307	u32 word, len, bits_per_word;
ccf06998	308
c9bfcb31 JT	309	mpc83xx_spi = spi_master_get_devdata(spi->master);
	310
	311	mpc83xx_spi->tx = t->tx_buf;
	312	mpc83xx_spi->rx = t->rx_buf;
	313	bits_per_word = spi->bits_per_word;
	314	if (t->bits_per_word)
	315	bits_per_word = t->bits_per_word;
	316	len = t->len;
aa77d96b PK	317	if (bits_per_word > 8) {
	318	/* invalid length? */
	319	if (len & 1)
	320	return -EINVAL;
c9bfcb31	321	len /= 2;
aa77d96b PK	322	}
	323	if (bits_per_word > 16) {
	324	/* invalid length? */
	325	if (len & 1)
	326	return -EINVAL;
c9bfcb31	327	len /= 2;
aa77d96b	328	}
c9bfcb31	329	mpc83xx_spi->count = len;
aa77d96b	330
c9bfcb31 JT	331	INIT_COMPLETION(mpc83xx_spi->done);
	332
	333	/* enable rx ints */
	334	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
	335
	336	/* transmit word */
	337	word = mpc83xx_spi->get_tx(mpc83xx_spi);
	338	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
	339
	340	wait_for_completion(&mpc83xx_spi->done);
	341
	342	/* disable rx ints */
	343	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	344
	345	return mpc83xx_spi->count;
	346	}
	347
	348	static void mpc83xx_spi_work(struct work_struct *work)
	349	{
	350	struct mpc83xx_spi *mpc83xx_spi =
	351	container_of(work, struct mpc83xx_spi, work);
	352
	353	spin_lock_irq(&mpc83xx_spi->lock);
	354	mpc83xx_spi->busy = 1;
	355	while (!list_empty(&mpc83xx_spi->queue)) {
	356	struct spi_message *m;
	357	struct spi_device *spi;
	358	struct spi_transfer *t = NULL;
	359	unsigned cs_change;
	360	int status, nsecs = 50;
	361
	362	m = container_of(mpc83xx_spi->queue.next,
	363	struct spi_message, queue);
	364	list_del_init(&m->queue);
	365	spin_unlock_irq(&mpc83xx_spi->lock);
	366
	367	spi = m->spi;
	368	cs_change = 1;
	369	status = 0;
	370	list_for_each_entry(t, &m->transfers, transfer_list) {
	371	if (t->bits_per_word \|\| t->speed_hz) {
	372	/* Don't allow changes if CS is active */
	373	status = -EINVAL;
	374
	375	if (cs_change)
	376	status = mpc83xx_spi_setup_transfer(spi, t);
	377	if (status < 0)
	378	break;
	379	}
	380
	381	if (cs_change)
	382	mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
	383	cs_change = t->cs_change;
	384	if (t->len)
	385	status = mpc83xx_spi_bufs(spi, t);
	386	if (status) {
	387	status = -EMSGSIZE;
	388	break;
	389	}
	390	m->actual_length += t->len;
	391
	392	if (t->delay_usecs)
	393	udelay(t->delay_usecs);
	394
395	if (cs_change) {
396	ndelay(nsecs);
397	mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
398	ndelay(nsecs);
399	}
400	}
401
402	m->status = status;
403	m->complete(m->context);
404
405	if (status \|\| !cs_change) {
406	ndelay(nsecs);
407	mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
408	}
409
410	mpc83xx_spi_setup_transfer(spi, NULL);
411
412	spin_lock_irq(&mpc83xx_spi->lock);
413	}
414	mpc83xx_spi->busy = 0;
415	spin_unlock_irq(&mpc83xx_spi->lock);
ccf06998 KG	416	}
ccf06998 KG	417
dccd573b	418	/* the spi->mode bits understood by this driver: */
2a485d7a AV	419	#define MODEBITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \
2a485d7a AV	420	\| SPI_LSB_FIRST \| SPI_LOOP)
dccd573b	421
ccf06998 KG	422	static int mpc83xx_spi_setup(struct spi_device *spi)
ccf06998 KG	423	{
ccf06998 KG	424	struct mpc83xx_spi *mpc83xx_spi;
ccf06998 KG	425	int retval;
c9bfcb31 JT	426	u32 hw_mode;
c9bfcb31 JT	427	struct spi_mpc83xx_cs *cs = spi->controller_state;
ccf06998	428
dccd573b DB	429	if (spi->mode & ~MODEBITS) {
	430	dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
	431	spi->mode & ~MODEBITS);
	432	return -EINVAL;
	433	}
	434
ccf06998 KG	435	if (!spi->max_speed_hz)
	436	return -EINVAL;
	437
c9bfcb31 JT	438	if (!cs) {
	439	cs = kzalloc(sizeof *cs, GFP_KERNEL);
	440	if (!cs)
	441	return -ENOMEM;
	442	spi->controller_state = cs;
	443	}
ccf06998 KG	444	mpc83xx_spi = spi_master_get_devdata(spi->master);
	445
	446	if (!spi->bits_per_word)
	447	spi->bits_per_word = 8;
	448
c9bfcb31 JT	449	hw_mode = cs->hw_mode; /* Save orginal settings */
	450	cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	451	/* mask out bits we are going to set */
	452	cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK \| SPMODE_CI_INACTIVEHIGH
	453	\| SPMODE_REV \| SPMODE_LOOP);
	454
	455	if (spi->mode & SPI_CPHA)
	456	cs->hw_mode \|= SPMODE_CP_BEGIN_EDGECLK;
	457	if (spi->mode & SPI_CPOL)
	458	cs->hw_mode \|= SPMODE_CI_INACTIVEHIGH;
	459	if (!(spi->mode & SPI_LSB_FIRST))
	460	cs->hw_mode \|= SPMODE_REV;
	461	if (spi->mode & SPI_LOOP)
	462	cs->hw_mode \|= SPMODE_LOOP;
	463
ccf06998	464	retval = mpc83xx_spi_setup_transfer(spi, NULL);
c9bfcb31 JT	465	if (retval < 0) {
c9bfcb31 JT	466	cs->hw_mode = hw_mode; /* Restore settings */
ccf06998	467	return retval;
c9bfcb31	468	}
ccf06998	469
c9bfcb31	470	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
b687d2a8	471	__func__, spi->mode & (SPI_CPOL \| SPI_CPHA),
c9bfcb31 JT	472	spi->bits_per_word, spi->max_speed_hz);
c9bfcb31 JT	473	#if 0 /* Don't think this is needed */
ccf06998 KG	474	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	475	* setup, unless the hardware defaults cooperate to avoid confusion
	476	* between normal (active low) and inverted chipselects.
	477	*/
	478
	479	/* deselect chip (low or high) */
c9bfcb31 JT	480	spin_lock(&mpc83xx_spi->lock);
	481	if (!mpc83xx_spi->busy)
	482	mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
	483	spin_unlock(&mpc83xx_spi->lock);
	484	#endif
ccf06998 KG	485	return 0;
	486	}
	487
34c8a20c	488	static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
ccf06998 KG	489	{
	490	struct mpc83xx_spi *mpc83xx_spi = context_data;
	491	u32 event;
	492	irqreturn_t ret = IRQ_NONE;
	493
	494	/* Get interrupt events(tx/rx) */
	495	event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
	496
	497	/* We need handle RX first */
	498	if (event & SPIE_NE) {
	499	u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
	500
	501	if (mpc83xx_spi->rx)
	502	mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
	503
	504	ret = IRQ_HANDLED;
	505	}
	506
	507	if ((event & SPIE_NF) == 0)
	508	/* spin until TX is done */
	509	while (((event =
	510	mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
	511	SPIE_NF) == 0)
	512	cpu_relax();
	513
	514	mpc83xx_spi->count -= 1;
	515	if (mpc83xx_spi->count) {
65e213cd JA	516	u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
65e213cd JA	517	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
ccf06998 KG	518	} else {
	519	complete(&mpc83xx_spi->done);
	520	}
	521
	522	/* Clear the events */
	523	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
	524
	525	return ret;
	526	}
c9bfcb31 JT	527	static int mpc83xx_spi_transfer(struct spi_device *spi,
	528	struct spi_message *m)
	529	{
	530	struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
	531	unsigned long flags;
	532
	533	m->actual_length = 0;
	534	m->status = -EINPROGRESS;
	535
	536	spin_lock_irqsave(&mpc83xx_spi->lock, flags);
	537	list_add_tail(&m->queue, &mpc83xx_spi->queue);
	538	queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
	539	spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
	540
	541	return 0;
	542	}
	543
	544
	545	static void mpc83xx_spi_cleanup(struct spi_device *spi)
	546	{
	547	kfree(spi->controller_state);
	548	}
ccf06998 KG	549
	550	static int __init mpc83xx_spi_probe(struct platform_device *dev)
	551	{
	552	struct spi_master *master;
	553	struct mpc83xx_spi *mpc83xx_spi;
	554	struct fsl_spi_platform_data *pdata;
	555	struct resource *r;
	556	u32 regval;
	557	int ret = 0;
	558
	559	/* Get resources(memory, IRQ) associated with the device */
	560	master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
	561
	562	if (master == NULL) {
	563	ret = -ENOMEM;
	564	goto err;
	565	}
	566
	567	platform_set_drvdata(dev, master);
	568	pdata = dev->dev.platform_data;
	569
	570	if (pdata == NULL) {
	571	ret = -ENODEV;
	572	goto free_master;
	573	}
	574
	575	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	576	if (r == NULL) {
	577	ret = -ENODEV;
	578	goto free_master;
	579	}
c9bfcb31 JT	580	master->setup = mpc83xx_spi_setup;
	581	master->transfer = mpc83xx_spi_transfer;
	582	master->cleanup = mpc83xx_spi_cleanup;
	583
ccf06998	584	mpc83xx_spi = spi_master_get_devdata(master);
ccf06998 KG	585	mpc83xx_spi->activate_cs = pdata->activate_cs;
ccf06998 KG	586	mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
f29ba280	587	mpc83xx_spi->qe_mode = pdata->qe_mode;
ccf06998 KG	588	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
ccf06998 KG	589	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
59a0ea50	590	mpc83xx_spi->spibrg = pdata->sysclk;
e24a4d1e	591
f29ba280 JT	592	mpc83xx_spi->rx_shift = 0;
	593	mpc83xx_spi->tx_shift = 0;
	594	if (mpc83xx_spi->qe_mode) {
	595	mpc83xx_spi->rx_shift = 16;
	596	mpc83xx_spi->tx_shift = 24;
	597	}
	598
ccf06998 KG	599	init_completion(&mpc83xx_spi->done);
	600
	601	mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
	602	if (mpc83xx_spi->base == NULL) {
	603	ret = -ENOMEM;
	604	goto put_master;
	605	}
	606
	607	mpc83xx_spi->irq = platform_get_irq(dev, 0);
	608
	609	if (mpc83xx_spi->irq < 0) {
	610	ret = -ENXIO;
	611	goto unmap_io;
	612	}
	613
	614	/* Register for SPI Interrupt */
	615	ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
	616	0, "mpc83xx_spi", mpc83xx_spi);
	617
	618	if (ret != 0)
	619	goto unmap_io;
	620
	621	master->bus_num = pdata->bus_num;
	622	master->num_chipselect = pdata->max_chipselect;
	623
	624	/* SPI controller initializations */
	625	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
	626	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	627	mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
	628	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
	629
	630	/* Enable SPI interface */
	631	regval = pdata->initial_spmode \| SPMODE_INIT_VAL \| SPMODE_ENABLE;
f29ba280 JT	632	if (pdata->qe_mode)
	633	regval \|= SPMODE_OP;
	634
ccf06998	635	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
c9bfcb31 JT	636	spin_lock_init(&mpc83xx_spi->lock);
	637	init_completion(&mpc83xx_spi->done);
	638	INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
	639	INIT_LIST_HEAD(&mpc83xx_spi->queue);
ccf06998	640
c9bfcb31	641	mpc83xx_spi->workqueue = create_singlethread_workqueue(
6c7377ab	642	dev_name(master->dev.parent));
c9bfcb31 JT	643	if (mpc83xx_spi->workqueue == NULL) {
c9bfcb31 JT	644	ret = -EBUSY;
ccf06998	645	goto free_irq;
c9bfcb31 JT	646	}
	647
	648	ret = spi_register_master(master);
	649	if (ret < 0)
	650	goto unreg_master;
ccf06998 KG	651
	652	printk(KERN_INFO
	653	"%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
6c7377ab	654	dev_name(&dev->dev), mpc83xx_spi->base, mpc83xx_spi->irq);
ccf06998 KG	655
	656	return ret;
	657
c9bfcb31 JT	658	unreg_master:
c9bfcb31 JT	659	destroy_workqueue(mpc83xx_spi->workqueue);
ccf06998 KG	660	free_irq:
	661	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
	662	unmap_io:
	663	iounmap(mpc83xx_spi->base);
	664	put_master:
	665	spi_master_put(master);
	666	free_master:
	667	kfree(master);
	668	err:
	669	return ret;
	670	}
	671
d1e44d9c	672	static int __exit mpc83xx_spi_remove(struct platform_device *dev)
ccf06998 KG	673	{
	674	struct mpc83xx_spi *mpc83xx_spi;
	675	struct spi_master *master;
	676
	677	master = platform_get_drvdata(dev);
	678	mpc83xx_spi = spi_master_get_devdata(master);
	679
c9bfcb31 JT	680	flush_workqueue(mpc83xx_spi->workqueue);
	681	destroy_workqueue(mpc83xx_spi->workqueue);
	682	spi_unregister_master(master);
	683
ccf06998 KG	684	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
ccf06998 KG	685	iounmap(mpc83xx_spi->base);
ccf06998 KG	686
	687	return 0;
	688	}
	689
7e38c3c4	690	MODULE_ALIAS("platform:mpc83xx_spi");
ccf06998	691	static struct platform_driver mpc83xx_spi_driver = {
d1e44d9c	692	.remove = __exit_p(mpc83xx_spi_remove),
ccf06998	693	.driver = {
7e38c3c4 KS	694	.name = "mpc83xx_spi",
7e38c3c4 KS	695	.owner = THIS_MODULE,
ccf06998 KG	696	},
	697	};
	698
	699	static int __init mpc83xx_spi_init(void)
	700	{
d1e44d9c	701	return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
ccf06998 KG	702	}
	703
	704	static void __exit mpc83xx_spi_exit(void)
	705	{
	706	platform_driver_unregister(&mpc83xx_spi_driver);
	707	}
	708
	709	module_init(mpc83xx_spi_init);
	710	module_exit(mpc83xx_spi_exit);
	711
	712	MODULE_AUTHOR("Kumar Gala");
	713	MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
	714	MODULE_LICENSE("GPL");