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Merge branch 'for-5.12' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[linux-block.git] / drivers / spi / spi-zynqmp-gqspi.c
CommitLineData
59899843 1// SPDX-License-Identifier: GPL-2.0-or-later
dfe11a11
RW		 2/*
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
4 * (master mode only)
5 *
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
dfe11a11
RW		 7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
ab7b7c71 13#include <linux/firmware/xlnx-zynqmp.h>
dfe11a11
RW		 14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of_irq.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
9e3a0003 20#include <linux/pm_runtime.h>
dfe11a11
RW		 21#include <linux/spi/spi.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
1c26372e 24#include <linux/spi/spi-mem.h>
dfe11a11
RW		 25
26/* Generic QSPI register offsets */
27#define GQSPI_CONFIG_OFST 0x00000100
28#define GQSPI_ISR_OFST 0x00000104
29#define GQSPI_IDR_OFST 0x0000010C
30#define GQSPI_IER_OFST 0x00000108
31#define GQSPI_IMASK_OFST 0x00000110
32#define GQSPI_EN_OFST 0x00000114
33#define GQSPI_TXD_OFST 0x0000011C
34#define GQSPI_RXD_OFST 0x00000120
35#define GQSPI_TX_THRESHOLD_OFST 0x00000128
36#define GQSPI_RX_THRESHOLD_OFST 0x0000012C
37#define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
38#define GQSPI_GEN_FIFO_OFST 0x00000140
39#define GQSPI_SEL_OFST 0x00000144
40#define GQSPI_GF_THRESHOLD_OFST 0x00000150
41#define GQSPI_FIFO_CTRL_OFST 0x0000014C
42#define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
43#define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
44#define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
45#define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
46#define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
47#define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
48#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
49#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
50#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
51
52/* GQSPI register bit masks */
53#define GQSPI_SEL_MASK 0x00000001
54#define GQSPI_EN_MASK 0x00000001
55#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
56#define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
57#define GQSPI_IDR_ALL_MASK 0x00000FBE
58#define GQSPI_CFG_MODE_EN_MASK 0xC0000000
59#define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
60#define GQSPI_CFG_ENDIAN_MASK 0x04000000
61#define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
62#define GQSPI_CFG_WP_HOLD_MASK 0x00080000
63#define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
64#define GQSPI_CFG_CLK_PHA_MASK 0x00000004
65#define GQSPI_CFG_CLK_POL_MASK 0x00000002
66#define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
67#define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
68#define GQSPI_GENFIFO_DATA_XFER 0x00000100
69#define GQSPI_GENFIFO_EXP 0x00000200
70#define GQSPI_GENFIFO_MODE_SPI 0x00000400
71#define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
72#define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
73#define GQSPI_GENFIFO_MODE_MASK 0x00000C00
74#define GQSPI_GENFIFO_CS_LOWER 0x00001000
75#define GQSPI_GENFIFO_CS_UPPER 0x00002000
76#define GQSPI_GENFIFO_BUS_LOWER 0x00004000
77#define GQSPI_GENFIFO_BUS_UPPER 0x00008000
78#define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
79#define GQSPI_GENFIFO_BUS_MASK 0x0000C000
80#define GQSPI_GENFIFO_TX 0x00010000
81#define GQSPI_GENFIFO_RX 0x00020000
82#define GQSPI_GENFIFO_STRIPE 0x00040000
83#define GQSPI_GENFIFO_POLL 0x00080000
84#define GQSPI_GENFIFO_EXP_START 0x00000100
85#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
86#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
87#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
88#define GQSPI_ISR_RXEMPTY_MASK 0x00000800
89#define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
90#define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
91#define GQSPI_ISR_TXEMPTY_MASK 0x00000100
92#define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
93#define GQSPI_ISR_RXFULL_MASK 0x00000020
94#define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
95#define GQSPI_ISR_TXFULL_MASK 0x00000008
96#define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
97#define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
98#define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
99#define GQSPI_IER_RXEMPTY_MASK 0x00000800
100#define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
101#define GQSPI_IER_RXNEMPTY_MASK 0x00000010
102#define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
103#define GQSPI_IER_TXEMPTY_MASK 0x00000100
104#define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
105#define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
106#define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
107#define GQSPI_ISR_IDR_MASK 0x00000994
108#define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
109#define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
110#define GQSPI_IRQ_MASK 0x00000980
111
112#define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
113#define GQSPI_GENFIFO_CS_SETUP 0x4
114#define GQSPI_GENFIFO_CS_HOLD 0x3
115#define GQSPI_TXD_DEPTH 64
116#define GQSPI_RX_FIFO_THRESHOLD 32
117#define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
118#define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
119#define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
120 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
121#define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
122#define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
123#define GQSPI_SELECT_FLASH_CS_LOWER 0x1
124#define GQSPI_SELECT_FLASH_CS_UPPER 0x2
125#define GQSPI_SELECT_FLASH_CS_BOTH 0x3
126#define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
127#define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
128#define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
129#define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
130#define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
131#define GQSPI_SELECT_MODE_SPI 0x1
132#define GQSPI_SELECT_MODE_DUALSPI 0x2
133#define GQSPI_SELECT_MODE_QUADSPI 0x4
134#define GQSPI_DMA_UNALIGN 0x3
135#define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
136
9e3a0003 137#define SPI_AUTOSUSPEND_TIMEOUT 3000
dfe11a11
RW		 138enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
139
140/**
141 * struct zynqmp_qspi - Defines qspi driver instance
142 * @regs: Virtual address of the QSPI controller registers
143 * @refclk: Pointer to the peripheral clock
144 * @pclk: Pointer to the APB clock
145 * @irq: IRQ number
146 * @dev: Pointer to struct device
147 * @txbuf: Pointer to the TX buffer
148 * @rxbuf: Pointer to the RX buffer
149 * @bytes_to_transfer: Number of bytes left to transfer
150 * @bytes_to_receive: Number of bytes left to receive
151 * @genfifocs: Used for chip select
152 * @genfifobus: Used to select the upper or lower bus
153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
154 * @dma_addr: DMA address after mapping the kernel buffer
155 * @genfifoentry: Used for storing the genfifoentry instruction.
156 * @mode: Defines the mode in which QSPI is operating
1c26372e 157 * @data_completion: completion structure
dfe11a11
RW		 158 */
159struct zynqmp_qspi {
160 void __iomem *regs;
161 struct clk *refclk;
162 struct clk *pclk;
163 int irq;
164 struct device *dev;
165 const void *txbuf;
166 void *rxbuf;
167 int bytes_to_transfer;
168 int bytes_to_receive;
169 u32 genfifocs;
170 u32 genfifobus;
171 u32 dma_rx_bytes;
172 dma_addr_t dma_addr;
173 u32 genfifoentry;
174 enum mode_type mode;
1c26372e 175 struct completion data_completion;
a0f65be6 176 struct mutex op_lock;
dfe11a11
RW		 177};
178
179/**
91af6eb0 180 * zynqmp_gqspi_read - For GQSPI controller read operation
dfe11a11
RW		 181 * @xqspi: Pointer to the zynqmp_qspi structure
182 * @offset: Offset from where to read
91af6eb0 183 * Return: Value at the offset
dfe11a11
RW		 184 */
185static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
186{
187 return readl_relaxed(xqspi->regs + offset);
188}
189
190/**
91af6eb0 191 * zynqmp_gqspi_write - For GQSPI controller write operation
dfe11a11
RW		 192 * @xqspi: Pointer to the zynqmp_qspi structure
193 * @offset: Offset where to write
194 * @val: Value to be written
195 */
196static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
197 u32 val)
198{
199 writel_relaxed(val, (xqspi->regs + offset));
200}
201
202/**
91af6eb0 203 * zynqmp_gqspi_selectslave - For selection of slave device
dfe11a11 204 * @instanceptr: Pointer to the zynqmp_qspi structure
4b42b0b4
LJ		 205 * @slavecs: For chip select
206 * @slavebus: To check which bus is selected- upper or lower
dfe11a11
RW		 207 */
208static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
209 u8 slavecs, u8 slavebus)
210{
211 /*
212 * Bus and CS lines selected here will be updated in the instance and
213 * used for subsequent GENFIFO entries during transfer.
214 */
215
216 /* Choose slave select line */
217 switch (slavecs) {
218 case GQSPI_SELECT_FLASH_CS_BOTH:
219 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
220 GQSPI_GENFIFO_CS_UPPER;
861a481c 221 break;
dfe11a11
RW		 222 case GQSPI_SELECT_FLASH_CS_UPPER:
223 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
224 break;
225 case GQSPI_SELECT_FLASH_CS_LOWER:
226 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
227 break;
228 default:
229 dev_warn(instanceptr->dev, "Invalid slave select\n");
230 }
231
232 /* Choose the bus */
233 switch (slavebus) {
234 case GQSPI_SELECT_FLASH_BUS_BOTH:
235 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
236 GQSPI_GENFIFO_BUS_UPPER;
237 break;
238 case GQSPI_SELECT_FLASH_BUS_UPPER:
239 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
240 break;
241 case GQSPI_SELECT_FLASH_BUS_LOWER:
242 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
243 break;
244 default:
245 dev_warn(instanceptr->dev, "Invalid slave bus\n");
246 }
247}
248
249/**
91af6eb0 250 * zynqmp_qspi_init_hw - Initialize the hardware
dfe11a11
RW		 251 * @xqspi: Pointer to the zynqmp_qspi structure
252 *
253 * The default settings of the QSPI controller's configurable parameters on
254 * reset are
255 * - Master mode
256 * - TX threshold set to 1
257 * - RX threshold set to 1
258 * - Flash memory interface mode enabled
259 * This function performs the following actions
260 * - Disable and clear all the interrupts
261 * - Enable manual slave select
262 * - Enable manual start
263 * - Deselect all the chip select lines
264 * - Set the little endian mode of TX FIFO and
265 * - Enable the QSPI controller
266 */
267static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
268{
269 u32 config_reg;
270
271 /* Select the GQSPI mode */
272 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
273 /* Clear and disable interrupts */
274 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
275 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
276 GQSPI_ISR_WR_TO_CLR_MASK);
277 /* Clear the DMA STS */
278 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
279 zynqmp_gqspi_read(xqspi,
280 GQSPI_QSPIDMA_DST_I_STS_OFST));
281 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
282 zynqmp_gqspi_read(xqspi,
283 GQSPI_QSPIDMA_DST_STS_OFST) |
284 GQSPI_QSPIDMA_DST_STS_WTC);
285 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
286 zynqmp_gqspi_write(xqspi,
287 GQSPI_QSPIDMA_DST_I_DIS_OFST,
288 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
289 /* Disable the GQSPI */
290 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
291 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
292 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
293 /* Manual start */
294 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
295 /* Little endian by default */
296 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
297 /* Disable poll time out */
298 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
299 /* Set hold bit */
300 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
301 /* Clear pre-scalar by default */
302 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
303 /* CPHA 0 */
304 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
305 /* CPOL 0 */
306 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
307 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
308
309 /* Clear the TX and RX FIFO */
310 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
311 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
312 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
313 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
314 /* Set by default to allow for high frequencies */
315 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
316 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
317 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
318 /* Reset thresholds */
319 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
320 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
321 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
322 GQSPI_RX_FIFO_THRESHOLD);
323 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
324 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
325 zynqmp_gqspi_selectslave(xqspi,
326 GQSPI_SELECT_FLASH_CS_LOWER,
327 GQSPI_SELECT_FLASH_BUS_LOWER);
328 /* Initialize DMA */
329 zynqmp_gqspi_write(xqspi,
f09a433b
AKM		 330 GQSPI_QSPIDMA_DST_CTRL_OFST,
331 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
dfe11a11
RW		 332
333 /* Enable the GQSPI */
334 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
335}
336
337/**
91af6eb0 338 * zynqmp_qspi_copy_read_data - Copy data to RX buffer
dfe11a11
RW		 339 * @xqspi: Pointer to the zynqmp_qspi structure
340 * @data: The variable where data is stored
341 * @size: Number of bytes to be copied from data to RX buffer
342 */
343static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
344 ulong data, u8 size)
345{
346 memcpy(xqspi->rxbuf, &data, size);
347 xqspi->rxbuf += size;
348 xqspi->bytes_to_receive -= size;
349}
350
dfe11a11 351/**
91af6eb0 352 * zynqmp_qspi_chipselect - Select or deselect the chip select line
dfe11a11
RW		 353 * @qspi: Pointer to the spi_device structure
354 * @is_high: Select(0) or deselect (1) the chip select line
355 */
356static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
357{
358 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
359 ulong timeout;
1c26372e 360 u32 genfifoentry = 0, statusreg;
dfe11a11
RW		 361
362 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
dfe11a11
RW		 363
364 if (!is_high) {
1c26372e
AKM		 365 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
366 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
367 genfifoentry |= xqspi->genfifobus;
dfe11a11
RW		 368 genfifoentry |= xqspi->genfifocs;
369 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
370 } else {
371 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
372 }
373
374 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
375
dfe11a11
RW		 376 /* Manually start the generic FIFO command */
377 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
f09a433b
AKM		 378 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
379 GQSPI_CFG_START_GEN_FIFO_MASK);
dfe11a11
RW		 380
381 timeout = jiffies + msecs_to_jiffies(1000);
382
383 /* Wait until the generic FIFO command is empty */
384 do {
385 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
386
387 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
f09a433b 388 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
dfe11a11 389 break;
f09a433b 390 cpu_relax();
dfe11a11
RW		 391 } while (!time_after_eq(jiffies, timeout));
392
393 if (time_after_eq(jiffies, timeout))
394 dev_err(xqspi->dev, "Chip select timed out\n");
395}
396
397/**
1c26372e
AKM		 398 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
399 * @xqspi: xqspi is a pointer to the GQSPI instance
400 * @spimode: spimode - SPI or DUAL or QUAD.
401 * Return: Mask to set desired SPI mode in GENFIFO entry.
402 */
403static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
404 u8 spimode)
405{
406 u32 mask = 0;
407
408 switch (spimode) {
409 case GQSPI_SELECT_MODE_DUALSPI:
410 mask = GQSPI_GENFIFO_MODE_DUALSPI;
411 break;
412 case GQSPI_SELECT_MODE_QUADSPI:
413 mask = GQSPI_GENFIFO_MODE_QUADSPI;
414 break;
415 case GQSPI_SELECT_MODE_SPI:
416 mask = GQSPI_GENFIFO_MODE_SPI;
417 break;
418 default:
419 dev_warn(xqspi->dev, "Invalid SPI mode\n");
420 }
421
422 return mask;
423}
424
425/**
426 * zynqmp_qspi_config_op - Configure QSPI controller for specified
dfe11a11 427 * transfer
1c26372e 428 * @xqspi: Pointer to the zynqmp_qspi structure
dfe11a11 429 * @qspi: Pointer to the spi_device structure
dfe11a11
RW		 430 *
431 * Sets the operational mode of QSPI controller for the next QSPI transfer and
432 * sets the requested clock frequency.
433 *
434 * Return: Always 0
435 *
436 * Note:
437 * If the requested frequency is not an exact match with what can be
438 * obtained using the pre-scalar value, the driver sets the clock
439 * frequency which is lower than the requested frequency (maximum lower)
440 * for the transfer.
441 *
442 * If the requested frequency is higher or lower than that is supported
443 * by the QSPI controller the driver will set the highest or lowest
444 * frequency supported by controller.
445 */
1c26372e
AKM		 446static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
447 struct spi_device *qspi)
dfe11a11 448{
dfe11a11 449 ulong clk_rate;
1c26372e 450 u32 config_reg, baud_rate_val = 0;
dfe11a11
RW		 451
452 /* Set the clock frequency */
453 /* If req_hz == 0, default to lowest speed */
454 clk_rate = clk_get_rate(xqspi->refclk);
455
456 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
457 (clk_rate /
1c26372e 458 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
dfe11a11
RW		 459 baud_rate_val++;
460
461 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
462
463 /* Set the QSPI clock phase and clock polarity */
464 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
465
466 if (qspi->mode & SPI_CPHA)
467 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
468 if (qspi->mode & SPI_CPOL)
469 config_reg |= GQSPI_CFG_CLK_POL_MASK;
470
471 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
472 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
473 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
474 return 0;
475}
476
477/**
1c26372e 478 * zynqmp_qspi_setup_op - Configure the QSPI controller
dfe11a11
RW		 479 * @qspi: Pointer to the spi_device structure
480 *
481 * Sets the operational mode of QSPI controller for the next QSPI transfer,
482 * baud rate and divisor value to setup the requested qspi clock.
483 *
484 * Return: 0 on success; error value otherwise.
485 */
1c26372e 486static int zynqmp_qspi_setup_op(struct spi_device *qspi)
dfe11a11 487{
1c26372e
AKM		 488 struct spi_controller *ctlr = qspi->master;
489 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
490 struct device *dev = &ctlr->dev;
491 int ret;
492
493 if (ctlr->busy)
dfe11a11 494 return -EBUSY;
1c26372e
AKM		 495
496 ret = clk_enable(xqspi->refclk);
497 if (ret) {
498 dev_err(dev, "Cannot enable device clock.\n");
499 return ret;
500 }
501
502 ret = clk_enable(xqspi->pclk);
503 if (ret) {
504 dev_err(dev, "Cannot enable APB clock.\n");
505 clk_disable(xqspi->refclk);
506 return ret;
507 }
508 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
509
dfe11a11
RW		 510 return 0;
511}
512
513/**
91af6eb0 514 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
dfe11a11
RW		 515 * the FIFO or the bytes required to be
516 * transmitted.
517 * @xqspi: Pointer to the zynqmp_qspi structure
518 * @size: Number of bytes to be copied from TX buffer to TX FIFO
519 */
520static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
521{
522 u32 count = 0, intermediate;
523
8ad07d79 524 while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
dfe11a11
RW		 525 memcpy(&intermediate, xqspi->txbuf, 4);
526 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
527
528 if (xqspi->bytes_to_transfer >= 4) {
529 xqspi->txbuf += 4;
530 xqspi->bytes_to_transfer -= 4;
531 } else {
532 xqspi->txbuf += xqspi->bytes_to_transfer;
533 xqspi->bytes_to_transfer = 0;
534 }
535 count++;
536 }
537}
538
539/**
91af6eb0 540 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
dfe11a11
RW		 541 * the FIFO.
542 * @xqspi: Pointer to the zynqmp_qspi structure
543 * @size: Number of bytes to be copied from RX buffer to RX FIFO
544 */
545static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
546{
547 ulong data;
548 int count = 0;
549
550 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
551 if (xqspi->bytes_to_receive >= 4) {
f09a433b 552 (*(u32 *)xqspi->rxbuf) =
dfe11a11
RW		 553 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
554 xqspi->rxbuf += 4;
555 xqspi->bytes_to_receive -= 4;
556 count += 4;
557 } else {
558 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
559 count += xqspi->bytes_to_receive;
560 zynqmp_qspi_copy_read_data(xqspi, data,
561 xqspi->bytes_to_receive);
562 xqspi->bytes_to_receive = 0;
563 }
564 }
565}
566
1c26372e
AKM		 567/**
568 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
569 * @xqspi: Pointer to the zynqmp_qspi structure
570 * @nbits: Transfer/Receive buswidth.
571 * @genfifoentry: Variable in which GENFIFO mask is saved
572 */
573static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
574 u32 genfifoentry)
575{
576 u32 transfer_len = 0;
577
578 if (xqspi->txbuf) {
579 genfifoentry &= ~GQSPI_GENFIFO_RX;
580 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
581 genfifoentry |= GQSPI_GENFIFO_TX;
582 transfer_len = xqspi->bytes_to_transfer;
8ad07d79 583 } else if (xqspi->rxbuf) {
1c26372e
AKM		 584 genfifoentry &= ~GQSPI_GENFIFO_TX;
585 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
586 genfifoentry |= GQSPI_GENFIFO_RX;
587 if (xqspi->mode == GQSPI_MODE_DMA)
588 transfer_len = xqspi->dma_rx_bytes;
589 else
590 transfer_len = xqspi->bytes_to_receive;
8ad07d79
QW		 591 } else {
592 /* Sending dummy circles here */
593 genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
594 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
595 transfer_len = xqspi->bytes_to_transfer;
1c26372e
AKM		 596 }
597 genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
598 xqspi->genfifoentry = genfifoentry;
599
600 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
601 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
602 genfifoentry |= transfer_len;
603 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
604 } else {
605 int tempcount = transfer_len;
606 u32 exponent = 8; /* 2^8 = 256 */
607 u8 imm_data = tempcount & 0xFF;
608
609 tempcount &= ~(tempcount & 0xFF);
610 /* Immediate entry */
611 if (tempcount != 0) {
612 /* Exponent entries */
613 genfifoentry |= GQSPI_GENFIFO_EXP;
614 while (tempcount != 0) {
615 if (tempcount & GQSPI_GENFIFO_EXP_START) {
616 genfifoentry &=
617 ~GQSPI_GENFIFO_IMM_DATA_MASK;
618 genfifoentry |= exponent;
619 zynqmp_gqspi_write(xqspi,
620 GQSPI_GEN_FIFO_OFST,
621 genfifoentry);
622 }
623 tempcount = tempcount >> 1;
624 exponent++;
625 }
626 }
627 if (imm_data != 0) {
628 genfifoentry &= ~GQSPI_GENFIFO_EXP;
629 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
630 genfifoentry |= (u8)(imm_data & 0xFF);
631 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
632 genfifoentry);
633 }
634 }
635 if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
636 /* Dummy generic FIFO entry */
637 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
638 }
639}
640
dfe11a11 641/**
91af6eb0 642 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
dfe11a11
RW		 643 * controller
644 * @xqspi: zynqmp_qspi instance pointer
645 *
646 * This function handles DMA interrupt only.
647 */
648static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
649{
650 u32 config_reg, genfifoentry;
651
652 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
f09a433b 653 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
dfe11a11
RW		 654 xqspi->rxbuf += xqspi->dma_rx_bytes;
655 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
656 xqspi->dma_rx_bytes = 0;
657
658 /* Disabling the DMA interrupts */
659 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
f09a433b 660 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
dfe11a11
RW		 661
662 if (xqspi->bytes_to_receive > 0) {
663 /* Switch to IO mode,for remaining bytes to receive */
664 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
665 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
666 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
667
668 /* Initiate the transfer of remaining bytes */
669 genfifoentry = xqspi->genfifoentry;
670 genfifoentry |= xqspi->bytes_to_receive;
671 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
672
673 /* Dummy generic FIFO entry */
674 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
675
676 /* Manual start */
677 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
f09a433b
AKM		 678 (zynqmp_gqspi_read(xqspi,
679 GQSPI_CONFIG_OFST) |
680 GQSPI_CFG_START_GEN_FIFO_MASK));
dfe11a11
RW		 681
682 /* Enable the RX interrupts for IO mode */
683 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
f09a433b
AKM		 684 GQSPI_IER_GENFIFOEMPTY_MASK |
685 GQSPI_IER_RXNEMPTY_MASK |
686 GQSPI_IER_RXEMPTY_MASK);
dfe11a11
RW		 687 }
688}
689
690/**
91af6eb0 691 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
dfe11a11
RW		 692 * @irq: IRQ number
693 * @dev_id: Pointer to the xqspi structure
694 *
695 * This function handles TX empty only.
696 * On TX empty interrupt this function reads the received data from RX FIFO
697 * and fills the TX FIFO if there is any data remaining to be transferred.
698 *
699 * Return: IRQ_HANDLED when interrupt is handled
700 * IRQ_NONE otherwise.
701 */
702static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
703{
1c26372e
AKM		 704 struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
705 irqreturn_t ret = IRQ_NONE;
dfe11a11
RW		 706 u32 status, mask, dma_status = 0;
707
708 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
709 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
710 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
711
712 /* Read and clear DMA status */
713 if (xqspi->mode == GQSPI_MODE_DMA) {
714 dma_status =
715 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
716 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
f09a433b 717 dma_status);
dfe11a11
RW		 718 }
719
720 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
721 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
722 ret = IRQ_HANDLED;
723 }
724
725 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
726 zynqmp_process_dma_irq(xqspi);
727 ret = IRQ_HANDLED;
728 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
729 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
730 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
731 ret = IRQ_HANDLED;
732 }
733
f09a433b
AKM		 734 if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
735 ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
dfe11a11 736 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
1c26372e 737 complete(&xqspi->data_completion);
dfe11a11
RW		 738 ret = IRQ_HANDLED;
739 }
740 return ret;
741}
742
743/**
1c26372e 744 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
dfe11a11
RW		 745 * @xqspi: xqspi is a pointer to the GQSPI instance.
746 */
1c26372e 747static void zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
dfe11a11
RW		 748{
749 u32 rx_bytes, rx_rem, config_reg;
750 dma_addr_t addr;
751 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
752
f09a433b
AKM		 753 if (xqspi->bytes_to_receive < 8 ||
754 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
dfe11a11
RW		 755 /* Setting to IO mode */
756 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
757 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
758 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
759 xqspi->mode = GQSPI_MODE_IO;
760 xqspi->dma_rx_bytes = 0;
761 return;
762 }
763
764 rx_rem = xqspi->bytes_to_receive % 4;
765 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
766
767 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
f09a433b 768 rx_bytes, DMA_FROM_DEVICE);
dfe11a11
RW		 769 if (dma_mapping_error(xqspi->dev, addr))
770 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
771
772 xqspi->dma_rx_bytes = rx_bytes;
773 xqspi->dma_addr = addr;
774 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
f09a433b 775 (u32)(addr & 0xffffffff));
dfe11a11
RW		 776 addr = ((addr >> 16) >> 16);
777 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
f09a433b 778 ((u32)addr) & 0xfff);
dfe11a11
RW		 779
780 /* Enabling the DMA mode */
781 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
782 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
783 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
784 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
785
786 /* Switch to DMA mode */
787 xqspi->mode = GQSPI_MODE_DMA;
788
789 /* Write the number of bytes to transfer */
790 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
791}
792
793/**
1c26372e
AKM		 794 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
795 * TX FIFO, and fills the TX FIFO with as many
796 * bytes as possible.
797 * @xqspi: Pointer to the GQSPI instance.
798 * @tx_nbits: Transfer buswidth.
799 * @genfifoentry: Variable in which GENFIFO mask is returned
800 * to calling function
dfe11a11 801 */
1c26372e
AKM		 802static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
803 u32 genfifoentry)
dfe11a11
RW		 804{
805 u32 config_reg;
806
1c26372e
AKM		 807 zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
808 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
809 if (xqspi->mode == GQSPI_MODE_DMA) {
810 config_reg = zynqmp_gqspi_read(xqspi,
811 GQSPI_CONFIG_OFST);
812 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
813 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
814 config_reg);
815 xqspi->mode = GQSPI_MODE_IO;
dfe11a11
RW		 816 }
817}
818
819/**
1c26372e
AKM		 820 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
821 * RX DMA operation.
822 * @xqspi: xqspi is a pointer to the GQSPI instance.
823 * @rx_nbits: Receive buswidth.
824 * @genfifoentry: genfifoentry is pointer to the variable in which
825 * GENFIFO mask is returned to calling function
dfe11a11 826 */
1c26372e
AKM		 827static void zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
828 u32 genfifoentry)
dfe11a11 829{
1c26372e 830 zynqmp_qspi_setuprxdma(xqspi);
41d31093 831 zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
dfe11a11
RW		 832}
833
834/**
91af6eb0 835 * zynqmp_qspi_suspend - Suspend method for the QSPI driver
4b42b0b4 836 * @dev: Address of the platform_device structure
dfe11a11
RW		 837 *
838 * This function stops the QSPI driver queue and disables the QSPI controller
839 *
840 * Return: Always 0
841 */
842static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
843{
1c26372e
AKM		 844 struct spi_controller *ctlr = dev_get_drvdata(dev);
845 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
dfe11a11 846
1c26372e 847 spi_controller_suspend(ctlr);
dfe11a11 848
1c26372e 849 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
dfe11a11
RW		 850
851 return 0;
852}
853
854/**
91af6eb0 855 * zynqmp_qspi_resume - Resume method for the QSPI driver
dfe11a11
RW		 856 * @dev: Address of the platform_device structure
857 *
858 * The function starts the QSPI driver queue and initializes the QSPI
859 * controller
860 *
861 * Return: 0 on success; error value otherwise
862 */
863static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
864{
1c26372e
AKM		 865 struct spi_controller *ctlr = dev_get_drvdata(dev);
866 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
dfe11a11
RW		 867 int ret = 0;
868
869 ret = clk_enable(xqspi->pclk);
870 if (ret) {
871 dev_err(dev, "Cannot enable APB clock.\n");
872 return ret;
873 }
874
875 ret = clk_enable(xqspi->refclk);
876 if (ret) {
877 dev_err(dev, "Cannot enable device clock.\n");
878 clk_disable(xqspi->pclk);
879 return ret;
880 }
881
1c26372e 882 spi_controller_resume(ctlr);
dfe11a11 883
9e3a0003
NSR		 884 clk_disable(xqspi->refclk);
885 clk_disable(xqspi->pclk);
dfe11a11
RW		 886 return 0;
887}
888
9e3a0003
NSR		 889/**
890 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
891 * @dev: Address of the platform_device structure
892 *
893 * This function disables the clocks
894 *
895 * Return: Always 0
896 */
897static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
898{
1c26372e 899 struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_get_drvdata(dev);
9e3a0003
NSR		 900
901 clk_disable(xqspi->refclk);
902 clk_disable(xqspi->pclk);
903
904 return 0;
905}
906
907/**
908 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
909 * @dev: Address of the platform_device structure
910 *
911 * This function enables the clocks
912 *
913 * Return: 0 on success and error value on error
914 */
915static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
916{
1c26372e 917 struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_get_drvdata(dev);
9e3a0003
NSR		 918 int ret;
919
920 ret = clk_enable(xqspi->pclk);
921 if (ret) {
922 dev_err(dev, "Cannot enable APB clock.\n");
923 return ret;
924 }
925
926 ret = clk_enable(xqspi->refclk);
927 if (ret) {
928 dev_err(dev, "Cannot enable device clock.\n");
929 clk_disable(xqspi->pclk);
930 return ret;
931 }
932
933 return 0;
934}
935
1c26372e
AKM		 936/**
937 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
938 * @mem: The SPI memory
939 * @op: The memory operation to execute
940 *
941 * Executes a memory operation.
942 *
943 * This function first selects the chip and starts the memory operation.
944 *
945 * Return: 0 in case of success, a negative error code otherwise.
946 */
947static int zynqmp_qspi_exec_op(struct spi_mem *mem,
948 const struct spi_mem_op *op)
949{
950 struct zynqmp_qspi *xqspi = spi_controller_get_devdata
951 (mem->spi->master);
952 int err = 0, i;
953 u8 *tmpbuf;
954 u32 genfifoentry = 0;
955
956 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
957 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
958 op->dummy.buswidth, op->data.buswidth);
959
a0f65be6 960 mutex_lock(&xqspi->op_lock);
1c26372e
AKM		 961 zynqmp_qspi_config_op(xqspi, mem->spi);
962 zynqmp_qspi_chipselect(mem->spi, false);
963 genfifoentry |= xqspi->genfifocs;
964 genfifoentry |= xqspi->genfifobus;
965
966 if (op->cmd.opcode) {
967 tmpbuf = kzalloc(op->cmd.nbytes, GFP_KERNEL | GFP_DMA);
60433572
WY		 968 if (!tmpbuf) {
969 mutex_unlock(&xqspi->op_lock);
1c26372e 970 return -ENOMEM;
60433572 971 }
1c26372e
AKM		 972 tmpbuf[0] = op->cmd.opcode;
973 reinit_completion(&xqspi->data_completion);
974 xqspi->txbuf = tmpbuf;
975 xqspi->rxbuf = NULL;
976 xqspi->bytes_to_transfer = op->cmd.nbytes;
977 xqspi->bytes_to_receive = 0;
978 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
979 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
980 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
981 GQSPI_CFG_START_GEN_FIFO_MASK);
982 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
983 GQSPI_IER_GENFIFOEMPTY_MASK |
984 GQSPI_IER_TXNOT_FULL_MASK);
a16bff68 985 if (!wait_for_completion_timeout
1c26372e
AKM		 986 (&xqspi->data_completion, msecs_to_jiffies(1000))) {
987 err = -ETIMEDOUT;
988 kfree(tmpbuf);
989 goto return_err;
990 }
991 kfree(tmpbuf);
992 }
993
994 if (op->addr.nbytes) {
995 for (i = 0; i < op->addr.nbytes; i++) {
996 *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
997 (8 * (op->addr.nbytes - i - 1));
998 }
999
1000 reinit_completion(&xqspi->data_completion);
1001 xqspi->rxbuf = NULL;
1002 xqspi->bytes_to_transfer = op->addr.nbytes;
1003 xqspi->bytes_to_receive = 0;
1004 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
1005 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1006 zynqmp_gqspi_read(xqspi,
1007 GQSPI_CONFIG_OFST) |
1008 GQSPI_CFG_START_GEN_FIFO_MASK);
1009 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1010 GQSPI_IER_TXEMPTY_MASK |
1011 GQSPI_IER_GENFIFOEMPTY_MASK |
1012 GQSPI_IER_TXNOT_FULL_MASK);
a16bff68 1013 if (!wait_for_completion_timeout
1c26372e
AKM		 1014 (&xqspi->data_completion, msecs_to_jiffies(1000))) {
1015 err = -ETIMEDOUT;
1016 goto return_err;
1017 }
1018 }
1019
1020 if (op->dummy.nbytes) {
8ad07d79 1021 xqspi->txbuf = NULL;
1c26372e 1022 xqspi->rxbuf = NULL;
8ad07d79
QW		 1023 /*
1024 * xqspi->bytes_to_transfer here represents the dummy circles
1025 * which need to be sent.
1026 */
1027 xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1c26372e 1028 xqspi->bytes_to_receive = 0;
8ad07d79
QW		 1029 /*
1030 * Using op->data.buswidth instead of op->dummy.buswidth here because
1031 * we need to use it to configure the correct SPI mode.
1032 */
1033 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1c26372e
AKM		 1034 genfifoentry);
1035 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1036 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1037 GQSPI_CFG_START_GEN_FIFO_MASK);
1c26372e
AKM		 1038 }
1039
1040 if (op->data.nbytes) {
1041 reinit_completion(&xqspi->data_completion);
1042 if (op->data.dir == SPI_MEM_DATA_OUT) {
1043 xqspi->txbuf = (u8 *)op->data.buf.out;
1044 xqspi->rxbuf = NULL;
1045 xqspi->bytes_to_transfer = op->data.nbytes;
1046 xqspi->bytes_to_receive = 0;
1047 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1048 genfifoentry);
1049 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1050 zynqmp_gqspi_read
1051 (xqspi, GQSPI_CONFIG_OFST) |
1052 GQSPI_CFG_START_GEN_FIFO_MASK);
1053 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1054 GQSPI_IER_TXEMPTY_MASK |
1055 GQSPI_IER_GENFIFOEMPTY_MASK |
1056 GQSPI_IER_TXNOT_FULL_MASK);
1057 } else {
1058 xqspi->txbuf = NULL;
1059 xqspi->rxbuf = (u8 *)op->data.buf.in;
1060 xqspi->bytes_to_receive = op->data.nbytes;
1061 xqspi->bytes_to_transfer = 0;
1062 zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1063 genfifoentry);
1064 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1065 zynqmp_gqspi_read
1066 (xqspi, GQSPI_CONFIG_OFST) |
1067 GQSPI_CFG_START_GEN_FIFO_MASK);
1068 if (xqspi->mode == GQSPI_MODE_DMA) {
1069 zynqmp_gqspi_write
1070 (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1071 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1072 } else {
1073 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1074 GQSPI_IER_GENFIFOEMPTY_MASK |
1075 GQSPI_IER_RXNEMPTY_MASK |
1076 GQSPI_IER_RXEMPTY_MASK);
1077 }
1078 }
a16bff68 1079 if (!wait_for_completion_timeout
1c26372e
AKM		 1080 (&xqspi->data_completion, msecs_to_jiffies(1000)))
1081 err = -ETIMEDOUT;
1082 }
1083
1084return_err:
1085
1086 zynqmp_qspi_chipselect(mem->spi, true);
a0f65be6 1087 mutex_unlock(&xqspi->op_lock);
1c26372e
AKM		 1088
1089 return err;
1090}
1091
9e3a0003
NSR		 1092static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1093 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1094 zynqmp_runtime_resume, NULL)
1095 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1096};
dfe11a11 1097
1c26372e
AKM		 1098static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1099 .exec_op = zynqmp_qspi_exec_op,
1100};
1101
dfe11a11 1102/**
91af6eb0 1103 * zynqmp_qspi_probe - Probe method for the QSPI driver
dfe11a11
RW		 1104 * @pdev: Pointer to the platform_device structure
1105 *
1106 * This function initializes the driver data structures and the hardware.
1107 *
1108 * Return: 0 on success; error value otherwise
1109 */
1110static int zynqmp_qspi_probe(struct platform_device *pdev)
1111{
1112 int ret = 0;
1c26372e 1113 struct spi_controller *ctlr;
dfe11a11 1114 struct zynqmp_qspi *xqspi;
dfe11a11 1115 struct device *dev = &pdev->dev;
1c26372e 1116 struct device_node *np = dev->of_node;
dfe11a11 1117
1c26372e
AKM		 1118 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1119 if (!ctlr)
dfe11a11
RW		 1120 return -ENOMEM;
1121
1c26372e
AKM		 1122 xqspi = spi_controller_get_devdata(ctlr);
1123 xqspi->dev = dev;
1124 platform_set_drvdata(pdev, xqspi);
dfe11a11 1125
214d1edb 1126 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
dfe11a11
RW		 1127 if (IS_ERR(xqspi->regs)) {
1128 ret = PTR_ERR(xqspi->regs);
1129 goto remove_master;
1130 }
1131
dfe11a11
RW		 1132 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1133 if (IS_ERR(xqspi->pclk)) {
1134 dev_err(dev, "pclk clock not found.\n");
1135 ret = PTR_ERR(xqspi->pclk);
1136 goto remove_master;
1137 }
1138
1c26372e 1139 init_completion(&xqspi->data_completion);
dfe11a11
RW		 1140
1141 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1142 if (IS_ERR(xqspi->refclk)) {
1143 dev_err(dev, "ref_clk clock not found.\n");
1144 ret = PTR_ERR(xqspi->refclk);
1145 goto clk_dis_pclk;
1146 }
1147
1c26372e
AKM		 1148 ret = clk_prepare_enable(xqspi->pclk);
1149 if (ret) {
1150 dev_err(dev, "Unable to enable APB clock.\n");
1151 goto remove_master;
1152 }
1153
dfe11a11
RW		 1154 ret = clk_prepare_enable(xqspi->refclk);
1155 if (ret) {
1156 dev_err(dev, "Unable to enable device clock.\n");
1157 goto clk_dis_pclk;
1158 }
1159
a0f65be6
QW		 1160 mutex_init(&xqspi->op_lock);
1161
9e3a0003
NSR		 1162 pm_runtime_use_autosuspend(&pdev->dev);
1163 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1164 pm_runtime_set_active(&pdev->dev);
1165 pm_runtime_enable(&pdev->dev);
58eaa7b2
DL		 1166
1167 ret = pm_runtime_get_sync(&pdev->dev);
1168 if (ret < 0) {
1169 dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
1170 goto clk_dis_all;
1171 }
1172
dfe11a11
RW		 1173 /* QSPI controller initializations */
1174 zynqmp_qspi_init_hw(xqspi);
1175
1176 xqspi->irq = platform_get_irq(pdev, 0);
1177 if (xqspi->irq <= 0) {
1178 ret = -ENXIO;
dfe11a11
RW		 1179 goto clk_dis_all;
1180 }
1181 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1c26372e 1182 0, pdev->name, xqspi);
dfe11a11
RW		 1183 if (ret != 0) {
1184 ret = -ENXIO;
1185 dev_err(dev, "request_irq failed\n");
1186 goto clk_dis_all;
1187 }
1188
1c26372e
AKM		 1189 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1190 ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1191 ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1192 ctlr->setup = zynqmp_qspi_setup_op;
1193 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1194 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1195 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
dfe11a11 1196 SPI_TX_DUAL | SPI_TX_QUAD;
1c26372e 1197 ctlr->dev.of_node = np;
58eaa7b2 1198 ctlr->auto_runtime_pm = true;
dfe11a11 1199
1c26372e
AKM		 1200 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1201 if (ret) {
1202 dev_err(&pdev->dev, "spi_register_controller failed\n");
dfe11a11 1203 goto clk_dis_all;
1c26372e 1204 }
dfe11a11 1205
58eaa7b2
DL		 1206 pm_runtime_mark_last_busy(&pdev->dev);
1207 pm_runtime_put_autosuspend(&pdev->dev);
1208
dfe11a11
RW		 1209 return 0;
1210
1211clk_dis_all:
58eaa7b2 1212 pm_runtime_put_sync(&pdev->dev);
9e3a0003
NSR		 1213 pm_runtime_set_suspended(&pdev->dev);
1214 pm_runtime_disable(&pdev->dev);
dfe11a11
RW		 1215 clk_disable_unprepare(xqspi->refclk);
1216clk_dis_pclk:
1217 clk_disable_unprepare(xqspi->pclk);
1218remove_master:
1c26372e 1219 spi_controller_put(ctlr);
dfe11a11
RW		 1220
1221 return ret;
1222}
1223
1224/**
91af6eb0 1225 * zynqmp_qspi_remove - Remove method for the QSPI driver
dfe11a11
RW		 1226 * @pdev: Pointer to the platform_device structure
1227 *
1228 * This function is called if a device is physically removed from the system or
1229 * if the driver module is being unloaded. It frees all resources allocated to
1230 * the device.
1231 *
1232 * Return: 0 Always
1233 */
1234static int zynqmp_qspi_remove(struct platform_device *pdev)
1235{
1c26372e 1236 struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
dfe11a11
RW		 1237
1238 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1239 clk_disable_unprepare(xqspi->refclk);
1240 clk_disable_unprepare(xqspi->pclk);
9e3a0003
NSR		 1241 pm_runtime_set_suspended(&pdev->dev);
1242 pm_runtime_disable(&pdev->dev);
dfe11a11 1243
dfe11a11
RW		 1244 return 0;
1245}
1246
1247static const struct of_device_id zynqmp_qspi_of_match[] = {
1248 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1249 { /* End of table */ }
1250};
1251
1252MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1253
1254static struct platform_driver zynqmp_qspi_driver = {
1255 .probe = zynqmp_qspi_probe,
1256 .remove = zynqmp_qspi_remove,
1257 .driver = {
1258 .name = "zynqmp-qspi",
1259 .of_match_table = zynqmp_qspi_of_match,
1260 .pm = &zynqmp_qspi_dev_pm_ops,
1261 },
1262};
1263
1264module_platform_driver(zynqmp_qspi_driver);
1265
1266MODULE_AUTHOR("Xilinx, Inc.");
1267MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1268MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)