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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 38
[linux-block.git] / drivers / spi / spi-zynqmp-gqspi.c
CommitLineData
dfe11a11
RW		 1/*
2 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
3 * (master mode only)
4 *
5 * Copyright (C) 2009 - 2015 Xilinx, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
ab7b7c71 17#include <linux/firmware/xlnx-zynqmp.h>
dfe11a11
RW		 18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
23#include <linux/platform_device.h>
9e3a0003 24#include <linux/pm_runtime.h>
dfe11a11
RW		 25#include <linux/spi/spi.h>
26#include <linux/spinlock.h>
27#include <linux/workqueue.h>
28
29/* Generic QSPI register offsets */
30#define GQSPI_CONFIG_OFST 0x00000100
31#define GQSPI_ISR_OFST 0x00000104
32#define GQSPI_IDR_OFST 0x0000010C
33#define GQSPI_IER_OFST 0x00000108
34#define GQSPI_IMASK_OFST 0x00000110
35#define GQSPI_EN_OFST 0x00000114
36#define GQSPI_TXD_OFST 0x0000011C
37#define GQSPI_RXD_OFST 0x00000120
38#define GQSPI_TX_THRESHOLD_OFST 0x00000128
39#define GQSPI_RX_THRESHOLD_OFST 0x0000012C
40#define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
41#define GQSPI_GEN_FIFO_OFST 0x00000140
42#define GQSPI_SEL_OFST 0x00000144
43#define GQSPI_GF_THRESHOLD_OFST 0x00000150
44#define GQSPI_FIFO_CTRL_OFST 0x0000014C
45#define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
46#define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
47#define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
48#define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
49#define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
50#define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
51#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
52#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
53#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
54
55/* GQSPI register bit masks */
56#define GQSPI_SEL_MASK 0x00000001
57#define GQSPI_EN_MASK 0x00000001
58#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
59#define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
60#define GQSPI_IDR_ALL_MASK 0x00000FBE
61#define GQSPI_CFG_MODE_EN_MASK 0xC0000000
62#define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
63#define GQSPI_CFG_ENDIAN_MASK 0x04000000
64#define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
65#define GQSPI_CFG_WP_HOLD_MASK 0x00080000
66#define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
67#define GQSPI_CFG_CLK_PHA_MASK 0x00000004
68#define GQSPI_CFG_CLK_POL_MASK 0x00000002
69#define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
70#define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
71#define GQSPI_GENFIFO_DATA_XFER 0x00000100
72#define GQSPI_GENFIFO_EXP 0x00000200
73#define GQSPI_GENFIFO_MODE_SPI 0x00000400
74#define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
75#define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
76#define GQSPI_GENFIFO_MODE_MASK 0x00000C00
77#define GQSPI_GENFIFO_CS_LOWER 0x00001000
78#define GQSPI_GENFIFO_CS_UPPER 0x00002000
79#define GQSPI_GENFIFO_BUS_LOWER 0x00004000
80#define GQSPI_GENFIFO_BUS_UPPER 0x00008000
81#define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
82#define GQSPI_GENFIFO_BUS_MASK 0x0000C000
83#define GQSPI_GENFIFO_TX 0x00010000
84#define GQSPI_GENFIFO_RX 0x00020000
85#define GQSPI_GENFIFO_STRIPE 0x00040000
86#define GQSPI_GENFIFO_POLL 0x00080000
87#define GQSPI_GENFIFO_EXP_START 0x00000100
88#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
89#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
90#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
91#define GQSPI_ISR_RXEMPTY_MASK 0x00000800
92#define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
93#define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
94#define GQSPI_ISR_TXEMPTY_MASK 0x00000100
95#define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
96#define GQSPI_ISR_RXFULL_MASK 0x00000020
97#define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
98#define GQSPI_ISR_TXFULL_MASK 0x00000008
99#define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
100#define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
101#define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
102#define GQSPI_IER_RXEMPTY_MASK 0x00000800
103#define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
104#define GQSPI_IER_RXNEMPTY_MASK 0x00000010
105#define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
106#define GQSPI_IER_TXEMPTY_MASK 0x00000100
107#define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
108#define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
109#define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
110#define GQSPI_ISR_IDR_MASK 0x00000994
111#define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
112#define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
113#define GQSPI_IRQ_MASK 0x00000980
114
115#define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
116#define GQSPI_GENFIFO_CS_SETUP 0x4
117#define GQSPI_GENFIFO_CS_HOLD 0x3
118#define GQSPI_TXD_DEPTH 64
119#define GQSPI_RX_FIFO_THRESHOLD 32
120#define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
121#define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
122#define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
123 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
124#define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
125#define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
126#define GQSPI_SELECT_FLASH_CS_LOWER 0x1
127#define GQSPI_SELECT_FLASH_CS_UPPER 0x2
128#define GQSPI_SELECT_FLASH_CS_BOTH 0x3
129#define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
130#define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
131#define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
132#define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
133#define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
134#define GQSPI_SELECT_MODE_SPI 0x1
135#define GQSPI_SELECT_MODE_DUALSPI 0x2
136#define GQSPI_SELECT_MODE_QUADSPI 0x4
137#define GQSPI_DMA_UNALIGN 0x3
138#define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
139
9e3a0003 140#define SPI_AUTOSUSPEND_TIMEOUT 3000
dfe11a11 141enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
3d031378 142static const struct zynqmp_eemi_ops *eemi_ops;
dfe11a11
RW		 143
144/**
145 * struct zynqmp_qspi - Defines qspi driver instance
146 * @regs: Virtual address of the QSPI controller registers
147 * @refclk: Pointer to the peripheral clock
148 * @pclk: Pointer to the APB clock
149 * @irq: IRQ number
150 * @dev: Pointer to struct device
151 * @txbuf: Pointer to the TX buffer
152 * @rxbuf: Pointer to the RX buffer
153 * @bytes_to_transfer: Number of bytes left to transfer
154 * @bytes_to_receive: Number of bytes left to receive
155 * @genfifocs: Used for chip select
156 * @genfifobus: Used to select the upper or lower bus
157 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
158 * @dma_addr: DMA address after mapping the kernel buffer
159 * @genfifoentry: Used for storing the genfifoentry instruction.
160 * @mode: Defines the mode in which QSPI is operating
161 */
162struct zynqmp_qspi {
163 void __iomem *regs;
164 struct clk *refclk;
165 struct clk *pclk;
166 int irq;
167 struct device *dev;
168 const void *txbuf;
169 void *rxbuf;
170 int bytes_to_transfer;
171 int bytes_to_receive;
172 u32 genfifocs;
173 u32 genfifobus;
174 u32 dma_rx_bytes;
175 dma_addr_t dma_addr;
176 u32 genfifoentry;
177 enum mode_type mode;
178};
179
180/**
181 * zynqmp_gqspi_read: For GQSPI controller read operation
182 * @xqspi: Pointer to the zynqmp_qspi structure
183 * @offset: Offset from where to read
184 */
185static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
186{
187 return readl_relaxed(xqspi->regs + offset);
188}
189
190/**
191 * zynqmp_gqspi_write: For GQSPI controller write operation
192 * @xqspi: Pointer to the zynqmp_qspi structure
193 * @offset: Offset where to write
194 * @val: Value to be written
195 */
196static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
197 u32 val)
198{
199 writel_relaxed(val, (xqspi->regs + offset));
200}
201
202/**
203 * zynqmp_gqspi_selectslave: For selection of slave device
204 * @instanceptr: Pointer to the zynqmp_qspi structure
205 * @flashcs: For chip select
206 * @flashbus: To check which bus is selected- upper or lower
207 */
208static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
209 u8 slavecs, u8 slavebus)
210{
211 /*
212 * Bus and CS lines selected here will be updated in the instance and
213 * used for subsequent GENFIFO entries during transfer.
214 */
215
216 /* Choose slave select line */
217 switch (slavecs) {
218 case GQSPI_SELECT_FLASH_CS_BOTH:
219 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
220 GQSPI_GENFIFO_CS_UPPER;
861a481c 221 break;
dfe11a11
RW		 222 case GQSPI_SELECT_FLASH_CS_UPPER:
223 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
224 break;
225 case GQSPI_SELECT_FLASH_CS_LOWER:
226 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
227 break;
228 default:
229 dev_warn(instanceptr->dev, "Invalid slave select\n");
230 }
231
232 /* Choose the bus */
233 switch (slavebus) {
234 case GQSPI_SELECT_FLASH_BUS_BOTH:
235 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
236 GQSPI_GENFIFO_BUS_UPPER;
237 break;
238 case GQSPI_SELECT_FLASH_BUS_UPPER:
239 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
240 break;
241 case GQSPI_SELECT_FLASH_BUS_LOWER:
242 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
243 break;
244 default:
245 dev_warn(instanceptr->dev, "Invalid slave bus\n");
246 }
247}
248
249/**
250 * zynqmp_qspi_init_hw: Initialize the hardware
251 * @xqspi: Pointer to the zynqmp_qspi structure
252 *
253 * The default settings of the QSPI controller's configurable parameters on
254 * reset are
255 * - Master mode
256 * - TX threshold set to 1
257 * - RX threshold set to 1
258 * - Flash memory interface mode enabled
259 * This function performs the following actions
260 * - Disable and clear all the interrupts
261 * - Enable manual slave select
262 * - Enable manual start
263 * - Deselect all the chip select lines
264 * - Set the little endian mode of TX FIFO and
265 * - Enable the QSPI controller
266 */
267static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
268{
269 u32 config_reg;
270
271 /* Select the GQSPI mode */
272 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
273 /* Clear and disable interrupts */
274 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
275 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
276 GQSPI_ISR_WR_TO_CLR_MASK);
277 /* Clear the DMA STS */
278 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
279 zynqmp_gqspi_read(xqspi,
280 GQSPI_QSPIDMA_DST_I_STS_OFST));
281 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
282 zynqmp_gqspi_read(xqspi,
283 GQSPI_QSPIDMA_DST_STS_OFST) |
284 GQSPI_QSPIDMA_DST_STS_WTC);
285 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
286 zynqmp_gqspi_write(xqspi,
287 GQSPI_QSPIDMA_DST_I_DIS_OFST,
288 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
289 /* Disable the GQSPI */
290 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
291 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
292 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
293 /* Manual start */
294 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
295 /* Little endian by default */
296 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
297 /* Disable poll time out */
298 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
299 /* Set hold bit */
300 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
301 /* Clear pre-scalar by default */
302 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
303 /* CPHA 0 */
304 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
305 /* CPOL 0 */
306 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
307 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
308
309 /* Clear the TX and RX FIFO */
310 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
311 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
312 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
313 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
314 /* Set by default to allow for high frequencies */
315 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
316 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
317 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
318 /* Reset thresholds */
319 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
320 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
321 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
322 GQSPI_RX_FIFO_THRESHOLD);
323 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
324 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
325 zynqmp_gqspi_selectslave(xqspi,
326 GQSPI_SELECT_FLASH_CS_LOWER,
327 GQSPI_SELECT_FLASH_BUS_LOWER);
328 /* Initialize DMA */
329 zynqmp_gqspi_write(xqspi,
330 GQSPI_QSPIDMA_DST_CTRL_OFST,
331 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
332
333 /* Enable the GQSPI */
334 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
335}
336
337/**
338 * zynqmp_qspi_copy_read_data: Copy data to RX buffer
339 * @xqspi: Pointer to the zynqmp_qspi structure
340 * @data: The variable where data is stored
341 * @size: Number of bytes to be copied from data to RX buffer
342 */
343static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
344 ulong data, u8 size)
345{
346 memcpy(xqspi->rxbuf, &data, size);
347 xqspi->rxbuf += size;
348 xqspi->bytes_to_receive -= size;
349}
350
351/**
352 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer.
353 * @master: Pointer to the spi_master structure which provides
354 * information about the controller.
355 *
356 * This function enables SPI master controller.
357 *
358 * Return: 0 on success; error value otherwise
359 */
360static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
361{
362 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
dfe11a11
RW		 363
364 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
365 return 0;
dfe11a11
RW		 366}
367
368/**
369 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer
370 * @master: Pointer to the spi_master structure which provides
371 * information about the controller.
372 *
373 * This function disables the SPI master controller.
374 *
375 * Return: Always 0
376 */
377static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
378{
379 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
380
381 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
dfe11a11
RW		 382 return 0;
383}
384
385/**
386 * zynqmp_qspi_chipselect: Select or deselect the chip select line
387 * @qspi: Pointer to the spi_device structure
388 * @is_high: Select(0) or deselect (1) the chip select line
389 */
390static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
391{
392 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
393 ulong timeout;
394 u32 genfifoentry = 0x0, statusreg;
395
396 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
397 genfifoentry |= xqspi->genfifobus;
398
399 if (!is_high) {
400 genfifoentry |= xqspi->genfifocs;
401 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
402 } else {
403 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
404 }
405
406 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
407
408 /* Dummy generic FIFO entry */
409 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
410
411 /* Manually start the generic FIFO command */
412 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
413 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
414 GQSPI_CFG_START_GEN_FIFO_MASK);
415
416 timeout = jiffies + msecs_to_jiffies(1000);
417
418 /* Wait until the generic FIFO command is empty */
419 do {
420 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
421
422 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
423 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
424 break;
425 else
426 cpu_relax();
427 } while (!time_after_eq(jiffies, timeout));
428
429 if (time_after_eq(jiffies, timeout))
430 dev_err(xqspi->dev, "Chip select timed out\n");
431}
432
433/**
434 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified
435 * transfer
436 * @qspi: Pointer to the spi_device structure
437 * @transfer: Pointer to the spi_transfer structure which provides
438 * information about next transfer setup parameters
439 *
440 * Sets the operational mode of QSPI controller for the next QSPI transfer and
441 * sets the requested clock frequency.
442 *
443 * Return: Always 0
444 *
445 * Note:
446 * If the requested frequency is not an exact match with what can be
447 * obtained using the pre-scalar value, the driver sets the clock
448 * frequency which is lower than the requested frequency (maximum lower)
449 * for the transfer.
450 *
451 * If the requested frequency is higher or lower than that is supported
452 * by the QSPI controller the driver will set the highest or lowest
453 * frequency supported by controller.
454 */
455static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
456 struct spi_transfer *transfer)
457{
458 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
459 ulong clk_rate;
460 u32 config_reg, req_hz, baud_rate_val = 0;
461
462 if (transfer)
463 req_hz = transfer->speed_hz;
464 else
465 req_hz = qspi->max_speed_hz;
466
467 /* Set the clock frequency */
468 /* If req_hz == 0, default to lowest speed */
469 clk_rate = clk_get_rate(xqspi->refclk);
470
471 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
472 (clk_rate /
473 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
474 baud_rate_val++;
475
476 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
477
478 /* Set the QSPI clock phase and clock polarity */
479 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
480
481 if (qspi->mode & SPI_CPHA)
482 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
483 if (qspi->mode & SPI_CPOL)
484 config_reg |= GQSPI_CFG_CLK_POL_MASK;
485
486 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
487 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
488 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
489 return 0;
490}
491
492/**
493 * zynqmp_qspi_setup: Configure the QSPI controller
494 * @qspi: Pointer to the spi_device structure
495 *
496 * Sets the operational mode of QSPI controller for the next QSPI transfer,
497 * baud rate and divisor value to setup the requested qspi clock.
498 *
499 * Return: 0 on success; error value otherwise.
500 */
501static int zynqmp_qspi_setup(struct spi_device *qspi)
502{
503 if (qspi->master->busy)
504 return -EBUSY;
505 return 0;
506}
507
508/**
509 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in
510 * the FIFO or the bytes required to be
511 * transmitted.
512 * @xqspi: Pointer to the zynqmp_qspi structure
513 * @size: Number of bytes to be copied from TX buffer to TX FIFO
514 */
515static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
516{
517 u32 count = 0, intermediate;
518
519 while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
520 memcpy(&intermediate, xqspi->txbuf, 4);
521 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
522
523 if (xqspi->bytes_to_transfer >= 4) {
524 xqspi->txbuf += 4;
525 xqspi->bytes_to_transfer -= 4;
526 } else {
527 xqspi->txbuf += xqspi->bytes_to_transfer;
528 xqspi->bytes_to_transfer = 0;
529 }
530 count++;
531 }
532}
533
534/**
535 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in
536 * the FIFO.
537 * @xqspi: Pointer to the zynqmp_qspi structure
538 * @size: Number of bytes to be copied from RX buffer to RX FIFO
539 */
540static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
541{
542 ulong data;
543 int count = 0;
544
545 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
546 if (xqspi->bytes_to_receive >= 4) {
547 (*(u32 *) xqspi->rxbuf) =
548 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
549 xqspi->rxbuf += 4;
550 xqspi->bytes_to_receive -= 4;
551 count += 4;
552 } else {
553 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
554 count += xqspi->bytes_to_receive;
555 zynqmp_qspi_copy_read_data(xqspi, data,
556 xqspi->bytes_to_receive);
557 xqspi->bytes_to_receive = 0;
558 }
559 }
560}
561
562/**
563 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI
564 * controller
565 * @xqspi: zynqmp_qspi instance pointer
566 *
567 * This function handles DMA interrupt only.
568 */
569static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
570{
571 u32 config_reg, genfifoentry;
572
573 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
574 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
575 xqspi->rxbuf += xqspi->dma_rx_bytes;
576 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
577 xqspi->dma_rx_bytes = 0;
578
579 /* Disabling the DMA interrupts */
580 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
581 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
582
583 if (xqspi->bytes_to_receive > 0) {
584 /* Switch to IO mode,for remaining bytes to receive */
585 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
586 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
587 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
588
589 /* Initiate the transfer of remaining bytes */
590 genfifoentry = xqspi->genfifoentry;
591 genfifoentry |= xqspi->bytes_to_receive;
592 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
593
594 /* Dummy generic FIFO entry */
595 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
596
597 /* Manual start */
598 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
599 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
600 GQSPI_CFG_START_GEN_FIFO_MASK));
601
602 /* Enable the RX interrupts for IO mode */
603 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
604 GQSPI_IER_GENFIFOEMPTY_MASK |
605 GQSPI_IER_RXNEMPTY_MASK |
606 GQSPI_IER_RXEMPTY_MASK);
607 }
608}
609
610/**
611 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller
612 * @irq: IRQ number
613 * @dev_id: Pointer to the xqspi structure
614 *
615 * This function handles TX empty only.
616 * On TX empty interrupt this function reads the received data from RX FIFO
617 * and fills the TX FIFO if there is any data remaining to be transferred.
618 *
619 * Return: IRQ_HANDLED when interrupt is handled
620 * IRQ_NONE otherwise.
621 */
622static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
623{
624 struct spi_master *master = dev_id;
625 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
626 int ret = IRQ_NONE;
627 u32 status, mask, dma_status = 0;
628
629 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
630 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
631 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
632
633 /* Read and clear DMA status */
634 if (xqspi->mode == GQSPI_MODE_DMA) {
635 dma_status =
636 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
637 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
638 dma_status);
639 }
640
641 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
642 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
643 ret = IRQ_HANDLED;
644 }
645
646 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
647 zynqmp_process_dma_irq(xqspi);
648 ret = IRQ_HANDLED;
649 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
650 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
651 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
652 ret = IRQ_HANDLED;
653 }
654
655 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
656 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
657 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
658 spi_finalize_current_transfer(master);
659 ret = IRQ_HANDLED;
660 }
661 return ret;
662}
663
664/**
665 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4.
666 * @xqspi: xqspi is a pointer to the GQSPI instance
667 * @spimode: spimode - SPI or DUAL or QUAD.
668 * Return: Mask to set desired SPI mode in GENFIFO entry.
669 */
670static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
671 u8 spimode)
672{
673 u32 mask = 0;
674
675 switch (spimode) {
676 case GQSPI_SELECT_MODE_DUALSPI:
677 mask = GQSPI_GENFIFO_MODE_DUALSPI;
678 break;
679 case GQSPI_SELECT_MODE_QUADSPI:
680 mask = GQSPI_GENFIFO_MODE_QUADSPI;
681 break;
682 case GQSPI_SELECT_MODE_SPI:
683 mask = GQSPI_GENFIFO_MODE_SPI;
684 break;
685 default:
686 dev_warn(xqspi->dev, "Invalid SPI mode\n");
687 }
688
689 return mask;
690}
691
692/**
693 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation
694 * @xqspi: xqspi is a pointer to the GQSPI instance.
695 */
696static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
697{
698 u32 rx_bytes, rx_rem, config_reg;
699 dma_addr_t addr;
700 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
701
702 if ((xqspi->bytes_to_receive < 8) ||
703 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
704 /* Setting to IO mode */
705 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
706 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
707 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
708 xqspi->mode = GQSPI_MODE_IO;
709 xqspi->dma_rx_bytes = 0;
710 return;
711 }
712
713 rx_rem = xqspi->bytes_to_receive % 4;
714 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
715
716 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
717 rx_bytes, DMA_FROM_DEVICE);
718 if (dma_mapping_error(xqspi->dev, addr))
719 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
720
721 xqspi->dma_rx_bytes = rx_bytes;
722 xqspi->dma_addr = addr;
723 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
724 (u32)(addr & 0xffffffff));
725 addr = ((addr >> 16) >> 16);
726 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
727 ((u32)addr) & 0xfff);
728
729 /* Enabling the DMA mode */
730 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
731 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
732 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
733 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
734
735 /* Switch to DMA mode */
736 xqspi->mode = GQSPI_MODE_DMA;
737
738 /* Write the number of bytes to transfer */
739 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
740}
741
742/**
743 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in
744 * the transfer and sets up the GENFIFO entries,
745 * TX FIFO as required.
746 * @xqspi: xqspi is a pointer to the GQSPI instance.
747 * @transfer: It is a pointer to the structure containing transfer data.
748 * @genfifoentry: genfifoentry is pointer to the variable in which
749 * GENFIFO mask is returned to calling function
750 */
751static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
752 struct spi_transfer *transfer,
753 u32 *genfifoentry)
754{
755 u32 config_reg;
756
757 /* Transmit */
758 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
759 /* Setup data to be TXed */
760 *genfifoentry &= ~GQSPI_GENFIFO_RX;
761 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
762 *genfifoentry |= GQSPI_GENFIFO_TX;
763 *genfifoentry |=
764 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
765 xqspi->bytes_to_transfer = transfer->len;
766 if (xqspi->mode == GQSPI_MODE_DMA) {
767 config_reg = zynqmp_gqspi_read(xqspi,
768 GQSPI_CONFIG_OFST);
769 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
770 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
771 config_reg);
772 xqspi->mode = GQSPI_MODE_IO;
773 }
774 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
775 /* Discard RX data */
776 xqspi->bytes_to_receive = 0;
777 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
778 /* Receive */
779
780 /* TX auto fill */
781 *genfifoentry &= ~GQSPI_GENFIFO_TX;
782 /* Setup RX */
783 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
784 *genfifoentry |= GQSPI_GENFIFO_RX;
785 *genfifoentry |=
786 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
787 xqspi->bytes_to_transfer = 0;
788 xqspi->bytes_to_receive = transfer->len;
789 zynq_qspi_setuprxdma(xqspi);
790 }
791}
792
793/**
794 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer
795 * @master: Pointer to the spi_master structure which provides
796 * information about the controller.
797 * @qspi: Pointer to the spi_device structure
798 * @transfer: Pointer to the spi_transfer structure which provide information
799 * about next transfer parameters
800 *
801 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
802 * transfer to be completed.
803 *
804 * Return: Number of bytes transferred in the last transfer
805 */
806static int zynqmp_qspi_start_transfer(struct spi_master *master,
807 struct spi_device *qspi,
808 struct spi_transfer *transfer)
809{
810 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
811 u32 genfifoentry = 0x0, transfer_len;
812
813 xqspi->txbuf = transfer->tx_buf;
814 xqspi->rxbuf = transfer->rx_buf;
815
816 zynqmp_qspi_setup_transfer(qspi, transfer);
817
818 genfifoentry |= xqspi->genfifocs;
819 genfifoentry |= xqspi->genfifobus;
820
821 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
822
823 if (xqspi->mode == GQSPI_MODE_DMA)
824 transfer_len = xqspi->dma_rx_bytes;
825 else
826 transfer_len = transfer->len;
827
828 xqspi->genfifoentry = genfifoentry;
829 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
830 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
831 genfifoentry |= transfer_len;
832 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
833 } else {
834 int tempcount = transfer_len;
835 u32 exponent = 8; /* 2^8 = 256 */
836 u8 imm_data = tempcount & 0xFF;
837
838 tempcount &= ~(tempcount & 0xFF);
839 /* Immediate entry */
840 if (tempcount != 0) {
841 /* Exponent entries */
842 genfifoentry |= GQSPI_GENFIFO_EXP;
843 while (tempcount != 0) {
844 if (tempcount & GQSPI_GENFIFO_EXP_START) {
845 genfifoentry &=
846 ~GQSPI_GENFIFO_IMM_DATA_MASK;
847 genfifoentry |= exponent;
848 zynqmp_gqspi_write(xqspi,
849 GQSPI_GEN_FIFO_OFST,
850 genfifoentry);
851 }
852 tempcount = tempcount >> 1;
853 exponent++;
854 }
855 }
856 if (imm_data != 0) {
857 genfifoentry &= ~GQSPI_GENFIFO_EXP;
858 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
859 genfifoentry |= (u8) (imm_data & 0xFF);
860 zynqmp_gqspi_write(xqspi,
861 GQSPI_GEN_FIFO_OFST, genfifoentry);
862 }
863 }
864
865 if ((xqspi->mode == GQSPI_MODE_IO) &&
866 (xqspi->rxbuf != NULL)) {
867 /* Dummy generic FIFO entry */
868 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
869 }
870
871 /* Since we are using manual mode */
872 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
873 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
874 GQSPI_CFG_START_GEN_FIFO_MASK);
875
876 if (xqspi->txbuf != NULL)
877 /* Enable interrupts for TX */
878 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
879 GQSPI_IER_TXEMPTY_MASK |
880 GQSPI_IER_GENFIFOEMPTY_MASK |
881 GQSPI_IER_TXNOT_FULL_MASK);
882
883 if (xqspi->rxbuf != NULL) {
884 /* Enable interrupts for RX */
885 if (xqspi->mode == GQSPI_MODE_DMA) {
886 /* Enable DMA interrupts */
887 zynqmp_gqspi_write(xqspi,
888 GQSPI_QSPIDMA_DST_I_EN_OFST,
889 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
890 } else {
891 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
892 GQSPI_IER_GENFIFOEMPTY_MASK |
893 GQSPI_IER_RXNEMPTY_MASK |
894 GQSPI_IER_RXEMPTY_MASK);
895 }
896 }
897
898 return transfer->len;
899}
900
901/**
902 * zynqmp_qspi_suspend: Suspend method for the QSPI driver
903 * @_dev: Address of the platform_device structure
904 *
905 * This function stops the QSPI driver queue and disables the QSPI controller
906 *
907 * Return: Always 0
908 */
909static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
910{
e1f16b04 911 struct spi_master *master = dev_get_drvdata(dev);
dfe11a11
RW		 912
913 spi_master_suspend(master);
914
915 zynqmp_unprepare_transfer_hardware(master);
916
917 return 0;
918}
919
920/**
921 * zynqmp_qspi_resume: Resume method for the QSPI driver
922 * @dev: Address of the platform_device structure
923 *
924 * The function starts the QSPI driver queue and initializes the QSPI
925 * controller
926 *
927 * Return: 0 on success; error value otherwise
928 */
929static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
930{
e1f16b04 931 struct spi_master *master = dev_get_drvdata(dev);
dfe11a11
RW		 932 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
933 int ret = 0;
934
935 ret = clk_enable(xqspi->pclk);
936 if (ret) {
937 dev_err(dev, "Cannot enable APB clock.\n");
938 return ret;
939 }
940
941 ret = clk_enable(xqspi->refclk);
942 if (ret) {
943 dev_err(dev, "Cannot enable device clock.\n");
944 clk_disable(xqspi->pclk);
945 return ret;
946 }
947
948 spi_master_resume(master);
949
9e3a0003
NSR		 950 clk_disable(xqspi->refclk);
951 clk_disable(xqspi->pclk);
dfe11a11
RW		 952 return 0;
953}
954
9e3a0003
NSR		 955/**
956 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
957 * @dev: Address of the platform_device structure
958 *
959 * This function disables the clocks
960 *
961 * Return: Always 0
962 */
963static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
964{
6eee6d31 965 struct spi_master *master = dev_get_drvdata(dev);
9e3a0003
NSR		 966 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
967
968 clk_disable(xqspi->refclk);
969 clk_disable(xqspi->pclk);
970
971 return 0;
972}
973
974/**
975 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
976 * @dev: Address of the platform_device structure
977 *
978 * This function enables the clocks
979 *
980 * Return: 0 on success and error value on error
981 */
982static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
983{
6eee6d31 984 struct spi_master *master = dev_get_drvdata(dev);
9e3a0003
NSR		 985 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
986 int ret;
987
988 ret = clk_enable(xqspi->pclk);
989 if (ret) {
990 dev_err(dev, "Cannot enable APB clock.\n");
991 return ret;
992 }
993
994 ret = clk_enable(xqspi->refclk);
995 if (ret) {
996 dev_err(dev, "Cannot enable device clock.\n");
997 clk_disable(xqspi->pclk);
998 return ret;
999 }
1000
1001 return 0;
1002}
1003
1004static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1005 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1006 zynqmp_runtime_resume, NULL)
1007 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1008};
dfe11a11
RW		 1009
1010/**
1011 * zynqmp_qspi_probe: Probe method for the QSPI driver
1012 * @pdev: Pointer to the platform_device structure
1013 *
1014 * This function initializes the driver data structures and the hardware.
1015 *
1016 * Return: 0 on success; error value otherwise
1017 */
1018static int zynqmp_qspi_probe(struct platform_device *pdev)
1019{
1020 int ret = 0;
1021 struct spi_master *master;
1022 struct zynqmp_qspi *xqspi;
1023 struct resource *res;
1024 struct device *dev = &pdev->dev;
1025
3d031378
RV		 1026 eemi_ops = zynqmp_pm_get_eemi_ops();
1027 if (IS_ERR(eemi_ops))
1028 return PTR_ERR(eemi_ops);
1029
dfe11a11
RW		 1030 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1031 if (!master)
1032 return -ENOMEM;
1033
1034 xqspi = spi_master_get_devdata(master);
1035 master->dev.of_node = pdev->dev.of_node;
1036 platform_set_drvdata(pdev, master);
1037
1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1039 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1040 if (IS_ERR(xqspi->regs)) {
1041 ret = PTR_ERR(xqspi->regs);
1042 goto remove_master;
1043 }
1044
1045 xqspi->dev = dev;
1046 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1047 if (IS_ERR(xqspi->pclk)) {
1048 dev_err(dev, "pclk clock not found.\n");
1049 ret = PTR_ERR(xqspi->pclk);
1050 goto remove_master;
1051 }
1052
1053 ret = clk_prepare_enable(xqspi->pclk);
1054 if (ret) {
1055 dev_err(dev, "Unable to enable APB clock.\n");
1056 goto remove_master;
1057 }
1058
1059 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1060 if (IS_ERR(xqspi->refclk)) {
1061 dev_err(dev, "ref_clk clock not found.\n");
1062 ret = PTR_ERR(xqspi->refclk);
1063 goto clk_dis_pclk;
1064 }
1065
1066 ret = clk_prepare_enable(xqspi->refclk);
1067 if (ret) {
1068 dev_err(dev, "Unable to enable device clock.\n");
1069 goto clk_dis_pclk;
1070 }
1071
9e3a0003
NSR		 1072 pm_runtime_use_autosuspend(&pdev->dev);
1073 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1074 pm_runtime_set_active(&pdev->dev);
1075 pm_runtime_enable(&pdev->dev);
dfe11a11
RW		 1076 /* QSPI controller initializations */
1077 zynqmp_qspi_init_hw(xqspi);
1078
9e3a0003
NSR		 1079 pm_runtime_mark_last_busy(&pdev->dev);
1080 pm_runtime_put_autosuspend(&pdev->dev);
dfe11a11
RW		 1081 xqspi->irq = platform_get_irq(pdev, 0);
1082 if (xqspi->irq <= 0) {
1083 ret = -ENXIO;
1084 dev_err(dev, "irq resource not found\n");
1085 goto clk_dis_all;
1086 }
1087 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1088 0, pdev->name, master);
1089 if (ret != 0) {
1090 ret = -ENXIO;
1091 dev_err(dev, "request_irq failed\n");
1092 goto clk_dis_all;
1093 }
1094
1095 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1096
1097 master->setup = zynqmp_qspi_setup;
1098 master->set_cs = zynqmp_qspi_chipselect;
1099 master->transfer_one = zynqmp_qspi_start_transfer;
1100 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1101 master->unprepare_transfer_hardware =
1102 zynqmp_unprepare_transfer_hardware;
1103 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1104 master->bits_per_word_mask = SPI_BPW_MASK(8);
1105 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1106 SPI_TX_DUAL | SPI_TX_QUAD;
1107
1108 if (master->dev.parent == NULL)
1109 master->dev.parent = &master->dev;
1110
1111 ret = spi_register_master(master);
1112 if (ret)
1113 goto clk_dis_all;
1114
1115 return 0;
1116
1117clk_dis_all:
9e3a0003
NSR		 1118 pm_runtime_set_suspended(&pdev->dev);
1119 pm_runtime_disable(&pdev->dev);
dfe11a11
RW		 1120 clk_disable_unprepare(xqspi->refclk);
1121clk_dis_pclk:
1122 clk_disable_unprepare(xqspi->pclk);
1123remove_master:
1124 spi_master_put(master);
1125
1126 return ret;
1127}
1128
1129/**
1130 * zynqmp_qspi_remove: Remove method for the QSPI driver
1131 * @pdev: Pointer to the platform_device structure
1132 *
1133 * This function is called if a device is physically removed from the system or
1134 * if the driver module is being unloaded. It frees all resources allocated to
1135 * the device.
1136 *
1137 * Return: 0 Always
1138 */
1139static int zynqmp_qspi_remove(struct platform_device *pdev)
1140{
1141 struct spi_master *master = platform_get_drvdata(pdev);
1142 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1143
1144 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1145 clk_disable_unprepare(xqspi->refclk);
1146 clk_disable_unprepare(xqspi->pclk);
9e3a0003
NSR		 1147 pm_runtime_set_suspended(&pdev->dev);
1148 pm_runtime_disable(&pdev->dev);
dfe11a11
RW		 1149
1150 spi_unregister_master(master);
1151
1152 return 0;
1153}
1154
1155static const struct of_device_id zynqmp_qspi_of_match[] = {
1156 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1157 { /* End of table */ }
1158};
1159
1160MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1161
1162static struct platform_driver zynqmp_qspi_driver = {
1163 .probe = zynqmp_qspi_probe,
1164 .remove = zynqmp_qspi_remove,
1165 .driver = {
1166 .name = "zynqmp-qspi",
1167 .of_match_table = zynqmp_qspi_of_match,
1168 .pm = &zynqmp_qspi_dev_pm_ops,
1169 },
1170};
1171
1172module_platform_driver(zynqmp_qspi_driver);
1173
1174MODULE_AUTHOR("Xilinx, Inc.");
1175MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1176MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)