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mfd: kempld-core: Constify variables that point to const structure
[linux-2.6-block.git] / drivers / spi / spi-zynqmp-gqspi.c
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dfe11a11
RW		 1/*
2 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
3 * (master mode only)
4 *
5 * Copyright (C) 2009 - 2015 Xilinx, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of_irq.h>
21#include <linux/of_address.h>
22#include <linux/platform_device.h>
9e3a0003 23#include <linux/pm_runtime.h>
dfe11a11
RW		 24#include <linux/spi/spi.h>
25#include <linux/spinlock.h>
26#include <linux/workqueue.h>
27
28/* Generic QSPI register offsets */
29#define GQSPI_CONFIG_OFST 0x00000100
30#define GQSPI_ISR_OFST 0x00000104
31#define GQSPI_IDR_OFST 0x0000010C
32#define GQSPI_IER_OFST 0x00000108
33#define GQSPI_IMASK_OFST 0x00000110
34#define GQSPI_EN_OFST 0x00000114
35#define GQSPI_TXD_OFST 0x0000011C
36#define GQSPI_RXD_OFST 0x00000120
37#define GQSPI_TX_THRESHOLD_OFST 0x00000128
38#define GQSPI_RX_THRESHOLD_OFST 0x0000012C
39#define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
40#define GQSPI_GEN_FIFO_OFST 0x00000140
41#define GQSPI_SEL_OFST 0x00000144
42#define GQSPI_GF_THRESHOLD_OFST 0x00000150
43#define GQSPI_FIFO_CTRL_OFST 0x0000014C
44#define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
45#define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
46#define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
47#define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
48#define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
49#define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
50#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
51#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
52#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
53
54/* GQSPI register bit masks */
55#define GQSPI_SEL_MASK 0x00000001
56#define GQSPI_EN_MASK 0x00000001
57#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
58#define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
59#define GQSPI_IDR_ALL_MASK 0x00000FBE
60#define GQSPI_CFG_MODE_EN_MASK 0xC0000000
61#define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
62#define GQSPI_CFG_ENDIAN_MASK 0x04000000
63#define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
64#define GQSPI_CFG_WP_HOLD_MASK 0x00080000
65#define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
66#define GQSPI_CFG_CLK_PHA_MASK 0x00000004
67#define GQSPI_CFG_CLK_POL_MASK 0x00000002
68#define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
69#define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
70#define GQSPI_GENFIFO_DATA_XFER 0x00000100
71#define GQSPI_GENFIFO_EXP 0x00000200
72#define GQSPI_GENFIFO_MODE_SPI 0x00000400
73#define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
74#define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
75#define GQSPI_GENFIFO_MODE_MASK 0x00000C00
76#define GQSPI_GENFIFO_CS_LOWER 0x00001000
77#define GQSPI_GENFIFO_CS_UPPER 0x00002000
78#define GQSPI_GENFIFO_BUS_LOWER 0x00004000
79#define GQSPI_GENFIFO_BUS_UPPER 0x00008000
80#define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
81#define GQSPI_GENFIFO_BUS_MASK 0x0000C000
82#define GQSPI_GENFIFO_TX 0x00010000
83#define GQSPI_GENFIFO_RX 0x00020000
84#define GQSPI_GENFIFO_STRIPE 0x00040000
85#define GQSPI_GENFIFO_POLL 0x00080000
86#define GQSPI_GENFIFO_EXP_START 0x00000100
87#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
88#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
89#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
90#define GQSPI_ISR_RXEMPTY_MASK 0x00000800
91#define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
92#define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
93#define GQSPI_ISR_TXEMPTY_MASK 0x00000100
94#define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
95#define GQSPI_ISR_RXFULL_MASK 0x00000020
96#define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
97#define GQSPI_ISR_TXFULL_MASK 0x00000008
98#define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
99#define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
100#define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
101#define GQSPI_IER_RXEMPTY_MASK 0x00000800
102#define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
103#define GQSPI_IER_RXNEMPTY_MASK 0x00000010
104#define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
105#define GQSPI_IER_TXEMPTY_MASK 0x00000100
106#define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
107#define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
108#define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
109#define GQSPI_ISR_IDR_MASK 0x00000994
110#define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
111#define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
112#define GQSPI_IRQ_MASK 0x00000980
113
114#define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
115#define GQSPI_GENFIFO_CS_SETUP 0x4
116#define GQSPI_GENFIFO_CS_HOLD 0x3
117#define GQSPI_TXD_DEPTH 64
118#define GQSPI_RX_FIFO_THRESHOLD 32
119#define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
120#define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
121#define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
122 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
123#define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
124#define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
125#define GQSPI_SELECT_FLASH_CS_LOWER 0x1
126#define GQSPI_SELECT_FLASH_CS_UPPER 0x2
127#define GQSPI_SELECT_FLASH_CS_BOTH 0x3
128#define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
129#define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
130#define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
131#define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
132#define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
133#define GQSPI_SELECT_MODE_SPI 0x1
134#define GQSPI_SELECT_MODE_DUALSPI 0x2
135#define GQSPI_SELECT_MODE_QUADSPI 0x4
136#define GQSPI_DMA_UNALIGN 0x3
137#define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
138
9e3a0003 139#define SPI_AUTOSUSPEND_TIMEOUT 3000
dfe11a11
RW		 140enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
141
142/**
143 * struct zynqmp_qspi - Defines qspi driver instance
144 * @regs: Virtual address of the QSPI controller registers
145 * @refclk: Pointer to the peripheral clock
146 * @pclk: Pointer to the APB clock
147 * @irq: IRQ number
148 * @dev: Pointer to struct device
149 * @txbuf: Pointer to the TX buffer
150 * @rxbuf: Pointer to the RX buffer
151 * @bytes_to_transfer: Number of bytes left to transfer
152 * @bytes_to_receive: Number of bytes left to receive
153 * @genfifocs: Used for chip select
154 * @genfifobus: Used to select the upper or lower bus
155 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
156 * @dma_addr: DMA address after mapping the kernel buffer
157 * @genfifoentry: Used for storing the genfifoentry instruction.
158 * @mode: Defines the mode in which QSPI is operating
159 */
160struct zynqmp_qspi {
161 void __iomem *regs;
162 struct clk *refclk;
163 struct clk *pclk;
164 int irq;
165 struct device *dev;
166 const void *txbuf;
167 void *rxbuf;
168 int bytes_to_transfer;
169 int bytes_to_receive;
170 u32 genfifocs;
171 u32 genfifobus;
172 u32 dma_rx_bytes;
173 dma_addr_t dma_addr;
174 u32 genfifoentry;
175 enum mode_type mode;
176};
177
178/**
179 * zynqmp_gqspi_read: For GQSPI controller read operation
180 * @xqspi: Pointer to the zynqmp_qspi structure
181 * @offset: Offset from where to read
182 */
183static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
184{
185 return readl_relaxed(xqspi->regs + offset);
186}
187
188/**
189 * zynqmp_gqspi_write: For GQSPI controller write operation
190 * @xqspi: Pointer to the zynqmp_qspi structure
191 * @offset: Offset where to write
192 * @val: Value to be written
193 */
194static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
195 u32 val)
196{
197 writel_relaxed(val, (xqspi->regs + offset));
198}
199
200/**
201 * zynqmp_gqspi_selectslave: For selection of slave device
202 * @instanceptr: Pointer to the zynqmp_qspi structure
203 * @flashcs: For chip select
204 * @flashbus: To check which bus is selected- upper or lower
205 */
206static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
207 u8 slavecs, u8 slavebus)
208{
209 /*
210 * Bus and CS lines selected here will be updated in the instance and
211 * used for subsequent GENFIFO entries during transfer.
212 */
213
214 /* Choose slave select line */
215 switch (slavecs) {
216 case GQSPI_SELECT_FLASH_CS_BOTH:
217 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
218 GQSPI_GENFIFO_CS_UPPER;
861a481c 219 break;
dfe11a11
RW		 220 case GQSPI_SELECT_FLASH_CS_UPPER:
221 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
222 break;
223 case GQSPI_SELECT_FLASH_CS_LOWER:
224 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
225 break;
226 default:
227 dev_warn(instanceptr->dev, "Invalid slave select\n");
228 }
229
230 /* Choose the bus */
231 switch (slavebus) {
232 case GQSPI_SELECT_FLASH_BUS_BOTH:
233 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
234 GQSPI_GENFIFO_BUS_UPPER;
235 break;
236 case GQSPI_SELECT_FLASH_BUS_UPPER:
237 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
238 break;
239 case GQSPI_SELECT_FLASH_BUS_LOWER:
240 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
241 break;
242 default:
243 dev_warn(instanceptr->dev, "Invalid slave bus\n");
244 }
245}
246
247/**
248 * zynqmp_qspi_init_hw: Initialize the hardware
249 * @xqspi: Pointer to the zynqmp_qspi structure
250 *
251 * The default settings of the QSPI controller's configurable parameters on
252 * reset are
253 * - Master mode
254 * - TX threshold set to 1
255 * - RX threshold set to 1
256 * - Flash memory interface mode enabled
257 * This function performs the following actions
258 * - Disable and clear all the interrupts
259 * - Enable manual slave select
260 * - Enable manual start
261 * - Deselect all the chip select lines
262 * - Set the little endian mode of TX FIFO and
263 * - Enable the QSPI controller
264 */
265static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
266{
267 u32 config_reg;
268
269 /* Select the GQSPI mode */
270 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
271 /* Clear and disable interrupts */
272 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
273 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
274 GQSPI_ISR_WR_TO_CLR_MASK);
275 /* Clear the DMA STS */
276 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
277 zynqmp_gqspi_read(xqspi,
278 GQSPI_QSPIDMA_DST_I_STS_OFST));
279 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
280 zynqmp_gqspi_read(xqspi,
281 GQSPI_QSPIDMA_DST_STS_OFST) |
282 GQSPI_QSPIDMA_DST_STS_WTC);
283 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
284 zynqmp_gqspi_write(xqspi,
285 GQSPI_QSPIDMA_DST_I_DIS_OFST,
286 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
287 /* Disable the GQSPI */
288 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
289 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
290 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
291 /* Manual start */
292 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
293 /* Little endian by default */
294 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
295 /* Disable poll time out */
296 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
297 /* Set hold bit */
298 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
299 /* Clear pre-scalar by default */
300 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
301 /* CPHA 0 */
302 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
303 /* CPOL 0 */
304 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
305 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
306
307 /* Clear the TX and RX FIFO */
308 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
309 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
310 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
311 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
312 /* Set by default to allow for high frequencies */
313 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
314 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
315 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
316 /* Reset thresholds */
317 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
318 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
319 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
320 GQSPI_RX_FIFO_THRESHOLD);
321 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
322 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
323 zynqmp_gqspi_selectslave(xqspi,
324 GQSPI_SELECT_FLASH_CS_LOWER,
325 GQSPI_SELECT_FLASH_BUS_LOWER);
326 /* Initialize DMA */
327 zynqmp_gqspi_write(xqspi,
328 GQSPI_QSPIDMA_DST_CTRL_OFST,
329 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
330
331 /* Enable the GQSPI */
332 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
333}
334
335/**
336 * zynqmp_qspi_copy_read_data: Copy data to RX buffer
337 * @xqspi: Pointer to the zynqmp_qspi structure
338 * @data: The variable where data is stored
339 * @size: Number of bytes to be copied from data to RX buffer
340 */
341static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
342 ulong data, u8 size)
343{
344 memcpy(xqspi->rxbuf, &data, size);
345 xqspi->rxbuf += size;
346 xqspi->bytes_to_receive -= size;
347}
348
349/**
350 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer.
351 * @master: Pointer to the spi_master structure which provides
352 * information about the controller.
353 *
354 * This function enables SPI master controller.
355 *
356 * Return: 0 on success; error value otherwise
357 */
358static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
359{
360 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
dfe11a11
RW		 361
362 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
363 return 0;
dfe11a11
RW		 364}
365
366/**
367 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer
368 * @master: Pointer to the spi_master structure which provides
369 * information about the controller.
370 *
371 * This function disables the SPI master controller.
372 *
373 * Return: Always 0
374 */
375static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
376{
377 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
378
379 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
dfe11a11
RW		 380 return 0;
381}
382
383/**
384 * zynqmp_qspi_chipselect: Select or deselect the chip select line
385 * @qspi: Pointer to the spi_device structure
386 * @is_high: Select(0) or deselect (1) the chip select line
387 */
388static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
389{
390 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
391 ulong timeout;
392 u32 genfifoentry = 0x0, statusreg;
393
394 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
395 genfifoentry |= xqspi->genfifobus;
396
397 if (!is_high) {
398 genfifoentry |= xqspi->genfifocs;
399 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
400 } else {
401 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
402 }
403
404 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
405
406 /* Dummy generic FIFO entry */
407 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
408
409 /* Manually start the generic FIFO command */
410 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
411 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
412 GQSPI_CFG_START_GEN_FIFO_MASK);
413
414 timeout = jiffies + msecs_to_jiffies(1000);
415
416 /* Wait until the generic FIFO command is empty */
417 do {
418 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
419
420 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
421 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
422 break;
423 else
424 cpu_relax();
425 } while (!time_after_eq(jiffies, timeout));
426
427 if (time_after_eq(jiffies, timeout))
428 dev_err(xqspi->dev, "Chip select timed out\n");
429}
430
431/**
432 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified
433 * transfer
434 * @qspi: Pointer to the spi_device structure
435 * @transfer: Pointer to the spi_transfer structure which provides
436 * information about next transfer setup parameters
437 *
438 * Sets the operational mode of QSPI controller for the next QSPI transfer and
439 * sets the requested clock frequency.
440 *
441 * Return: Always 0
442 *
443 * Note:
444 * If the requested frequency is not an exact match with what can be
445 * obtained using the pre-scalar value, the driver sets the clock
446 * frequency which is lower than the requested frequency (maximum lower)
447 * for the transfer.
448 *
449 * If the requested frequency is higher or lower than that is supported
450 * by the QSPI controller the driver will set the highest or lowest
451 * frequency supported by controller.
452 */
453static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
454 struct spi_transfer *transfer)
455{
456 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
457 ulong clk_rate;
458 u32 config_reg, req_hz, baud_rate_val = 0;
459
460 if (transfer)
461 req_hz = transfer->speed_hz;
462 else
463 req_hz = qspi->max_speed_hz;
464
465 /* Set the clock frequency */
466 /* If req_hz == 0, default to lowest speed */
467 clk_rate = clk_get_rate(xqspi->refclk);
468
469 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
470 (clk_rate /
471 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
472 baud_rate_val++;
473
474 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
475
476 /* Set the QSPI clock phase and clock polarity */
477 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
478
479 if (qspi->mode & SPI_CPHA)
480 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
481 if (qspi->mode & SPI_CPOL)
482 config_reg |= GQSPI_CFG_CLK_POL_MASK;
483
484 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
485 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
486 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
487 return 0;
488}
489
490/**
491 * zynqmp_qspi_setup: Configure the QSPI controller
492 * @qspi: Pointer to the spi_device structure
493 *
494 * Sets the operational mode of QSPI controller for the next QSPI transfer,
495 * baud rate and divisor value to setup the requested qspi clock.
496 *
497 * Return: 0 on success; error value otherwise.
498 */
499static int zynqmp_qspi_setup(struct spi_device *qspi)
500{
501 if (qspi->master->busy)
502 return -EBUSY;
503 return 0;
504}
505
506/**
507 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in
508 * the FIFO or the bytes required to be
509 * transmitted.
510 * @xqspi: Pointer to the zynqmp_qspi structure
511 * @size: Number of bytes to be copied from TX buffer to TX FIFO
512 */
513static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
514{
515 u32 count = 0, intermediate;
516
517 while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
518 memcpy(&intermediate, xqspi->txbuf, 4);
519 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
520
521 if (xqspi->bytes_to_transfer >= 4) {
522 xqspi->txbuf += 4;
523 xqspi->bytes_to_transfer -= 4;
524 } else {
525 xqspi->txbuf += xqspi->bytes_to_transfer;
526 xqspi->bytes_to_transfer = 0;
527 }
528 count++;
529 }
530}
531
532/**
533 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in
534 * the FIFO.
535 * @xqspi: Pointer to the zynqmp_qspi structure
536 * @size: Number of bytes to be copied from RX buffer to RX FIFO
537 */
538static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
539{
540 ulong data;
541 int count = 0;
542
543 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
544 if (xqspi->bytes_to_receive >= 4) {
545 (*(u32 *) xqspi->rxbuf) =
546 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
547 xqspi->rxbuf += 4;
548 xqspi->bytes_to_receive -= 4;
549 count += 4;
550 } else {
551 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
552 count += xqspi->bytes_to_receive;
553 zynqmp_qspi_copy_read_data(xqspi, data,
554 xqspi->bytes_to_receive);
555 xqspi->bytes_to_receive = 0;
556 }
557 }
558}
559
560/**
561 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI
562 * controller
563 * @xqspi: zynqmp_qspi instance pointer
564 *
565 * This function handles DMA interrupt only.
566 */
567static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
568{
569 u32 config_reg, genfifoentry;
570
571 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
572 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
573 xqspi->rxbuf += xqspi->dma_rx_bytes;
574 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
575 xqspi->dma_rx_bytes = 0;
576
577 /* Disabling the DMA interrupts */
578 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
579 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
580
581 if (xqspi->bytes_to_receive > 0) {
582 /* Switch to IO mode,for remaining bytes to receive */
583 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
584 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
585 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
586
587 /* Initiate the transfer of remaining bytes */
588 genfifoentry = xqspi->genfifoentry;
589 genfifoentry |= xqspi->bytes_to_receive;
590 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
591
592 /* Dummy generic FIFO entry */
593 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
594
595 /* Manual start */
596 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
597 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
598 GQSPI_CFG_START_GEN_FIFO_MASK));
599
600 /* Enable the RX interrupts for IO mode */
601 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
602 GQSPI_IER_GENFIFOEMPTY_MASK |
603 GQSPI_IER_RXNEMPTY_MASK |
604 GQSPI_IER_RXEMPTY_MASK);
605 }
606}
607
608/**
609 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller
610 * @irq: IRQ number
611 * @dev_id: Pointer to the xqspi structure
612 *
613 * This function handles TX empty only.
614 * On TX empty interrupt this function reads the received data from RX FIFO
615 * and fills the TX FIFO if there is any data remaining to be transferred.
616 *
617 * Return: IRQ_HANDLED when interrupt is handled
618 * IRQ_NONE otherwise.
619 */
620static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
621{
622 struct spi_master *master = dev_id;
623 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
624 int ret = IRQ_NONE;
625 u32 status, mask, dma_status = 0;
626
627 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
628 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
629 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
630
631 /* Read and clear DMA status */
632 if (xqspi->mode == GQSPI_MODE_DMA) {
633 dma_status =
634 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
635 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
636 dma_status);
637 }
638
639 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
640 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
641 ret = IRQ_HANDLED;
642 }
643
644 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
645 zynqmp_process_dma_irq(xqspi);
646 ret = IRQ_HANDLED;
647 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
648 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
649 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
650 ret = IRQ_HANDLED;
651 }
652
653 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
654 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
655 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
656 spi_finalize_current_transfer(master);
657 ret = IRQ_HANDLED;
658 }
659 return ret;
660}
661
662/**
663 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4.
664 * @xqspi: xqspi is a pointer to the GQSPI instance
665 * @spimode: spimode - SPI or DUAL or QUAD.
666 * Return: Mask to set desired SPI mode in GENFIFO entry.
667 */
668static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
669 u8 spimode)
670{
671 u32 mask = 0;
672
673 switch (spimode) {
674 case GQSPI_SELECT_MODE_DUALSPI:
675 mask = GQSPI_GENFIFO_MODE_DUALSPI;
676 break;
677 case GQSPI_SELECT_MODE_QUADSPI:
678 mask = GQSPI_GENFIFO_MODE_QUADSPI;
679 break;
680 case GQSPI_SELECT_MODE_SPI:
681 mask = GQSPI_GENFIFO_MODE_SPI;
682 break;
683 default:
684 dev_warn(xqspi->dev, "Invalid SPI mode\n");
685 }
686
687 return mask;
688}
689
690/**
691 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation
692 * @xqspi: xqspi is a pointer to the GQSPI instance.
693 */
694static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
695{
696 u32 rx_bytes, rx_rem, config_reg;
697 dma_addr_t addr;
698 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
699
700 if ((xqspi->bytes_to_receive < 8) ||
701 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
702 /* Setting to IO mode */
703 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
704 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
705 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
706 xqspi->mode = GQSPI_MODE_IO;
707 xqspi->dma_rx_bytes = 0;
708 return;
709 }
710
711 rx_rem = xqspi->bytes_to_receive % 4;
712 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
713
714 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
715 rx_bytes, DMA_FROM_DEVICE);
716 if (dma_mapping_error(xqspi->dev, addr))
717 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
718
719 xqspi->dma_rx_bytes = rx_bytes;
720 xqspi->dma_addr = addr;
721 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
722 (u32)(addr & 0xffffffff));
723 addr = ((addr >> 16) >> 16);
724 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
725 ((u32)addr) & 0xfff);
726
727 /* Enabling the DMA mode */
728 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
729 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
730 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
731 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
732
733 /* Switch to DMA mode */
734 xqspi->mode = GQSPI_MODE_DMA;
735
736 /* Write the number of bytes to transfer */
737 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
738}
739
740/**
741 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in
742 * the transfer and sets up the GENFIFO entries,
743 * TX FIFO as required.
744 * @xqspi: xqspi is a pointer to the GQSPI instance.
745 * @transfer: It is a pointer to the structure containing transfer data.
746 * @genfifoentry: genfifoentry is pointer to the variable in which
747 * GENFIFO mask is returned to calling function
748 */
749static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
750 struct spi_transfer *transfer,
751 u32 *genfifoentry)
752{
753 u32 config_reg;
754
755 /* Transmit */
756 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
757 /* Setup data to be TXed */
758 *genfifoentry &= ~GQSPI_GENFIFO_RX;
759 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
760 *genfifoentry |= GQSPI_GENFIFO_TX;
761 *genfifoentry |=
762 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
763 xqspi->bytes_to_transfer = transfer->len;
764 if (xqspi->mode == GQSPI_MODE_DMA) {
765 config_reg = zynqmp_gqspi_read(xqspi,
766 GQSPI_CONFIG_OFST);
767 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
768 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
769 config_reg);
770 xqspi->mode = GQSPI_MODE_IO;
771 }
772 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
773 /* Discard RX data */
774 xqspi->bytes_to_receive = 0;
775 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
776 /* Receive */
777
778 /* TX auto fill */
779 *genfifoentry &= ~GQSPI_GENFIFO_TX;
780 /* Setup RX */
781 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
782 *genfifoentry |= GQSPI_GENFIFO_RX;
783 *genfifoentry |=
784 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
785 xqspi->bytes_to_transfer = 0;
786 xqspi->bytes_to_receive = transfer->len;
787 zynq_qspi_setuprxdma(xqspi);
788 }
789}
790
791/**
792 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer
793 * @master: Pointer to the spi_master structure which provides
794 * information about the controller.
795 * @qspi: Pointer to the spi_device structure
796 * @transfer: Pointer to the spi_transfer structure which provide information
797 * about next transfer parameters
798 *
799 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
800 * transfer to be completed.
801 *
802 * Return: Number of bytes transferred in the last transfer
803 */
804static int zynqmp_qspi_start_transfer(struct spi_master *master,
805 struct spi_device *qspi,
806 struct spi_transfer *transfer)
807{
808 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
809 u32 genfifoentry = 0x0, transfer_len;
810
811 xqspi->txbuf = transfer->tx_buf;
812 xqspi->rxbuf = transfer->rx_buf;
813
814 zynqmp_qspi_setup_transfer(qspi, transfer);
815
816 genfifoentry |= xqspi->genfifocs;
817 genfifoentry |= xqspi->genfifobus;
818
819 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
820
821 if (xqspi->mode == GQSPI_MODE_DMA)
822 transfer_len = xqspi->dma_rx_bytes;
823 else
824 transfer_len = transfer->len;
825
826 xqspi->genfifoentry = genfifoentry;
827 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
828 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
829 genfifoentry |= transfer_len;
830 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
831 } else {
832 int tempcount = transfer_len;
833 u32 exponent = 8; /* 2^8 = 256 */
834 u8 imm_data = tempcount & 0xFF;
835
836 tempcount &= ~(tempcount & 0xFF);
837 /* Immediate entry */
838 if (tempcount != 0) {
839 /* Exponent entries */
840 genfifoentry |= GQSPI_GENFIFO_EXP;
841 while (tempcount != 0) {
842 if (tempcount & GQSPI_GENFIFO_EXP_START) {
843 genfifoentry &=
844 ~GQSPI_GENFIFO_IMM_DATA_MASK;
845 genfifoentry |= exponent;
846 zynqmp_gqspi_write(xqspi,
847 GQSPI_GEN_FIFO_OFST,
848 genfifoentry);
849 }
850 tempcount = tempcount >> 1;
851 exponent++;
852 }
853 }
854 if (imm_data != 0) {
855 genfifoentry &= ~GQSPI_GENFIFO_EXP;
856 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
857 genfifoentry |= (u8) (imm_data & 0xFF);
858 zynqmp_gqspi_write(xqspi,
859 GQSPI_GEN_FIFO_OFST, genfifoentry);
860 }
861 }
862
863 if ((xqspi->mode == GQSPI_MODE_IO) &&
864 (xqspi->rxbuf != NULL)) {
865 /* Dummy generic FIFO entry */
866 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
867 }
868
869 /* Since we are using manual mode */
870 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
871 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
872 GQSPI_CFG_START_GEN_FIFO_MASK);
873
874 if (xqspi->txbuf != NULL)
875 /* Enable interrupts for TX */
876 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
877 GQSPI_IER_TXEMPTY_MASK |
878 GQSPI_IER_GENFIFOEMPTY_MASK |
879 GQSPI_IER_TXNOT_FULL_MASK);
880
881 if (xqspi->rxbuf != NULL) {
882 /* Enable interrupts for RX */
883 if (xqspi->mode == GQSPI_MODE_DMA) {
884 /* Enable DMA interrupts */
885 zynqmp_gqspi_write(xqspi,
886 GQSPI_QSPIDMA_DST_I_EN_OFST,
887 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
888 } else {
889 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
890 GQSPI_IER_GENFIFOEMPTY_MASK |
891 GQSPI_IER_RXNEMPTY_MASK |
892 GQSPI_IER_RXEMPTY_MASK);
893 }
894 }
895
896 return transfer->len;
897}
898
899/**
900 * zynqmp_qspi_suspend: Suspend method for the QSPI driver
901 * @_dev: Address of the platform_device structure
902 *
903 * This function stops the QSPI driver queue and disables the QSPI controller
904 *
905 * Return: Always 0
906 */
907static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
908{
e1f16b04 909 struct spi_master *master = dev_get_drvdata(dev);
dfe11a11
RW		 910
911 spi_master_suspend(master);
912
913 zynqmp_unprepare_transfer_hardware(master);
914
915 return 0;
916}
917
918/**
919 * zynqmp_qspi_resume: Resume method for the QSPI driver
920 * @dev: Address of the platform_device structure
921 *
922 * The function starts the QSPI driver queue and initializes the QSPI
923 * controller
924 *
925 * Return: 0 on success; error value otherwise
926 */
927static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
928{
e1f16b04 929 struct spi_master *master = dev_get_drvdata(dev);
dfe11a11
RW		 930 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
931 int ret = 0;
932
933 ret = clk_enable(xqspi->pclk);
934 if (ret) {
935 dev_err(dev, "Cannot enable APB clock.\n");
936 return ret;
937 }
938
939 ret = clk_enable(xqspi->refclk);
940 if (ret) {
941 dev_err(dev, "Cannot enable device clock.\n");
942 clk_disable(xqspi->pclk);
943 return ret;
944 }
945
946 spi_master_resume(master);
947
9e3a0003
NSR		 948 clk_disable(xqspi->refclk);
949 clk_disable(xqspi->pclk);
dfe11a11
RW		 950 return 0;
951}
952
9e3a0003
NSR		 953/**
954 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
955 * @dev: Address of the platform_device structure
956 *
957 * This function disables the clocks
958 *
959 * Return: Always 0
960 */
961static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
962{
963 struct platform_device *pdev = to_platform_device(dev);
964 struct spi_master *master = platform_get_drvdata(pdev);
965 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
966
967 clk_disable(xqspi->refclk);
968 clk_disable(xqspi->pclk);
969
970 return 0;
971}
972
973/**
974 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
975 * @dev: Address of the platform_device structure
976 *
977 * This function enables the clocks
978 *
979 * Return: 0 on success and error value on error
980 */
981static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
982{
983 struct platform_device *pdev = to_platform_device(dev);
984 struct spi_master *master = platform_get_drvdata(pdev);
985 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
986 int ret;
987
988 ret = clk_enable(xqspi->pclk);
989 if (ret) {
990 dev_err(dev, "Cannot enable APB clock.\n");
991 return ret;
992 }
993
994 ret = clk_enable(xqspi->refclk);
995 if (ret) {
996 dev_err(dev, "Cannot enable device clock.\n");
997 clk_disable(xqspi->pclk);
998 return ret;
999 }
1000
1001 return 0;
1002}
1003
1004static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1005 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1006 zynqmp_runtime_resume, NULL)
1007 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1008};
dfe11a11
RW		 1009
1010/**
1011 * zynqmp_qspi_probe: Probe method for the QSPI driver
1012 * @pdev: Pointer to the platform_device structure
1013 *
1014 * This function initializes the driver data structures and the hardware.
1015 *
1016 * Return: 0 on success; error value otherwise
1017 */
1018static int zynqmp_qspi_probe(struct platform_device *pdev)
1019{
1020 int ret = 0;
1021 struct spi_master *master;
1022 struct zynqmp_qspi *xqspi;
1023 struct resource *res;
1024 struct device *dev = &pdev->dev;
1025
1026 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1027 if (!master)
1028 return -ENOMEM;
1029
1030 xqspi = spi_master_get_devdata(master);
1031 master->dev.of_node = pdev->dev.of_node;
1032 platform_set_drvdata(pdev, master);
1033
1034 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1035 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1036 if (IS_ERR(xqspi->regs)) {
1037 ret = PTR_ERR(xqspi->regs);
1038 goto remove_master;
1039 }
1040
1041 xqspi->dev = dev;
1042 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1043 if (IS_ERR(xqspi->pclk)) {
1044 dev_err(dev, "pclk clock not found.\n");
1045 ret = PTR_ERR(xqspi->pclk);
1046 goto remove_master;
1047 }
1048
1049 ret = clk_prepare_enable(xqspi->pclk);
1050 if (ret) {
1051 dev_err(dev, "Unable to enable APB clock.\n");
1052 goto remove_master;
1053 }
1054
1055 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1056 if (IS_ERR(xqspi->refclk)) {
1057 dev_err(dev, "ref_clk clock not found.\n");
1058 ret = PTR_ERR(xqspi->refclk);
1059 goto clk_dis_pclk;
1060 }
1061
1062 ret = clk_prepare_enable(xqspi->refclk);
1063 if (ret) {
1064 dev_err(dev, "Unable to enable device clock.\n");
1065 goto clk_dis_pclk;
1066 }
1067
9e3a0003
NSR		 1068 pm_runtime_use_autosuspend(&pdev->dev);
1069 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1070 pm_runtime_set_active(&pdev->dev);
1071 pm_runtime_enable(&pdev->dev);
dfe11a11
RW		 1072 /* QSPI controller initializations */
1073 zynqmp_qspi_init_hw(xqspi);
1074
9e3a0003
NSR		 1075 pm_runtime_mark_last_busy(&pdev->dev);
1076 pm_runtime_put_autosuspend(&pdev->dev);
dfe11a11
RW		 1077 xqspi->irq = platform_get_irq(pdev, 0);
1078 if (xqspi->irq <= 0) {
1079 ret = -ENXIO;
1080 dev_err(dev, "irq resource not found\n");
1081 goto clk_dis_all;
1082 }
1083 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1084 0, pdev->name, master);
1085 if (ret != 0) {
1086 ret = -ENXIO;
1087 dev_err(dev, "request_irq failed\n");
1088 goto clk_dis_all;
1089 }
1090
1091 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1092
1093 master->setup = zynqmp_qspi_setup;
1094 master->set_cs = zynqmp_qspi_chipselect;
1095 master->transfer_one = zynqmp_qspi_start_transfer;
1096 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1097 master->unprepare_transfer_hardware =
1098 zynqmp_unprepare_transfer_hardware;
1099 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1100 master->bits_per_word_mask = SPI_BPW_MASK(8);
1101 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1102 SPI_TX_DUAL | SPI_TX_QUAD;
1103
1104 if (master->dev.parent == NULL)
1105 master->dev.parent = &master->dev;
1106
1107 ret = spi_register_master(master);
1108 if (ret)
1109 goto clk_dis_all;
1110
1111 return 0;
1112
1113clk_dis_all:
9e3a0003
NSR		 1114 pm_runtime_set_suspended(&pdev->dev);
1115 pm_runtime_disable(&pdev->dev);
dfe11a11
RW		 1116 clk_disable_unprepare(xqspi->refclk);
1117clk_dis_pclk:
1118 clk_disable_unprepare(xqspi->pclk);
1119remove_master:
1120 spi_master_put(master);
1121
1122 return ret;
1123}
1124
1125/**
1126 * zynqmp_qspi_remove: Remove method for the QSPI driver
1127 * @pdev: Pointer to the platform_device structure
1128 *
1129 * This function is called if a device is physically removed from the system or
1130 * if the driver module is being unloaded. It frees all resources allocated to
1131 * the device.
1132 *
1133 * Return: 0 Always
1134 */
1135static int zynqmp_qspi_remove(struct platform_device *pdev)
1136{
1137 struct spi_master *master = platform_get_drvdata(pdev);
1138 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1139
1140 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1141 clk_disable_unprepare(xqspi->refclk);
1142 clk_disable_unprepare(xqspi->pclk);
9e3a0003
NSR		 1143 pm_runtime_set_suspended(&pdev->dev);
1144 pm_runtime_disable(&pdev->dev);
dfe11a11
RW		 1145
1146 spi_unregister_master(master);
1147
1148 return 0;
1149}
1150
1151static const struct of_device_id zynqmp_qspi_of_match[] = {
1152 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1153 { /* End of table */ }
1154};
1155
1156MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1157
1158static struct platform_driver zynqmp_qspi_driver = {
1159 .probe = zynqmp_qspi_probe,
1160 .remove = zynqmp_qspi_remove,
1161 .driver = {
1162 .name = "zynqmp-qspi",
1163 .of_match_table = zynqmp_qspi_of_match,
1164 .pm = &zynqmp_qspi_dev_pm_ops,
1165 },
1166};
1167
1168module_platform_driver(zynqmp_qspi_driver);
1169
1170MODULE_AUTHOR("Xilinx, Inc.");
1171MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1172MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)