Commit | Line | Data |
---|---|---|
ae918c02 | 1 | /* |
ae918c02 AK |
2 | * Xilinx SPI controller driver (master mode only) |
3 | * | |
4 | * Author: MontaVista Software, Inc. | |
5 | * source@mvista.com | |
6 | * | |
8fd8821b GL |
7 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
8 | * Copyright (c) 2009 Intel Corporation | |
9 | * 2002-2007 (c) MontaVista Software, Inc. | |
10 | ||
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
ae918c02 AK |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
eae6cb31 | 19 | #include <linux/of.h> |
8fd8821b | 20 | #include <linux/platform_device.h> |
ae918c02 AK |
21 | #include <linux/spi/spi.h> |
22 | #include <linux/spi/spi_bitbang.h> | |
d5af91a1 | 23 | #include <linux/spi/xilinx_spi.h> |
eae6cb31 | 24 | #include <linux/io.h> |
d5af91a1 | 25 | |
fc3ba952 | 26 | #define XILINX_SPI_NAME "xilinx_spi" |
ae918c02 AK |
27 | |
28 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | |
29 | * Product Specification", DS464 | |
30 | */ | |
c9da2e12 | 31 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
ae918c02 | 32 | |
082339bc | 33 | #define XSPI_CR_LOOP 0x01 |
ae918c02 AK |
34 | #define XSPI_CR_ENABLE 0x02 |
35 | #define XSPI_CR_MASTER_MODE 0x04 | |
36 | #define XSPI_CR_CPOL 0x08 | |
37 | #define XSPI_CR_CPHA 0x10 | |
38 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) | |
39 | #define XSPI_CR_TXFIFO_RESET 0x20 | |
40 | #define XSPI_CR_RXFIFO_RESET 0x40 | |
41 | #define XSPI_CR_MANUAL_SSELECT 0x80 | |
42 | #define XSPI_CR_TRANS_INHIBIT 0x100 | |
c9da2e12 | 43 | #define XSPI_CR_LSB_FIRST 0x200 |
ae918c02 | 44 | |
c9da2e12 | 45 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
ae918c02 AK |
46 | |
47 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | |
48 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | |
49 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ | |
50 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | |
51 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | |
52 | ||
c9da2e12 RR |
53 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
54 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ | |
ae918c02 AK |
55 | |
56 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | |
57 | ||
58 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 | |
59 | * IPIF registers are 32 bit | |
60 | */ | |
61 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ | |
62 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 | |
63 | ||
64 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ | |
65 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ | |
66 | ||
67 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ | |
68 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while | |
69 | * disabled */ | |
70 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ | |
71 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | |
72 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | |
73 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | |
c9da2e12 | 74 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
ae918c02 AK |
75 | |
76 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | |
77 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | |
78 | ||
79 | struct xilinx_spi { | |
80 | /* bitbang has to be first */ | |
81 | struct spi_bitbang bitbang; | |
82 | struct completion done; | |
d5af91a1 | 83 | struct resource mem; /* phys mem */ |
ae918c02 AK |
84 | void __iomem *regs; /* virt. address of the control registers */ |
85 | ||
86 | u32 irq; | |
87 | ||
ae918c02 AK |
88 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
89 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | |
90 | int remaining_bytes; /* the number of bytes left to transfer */ | |
c9da2e12 | 91 | u8 bits_per_word; |
86fc5935 RR |
92 | unsigned int (*read_fn) (void __iomem *); |
93 | void (*write_fn) (u32, void __iomem *); | |
c9da2e12 RR |
94 | void (*tx_fn) (struct xilinx_spi *); |
95 | void (*rx_fn) (struct xilinx_spi *); | |
ae918c02 AK |
96 | }; |
97 | ||
97782149 PM |
98 | static void xspi_write32(u32 val, void __iomem *addr) |
99 | { | |
100 | iowrite32(val, addr); | |
101 | } | |
102 | ||
103 | static unsigned int xspi_read32(void __iomem *addr) | |
104 | { | |
105 | return ioread32(addr); | |
106 | } | |
107 | ||
108 | static void xspi_write32_be(u32 val, void __iomem *addr) | |
109 | { | |
110 | iowrite32be(val, addr); | |
111 | } | |
112 | ||
113 | static unsigned int xspi_read32_be(void __iomem *addr) | |
114 | { | |
115 | return ioread32be(addr); | |
116 | } | |
117 | ||
c9da2e12 RR |
118 | static void xspi_tx8(struct xilinx_spi *xspi) |
119 | { | |
120 | xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); | |
121 | xspi->tx_ptr++; | |
122 | } | |
123 | ||
124 | static void xspi_tx16(struct xilinx_spi *xspi) | |
125 | { | |
126 | xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
127 | xspi->tx_ptr += 2; | |
128 | } | |
129 | ||
130 | static void xspi_tx32(struct xilinx_spi *xspi) | |
131 | { | |
132 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
133 | xspi->tx_ptr += 4; | |
134 | } | |
135 | ||
136 | static void xspi_rx8(struct xilinx_spi *xspi) | |
137 | { | |
138 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
139 | if (xspi->rx_ptr) { | |
140 | *xspi->rx_ptr = data & 0xff; | |
141 | xspi->rx_ptr++; | |
142 | } | |
143 | } | |
144 | ||
145 | static void xspi_rx16(struct xilinx_spi *xspi) | |
146 | { | |
147 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
148 | if (xspi->rx_ptr) { | |
149 | *(u16 *)(xspi->rx_ptr) = data & 0xffff; | |
150 | xspi->rx_ptr += 2; | |
151 | } | |
152 | } | |
153 | ||
154 | static void xspi_rx32(struct xilinx_spi *xspi) | |
155 | { | |
156 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
157 | if (xspi->rx_ptr) { | |
158 | *(u32 *)(xspi->rx_ptr) = data; | |
159 | xspi->rx_ptr += 4; | |
160 | } | |
161 | } | |
162 | ||
86fc5935 | 163 | static void xspi_init_hw(struct xilinx_spi *xspi) |
ae918c02 | 164 | { |
86fc5935 RR |
165 | void __iomem *regs_base = xspi->regs; |
166 | ||
ae918c02 | 167 | /* Reset the SPI device */ |
86fc5935 RR |
168 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
169 | regs_base + XIPIF_V123B_RESETR_OFFSET); | |
ae918c02 | 170 | /* Disable all the interrupts just in case */ |
86fc5935 | 171 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); |
ae918c02 | 172 | /* Enable the global IPIF interrupt */ |
86fc5935 RR |
173 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, |
174 | regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ae918c02 | 175 | /* Deselect the slave on the SPI bus */ |
86fc5935 | 176 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
ae918c02 AK |
177 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
178 | * put SPI controller into master mode, and enable it */ | |
86fc5935 | 179 | xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | |
c9da2e12 RR |
180 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | |
181 | XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); | |
ae918c02 AK |
182 | } |
183 | ||
184 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |
185 | { | |
186 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
187 | ||
188 | if (is_on == BITBANG_CS_INACTIVE) { | |
189 | /* Deselect the slave on the SPI bus */ | |
86fc5935 | 190 | xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); |
ae918c02 AK |
191 | } else if (is_on == BITBANG_CS_ACTIVE) { |
192 | /* Set the SPI clock phase and polarity */ | |
86fc5935 | 193 | u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) |
ae918c02 AK |
194 | & ~XSPI_CR_MODE_MASK; |
195 | if (spi->mode & SPI_CPHA) | |
196 | cr |= XSPI_CR_CPHA; | |
197 | if (spi->mode & SPI_CPOL) | |
198 | cr |= XSPI_CR_CPOL; | |
86fc5935 | 199 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
ae918c02 AK |
200 | |
201 | /* We do not check spi->max_speed_hz here as the SPI clock | |
202 | * frequency is not software programmable (the IP block design | |
203 | * parameter) | |
204 | */ | |
205 | ||
206 | /* Activate the chip select */ | |
86fc5935 RR |
207 | xspi->write_fn(~(0x0001 << spi->chip_select), |
208 | xspi->regs + XSPI_SSR_OFFSET); | |
ae918c02 AK |
209 | } |
210 | } | |
211 | ||
212 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | |
213 | * custom txrx_bufs(). We have nothing to setup here as the SPI IP block | |
c9da2e12 RR |
214 | * supports 8 or 16 bits per word which cannot be changed in software. |
215 | * SPI clock can't be changed in software either. | |
216 | * Check for correct bits per word. Chip select delay calculations could be | |
ae918c02 AK |
217 | * added here as soon as bitbang_work() can be made aware of the delay value. |
218 | */ | |
219 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | |
220 | struct spi_transfer *t) | |
221 | { | |
c9da2e12 | 222 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
ae918c02 | 223 | u8 bits_per_word; |
ae918c02 | 224 | |
1a8d3b77 JL |
225 | bits_per_word = (t && t->bits_per_word) |
226 | ? t->bits_per_word : spi->bits_per_word; | |
c9da2e12 | 227 | if (bits_per_word != xspi->bits_per_word) { |
ae918c02 | 228 | dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", |
b687d2a8 | 229 | __func__, bits_per_word); |
ae918c02 AK |
230 | return -EINVAL; |
231 | } | |
232 | ||
ae918c02 AK |
233 | return 0; |
234 | } | |
235 | ||
ae918c02 AK |
236 | static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) |
237 | { | |
238 | u8 sr; | |
239 | ||
240 | /* Fill the Tx FIFO with as many bytes as possible */ | |
86fc5935 | 241 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 | 242 | while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { |
86fc5935 | 243 | if (xspi->tx_ptr) |
c9da2e12 | 244 | xspi->tx_fn(xspi); |
86fc5935 RR |
245 | else |
246 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
c9da2e12 | 247 | xspi->remaining_bytes -= xspi->bits_per_word / 8; |
86fc5935 | 248 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 AK |
249 | } |
250 | } | |
251 | ||
252 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | |
253 | { | |
254 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
255 | u32 ipif_ier; | |
ae918c02 AK |
256 | |
257 | /* We get here with transmitter inhibited */ | |
258 | ||
259 | xspi->tx_ptr = t->tx_buf; | |
260 | xspi->rx_ptr = t->rx_buf; | |
261 | xspi->remaining_bytes = t->len; | |
262 | INIT_COMPLETION(xspi->done); | |
263 | ||
ae918c02 AK |
264 | |
265 | /* Enable the transmit empty interrupt, which we use to determine | |
266 | * progress on the transmission. | |
267 | */ | |
86fc5935 RR |
268 | ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); |
269 | xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, | |
270 | xspi->regs + XIPIF_V123B_IIER_OFFSET); | |
ae918c02 | 271 | |
68c315bb PC |
272 | for (;;) { |
273 | u16 cr; | |
274 | u8 sr; | |
275 | ||
276 | xilinx_spi_fill_tx_fifo(xspi); | |
277 | ||
278 | /* Start the transfer by not inhibiting the transmitter any | |
279 | * longer | |
280 | */ | |
281 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & | |
282 | ~XSPI_CR_TRANS_INHIBIT; | |
283 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
284 | ||
285 | wait_for_completion(&xspi->done); | |
286 | ||
287 | /* A transmit has just completed. Process received data and | |
288 | * check for more data to transmit. Always inhibit the | |
289 | * transmitter while the Isr refills the transmit register/FIFO, | |
290 | * or make sure it is stopped if we're done. | |
291 | */ | |
292 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
293 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | |
294 | xspi->regs + XSPI_CR_OFFSET); | |
295 | ||
296 | /* Read out all the data from the Rx FIFO */ | |
297 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
298 | while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { | |
299 | xspi->rx_fn(xspi); | |
300 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
301 | } | |
ae918c02 | 302 | |
68c315bb | 303 | /* See if there is more data to send */ |
e33d085d | 304 | if (xspi->remaining_bytes <= 0) |
68c315bb PC |
305 | break; |
306 | } | |
ae918c02 AK |
307 | |
308 | /* Disable the transmit empty interrupt */ | |
86fc5935 | 309 | xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); |
ae918c02 AK |
310 | |
311 | return t->len - xspi->remaining_bytes; | |
312 | } | |
313 | ||
314 | ||
315 | /* This driver supports single master mode only. Hence Tx FIFO Empty | |
316 | * is the only interrupt we care about. | |
317 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode | |
318 | * Fault are not to happen. | |
319 | */ | |
320 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |
321 | { | |
322 | struct xilinx_spi *xspi = dev_id; | |
323 | u32 ipif_isr; | |
324 | ||
325 | /* Get the IPIF interrupts, and clear them immediately */ | |
86fc5935 RR |
326 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
327 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
ae918c02 AK |
328 | |
329 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ | |
68c315bb | 330 | complete(&xspi->done); |
ae918c02 AK |
331 | } |
332 | ||
333 | return IRQ_HANDLED; | |
334 | } | |
335 | ||
eae6cb31 GL |
336 | static const struct of_device_id xilinx_spi_of_match[] = { |
337 | { .compatible = "xlnx,xps-spi-2.00.a", }, | |
338 | { .compatible = "xlnx,xps-spi-2.00.b", }, | |
339 | {} | |
340 | }; | |
341 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); | |
eae6cb31 | 342 | |
7cb2abd0 | 343 | static int xilinx_spi_probe(struct platform_device *pdev) |
ae918c02 | 344 | { |
ae918c02 | 345 | struct xilinx_spi *xspi; |
d81c0bbb MB |
346 | struct xspi_platform_data *pdata; |
347 | struct resource *r; | |
348 | int ret, irq, num_cs = 0, bits_per_word = 8; | |
349 | struct spi_master *master; | |
082339bc | 350 | u32 tmp; |
d81c0bbb MB |
351 | u8 i; |
352 | ||
7cb2abd0 | 353 | pdata = pdev->dev.platform_data; |
d81c0bbb MB |
354 | if (pdata) { |
355 | num_cs = pdata->num_chipselect; | |
356 | bits_per_word = pdata->bits_per_word; | |
357 | } | |
358 | ||
7cb2abd0 | 359 | if (pdev->dev.of_node) { |
d81c0bbb MB |
360 | const __be32 *prop; |
361 | int len; | |
362 | ||
363 | /* number of slave select bits is required */ | |
7cb2abd0 | 364 | prop = of_get_property(pdev->dev.of_node, "xlnx,num-ss-bits", |
d81c0bbb MB |
365 | &len); |
366 | if (prop && len >= sizeof(*prop)) | |
367 | num_cs = __be32_to_cpup(prop); | |
368 | } | |
ae918c02 | 369 | |
d81c0bbb | 370 | if (!num_cs) { |
7cb2abd0 MB |
371 | dev_err(&pdev->dev, |
372 | "Missing slave select configuration data\n"); | |
d81c0bbb MB |
373 | return -EINVAL; |
374 | } | |
375 | ||
7cb2abd0 | 376 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
d81c0bbb MB |
377 | if (!r) |
378 | return -ENODEV; | |
379 | ||
7cb2abd0 | 380 | irq = platform_get_irq(pdev, 0); |
d81c0bbb MB |
381 | if (irq < 0) |
382 | return -ENXIO; | |
383 | ||
7cb2abd0 | 384 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
d5af91a1 | 385 | if (!master) |
d81c0bbb | 386 | return -ENODEV; |
ae918c02 | 387 | |
e7db06b5 DB |
388 | /* the spi->mode bits understood by this driver: */ |
389 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
390 | ||
ae918c02 AK |
391 | xspi = spi_master_get_devdata(master); |
392 | xspi->bitbang.master = spi_master_get(master); | |
393 | xspi->bitbang.chipselect = xilinx_spi_chipselect; | |
394 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | |
395 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; | |
ae918c02 AK |
396 | init_completion(&xspi->done); |
397 | ||
7cb2abd0 | 398 | xspi->regs = devm_ioremap_resource(&pdev->dev, r); |
c40537d0 MB |
399 | if (IS_ERR(xspi->regs)) { |
400 | ret = PTR_ERR(xspi->regs); | |
ae918c02 | 401 | goto put_master; |
ae918c02 AK |
402 | } |
403 | ||
7cb2abd0 | 404 | master->bus_num = pdev->dev.id; |
91565c40 | 405 | master->num_chipselect = num_cs; |
7cb2abd0 | 406 | master->dev.of_node = pdev->dev.of_node; |
ae918c02 | 407 | |
d81c0bbb | 408 | xspi->mem = *r; |
d5af91a1 | 409 | xspi->irq = irq; |
082339bc MS |
410 | |
411 | /* | |
412 | * Detect endianess on the IP via loop bit in CR. Detection | |
413 | * must be done before reset is sent because incorrect reset | |
414 | * value generates error interrupt. | |
415 | * Setup little endian helper functions first and try to use them | |
416 | * and check if bit was correctly setup or not. | |
417 | */ | |
418 | xspi->read_fn = xspi_read32; | |
419 | xspi->write_fn = xspi_write32; | |
420 | ||
421 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); | |
422 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
423 | tmp &= XSPI_CR_LOOP; | |
424 | if (tmp != XSPI_CR_LOOP) { | |
97782149 PM |
425 | xspi->read_fn = xspi_read32_be; |
426 | xspi->write_fn = xspi_write32_be; | |
86fc5935 | 427 | } |
082339bc | 428 | |
91565c40 | 429 | xspi->bits_per_word = bits_per_word; |
c9da2e12 RR |
430 | if (xspi->bits_per_word == 8) { |
431 | xspi->tx_fn = xspi_tx8; | |
432 | xspi->rx_fn = xspi_rx8; | |
433 | } else if (xspi->bits_per_word == 16) { | |
434 | xspi->tx_fn = xspi_tx16; | |
435 | xspi->rx_fn = xspi_rx16; | |
436 | } else if (xspi->bits_per_word == 32) { | |
437 | xspi->tx_fn = xspi_tx32; | |
438 | xspi->rx_fn = xspi_rx32; | |
d81c0bbb MB |
439 | } else { |
440 | ret = -EINVAL; | |
c40537d0 | 441 | goto put_master; |
d81c0bbb | 442 | } |
c9da2e12 | 443 | |
ae918c02 AK |
444 | |
445 | /* SPI controller initializations */ | |
86fc5935 | 446 | xspi_init_hw(xspi); |
ae918c02 AK |
447 | |
448 | /* Register for SPI Interrupt */ | |
d5af91a1 RR |
449 | ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); |
450 | if (ret) | |
c40537d0 | 451 | goto put_master; |
ae918c02 | 452 | |
d5af91a1 RR |
453 | ret = spi_bitbang_start(&xspi->bitbang); |
454 | if (ret) { | |
7cb2abd0 | 455 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
ae918c02 AK |
456 | goto free_irq; |
457 | } | |
458 | ||
7cb2abd0 | 459 | dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", |
d81c0bbb MB |
460 | (unsigned long long)r->start, xspi->regs, xspi->irq); |
461 | ||
462 | if (pdata) { | |
463 | for (i = 0; i < pdata->num_devices; i++) | |
464 | spi_new_device(master, pdata->devices + i); | |
465 | } | |
466 | ||
7cb2abd0 | 467 | platform_set_drvdata(pdev, master); |
d81c0bbb | 468 | return 0; |
ae918c02 AK |
469 | |
470 | free_irq: | |
471 | free_irq(xspi->irq, xspi); | |
ae918c02 AK |
472 | put_master: |
473 | spi_master_put(master); | |
d81c0bbb MB |
474 | |
475 | return ret; | |
ae918c02 AK |
476 | } |
477 | ||
7cb2abd0 | 478 | static int xilinx_spi_remove(struct platform_device *pdev) |
ae918c02 | 479 | { |
7cb2abd0 | 480 | struct spi_master *master = platform_get_drvdata(pdev); |
d81c0bbb | 481 | struct xilinx_spi *xspi = spi_master_get_devdata(master); |
ae918c02 AK |
482 | |
483 | spi_bitbang_stop(&xspi->bitbang); | |
484 | free_irq(xspi->irq, xspi); | |
ff82c587 | 485 | |
d5af91a1 | 486 | spi_master_put(xspi->bitbang.master); |
8fd8821b GL |
487 | |
488 | return 0; | |
489 | } | |
490 | ||
491 | /* work with hotplug and coldplug */ | |
492 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); | |
493 | ||
494 | static struct platform_driver xilinx_spi_driver = { | |
495 | .probe = xilinx_spi_probe, | |
fd4a319b | 496 | .remove = xilinx_spi_remove, |
8fd8821b GL |
497 | .driver = { |
498 | .name = XILINX_SPI_NAME, | |
499 | .owner = THIS_MODULE, | |
eae6cb31 | 500 | .of_match_table = xilinx_spi_of_match, |
8fd8821b GL |
501 | }, |
502 | }; | |
940ab889 | 503 | module_platform_driver(xilinx_spi_driver); |
8fd8821b | 504 | |
ae918c02 AK |
505 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
506 | MODULE_DESCRIPTION("Xilinx SPI driver"); | |
507 | MODULE_LICENSE("GPL"); |