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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ae918c02 | 2 | /* |
ae918c02 AK |
3 | * Xilinx SPI controller driver (master mode only) |
4 | * | |
5 | * Author: MontaVista Software, Inc. | |
6 | * source@mvista.com | |
7 | * | |
8fd8821b GL |
8 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
9 | * Copyright (c) 2009 Intel Corporation | |
10 | * 2002-2007 (c) MontaVista Software, Inc. | |
11 | ||
ae918c02 AK |
12 | */ |
13 | ||
14 | #include <linux/module.h> | |
ae918c02 | 15 | #include <linux/interrupt.h> |
eae6cb31 | 16 | #include <linux/of.h> |
8fd8821b | 17 | #include <linux/platform_device.h> |
ae918c02 AK |
18 | #include <linux/spi/spi.h> |
19 | #include <linux/spi/spi_bitbang.h> | |
d5af91a1 | 20 | #include <linux/spi/xilinx_spi.h> |
eae6cb31 | 21 | #include <linux/io.h> |
d5af91a1 | 22 | |
eb25f16c RR |
23 | #define XILINX_SPI_MAX_CS 32 |
24 | ||
fc3ba952 | 25 | #define XILINX_SPI_NAME "xilinx_spi" |
ae918c02 AK |
26 | |
27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | |
28 | * Product Specification", DS464 | |
29 | */ | |
c9da2e12 | 30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
ae918c02 | 31 | |
082339bc | 32 | #define XSPI_CR_LOOP 0x01 |
ae918c02 AK |
33 | #define XSPI_CR_ENABLE 0x02 |
34 | #define XSPI_CR_MASTER_MODE 0x04 | |
35 | #define XSPI_CR_CPOL 0x08 | |
36 | #define XSPI_CR_CPHA 0x10 | |
bca690db | 37 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ |
0240f945 | 38 | XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) |
ae918c02 AK |
39 | #define XSPI_CR_TXFIFO_RESET 0x20 |
40 | #define XSPI_CR_RXFIFO_RESET 0x40 | |
41 | #define XSPI_CR_MANUAL_SSELECT 0x80 | |
42 | #define XSPI_CR_TRANS_INHIBIT 0x100 | |
c9da2e12 | 43 | #define XSPI_CR_LSB_FIRST 0x200 |
ae918c02 | 44 | |
c9da2e12 | 45 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
ae918c02 AK |
46 | |
47 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | |
48 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | |
49 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ | |
50 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | |
51 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | |
52 | ||
c9da2e12 RR |
53 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
54 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ | |
ae918c02 AK |
55 | |
56 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | |
57 | ||
58 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 | |
59 | * IPIF registers are 32 bit | |
60 | */ | |
61 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ | |
62 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 | |
63 | ||
64 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ | |
65 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ | |
66 | ||
67 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ | |
68 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while | |
69 | * disabled */ | |
70 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ | |
71 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | |
72 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | |
73 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | |
c9da2e12 | 74 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
ae918c02 AK |
75 | |
76 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | |
77 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | |
78 | ||
79 | struct xilinx_spi { | |
80 | /* bitbang has to be first */ | |
81 | struct spi_bitbang bitbang; | |
82 | struct completion done; | |
ae918c02 AK |
83 | void __iomem *regs; /* virt. address of the control registers */ |
84 | ||
9ca1273b | 85 | int irq; |
1dd46599 | 86 | bool force_irq; /* force irq to setup master inhibit */ |
ae918c02 AK |
87 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
88 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | |
17aaaa80 | 89 | u8 bytes_per_word; |
4c9a7614 | 90 | int buffer_size; /* buffer size in words */ |
f9c6ef6c | 91 | u32 cs_inactive; /* Level of the CS pins when inactive*/ |
6ff8672a JH |
92 | unsigned int (*read_fn)(void __iomem *); |
93 | void (*write_fn)(u32, void __iomem *); | |
ae918c02 AK |
94 | }; |
95 | ||
0635287a MB |
96 | static void xspi_write32(u32 val, void __iomem *addr) |
97 | { | |
98 | iowrite32(val, addr); | |
99 | } | |
100 | ||
101 | static unsigned int xspi_read32(void __iomem *addr) | |
102 | { | |
103 | return ioread32(addr); | |
104 | } | |
105 | ||
106 | static void xspi_write32_be(u32 val, void __iomem *addr) | |
107 | { | |
108 | iowrite32be(val, addr); | |
109 | } | |
110 | ||
111 | static unsigned int xspi_read32_be(void __iomem *addr) | |
112 | { | |
113 | return ioread32be(addr); | |
114 | } | |
115 | ||
24ba5e59 | 116 | static void xilinx_spi_tx(struct xilinx_spi *xspi) |
c9da2e12 | 117 | { |
34093cb9 RRD |
118 | u32 data = 0; |
119 | ||
c3092941 RRD |
120 | if (!xspi->tx_ptr) { |
121 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
122 | return; | |
123 | } | |
34093cb9 RRD |
124 | |
125 | switch (xspi->bytes_per_word) { | |
126 | case 1: | |
127 | data = *(u8 *)(xspi->tx_ptr); | |
128 | break; | |
129 | case 2: | |
130 | data = *(u16 *)(xspi->tx_ptr); | |
131 | break; | |
132 | case 4: | |
133 | data = *(u32 *)(xspi->tx_ptr); | |
134 | break; | |
135 | } | |
136 | ||
137 | xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); | |
17aaaa80 | 138 | xspi->tx_ptr += xspi->bytes_per_word; |
c9da2e12 RR |
139 | } |
140 | ||
24ba5e59 | 141 | static void xilinx_spi_rx(struct xilinx_spi *xspi) |
c9da2e12 RR |
142 | { |
143 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
c9da2e12 | 144 | |
24ba5e59 RRD |
145 | if (!xspi->rx_ptr) |
146 | return; | |
c9da2e12 | 147 | |
17aaaa80 RRD |
148 | switch (xspi->bytes_per_word) { |
149 | case 1: | |
24ba5e59 RRD |
150 | *(u8 *)(xspi->rx_ptr) = data; |
151 | break; | |
17aaaa80 | 152 | case 2: |
24ba5e59 RRD |
153 | *(u16 *)(xspi->rx_ptr) = data; |
154 | break; | |
17aaaa80 | 155 | case 4: |
c9da2e12 | 156 | *(u32 *)(xspi->rx_ptr) = data; |
24ba5e59 | 157 | break; |
c9da2e12 | 158 | } |
24ba5e59 | 159 | |
17aaaa80 | 160 | xspi->rx_ptr += xspi->bytes_per_word; |
c9da2e12 RR |
161 | } |
162 | ||
86fc5935 | 163 | static void xspi_init_hw(struct xilinx_spi *xspi) |
ae918c02 | 164 | { |
86fc5935 RR |
165 | void __iomem *regs_base = xspi->regs; |
166 | ||
ae918c02 | 167 | /* Reset the SPI device */ |
86fc5935 RR |
168 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
169 | regs_base + XIPIF_V123B_RESETR_OFFSET); | |
899929ba RRD |
170 | /* Enable the transmit empty interrupt, which we use to determine |
171 | * progress on the transmission. | |
172 | */ | |
173 | xspi->write_fn(XSPI_INTR_TX_EMPTY, | |
174 | regs_base + XIPIF_V123B_IIER_OFFSET); | |
22417352 RRD |
175 | /* Disable the global IPIF interrupt */ |
176 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ae918c02 | 177 | /* Deselect the slave on the SPI bus */ |
86fc5935 | 178 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
ae918c02 AK |
179 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
180 | * put SPI controller into master mode, and enable it */ | |
22417352 RRD |
181 | xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE | |
182 | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET, | |
183 | regs_base + XSPI_CR_OFFSET); | |
ae918c02 AK |
184 | } |
185 | ||
186 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |
187 | { | |
188 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
f9c6ef6c RRD |
189 | u16 cr; |
190 | u32 cs; | |
ae918c02 AK |
191 | |
192 | if (is_on == BITBANG_CS_INACTIVE) { | |
193 | /* Deselect the slave on the SPI bus */ | |
f9c6ef6c RRD |
194 | xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); |
195 | return; | |
ae918c02 | 196 | } |
f9c6ef6c RRD |
197 | |
198 | /* Set the SPI clock phase and polarity */ | |
199 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; | |
200 | if (spi->mode & SPI_CPHA) | |
201 | cr |= XSPI_CR_CPHA; | |
202 | if (spi->mode & SPI_CPOL) | |
203 | cr |= XSPI_CR_CPOL; | |
204 | if (spi->mode & SPI_LSB_FIRST) | |
205 | cr |= XSPI_CR_LSB_FIRST; | |
206 | if (spi->mode & SPI_LOOP) | |
207 | cr |= XSPI_CR_LOOP; | |
208 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
209 | ||
210 | /* We do not check spi->max_speed_hz here as the SPI clock | |
211 | * frequency is not software programmable (the IP block design | |
212 | * parameter) | |
213 | */ | |
214 | ||
215 | cs = xspi->cs_inactive; | |
9e264f3f | 216 | cs ^= BIT(spi_get_chipselect(spi, 0)); |
f9c6ef6c RRD |
217 | |
218 | /* Activate the chip select */ | |
219 | xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); | |
ae918c02 AK |
220 | } |
221 | ||
222 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | |
9bf46f6d | 223 | * custom txrx_bufs(). |
ae918c02 AK |
224 | */ |
225 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | |
226 | struct spi_transfer *t) | |
227 | { | |
f9c6ef6c RRD |
228 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
229 | ||
230 | if (spi->mode & SPI_CS_HIGH) | |
9e264f3f | 231 | xspi->cs_inactive &= ~BIT(spi_get_chipselect(spi, 0)); |
f9c6ef6c | 232 | else |
9e264f3f | 233 | xspi->cs_inactive |= BIT(spi_get_chipselect(spi, 0)); |
f9c6ef6c | 234 | |
ae918c02 AK |
235 | return 0; |
236 | } | |
237 | ||
ae918c02 AK |
238 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
239 | { | |
240 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
b563bfb8 | 241 | int remaining_words; /* the number of words left to transfer */ |
22417352 RRD |
242 | bool use_irq = false; |
243 | u16 cr = 0; | |
ae918c02 AK |
244 | |
245 | /* We get here with transmitter inhibited */ | |
246 | ||
247 | xspi->tx_ptr = t->tx_buf; | |
248 | xspi->rx_ptr = t->rx_buf; | |
b563bfb8 | 249 | remaining_words = t->len / xspi->bytes_per_word; |
ae918c02 | 250 | |
1dd46599 VF |
251 | if (xspi->irq >= 0 && |
252 | (xspi->force_irq || remaining_words > xspi->buffer_size)) { | |
74346841 | 253 | u32 isr; |
22417352 | 254 | use_irq = true; |
22417352 RRD |
255 | /* Inhibit irq to avoid spurious irqs on tx_empty*/ |
256 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
257 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | |
258 | xspi->regs + XSPI_CR_OFFSET); | |
74346841 RRD |
259 | /* ACK old irqs (if any) */ |
260 | isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
261 | if (isr) | |
262 | xspi->write_fn(isr, | |
263 | xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
264 | /* Enable the global IPIF interrupt */ | |
265 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, | |
266 | xspi->regs + XIPIF_V123B_DGIER_OFFSET); | |
267 | reinit_completion(&xspi->done); | |
22417352 RRD |
268 | } |
269 | ||
b563bfb8 | 270 | while (remaining_words) { |
b563bfb8 | 271 | int n_words, tx_words, rx_words; |
eca37c7c | 272 | u32 sr; |
5a1314fa | 273 | int stalled; |
68c315bb | 274 | |
b563bfb8 | 275 | n_words = min(remaining_words, xspi->buffer_size); |
4c9a7614 | 276 | |
b563bfb8 RRD |
277 | tx_words = n_words; |
278 | while (tx_words--) | |
279 | xilinx_spi_tx(xspi); | |
68c315bb PC |
280 | |
281 | /* Start the transfer by not inhibiting the transmitter any | |
282 | * longer | |
283 | */ | |
68c315bb | 284 | |
22417352 | 285 | if (use_irq) { |
d9f58812 | 286 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
5fe11cc0 | 287 | wait_for_completion(&xspi->done); |
eca37c7c RRD |
288 | /* A transmit has just completed. Process received data |
289 | * and check for more data to transmit. Always inhibit | |
290 | * the transmitter while the Isr refills the transmit | |
291 | * register/FIFO, or make sure it is stopped if we're | |
292 | * done. | |
293 | */ | |
d9f58812 | 294 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
eca37c7c RRD |
295 | xspi->regs + XSPI_CR_OFFSET); |
296 | sr = XSPI_SR_TX_EMPTY_MASK; | |
297 | } else | |
298 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
68c315bb PC |
299 | |
300 | /* Read out all the data from the Rx FIFO */ | |
b563bfb8 | 301 | rx_words = n_words; |
5a1314fa | 302 | stalled = 10; |
eca37c7c | 303 | while (rx_words) { |
5a1314fa RR |
304 | if (rx_words == n_words && !(stalled--) && |
305 | !(sr & XSPI_SR_TX_EMPTY_MASK) && | |
306 | (sr & XSPI_SR_RX_EMPTY_MASK)) { | |
307 | dev_err(&spi->dev, | |
308 | "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n"); | |
309 | xspi_init_hw(xspi); | |
310 | return -EIO; | |
311 | } | |
312 | ||
eca37c7c RRD |
313 | if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) { |
314 | xilinx_spi_rx(xspi); | |
315 | rx_words--; | |
316 | continue; | |
317 | } | |
318 | ||
319 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
320 | if (!(sr & XSPI_SR_RX_EMPTY_MASK)) { | |
321 | xilinx_spi_rx(xspi); | |
322 | rx_words--; | |
323 | } | |
324 | } | |
b563bfb8 RRD |
325 | |
326 | remaining_words -= n_words; | |
68c315bb | 327 | } |
ae918c02 | 328 | |
16ea9b8a | 329 | if (use_irq) { |
22417352 | 330 | xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET); |
16ea9b8a RRD |
331 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
332 | } | |
22417352 | 333 | |
d79b2d07 | 334 | return t->len; |
ae918c02 AK |
335 | } |
336 | ||
337 | ||
338 | /* This driver supports single master mode only. Hence Tx FIFO Empty | |
339 | * is the only interrupt we care about. | |
340 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode | |
341 | * Fault are not to happen. | |
342 | */ | |
343 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |
344 | { | |
345 | struct xilinx_spi *xspi = dev_id; | |
346 | u32 ipif_isr; | |
347 | ||
348 | /* Get the IPIF interrupts, and clear them immediately */ | |
86fc5935 RR |
349 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
350 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
ae918c02 AK |
351 | |
352 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ | |
68c315bb | 353 | complete(&xspi->done); |
d3364847 | 354 | return IRQ_HANDLED; |
ae918c02 AK |
355 | } |
356 | ||
d3364847 | 357 | return IRQ_NONE; |
ae918c02 AK |
358 | } |
359 | ||
4c9a7614 RRD |
360 | static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) |
361 | { | |
362 | u8 sr; | |
363 | int n_words = 0; | |
364 | ||
365 | /* | |
366 | * Before the buffer_size detection we reset the core | |
367 | * to make sure we start with a clean state. | |
368 | */ | |
369 | xspi->write_fn(XIPIF_V123B_RESET_MASK, | |
370 | xspi->regs + XIPIF_V123B_RESETR_OFFSET); | |
371 | ||
372 | /* Fill the Tx FIFO with as many words as possible */ | |
373 | do { | |
374 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
375 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
376 | n_words++; | |
377 | } while (!(sr & XSPI_SR_TX_FULL_MASK)); | |
378 | ||
379 | return n_words; | |
380 | } | |
381 | ||
eae6cb31 | 382 | static const struct of_device_id xilinx_spi_of_match[] = { |
a094c2fa | 383 | { .compatible = "xlnx,axi-quad-spi-1.00.a", }, |
eae6cb31 GL |
384 | { .compatible = "xlnx,xps-spi-2.00.a", }, |
385 | { .compatible = "xlnx,xps-spi-2.00.b", }, | |
386 | {} | |
387 | }; | |
388 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); | |
eae6cb31 | 389 | |
7cb2abd0 | 390 | static int xilinx_spi_probe(struct platform_device *pdev) |
ae918c02 | 391 | { |
ae918c02 | 392 | struct xilinx_spi *xspi; |
d81c0bbb | 393 | struct xspi_platform_data *pdata; |
ad3fdbca | 394 | struct resource *res; |
e58f7d15 | 395 | int ret, num_cs = 0, bits_per_word; |
d81c0bbb | 396 | struct spi_master *master; |
1dd46599 | 397 | bool force_irq = false; |
082339bc | 398 | u32 tmp; |
d81c0bbb MB |
399 | u8 i; |
400 | ||
8074cf06 | 401 | pdata = dev_get_platdata(&pdev->dev); |
d81c0bbb MB |
402 | if (pdata) { |
403 | num_cs = pdata->num_chipselect; | |
404 | bits_per_word = pdata->bits_per_word; | |
1dd46599 | 405 | force_irq = pdata->force_irq; |
be3acdff MS |
406 | } else { |
407 | of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", | |
408 | &num_cs); | |
e58f7d15 AGM |
409 | ret = of_property_read_u32(pdev->dev.of_node, |
410 | "xlnx,num-transfer-bits", | |
411 | &bits_per_word); | |
412 | if (ret) | |
413 | bits_per_word = 8; | |
d81c0bbb | 414 | } |
ae918c02 | 415 | |
d81c0bbb | 416 | if (!num_cs) { |
7cb2abd0 MB |
417 | dev_err(&pdev->dev, |
418 | "Missing slave select configuration data\n"); | |
d81c0bbb MB |
419 | return -EINVAL; |
420 | } | |
421 | ||
eb25f16c RR |
422 | if (num_cs > XILINX_SPI_MAX_CS) { |
423 | dev_err(&pdev->dev, "Invalid number of spi slaves\n"); | |
424 | return -EINVAL; | |
425 | } | |
426 | ||
2d064581 | 427 | master = devm_spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
d5af91a1 | 428 | if (!master) |
d81c0bbb | 429 | return -ENODEV; |
ae918c02 | 430 | |
e7db06b5 | 431 | /* the spi->mode bits understood by this driver: */ |
f9c6ef6c RRD |
432 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | |
433 | SPI_CS_HIGH; | |
e7db06b5 | 434 | |
ae918c02 | 435 | xspi = spi_master_get_devdata(master); |
f9c6ef6c | 436 | xspi->cs_inactive = 0xffffffff; |
94c69f76 | 437 | xspi->bitbang.master = master; |
ae918c02 AK |
438 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
439 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | |
440 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; | |
ae918c02 AK |
441 | init_completion(&xspi->done); |
442 | ||
0623ec17 | 443 | xspi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
2d064581 YY |
444 | if (IS_ERR(xspi->regs)) |
445 | return PTR_ERR(xspi->regs); | |
ae918c02 | 446 | |
4b153a21 | 447 | master->bus_num = pdev->id; |
91565c40 | 448 | master->num_chipselect = num_cs; |
7cb2abd0 | 449 | master->dev.of_node = pdev->dev.of_node; |
082339bc MS |
450 | |
451 | /* | |
452 | * Detect endianess on the IP via loop bit in CR. Detection | |
453 | * must be done before reset is sent because incorrect reset | |
454 | * value generates error interrupt. | |
455 | * Setup little endian helper functions first and try to use them | |
456 | * and check if bit was correctly setup or not. | |
457 | */ | |
0635287a MB |
458 | xspi->read_fn = xspi_read32; |
459 | xspi->write_fn = xspi_write32; | |
082339bc MS |
460 | |
461 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); | |
462 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
463 | tmp &= XSPI_CR_LOOP; | |
464 | if (tmp != XSPI_CR_LOOP) { | |
0635287a MB |
465 | xspi->read_fn = xspi_read32_be; |
466 | xspi->write_fn = xspi_write32_be; | |
86fc5935 | 467 | } |
082339bc | 468 | |
9bf46f6d | 469 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
17aaaa80 | 470 | xspi->bytes_per_word = bits_per_word / 8; |
4c9a7614 RRD |
471 | xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); |
472 | ||
7b3b7432 | 473 | xspi->irq = platform_get_irq(pdev, 0); |
4db9bf54 | 474 | if (xspi->irq < 0 && xspi->irq != -ENXIO) { |
2d064581 | 475 | return xspi->irq; |
4db9bf54 | 476 | } else if (xspi->irq >= 0) { |
5fe11cc0 RRD |
477 | /* Register for SPI Interrupt */ |
478 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, | |
479 | dev_name(&pdev->dev), xspi); | |
480 | if (ret) | |
2d064581 | 481 | return ret; |
1dd46599 VF |
482 | |
483 | xspi->force_irq = force_irq; | |
7b3b7432 MS |
484 | } |
485 | ||
5fe11cc0 RRD |
486 | /* SPI controller initializations */ |
487 | xspi_init_hw(xspi); | |
ae918c02 | 488 | |
d5af91a1 RR |
489 | ret = spi_bitbang_start(&xspi->bitbang); |
490 | if (ret) { | |
7cb2abd0 | 491 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
2d064581 | 492 | return ret; |
eae6cb31 GL |
493 | } |
494 | ||
985be7eb | 495 | dev_info(&pdev->dev, "at %pR, irq=%d\n", res, xspi->irq); |
8fd8821b | 496 | |
eae6cb31 GL |
497 | if (pdata) { |
498 | for (i = 0; i < pdata->num_devices; i++) | |
499 | spi_new_device(master, pdata->devices + i); | |
500 | } | |
8fd8821b | 501 | |
7cb2abd0 | 502 | platform_set_drvdata(pdev, master); |
8fd8821b GL |
503 | return 0; |
504 | } | |
505 | ||
3b1d7e11 | 506 | static void xilinx_spi_remove(struct platform_device *pdev) |
8fd8821b | 507 | { |
7cb2abd0 | 508 | struct spi_master *master = platform_get_drvdata(pdev); |
d81c0bbb | 509 | struct xilinx_spi *xspi = spi_master_get_devdata(master); |
7b3b7432 | 510 | void __iomem *regs_base = xspi->regs; |
ae918c02 AK |
511 | |
512 | spi_bitbang_stop(&xspi->bitbang); | |
7b3b7432 MS |
513 | |
514 | /* Disable all the interrupts just in case */ | |
515 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); | |
516 | /* Disable the global IPIF interrupt */ | |
517 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ff82c587 | 518 | |
d5af91a1 | 519 | spi_master_put(xspi->bitbang.master); |
8fd8821b GL |
520 | } |
521 | ||
522 | /* work with hotplug and coldplug */ | |
523 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); | |
524 | ||
525 | static struct platform_driver xilinx_spi_driver = { | |
526 | .probe = xilinx_spi_probe, | |
3b1d7e11 | 527 | .remove_new = xilinx_spi_remove, |
8fd8821b GL |
528 | .driver = { |
529 | .name = XILINX_SPI_NAME, | |
eae6cb31 | 530 | .of_match_table = xilinx_spi_of_match, |
8fd8821b GL |
531 | }, |
532 | }; | |
940ab889 | 533 | module_platform_driver(xilinx_spi_driver); |
8fd8821b | 534 | |
ae918c02 AK |
535 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
536 | MODULE_DESCRIPTION("Xilinx SPI driver"); | |
537 | MODULE_LICENSE("GPL"); |