[linux-2.6-block.git] / drivers / spi / spi-xilinx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Xilinx SPI controller driver (host mode only)
 *
 * Author: MontaVista Software, Inc.
 *	source@mvista.com
 *
 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
 * Copyright (c) 2009 Intel Corporation
 * 2002-2007 (c) MontaVista Software, Inc.

 */

#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/spi/xilinx_spi.h>
#include <linux/io.h>

#define XILINX_SPI_MAX_CS	32

#define XILINX_SPI_NAME "xilinx_spi"

/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 * Product Specification", DS464
 */
#define XSPI_CR_OFFSET		0x60	/* Control Register */

#define XSPI_CR_LOOP		0x01
#define XSPI_CR_ENABLE		0x02
#define XSPI_CR_MASTER_MODE	0x04
#define XSPI_CR_CPOL		0x08
#define XSPI_CR_CPHA		0x10
#define XSPI_CR_MODE_MASK	(XSPI_CR_CPHA | XSPI_CR_CPOL | \
				 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
#define XSPI_CR_TXFIFO_RESET	0x20
#define XSPI_CR_RXFIFO_RESET	0x40
#define XSPI_CR_MANUAL_SSELECT	0x80
#define XSPI_CR_TRANS_INHIBIT	0x100
#define XSPI_CR_LSB_FIRST	0x200

#define XSPI_SR_OFFSET		0x64	/* Status Register */

#define XSPI_SR_RX_EMPTY_MASK	0x01	/* Receive FIFO is empty */
#define XSPI_SR_RX_FULL_MASK	0x02	/* Receive FIFO is full */
#define XSPI_SR_TX_EMPTY_MASK	0x04	/* Transmit FIFO is empty */
#define XSPI_SR_TX_FULL_MASK	0x08	/* Transmit FIFO is full */
#define XSPI_SR_MODE_FAULT_MASK	0x10	/* Mode fault error */

#define XSPI_TXD_OFFSET		0x68	/* Data Transmit Register */
#define XSPI_RXD_OFFSET		0x6c	/* Data Receive Register */

#define XSPI_SSR_OFFSET		0x70	/* 32-bit Slave Select Register */

/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 * IPIF registers are 32 bit
 */
#define XIPIF_V123B_DGIER_OFFSET	0x1c	/* IPIF global int enable reg */
#define XIPIF_V123B_GINTR_ENABLE	0x80000000

#define XIPIF_V123B_IISR_OFFSET		0x20	/* IPIF interrupt status reg */
#define XIPIF_V123B_IIER_OFFSET		0x28	/* IPIF interrupt enable reg */

#define XSPI_INTR_MODE_FAULT		0x01	/* Mode fault error */
#define XSPI_INTR_SLAVE_MODE_FAULT	0x02	/* Selected as slave while
						 * disabled */
#define XSPI_INTR_TX_EMPTY		0x04	/* TxFIFO is empty */
#define XSPI_INTR_TX_UNDERRUN		0x08	/* TxFIFO was underrun */
#define XSPI_INTR_RX_FULL		0x10	/* RxFIFO is full */
#define XSPI_INTR_RX_OVERRUN		0x20	/* RxFIFO was overrun */
#define XSPI_INTR_TX_HALF_EMPTY		0x40	/* TxFIFO is half empty */

#define XIPIF_V123B_RESETR_OFFSET	0x40	/* IPIF reset register */
#define XIPIF_V123B_RESET_MASK		0x0a	/* the value to write */

struct xilinx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;
	void __iomem	*regs;	/* virt. address of the control registers */

	int		irq;
	bool force_irq;		/* force irq to setup host inhibit */
	u8 *rx_ptr;		/* pointer in the Tx buffer */
	const u8 *tx_ptr;	/* pointer in the Rx buffer */
	u8 bytes_per_word;
	int buffer_size;	/* buffer size in words */
	u32 cs_inactive;	/* Level of the CS pins when inactive*/
	unsigned int (*read_fn)(void __iomem *);
	void (*write_fn)(u32, void __iomem *);
};

static void xspi_write32(u32 val, void __iomem *addr)
{
	iowrite32(val, addr);
}

static unsigned int xspi_read32(void __iomem *addr)
{
	return ioread32(addr);
}

static void xspi_write32_be(u32 val, void __iomem *addr)
{
	iowrite32be(val, addr);
}

static unsigned int xspi_read32_be(void __iomem *addr)
{
	return ioread32be(addr);
}

static void xilinx_spi_tx(struct xilinx_spi *xspi)
{
	u32 data = 0;

	if (!xspi->tx_ptr) {
		xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
		return;
	}

	switch (xspi->bytes_per_word) {
	case 1:
		data = *(u8 *)(xspi->tx_ptr);
		break;
	case 2:
		data = *(u16 *)(xspi->tx_ptr);
		break;
	case 4:
		data = *(u32 *)(xspi->tx_ptr);
		break;
	}

	xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += xspi->bytes_per_word;
}

static void xilinx_spi_rx(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);

	if (!xspi->rx_ptr)
		return;

	switch (xspi->bytes_per_word) {
	case 1:
		*(u8 *)(xspi->rx_ptr) = data;
		break;
	case 2:
		*(u16 *)(xspi->rx_ptr) = data;
		break;
	case 4:
		*(u32 *)(xspi->rx_ptr) = data;
		break;
	}

	xspi->rx_ptr += xspi->bytes_per_word;
}

static void xspi_init_hw(struct xilinx_spi *xspi)
{
	void __iomem *regs_base = xspi->regs;

	/* Reset the SPI device */
	xspi->write_fn(XIPIF_V123B_RESET_MASK,
		regs_base + XIPIF_V123B_RESETR_OFFSET);
	/* Enable the transmit empty interrupt, which we use to determine
	 * progress on the transmission.
	 */
	xspi->write_fn(XSPI_INTR_TX_EMPTY,
			regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Disable the global IPIF interrupt */
	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
	/* Deselect the Target on the SPI bus */
	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
	/* Disable the transmitter, enable Manual Target Select Assertion,
	 * put SPI controller into host mode, and enable it */
	xspi->write_fn(XSPI_CR_MANUAL_SSELECT |	XSPI_CR_MASTER_MODE |
		XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |	XSPI_CR_RXFIFO_RESET,
		regs_base + XSPI_CR_OFFSET);
}

static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
{
	struct xilinx_spi *xspi = spi_controller_get_devdata(spi->controller);
	u16 cr;
	u32 cs;

	if (is_on == BITBANG_CS_INACTIVE) {
		/* Deselect the target on the SPI bus */
		xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
		return;
	}

	/* Set the SPI clock phase and polarity */
	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)	& ~XSPI_CR_MODE_MASK;
	if (spi->mode & SPI_CPHA)
		cr |= XSPI_CR_CPHA;
	if (spi->mode & SPI_CPOL)
		cr |= XSPI_CR_CPOL;
	if (spi->mode & SPI_LSB_FIRST)
		cr |= XSPI_CR_LSB_FIRST;
	if (spi->mode & SPI_LOOP)
		cr |= XSPI_CR_LOOP;
	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

	/* We do not check spi->max_speed_hz here as the SPI clock
	 * frequency is not software programmable (the IP block design
	 * parameter)
	 */

	cs = xspi->cs_inactive;
	cs ^= BIT(spi_get_chipselect(spi, 0));

	/* Activate the chip select */
	xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
}

/* spi_bitbang requires custom setup_transfer() to be defined if there is a
 * custom txrx_bufs().
 */
static int xilinx_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_controller_get_devdata(spi->controller);

	if (spi->mode & SPI_CS_HIGH)
		xspi->cs_inactive &= ~BIT(spi_get_chipselect(spi, 0));
	else
		xspi->cs_inactive |= BIT(spi_get_chipselect(spi, 0));

	return 0;
}

static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_controller_get_devdata(spi->controller);
	int remaining_words;	/* the number of words left to transfer */
	bool use_irq = false;
	u16 cr = 0;

	/* We get here with transmitter inhibited */

	xspi->tx_ptr = t->tx_buf;
	xspi->rx_ptr = t->rx_buf;
	remaining_words = t->len / xspi->bytes_per_word;

	if (xspi->irq >= 0 &&
	    (xspi->force_irq || remaining_words > xspi->buffer_size)) {
		u32 isr;
		use_irq = true;
		/* Inhibit irq to avoid spurious irqs on tx_empty*/
		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
		xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
			       xspi->regs + XSPI_CR_OFFSET);
		/* ACK old irqs (if any) */
		isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
		if (isr)
			xspi->write_fn(isr,
				       xspi->regs + XIPIF_V123B_IISR_OFFSET);
		/* Enable the global IPIF interrupt */
		xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
				xspi->regs + XIPIF_V123B_DGIER_OFFSET);
		reinit_completion(&xspi->done);
	}

	while (remaining_words) {
		int n_words, tx_words, rx_words;
		u32 sr;
		int stalled;

		n_words = min(remaining_words, xspi->buffer_size);

		tx_words = n_words;
		while (tx_words--)
			xilinx_spi_tx(xspi);

		/* Start the transfer by not inhibiting the transmitter any
		 * longer
		 */

		if (use_irq) {
			xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
			wait_for_completion(&xspi->done);
			/* A transmit has just completed. Process received data
			 * and check for more data to transmit. Always inhibit
			 * the transmitter while the Isr refills the transmit
			 * register/FIFO, or make sure it is stopped if we're
			 * done.
			 */
			xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
				       xspi->regs + XSPI_CR_OFFSET);
			sr = XSPI_SR_TX_EMPTY_MASK;
		} else
			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);

		/* Read out all the data from the Rx FIFO */
		rx_words = n_words;
		stalled = 10;
		while (rx_words) {
			if (rx_words == n_words && !(stalled--) &&
			    !(sr & XSPI_SR_TX_EMPTY_MASK) &&
			    (sr & XSPI_SR_RX_EMPTY_MASK)) {
				dev_err(&spi->dev,
					"Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
				xspi_init_hw(xspi);
				return -EIO;
			}

			if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
				xilinx_spi_rx(xspi);
				rx_words--;
				continue;
			}

			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
			if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
				xilinx_spi_rx(xspi);
				rx_words--;
			}
		}

		remaining_words -= n_words;
	}

	if (use_irq) {
		xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
	}

	return t->len;
}


/* This driver supports single host mode only. Hence Tx FIFO Empty
 * is the only interrupt we care about.
 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Target Mode
 * Fault are not to happen.
 */
static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
{
	struct xilinx_spi *xspi = dev_id;
	u32 ipif_isr;

	/* Get the IPIF interrupts, and clear them immediately */
	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);

	if (ipif_isr & XSPI_INTR_TX_EMPTY) {	/* Transmission completed */
		complete(&xspi->done);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
{
	u8 sr;
	int n_words = 0;

	/*
	 * Before the buffer_size detection we reset the core
	 * to make sure we start with a clean state.
	 */
	xspi->write_fn(XIPIF_V123B_RESET_MASK,
		xspi->regs + XIPIF_V123B_RESETR_OFFSET);

	/* Fill the Tx FIFO with as many words as possible */
	do {
		xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		n_words++;
	} while (!(sr & XSPI_SR_TX_FULL_MASK));

	return n_words;
}

static const struct of_device_id xilinx_spi_of_match[] = {
	{ .compatible = "xlnx,axi-quad-spi-1.00.a", },
	{ .compatible = "xlnx,xps-spi-2.00.a", },
	{ .compatible = "xlnx,xps-spi-2.00.b", },
	{}
};
MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);

static int xilinx_spi_probe(struct platform_device *pdev)
{
	struct xilinx_spi *xspi;
	struct xspi_platform_data *pdata;
	struct resource *res;
	int ret, num_cs = 0, bits_per_word;
	struct spi_controller *host;
	bool force_irq = false;
	u32 tmp;
	u8 i;

	pdata = dev_get_platdata(&pdev->dev);
	if (pdata) {
		num_cs = pdata->num_chipselect;
		bits_per_word = pdata->bits_per_word;
		force_irq = pdata->force_irq;
	} else {
		of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
					  &num_cs);
		ret = of_property_read_u32(pdev->dev.of_node,
					   "xlnx,num-transfer-bits",
					   &bits_per_word);
		if (ret)
			bits_per_word = 8;
	}

	if (!num_cs) {
		dev_err(&pdev->dev,
			"Missing target select configuration data\n");
		return -EINVAL;
	}

	if (num_cs > XILINX_SPI_MAX_CS) {
		dev_err(&pdev->dev, "Invalid number of spi targets\n");
		return -EINVAL;
	}

	host = devm_spi_alloc_host(&pdev->dev, sizeof(struct xilinx_spi));
	if (!host)
		return -ENODEV;

	/* the spi->mode bits understood by this driver: */
	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
			  SPI_CS_HIGH;

	xspi = spi_controller_get_devdata(host);
	xspi->cs_inactive = 0xffffffff;
	xspi->bitbang.ctlr = host;
	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
	init_completion(&xspi->done);

	xspi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
	if (IS_ERR(xspi->regs))
		return PTR_ERR(xspi->regs);

	host->bus_num = pdev->id;
	host->num_chipselect = num_cs;
	host->dev.of_node = pdev->dev.of_node;

	/*
	 * Detect endianess on the IP via loop bit in CR. Detection
	 * must be done before reset is sent because incorrect reset
	 * value generates error interrupt.
	 * Setup little endian helper functions first and try to use them
	 * and check if bit was correctly setup or not.
	 */
	xspi->read_fn = xspi_read32;
	xspi->write_fn = xspi_write32;

	xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
	tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	tmp &= XSPI_CR_LOOP;
	if (tmp != XSPI_CR_LOOP) {
		xspi->read_fn = xspi_read32_be;
		xspi->write_fn = xspi_write32_be;
	}

	host->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
	xspi->bytes_per_word = bits_per_word / 8;
	xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);

	xspi->irq = platform_get_irq(pdev, 0);
	if (xspi->irq < 0 && xspi->irq != -ENXIO) {
		return xspi->irq;
	} else if (xspi->irq >= 0) {
		/* Register for SPI Interrupt */
		ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
				dev_name(&pdev->dev), xspi);
		if (ret)
			return ret;

		xspi->force_irq = force_irq;
	}

	/* SPI controller initializations */
	xspi_init_hw(xspi);

	ret = spi_bitbang_start(&xspi->bitbang);
	if (ret) {
		dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
		return ret;
	}

	dev_info(&pdev->dev, "at %pR, irq=%d\n", res, xspi->irq);

	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			spi_new_device(host, pdata->devices + i);
	}

	platform_set_drvdata(pdev, host);
	return 0;
}

static void xilinx_spi_remove(struct platform_device *pdev)
{
	struct spi_controller *host = platform_get_drvdata(pdev);
	struct xilinx_spi *xspi = spi_controller_get_devdata(host);
	void __iomem *regs_base = xspi->regs;

	spi_bitbang_stop(&xspi->bitbang);

	/* Disable all the interrupts just in case */
	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Disable the global IPIF interrupt */
	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);

	spi_controller_put(xspi->bitbang.ctlr);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:" XILINX_SPI_NAME);

static struct platform_driver xilinx_spi_driver = {
	.probe = xilinx_spi_probe,
	.remove_new = xilinx_spi_remove,
	.driver = {
		.name = XILINX_SPI_NAME,
		.of_match_table = xilinx_spi_of_match,
	},
};
module_platform_driver(xilinx_spi_driver);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("Xilinx SPI driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
ae918c02	2	/*
709b785a	3	* Xilinx SPI controller driver (host mode only)
ae918c02 AK	4	*
	5	* Author: MontaVista Software, Inc.
	6	* source@mvista.com
	7	*
8fd8821b GL	8	* Copyright (c) 2010 Secret Lab Technologies, Ltd.
	9	* Copyright (c) 2009 Intel Corporation
	10	* 2002-2007 (c) MontaVista Software, Inc.
	11
ae918c02 AK	12	*/
	13
	14	#include <linux/module.h>
ae918c02	15	#include <linux/interrupt.h>
eae6cb31	16	#include <linux/of.h>
8fd8821b	17	#include <linux/platform_device.h>
ae918c02 AK	18	#include <linux/spi/spi.h>
ae918c02 AK	19	#include <linux/spi/spi_bitbang.h>
d5af91a1	20	#include <linux/spi/xilinx_spi.h>
eae6cb31	21	#include <linux/io.h>
d5af91a1	22
eb25f16c RR	23	#define XILINX_SPI_MAX_CS 32
eb25f16c RR	24
fc3ba952	25	#define XILINX_SPI_NAME "xilinx_spi"
ae918c02 AK	26
	27	/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
	28	* Product Specification", DS464
	29	*/
c9da2e12	30	#define XSPI_CR_OFFSET 0x60 /* Control Register */
ae918c02	31
082339bc	32	#define XSPI_CR_LOOP 0x01
ae918c02 AK	33	#define XSPI_CR_ENABLE 0x02
	34	#define XSPI_CR_MASTER_MODE 0x04
	35	#define XSPI_CR_CPOL 0x08
	36	#define XSPI_CR_CPHA 0x10
bca690db	37	#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA \| XSPI_CR_CPOL \| \
0240f945	38	XSPI_CR_LSB_FIRST \| XSPI_CR_LOOP)
ae918c02 AK	39	#define XSPI_CR_TXFIFO_RESET 0x20
	40	#define XSPI_CR_RXFIFO_RESET 0x40
	41	#define XSPI_CR_MANUAL_SSELECT 0x80
	42	#define XSPI_CR_TRANS_INHIBIT 0x100
c9da2e12	43	#define XSPI_CR_LSB_FIRST 0x200
ae918c02	44
c9da2e12	45	#define XSPI_SR_OFFSET 0x64 /* Status Register */
ae918c02 AK	46
	47	#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
	48	#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
	49	#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
	50	#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
	51	#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
	52
c9da2e12 RR	53	#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
c9da2e12 RR	54	#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
ae918c02 AK	55
	56	#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
	57
	58	/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
	59	* IPIF registers are 32 bit
	60	*/
	61	#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
	62	#define XIPIF_V123B_GINTR_ENABLE 0x80000000
	63
	64	#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
	65	#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
	66
	67	#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
	68	#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
	69	* disabled */
	70	#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
	71	#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
	72	#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
	73	#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
c9da2e12	74	#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
ae918c02 AK	75
	76	#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
	77	#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
	78
	79	struct xilinx_spi {
	80	/* bitbang has to be first */
	81	struct spi_bitbang bitbang;
	82	struct completion done;
ae918c02 AK	83	void __iomem regs; / virt. address of the control registers */
ae918c02 AK	84
9ca1273b	85	int irq;
709b785a	86	bool force_irq; /* force irq to setup host inhibit */
ae918c02 AK	87	u8 rx_ptr; / pointer in the Tx buffer */
ae918c02 AK	88	const u8 tx_ptr; / pointer in the Rx buffer */
17aaaa80	89	u8 bytes_per_word;
4c9a7614	90	int buffer_size; /* buffer size in words */
f9c6ef6c	91	u32 cs_inactive; /* Level of the CS pins when inactive*/
6ff8672a JH	92	unsigned int (read_fn)(void __iomem );
6ff8672a JH	93	void (write_fn)(u32, void __iomem );
ae918c02 AK	94	};
ae918c02 AK	95
0635287a MB	96	static void xspi_write32(u32 val, void __iomem *addr)
	97	{
	98	iowrite32(val, addr);
	99	}
	100
	101	static unsigned int xspi_read32(void __iomem *addr)
	102	{
	103	return ioread32(addr);
	104	}
	105
	106	static void xspi_write32_be(u32 val, void __iomem *addr)
	107	{
	108	iowrite32be(val, addr);
	109	}
	110
	111	static unsigned int xspi_read32_be(void __iomem *addr)
	112	{
	113	return ioread32be(addr);
	114	}
	115
24ba5e59	116	static void xilinx_spi_tx(struct xilinx_spi *xspi)
c9da2e12	117	{
34093cb9 RRD	118	u32 data = 0;
34093cb9 RRD	119
c3092941 RRD	120	if (!xspi->tx_ptr) {
	121	xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
	122	return;
	123	}
34093cb9 RRD	124
	125	switch (xspi->bytes_per_word) {
	126	case 1:
	127	data = (u8 )(xspi->tx_ptr);
	128	break;
	129	case 2:
	130	data = (u16 )(xspi->tx_ptr);
	131	break;
	132	case 4:
	133	data = (u32 )(xspi->tx_ptr);
	134	break;
	135	}
	136
	137	xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
17aaaa80	138	xspi->tx_ptr += xspi->bytes_per_word;
c9da2e12 RR	139	}
c9da2e12 RR	140
24ba5e59	141	static void xilinx_spi_rx(struct xilinx_spi *xspi)
c9da2e12 RR	142	{
c9da2e12 RR	143	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
c9da2e12	144
24ba5e59 RRD	145	if (!xspi->rx_ptr)
24ba5e59 RRD	146	return;
c9da2e12	147
17aaaa80 RRD	148	switch (xspi->bytes_per_word) {
17aaaa80 RRD	149	case 1:
24ba5e59 RRD	150	(u8 )(xspi->rx_ptr) = data;
24ba5e59 RRD	151	break;
17aaaa80	152	case 2:
24ba5e59 RRD	153	(u16 )(xspi->rx_ptr) = data;
24ba5e59 RRD	154	break;
17aaaa80	155	case 4:
c9da2e12	156	(u32 )(xspi->rx_ptr) = data;
24ba5e59	157	break;
c9da2e12	158	}
24ba5e59	159
17aaaa80	160	xspi->rx_ptr += xspi->bytes_per_word;
c9da2e12 RR	161	}
c9da2e12 RR	162
86fc5935	163	static void xspi_init_hw(struct xilinx_spi *xspi)
ae918c02	164	{
86fc5935 RR	165	void __iomem *regs_base = xspi->regs;
86fc5935 RR	166
ae918c02	167	/* Reset the SPI device */
86fc5935 RR	168	xspi->write_fn(XIPIF_V123B_RESET_MASK,
86fc5935 RR	169	regs_base + XIPIF_V123B_RESETR_OFFSET);
899929ba RRD	170	/* Enable the transmit empty interrupt, which we use to determine
	171	* progress on the transmission.
	172	*/
	173	xspi->write_fn(XSPI_INTR_TX_EMPTY,
	174	regs_base + XIPIF_V123B_IIER_OFFSET);
22417352 RRD	175	/* Disable the global IPIF interrupt */
22417352 RRD	176	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
709b785a	177	/* Deselect the Target on the SPI bus */
86fc5935	178	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
709b785a YY	179	/* Disable the transmitter, enable Manual Target Select Assertion,
709b785a YY	180	* put SPI controller into host mode, and enable it */
22417352 RRD	181	xspi->write_fn(XSPI_CR_MANUAL_SSELECT \| XSPI_CR_MASTER_MODE \|
	182	XSPI_CR_ENABLE \| XSPI_CR_TXFIFO_RESET \| XSPI_CR_RXFIFO_RESET,
	183	regs_base + XSPI_CR_OFFSET);
ae918c02 AK	184	}
	185
	186	static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
	187	{
709b785a	188	struct xilinx_spi *xspi = spi_controller_get_devdata(spi->controller);
f9c6ef6c RRD	189	u16 cr;
f9c6ef6c RRD	190	u32 cs;
ae918c02 AK	191
ae918c02 AK	192	if (is_on == BITBANG_CS_INACTIVE) {
709b785a	193	/* Deselect the target on the SPI bus */
f9c6ef6c RRD	194	xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
f9c6ef6c RRD	195	return;
ae918c02	196	}
f9c6ef6c RRD	197
	198	/* Set the SPI clock phase and polarity */
	199	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
	200	if (spi->mode & SPI_CPHA)
	201	cr \|= XSPI_CR_CPHA;
	202	if (spi->mode & SPI_CPOL)
	203	cr \|= XSPI_CR_CPOL;
	204	if (spi->mode & SPI_LSB_FIRST)
	205	cr \|= XSPI_CR_LSB_FIRST;
	206	if (spi->mode & SPI_LOOP)
	207	cr \|= XSPI_CR_LOOP;
	208	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
	209
	210	/* We do not check spi->max_speed_hz here as the SPI clock
	211	* frequency is not software programmable (the IP block design
	212	* parameter)
	213	*/
	214
	215	cs = xspi->cs_inactive;
9e264f3f	216	cs ^= BIT(spi_get_chipselect(spi, 0));
f9c6ef6c RRD	217
	218	/* Activate the chip select */
	219	xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	220	}
	221
	222	/* spi_bitbang requires custom setup_transfer() to be defined if there is a
9bf46f6d	223	* custom txrx_bufs().
ae918c02 AK	224	*/
	225	static int xilinx_spi_setup_transfer(struct spi_device *spi,
	226	struct spi_transfer *t)
	227	{
709b785a	228	struct xilinx_spi *xspi = spi_controller_get_devdata(spi->controller);
f9c6ef6c RRD	229
f9c6ef6c RRD	230	if (spi->mode & SPI_CS_HIGH)
9e264f3f	231	xspi->cs_inactive &= ~BIT(spi_get_chipselect(spi, 0));
f9c6ef6c	232	else
9e264f3f	233	xspi->cs_inactive \|= BIT(spi_get_chipselect(spi, 0));
f9c6ef6c	234
ae918c02 AK	235	return 0;
	236	}
	237
ae918c02 AK	238	static int xilinx_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
ae918c02 AK	239	{
709b785a	240	struct xilinx_spi *xspi = spi_controller_get_devdata(spi->controller);
b563bfb8	241	int remaining_words; /* the number of words left to transfer */
22417352 RRD	242	bool use_irq = false;
22417352 RRD	243	u16 cr = 0;
ae918c02 AK	244
	245	/* We get here with transmitter inhibited */
	246
	247	xspi->tx_ptr = t->tx_buf;
	248	xspi->rx_ptr = t->rx_buf;
b563bfb8	249	remaining_words = t->len / xspi->bytes_per_word;
ae918c02	250
1dd46599 VF	251	if (xspi->irq >= 0 &&
1dd46599 VF	252	(xspi->force_irq \|\| remaining_words > xspi->buffer_size)) {
74346841	253	u32 isr;
22417352	254	use_irq = true;
22417352 RRD	255	/* Inhibit irq to avoid spurious irqs on tx_empty*/
	256	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	257	xspi->write_fn(cr \| XSPI_CR_TRANS_INHIBIT,
	258	xspi->regs + XSPI_CR_OFFSET);
74346841 RRD	259	/* ACK old irqs (if any) */
	260	isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	261	if (isr)
	262	xspi->write_fn(isr,
	263	xspi->regs + XIPIF_V123B_IISR_OFFSET);
	264	/* Enable the global IPIF interrupt */
	265	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
	266	xspi->regs + XIPIF_V123B_DGIER_OFFSET);
	267	reinit_completion(&xspi->done);
22417352 RRD	268	}
22417352 RRD	269
b563bfb8	270	while (remaining_words) {
b563bfb8	271	int n_words, tx_words, rx_words;
eca37c7c	272	u32 sr;
5a1314fa	273	int stalled;
68c315bb	274
b563bfb8	275	n_words = min(remaining_words, xspi->buffer_size);
4c9a7614	276
b563bfb8 RRD	277	tx_words = n_words;
	278	while (tx_words--)
	279	xilinx_spi_tx(xspi);
68c315bb PC	280
	281	/* Start the transfer by not inhibiting the transmitter any
	282	* longer
	283	*/
68c315bb	284
22417352	285	if (use_irq) {
d9f58812	286	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
5fe11cc0	287	wait_for_completion(&xspi->done);
eca37c7c RRD	288	/* A transmit has just completed. Process received data
	289	* and check for more data to transmit. Always inhibit
	290	* the transmitter while the Isr refills the transmit
	291	* register/FIFO, or make sure it is stopped if we're
	292	* done.
	293	*/
d9f58812	294	xspi->write_fn(cr \| XSPI_CR_TRANS_INHIBIT,
eca37c7c RRD	295	xspi->regs + XSPI_CR_OFFSET);
	296	sr = XSPI_SR_TX_EMPTY_MASK;
	297	} else
	298	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
68c315bb PC	299
68c315bb PC	300	/* Read out all the data from the Rx FIFO */
b563bfb8	301	rx_words = n_words;
5a1314fa	302	stalled = 10;
eca37c7c	303	while (rx_words) {
5a1314fa RR	304	if (rx_words == n_words && !(stalled--) &&
	305	!(sr & XSPI_SR_TX_EMPTY_MASK) &&
	306	(sr & XSPI_SR_RX_EMPTY_MASK)) {
	307	dev_err(&spi->dev,
	308	"Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
	309	xspi_init_hw(xspi);
	310	return -EIO;
	311	}
	312
eca37c7c RRD	313	if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
	314	xilinx_spi_rx(xspi);
	315	rx_words--;
	316	continue;
	317	}
	318
	319	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	320	if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
	321	xilinx_spi_rx(xspi);
	322	rx_words--;
	323	}
	324	}
b563bfb8 RRD	325
b563bfb8 RRD	326	remaining_words -= n_words;
68c315bb	327	}
ae918c02	328
16ea9b8a	329	if (use_irq) {
22417352	330	xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
16ea9b8a RRD	331	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
16ea9b8a RRD	332	}
22417352	333
d79b2d07	334	return t->len;
ae918c02 AK	335	}
	336
	337
709b785a	338	/* This driver supports single host mode only. Hence Tx FIFO Empty
ae918c02	339	* is the only interrupt we care about.
709b785a	340	* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Target Mode
ae918c02 AK	341	* Fault are not to happen.
	342	*/
	343	static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
	344	{
	345	struct xilinx_spi *xspi = dev_id;
	346	u32 ipif_isr;
	347
	348	/* Get the IPIF interrupts, and clear them immediately */
86fc5935 RR	349	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
86fc5935 RR	350	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
ae918c02 AK	351
ae918c02 AK	352	if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
68c315bb	353	complete(&xspi->done);
d3364847	354	return IRQ_HANDLED;
ae918c02 AK	355	}
ae918c02 AK	356
d3364847	357	return IRQ_NONE;
ae918c02 AK	358	}
ae918c02 AK	359
4c9a7614 RRD	360	static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
	361	{
	362	u8 sr;
	363	int n_words = 0;
	364
	365	/*
	366	* Before the buffer_size detection we reset the core
	367	* to make sure we start with a clean state.
	368	*/
	369	xspi->write_fn(XIPIF_V123B_RESET_MASK,
	370	xspi->regs + XIPIF_V123B_RESETR_OFFSET);
	371
	372	/* Fill the Tx FIFO with as many words as possible */
	373	do {
	374	xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
	375	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	376	n_words++;
	377	} while (!(sr & XSPI_SR_TX_FULL_MASK));
	378
	379	return n_words;
	380	}
	381
eae6cb31	382	static const struct of_device_id xilinx_spi_of_match[] = {
a094c2fa	383	{ .compatible = "xlnx,axi-quad-spi-1.00.a", },
eae6cb31 GL	384	{ .compatible = "xlnx,xps-spi-2.00.a", },
	385	{ .compatible = "xlnx,xps-spi-2.00.b", },
	386	{}
	387	};
	388	MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
eae6cb31	389
7cb2abd0	390	static int xilinx_spi_probe(struct platform_device *pdev)
ae918c02	391	{
ae918c02	392	struct xilinx_spi *xspi;
d81c0bbb	393	struct xspi_platform_data *pdata;
ad3fdbca	394	struct resource *res;
e58f7d15	395	int ret, num_cs = 0, bits_per_word;
709b785a	396	struct spi_controller *host;
1dd46599	397	bool force_irq = false;
082339bc	398	u32 tmp;
d81c0bbb MB	399	u8 i;
d81c0bbb MB	400
8074cf06	401	pdata = dev_get_platdata(&pdev->dev);
d81c0bbb MB	402	if (pdata) {
	403	num_cs = pdata->num_chipselect;
	404	bits_per_word = pdata->bits_per_word;
1dd46599	405	force_irq = pdata->force_irq;
be3acdff MS	406	} else {
	407	of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
	408	&num_cs);
e58f7d15 AGM	409	ret = of_property_read_u32(pdev->dev.of_node,
	410	"xlnx,num-transfer-bits",
	411	&bits_per_word);
	412	if (ret)
	413	bits_per_word = 8;
d81c0bbb	414	}
ae918c02	415
d81c0bbb	416	if (!num_cs) {
7cb2abd0	417	dev_err(&pdev->dev,
709b785a	418	"Missing target select configuration data\n");
d81c0bbb MB	419	return -EINVAL;
	420	}
	421
eb25f16c	422	if (num_cs > XILINX_SPI_MAX_CS) {
709b785a	423	dev_err(&pdev->dev, "Invalid number of spi targets\n");
eb25f16c RR	424	return -EINVAL;
	425	}
	426
709b785a YY	427	host = devm_spi_alloc_host(&pdev->dev, sizeof(struct xilinx_spi));
709b785a YY	428	if (!host)
d81c0bbb	429	return -ENODEV;
ae918c02	430
e7db06b5	431	/* the spi->mode bits understood by this driver: */
709b785a YY	432	host->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LSB_FIRST \| SPI_LOOP \|
709b785a YY	433	SPI_CS_HIGH;
e7db06b5	434
709b785a	435	xspi = spi_controller_get_devdata(host);
f9c6ef6c	436	xspi->cs_inactive = 0xffffffff;
22592331	437	xspi->bitbang.ctlr = host;
ae918c02 AK	438	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	439	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	440	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
ae918c02 AK	441	init_completion(&xspi->done);
ae918c02 AK	442
0623ec17	443	xspi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2d064581 YY	444	if (IS_ERR(xspi->regs))
2d064581 YY	445	return PTR_ERR(xspi->regs);
ae918c02	446
709b785a YY	447	host->bus_num = pdev->id;
	448	host->num_chipselect = num_cs;
	449	host->dev.of_node = pdev->dev.of_node;
082339bc MS	450
	451	/*
	452	* Detect endianess on the IP via loop bit in CR. Detection
	453	* must be done before reset is sent because incorrect reset
	454	* value generates error interrupt.
	455	* Setup little endian helper functions first and try to use them
	456	* and check if bit was correctly setup or not.
	457	*/
0635287a MB	458	xspi->read_fn = xspi_read32;
0635287a MB	459	xspi->write_fn = xspi_write32;
082339bc MS	460
	461	xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
	462	tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	463	tmp &= XSPI_CR_LOOP;
	464	if (tmp != XSPI_CR_LOOP) {
0635287a MB	465	xspi->read_fn = xspi_read32_be;
0635287a MB	466	xspi->write_fn = xspi_write32_be;
86fc5935	467	}
082339bc	468
709b785a	469	host->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
17aaaa80	470	xspi->bytes_per_word = bits_per_word / 8;
4c9a7614 RRD	471	xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
4c9a7614 RRD	472
7b3b7432	473	xspi->irq = platform_get_irq(pdev, 0);
4db9bf54	474	if (xspi->irq < 0 && xspi->irq != -ENXIO) {
2d064581	475	return xspi->irq;
4db9bf54	476	} else if (xspi->irq >= 0) {
5fe11cc0 RRD	477	/* Register for SPI Interrupt */
	478	ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
	479	dev_name(&pdev->dev), xspi);
	480	if (ret)
2d064581	481	return ret;
1dd46599 VF	482
1dd46599 VF	483	xspi->force_irq = force_irq;
7b3b7432 MS	484	}
7b3b7432 MS	485
5fe11cc0 RRD	486	/* SPI controller initializations */
5fe11cc0 RRD	487	xspi_init_hw(xspi);
ae918c02	488
d5af91a1 RR	489	ret = spi_bitbang_start(&xspi->bitbang);
d5af91a1 RR	490	if (ret) {
7cb2abd0	491	dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
2d064581	492	return ret;
eae6cb31 GL	493	}
eae6cb31 GL	494
985be7eb	495	dev_info(&pdev->dev, "at %pR, irq=%d\n", res, xspi->irq);
8fd8821b	496
eae6cb31 GL	497	if (pdata) {
eae6cb31 GL	498	for (i = 0; i < pdata->num_devices; i++)
709b785a	499	spi_new_device(host, pdata->devices + i);
eae6cb31	500	}
8fd8821b	501
709b785a	502	platform_set_drvdata(pdev, host);
8fd8821b GL	503	return 0;
	504	}
	505
3b1d7e11	506	static void xilinx_spi_remove(struct platform_device *pdev)
8fd8821b	507	{
709b785a YY	508	struct spi_controller *host = platform_get_drvdata(pdev);
709b785a YY	509	struct xilinx_spi *xspi = spi_controller_get_devdata(host);
7b3b7432	510	void __iomem *regs_base = xspi->regs;
ae918c02 AK	511
ae918c02 AK	512	spi_bitbang_stop(&xspi->bitbang);
7b3b7432 MS	513
	514	/* Disable all the interrupts just in case */
	515	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	516	/* Disable the global IPIF interrupt */
	517	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
ff82c587	518
22592331	519	spi_controller_put(xspi->bitbang.ctlr);
8fd8821b GL	520	}
	521
	522	/* work with hotplug and coldplug */
	523	MODULE_ALIAS("platform:" XILINX_SPI_NAME);
	524
	525	static struct platform_driver xilinx_spi_driver = {
	526	.probe = xilinx_spi_probe,
3b1d7e11	527	.remove_new = xilinx_spi_remove,
8fd8821b GL	528	.driver = {
8fd8821b GL	529	.name = XILINX_SPI_NAME,
eae6cb31	530	.of_match_table = xilinx_spi_of_match,
8fd8821b GL	531	},
8fd8821b GL	532	};
940ab889	533	module_platform_driver(xilinx_spi_driver);
8fd8821b	534
ae918c02 AK	535	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	536	MODULE_DESCRIPTION("Xilinx SPI driver");
	537	MODULE_LICENSE("GPL");