[linux-block.git] / drivers / spi / spi-uniphier.c

// SPDX-License-Identifier: GPL-2.0
// spi-uniphier.c - Socionext UniPhier SPI controller driver
// Copyright 2012      Panasonic Corporation
// Copyright 2016-2018 Socionext Inc.

#include <linux/kernel.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>

#include <asm/unaligned.h>

#define SSI_TIMEOUT_MS		2000
#define SSI_POLL_TIMEOUT_US	200
#define SSI_MAX_CLK_DIVIDER	254
#define SSI_MIN_CLK_DIVIDER	4

struct uniphier_spi_priv {
	void __iomem *base;
	struct clk *clk;
	struct spi_master *master;
	struct completion xfer_done;

	int error;
	unsigned int tx_bytes;
	unsigned int rx_bytes;
	const u8 *tx_buf;
	u8 *rx_buf;

	bool is_save_param;
	u8 bits_per_word;
	u16 mode;
	u32 speed_hz;
};

#define SSI_CTL			0x00
#define   SSI_CTL_EN		BIT(0)

#define SSI_CKS			0x04
#define   SSI_CKS_CKRAT_MASK	GENMASK(7, 0)
#define   SSI_CKS_CKPHS		BIT(14)
#define   SSI_CKS_CKINIT	BIT(13)
#define   SSI_CKS_CKDLY		BIT(12)

#define SSI_TXWDS		0x08
#define   SSI_TXWDS_WDLEN_MASK	GENMASK(13, 8)
#define   SSI_TXWDS_TDTF_MASK	GENMASK(7, 6)
#define   SSI_TXWDS_DTLEN_MASK	GENMASK(5, 0)

#define SSI_RXWDS		0x0c
#define   SSI_RXWDS_DTLEN_MASK	GENMASK(5, 0)

#define SSI_FPS			0x10
#define   SSI_FPS_FSPOL		BIT(15)
#define   SSI_FPS_FSTRT		BIT(14)

#define SSI_SR			0x14
#define   SSI_SR_RNE		BIT(0)

#define SSI_IE			0x18
#define   SSI_IE_RCIE		BIT(3)
#define   SSI_IE_RORIE		BIT(0)

#define SSI_IS			0x1c
#define   SSI_IS_RXRS		BIT(9)
#define   SSI_IS_RCID		BIT(3)
#define   SSI_IS_RORID		BIT(0)

#define SSI_IC			0x1c
#define   SSI_IC_TCIC		BIT(4)
#define   SSI_IC_RCIC		BIT(3)
#define   SSI_IC_RORIC		BIT(0)

#define SSI_FC			0x20
#define   SSI_FC_TXFFL		BIT(12)
#define   SSI_FC_TXFTH_MASK	GENMASK(11, 8)
#define   SSI_FC_RXFFL		BIT(4)
#define   SSI_FC_RXFTH_MASK	GENMASK(3, 0)

#define SSI_TXDR		0x24
#define SSI_RXDR		0x24

#define SSI_FIFO_DEPTH		8U

static inline unsigned int bytes_per_word(unsigned int bits)
{
	return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
}

static inline void uniphier_spi_irq_enable(struct uniphier_spi_priv *priv,
					   u32 mask)
{
	u32 val;

	val = readl(priv->base + SSI_IE);
	val |= mask;
	writel(val, priv->base + SSI_IE);
}

static inline void uniphier_spi_irq_disable(struct uniphier_spi_priv *priv,
					    u32 mask)
{
	u32 val;

	val = readl(priv->base + SSI_IE);
	val &= ~mask;
	writel(val, priv->base + SSI_IE);
}

static void uniphier_spi_set_mode(struct spi_device *spi)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	u32 val1, val2;

	/*
	 * clock setting
	 * CKPHS    capture timing. 0:rising edge, 1:falling edge
	 * CKINIT   clock initial level. 0:low, 1:high
	 * CKDLY    clock delay. 0:no delay, 1:delay depending on FSTRT
	 *          (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
	 *
	 * frame setting
	 * FSPOL    frame signal porarity. 0: low, 1: high
	 * FSTRT    start frame timing
	 *          0: rising edge of clock, 1: falling edge of clock
	 */
	switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
	case SPI_MODE_0:
		/* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
		val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
		val2 = 0;
		break;
	case SPI_MODE_1:
		/* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
		val1 = 0;
		val2 = SSI_FPS_FSTRT;
		break;
	case SPI_MODE_2:
		/* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
		val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
		val2 = SSI_FPS_FSTRT;
		break;
	case SPI_MODE_3:
		/* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
		val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
		val2 = 0;
		break;
	}

	if (!(spi->mode & SPI_CS_HIGH))
		val2 |= SSI_FPS_FSPOL;

	writel(val1, priv->base + SSI_CKS);
	writel(val2, priv->base + SSI_FPS);

	val1 = 0;
	if (spi->mode & SPI_LSB_FIRST)
		val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
	writel(val1, priv->base + SSI_TXWDS);
	writel(val1, priv->base + SSI_RXWDS);
}

static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	u32 val;

	val = readl(priv->base + SSI_TXWDS);
	val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
	val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
	val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
	writel(val, priv->base + SSI_TXWDS);

	val = readl(priv->base + SSI_RXWDS);
	val &= ~SSI_RXWDS_DTLEN_MASK;
	val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
	writel(val, priv->base + SSI_RXWDS);
}

static void uniphier_spi_set_baudrate(struct spi_device *spi,
				      unsigned int speed)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	u32 val, ckdiv;

	/*
	 * the supported rates are even numbers from 4 to 254. (4,6,8...254)
	 * round up as we look for equal or less speed
	 */
	ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
	ckdiv = round_up(ckdiv, 2);

	val = readl(priv->base + SSI_CKS);
	val &= ~SSI_CKS_CKRAT_MASK;
	val |= ckdiv & SSI_CKS_CKRAT_MASK;
	writel(val, priv->base + SSI_CKS);
}

static void uniphier_spi_setup_transfer(struct spi_device *spi,
				       struct spi_transfer *t)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	u32 val;

	priv->error = 0;
	priv->tx_buf = t->tx_buf;
	priv->rx_buf = t->rx_buf;
	priv->tx_bytes = priv->rx_bytes = t->len;

	if (!priv->is_save_param || priv->mode != spi->mode) {
		uniphier_spi_set_mode(spi);
		priv->mode = spi->mode;
		priv->is_save_param = false;
	}

	if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
		uniphier_spi_set_transfer_size(spi, t->bits_per_word);
		priv->bits_per_word = t->bits_per_word;
	}

	if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
		uniphier_spi_set_baudrate(spi, t->speed_hz);
		priv->speed_hz = t->speed_hz;
	}

	priv->is_save_param = true;

	/* reset FIFOs */
	val = SSI_FC_TXFFL | SSI_FC_RXFFL;
	writel(val, priv->base + SSI_FC);
}

static void uniphier_spi_send(struct uniphier_spi_priv *priv)
{
	int wsize;
	u32 val = 0;

	wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
	priv->tx_bytes -= wsize;

	if (priv->tx_buf) {
		switch (wsize) {
		case 1:
			val = *priv->tx_buf;
			break;
		case 2:
			val = get_unaligned_le16(priv->tx_buf);
			break;
		case 4:
			val = get_unaligned_le32(priv->tx_buf);
			break;
		}

		priv->tx_buf += wsize;
	}

	writel(val, priv->base + SSI_TXDR);
}

static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
{
	int rsize;
	u32 val;

	rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
	priv->rx_bytes -= rsize;

	val = readl(priv->base + SSI_RXDR);

	if (priv->rx_buf) {
		switch (rsize) {
		case 1:
			*priv->rx_buf = val;
			break;
		case 2:
			put_unaligned_le16(val, priv->rx_buf);
			break;
		case 4:
			put_unaligned_le32(val, priv->rx_buf);
			break;
		}

		priv->rx_buf += rsize;
	}
}

static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,
					    unsigned int threshold)
{
	u32 val;

	val = readl(priv->base + SSI_FC);
	val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
	val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold);
	val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold);
	writel(val, priv->base + SSI_FC);
}

static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
{
	unsigned int fifo_threshold, fill_words;
	unsigned int bpw = bytes_per_word(priv->bits_per_word);

	fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw);
	fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);

	uniphier_spi_set_fifo_threshold(priv, fifo_threshold);

	fill_words = fifo_threshold -
		DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw);

	while (fill_words--)
		uniphier_spi_send(priv);
}

static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	u32 val;

	val = readl(priv->base + SSI_FPS);

	if (enable)
		val |= SSI_FPS_FSPOL;
	else
		val &= ~SSI_FPS_FSPOL;

	writel(val, priv->base + SSI_FPS);
}

static int uniphier_spi_transfer_one_irq(struct spi_master *master,
					 struct spi_device *spi,
					 struct spi_transfer *t)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	struct device *dev = master->dev.parent;
	unsigned long time_left;

	reinit_completion(&priv->xfer_done);

	uniphier_spi_fill_tx_fifo(priv);

	uniphier_spi_irq_enable(priv, SSI_IE_RCIE | SSI_IE_RORIE);

	time_left = wait_for_completion_timeout(&priv->xfer_done,
					msecs_to_jiffies(SSI_TIMEOUT_MS));

	uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE);

	if (!time_left) {
		dev_err(dev, "transfer timeout.\n");
		return -ETIMEDOUT;
	}

	return priv->error;
}

static int uniphier_spi_transfer_one_poll(struct spi_master *master,
					  struct spi_device *spi,
					  struct spi_transfer *t)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	int loop = SSI_POLL_TIMEOUT_US * 10;

	while (priv->tx_bytes) {
		uniphier_spi_fill_tx_fifo(priv);

		while ((priv->rx_bytes - priv->tx_bytes) > 0) {
			while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
								&& loop--)
				ndelay(100);

			if (loop == -1)
				goto irq_transfer;

			uniphier_spi_recv(priv);
		}
	}

	return 0;

irq_transfer:
	return uniphier_spi_transfer_one_irq(master, spi, t);
}

static int uniphier_spi_transfer_one(struct spi_master *master,
				     struct spi_device *spi,
				     struct spi_transfer *t)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	unsigned long threshold;

	/* Terminate and return success for 0 byte length transfer */
	if (!t->len)
		return 0;

	uniphier_spi_setup_transfer(spi, t);

	/*
	 * If the transfer operation will take longer than
	 * SSI_POLL_TIMEOUT_US, it should use irq.
	 */
	threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
					USEC_PER_SEC * BITS_PER_BYTE);
	if (t->len > threshold)
		return uniphier_spi_transfer_one_irq(master, spi, t);
	else
		return uniphier_spi_transfer_one_poll(master, spi, t);
}

static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);

	writel(SSI_CTL_EN, priv->base + SSI_CTL);

	return 0;
}

static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);

	writel(0, priv->base + SSI_CTL);

	return 0;
}

static void uniphier_spi_handle_err(struct spi_master *master,
				    struct spi_message *msg)
{
	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	u32 val;

	/* stop running spi transfer */
	writel(0, priv->base + SSI_CTL);

	/* reset FIFOs */
	val = SSI_FC_TXFFL | SSI_FC_RXFFL;
	writel(val, priv->base + SSI_FC);

	uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
}

static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
{
	struct uniphier_spi_priv *priv = dev_id;
	u32 val, stat;

	stat = readl(priv->base + SSI_IS);
	val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
	writel(val, priv->base + SSI_IC);

	/* rx fifo overrun */
	if (stat & SSI_IS_RORID) {
		priv->error = -EIO;
		goto done;
	}

	/* rx complete */
	if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
		while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
				(priv->rx_bytes - priv->tx_bytes) > 0)
			uniphier_spi_recv(priv);

		if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
				(priv->rx_bytes != priv->tx_bytes)) {
			priv->error = -EIO;
			goto done;
		} else if (priv->rx_bytes == 0)
			goto done;

		/* next tx transfer */
		uniphier_spi_fill_tx_fifo(priv);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;

done:
	complete(&priv->xfer_done);
	return IRQ_HANDLED;
}

static int uniphier_spi_probe(struct platform_device *pdev)
{
	struct uniphier_spi_priv *priv;
	struct spi_master *master;
	unsigned long clk_rate;
	int irq;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);

	priv = spi_master_get_devdata(master);
	priv->master = master;
	priv->is_save_param = false;

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->base)) {
		ret = PTR_ERR(priv->base);
		goto out_master_put;
	}

	priv->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		ret = PTR_ERR(priv->clk);
		goto out_master_put;
	}

	ret = clk_prepare_enable(priv->clk);
	if (ret)
		goto out_master_put;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = irq;
		goto out_disable_clk;
	}

	ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
			       0, "uniphier-spi", priv);
	if (ret) {
		dev_err(&pdev->dev, "failed to request IRQ\n");
		goto out_disable_clk;
	}

	init_completion(&priv->xfer_done);

	clk_rate = clk_get_rate(priv->clk);

	master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
	master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
	master->dev.of_node = pdev->dev.of_node;
	master->bus_num = pdev->id;
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);

	master->set_cs = uniphier_spi_set_cs;
	master->transfer_one = uniphier_spi_transfer_one;
	master->prepare_transfer_hardware
				= uniphier_spi_prepare_transfer_hardware;
	master->unprepare_transfer_hardware
				= uniphier_spi_unprepare_transfer_hardware;
	master->handle_err = uniphier_spi_handle_err;
	master->num_chipselect = 1;

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret)
		goto out_disable_clk;

	return 0;

out_disable_clk:
	clk_disable_unprepare(priv->clk);

out_master_put:
	spi_master_put(master);
	return ret;
}

static int uniphier_spi_remove(struct platform_device *pdev)
{
	struct uniphier_spi_priv *priv = platform_get_drvdata(pdev);

	clk_disable_unprepare(priv->clk);

	return 0;
}

static const struct of_device_id uniphier_spi_match[] = {
	{ .compatible = "socionext,uniphier-scssi" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_spi_match);

static struct platform_driver uniphier_spi_driver = {
	.probe = uniphier_spi_probe,
	.remove = uniphier_spi_remove,
	.driver = {
		.name = "uniphier-spi",
		.of_match_table = uniphier_spi_match,
	},
};
module_platform_driver(uniphier_spi_driver);

MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
5ba155a4 KH	1	// SPDX-License-Identifier: GPL-2.0
	2	// spi-uniphier.c - Socionext UniPhier SPI controller driver
	3	// Copyright 2012 Panasonic Corporation
	4	// Copyright 2016-2018 Socionext Inc.
	5
	6	#include <linux/kernel.h>
	7	#include <linux/bitfield.h>
	8	#include <linux/bitops.h>
	9	#include <linux/clk.h>
37ffab81	10	#include <linux/delay.h>
5ba155a4 KH	11	#include <linux/interrupt.h>
	12	#include <linux/io.h>
	13	#include <linux/module.h>
5ba155a4 KH	14	#include <linux/platform_device.h>
	15	#include <linux/spi/spi.h>
	16
	17	#include <asm/unaligned.h>
	18
	19	#define SSI_TIMEOUT_MS 2000
37ffab81	20	#define SSI_POLL_TIMEOUT_US 200
5ba155a4 KH	21	#define SSI_MAX_CLK_DIVIDER 254
	22	#define SSI_MIN_CLK_DIVIDER 4
	23
	24	struct uniphier_spi_priv {
	25	void __iomem *base;
	26	struct clk *clk;
	27	struct spi_master *master;
	28	struct completion xfer_done;
	29
	30	int error;
	31	unsigned int tx_bytes;
	32	unsigned int rx_bytes;
	33	const u8 *tx_buf;
	34	u8 *rx_buf;
	35
	36	bool is_save_param;
	37	u8 bits_per_word;
	38	u16 mode;
	39	u32 speed_hz;
	40	};
	41
	42	#define SSI_CTL 0x00
	43	#define SSI_CTL_EN BIT(0)
	44
	45	#define SSI_CKS 0x04
	46	#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
	47	#define SSI_CKS_CKPHS BIT(14)
	48	#define SSI_CKS_CKINIT BIT(13)
	49	#define SSI_CKS_CKDLY BIT(12)
	50
	51	#define SSI_TXWDS 0x08
	52	#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
	53	#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
	54	#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
	55
	56	#define SSI_RXWDS 0x0c
	57	#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
	58
	59	#define SSI_FPS 0x10
	60	#define SSI_FPS_FSPOL BIT(15)
	61	#define SSI_FPS_FSTRT BIT(14)
	62
	63	#define SSI_SR 0x14
	64	#define SSI_SR_RNE BIT(0)
	65
	66	#define SSI_IE 0x18
	67	#define SSI_IE_RCIE BIT(3)
	68	#define SSI_IE_RORIE BIT(0)
	69
	70	#define SSI_IS 0x1c
	71	#define SSI_IS_RXRS BIT(9)
	72	#define SSI_IS_RCID BIT(3)
	73	#define SSI_IS_RORID BIT(0)
	74
	75	#define SSI_IC 0x1c
	76	#define SSI_IC_TCIC BIT(4)
	77	#define SSI_IC_RCIC BIT(3)
	78	#define SSI_IC_RORIC BIT(0)
	79
	80	#define SSI_FC 0x20
	81	#define SSI_FC_TXFFL BIT(12)
	82	#define SSI_FC_TXFTH_MASK GENMASK(11, 8)
	83	#define SSI_FC_RXFFL BIT(4)
	84	#define SSI_FC_RXFTH_MASK GENMASK(3, 0)
85
86	#define SSI_TXDR 0x24
87	#define SSI_RXDR 0x24
88
89	#define SSI_FIFO_DEPTH 8U
90
91	static inline unsigned int bytes_per_word(unsigned int bits)
92	{
93	return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
94	}
95
9859db51 KH	96	static inline void uniphier_spi_irq_enable(struct uniphier_spi_priv *priv,
9859db51 KH	97	u32 mask)
5ba155a4	98	{
5ba155a4 KH	99	u32 val;
	100
	101	val = readl(priv->base + SSI_IE);
	102	val \|= mask;
	103	writel(val, priv->base + SSI_IE);
	104	}
	105
9859db51 KH	106	static inline void uniphier_spi_irq_disable(struct uniphier_spi_priv *priv,
9859db51 KH	107	u32 mask)
5ba155a4	108	{
5ba155a4 KH	109	u32 val;
	110
	111	val = readl(priv->base + SSI_IE);
	112	val &= ~mask;
	113	writel(val, priv->base + SSI_IE);
	114	}
	115
	116	static void uniphier_spi_set_mode(struct spi_device *spi)
	117	{
	118	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	119	u32 val1, val2;
	120
	121	/*
	122	* clock setting
	123	* CKPHS capture timing. 0:rising edge, 1:falling edge
	124	* CKINIT clock initial level. 0:low, 1:high
	125	* CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
	126	* (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
	127	*
	128	* frame setting
	129	* FSPOL frame signal porarity. 0: low, 1: high
	130	* FSTRT start frame timing
	131	* 0: rising edge of clock, 1: falling edge of clock
	132	*/
	133	switch (spi->mode & (SPI_CPOL \| SPI_CPHA)) {
	134	case SPI_MODE_0:
	135	/* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
	136	val1 = SSI_CKS_CKPHS \| SSI_CKS_CKDLY;
	137	val2 = 0;
	138	break;
	139	case SPI_MODE_1:
	140	/* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
	141	val1 = 0;
	142	val2 = SSI_FPS_FSTRT;
	143	break;
	144	case SPI_MODE_2:
	145	/* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
	146	val1 = SSI_CKS_CKINIT \| SSI_CKS_CKDLY;
	147	val2 = SSI_FPS_FSTRT;
	148	break;
	149	case SPI_MODE_3:
	150	/* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
	151	val1 = SSI_CKS_CKPHS \| SSI_CKS_CKINIT;
	152	val2 = 0;
	153	break;
	154	}
	155
	156	if (!(spi->mode & SPI_CS_HIGH))
	157	val2 \|= SSI_FPS_FSPOL;
	158
	159	writel(val1, priv->base + SSI_CKS);
	160	writel(val2, priv->base + SSI_FPS);
	161
	162	val1 = 0;
	163	if (spi->mode & SPI_LSB_FIRST)
	164	val1 \|= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
	165	writel(val1, priv->base + SSI_TXWDS);
	166	writel(val1, priv->base + SSI_RXWDS);
	167	}
	168
	169	static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
	170	{
	171	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	172	u32 val;
173
174	val = readl(priv->base + SSI_TXWDS);
175	val &= ~(SSI_TXWDS_WDLEN_MASK \| SSI_TXWDS_DTLEN_MASK);
176	val \|= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
177	val \|= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
178	writel(val, priv->base + SSI_TXWDS);
179
180	val = readl(priv->base + SSI_RXWDS);
181	val &= ~SSI_RXWDS_DTLEN_MASK;
182	val \|= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
183	writel(val, priv->base + SSI_RXWDS);
184	}
185
186	static void uniphier_spi_set_baudrate(struct spi_device *spi,
187	unsigned int speed)
188	{
189	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
190	u32 val, ckdiv;
191
192	/*
193	* the supported rates are even numbers from 4 to 254. (4,6,8...254)
194	* round up as we look for equal or less speed
195	*/
196	ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
197	ckdiv = round_up(ckdiv, 2);
198
199	val = readl(priv->base + SSI_CKS);
200	val &= ~SSI_CKS_CKRAT_MASK;
201	val \|= ckdiv & SSI_CKS_CKRAT_MASK;
202	writel(val, priv->base + SSI_CKS);
203	}
204
205	static void uniphier_spi_setup_transfer(struct spi_device *spi,
206	struct spi_transfer *t)
207	{
208	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
209	u32 val;
210
211	priv->error = 0;
212	priv->tx_buf = t->tx_buf;
213	priv->rx_buf = t->rx_buf;
214	priv->tx_bytes = priv->rx_bytes = t->len;
215
216	if (!priv->is_save_param \|\| priv->mode != spi->mode) {
217	uniphier_spi_set_mode(spi);
218	priv->mode = spi->mode;
3c633f9d	219	priv->is_save_param = false;
5ba155a4 KH	220	}
	221
	222	if (!priv->is_save_param \|\| priv->bits_per_word != t->bits_per_word) {
	223	uniphier_spi_set_transfer_size(spi, t->bits_per_word);
	224	priv->bits_per_word = t->bits_per_word;
	225	}
	226
	227	if (!priv->is_save_param \|\| priv->speed_hz != t->speed_hz) {
	228	uniphier_spi_set_baudrate(spi, t->speed_hz);
	229	priv->speed_hz = t->speed_hz;
	230	}
	231
151d0eaf	232	priv->is_save_param = true;
5ba155a4 KH	233
	234	/* reset FIFOs */
	235	val = SSI_FC_TXFFL \| SSI_FC_RXFFL;
	236	writel(val, priv->base + SSI_FC);
	237	}
	238
	239	static void uniphier_spi_send(struct uniphier_spi_priv *priv)
	240	{
	241	int wsize;
	242	u32 val = 0;
	243
	244	wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
	245	priv->tx_bytes -= wsize;
	246
	247	if (priv->tx_buf) {
	248	switch (wsize) {
	249	case 1:
	250	val = *priv->tx_buf;
	251	break;
	252	case 2:
	253	val = get_unaligned_le16(priv->tx_buf);
	254	break;
	255	case 4:
	256	val = get_unaligned_le32(priv->tx_buf);
	257	break;
	258	}
	259
	260	priv->tx_buf += wsize;
	261	}
	262
	263	writel(val, priv->base + SSI_TXDR);
	264	}
	265
	266	static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
	267	{
	268	int rsize;
	269	u32 val;
	270
	271	rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
	272	priv->rx_bytes -= rsize;
	273
	274	val = readl(priv->base + SSI_RXDR);
	275
	276	if (priv->rx_buf) {
	277	switch (rsize) {
	278	case 1:
	279	*priv->rx_buf = val;
	280	break;
	281	case 2:
	282	put_unaligned_le16(val, priv->rx_buf);
	283	break;
	284	case 4:
	285	put_unaligned_le32(val, priv->rx_buf);
	286	break;
	287	}
	288
	289	priv->rx_buf += rsize;
	290	}
	291	}
	292
9cd34efb KH	293	static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,
9cd34efb KH	294	unsigned int threshold)
5ba155a4	295	{
5ba155a4 KH	296	u32 val;
5ba155a4 KH	297
5ba155a4 KH	298	val = readl(priv->base + SSI_FC);
5ba155a4 KH	299	val &= ~(SSI_FC_TXFTH_MASK \| SSI_FC_RXFTH_MASK);
9cd34efb KH	300	val \|= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold);
9cd34efb KH	301	val \|= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold);
5ba155a4	302	writel(val, priv->base + SSI_FC);
9cd34efb KH	303	}
	304
	305	static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
	306	{
	307	unsigned int fifo_threshold, fill_words;
	308	unsigned int bpw = bytes_per_word(priv->bits_per_word);
	309
	310	fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw);
	311	fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
	312
	313	uniphier_spi_set_fifo_threshold(priv, fifo_threshold);
	314
	315	fill_words = fifo_threshold -
	316	DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw);
5ba155a4	317
9cd34efb	318	while (fill_words--)
5ba155a4 KH	319	uniphier_spi_send(priv);
	320	}
	321
	322	static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
	323	{
	324	struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
	325	u32 val;
	326
	327	val = readl(priv->base + SSI_FPS);
	328
	329	if (enable)
	330	val \|= SSI_FPS_FSPOL;
	331	else
	332	val &= ~SSI_FPS_FSPOL;
	333
	334	writel(val, priv->base + SSI_FPS);
	335	}
	336
37ffab81 KH	337	static int uniphier_spi_transfer_one_irq(struct spi_master *master,
	338	struct spi_device *spi,
	339	struct spi_transfer *t)
5ba155a4 KH	340	{
5ba155a4 KH	341	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
e4671df0 KH	342	struct device *dev = master->dev.parent;
e4671df0 KH	343	unsigned long time_left;
5ba155a4	344
5ba155a4 KH	345	reinit_completion(&priv->xfer_done);
	346
	347	uniphier_spi_fill_tx_fifo(priv);
	348
9859db51	349	uniphier_spi_irq_enable(priv, SSI_IE_RCIE \| SSI_IE_RORIE);
5ba155a4	350
e4671df0 KH	351	time_left = wait_for_completion_timeout(&priv->xfer_done,
e4671df0 KH	352	msecs_to_jiffies(SSI_TIMEOUT_MS));
5ba155a4	353
9859db51	354	uniphier_spi_irq_disable(priv, SSI_IE_RCIE \| SSI_IE_RORIE);
5ba155a4	355
e4671df0 KH	356	if (!time_left) {
	357	dev_err(dev, "transfer timeout.\n");
	358	return -ETIMEDOUT;
	359	}
5ba155a4 KH	360
	361	return priv->error;
	362	}
	363
37ffab81 KH	364	static int uniphier_spi_transfer_one_poll(struct spi_master *master,
	365	struct spi_device *spi,
	366	struct spi_transfer *t)
	367	{
	368	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	369	int loop = SSI_POLL_TIMEOUT_US * 10;
	370
	371	while (priv->tx_bytes) {
	372	uniphier_spi_fill_tx_fifo(priv);
	373
	374	while ((priv->rx_bytes - priv->tx_bytes) > 0) {
	375	while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
	376	&& loop--)
	377	ndelay(100);
	378
	379	if (loop == -1)
	380	goto irq_transfer;
	381
	382	uniphier_spi_recv(priv);
	383	}
	384	}
	385
	386	return 0;
	387
	388	irq_transfer:
	389	return uniphier_spi_transfer_one_irq(master, spi, t);
	390	}
	391
	392	static int uniphier_spi_transfer_one(struct spi_master *master,
	393	struct spi_device *spi,
	394	struct spi_transfer *t)
	395	{
	396	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	397	unsigned long threshold;
	398
	399	/* Terminate and return success for 0 byte length transfer */
	400	if (!t->len)
	401	return 0;
	402
	403	uniphier_spi_setup_transfer(spi, t);
	404
	405	/*
	406	* If the transfer operation will take longer than
	407	* SSI_POLL_TIMEOUT_US, it should use irq.
	408	*/
	409	threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
	410	USEC_PER_SEC * BITS_PER_BYTE);
	411	if (t->len > threshold)
	412	return uniphier_spi_transfer_one_irq(master, spi, t);
	413	else
	414	return uniphier_spi_transfer_one_poll(master, spi, t);
	415	}
	416
5ba155a4 KH	417	static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
	418	{
	419	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	420
	421	writel(SSI_CTL_EN, priv->base + SSI_CTL);
	422
	423	return 0;
	424	}
	425
	426	static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
	427	{
	428	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	429
	430	writel(0, priv->base + SSI_CTL);
	431
	432	return 0;
	433	}
	434
11299c5c KH	435	static void uniphier_spi_handle_err(struct spi_master *master,
	436	struct spi_message *msg)
	437	{
	438	struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
	439	u32 val;
	440
	441	/* stop running spi transfer */
	442	writel(0, priv->base + SSI_CTL);
	443
	444	/* reset FIFOs */
	445	val = SSI_FC_TXFFL \| SSI_FC_RXFFL;
	446	writel(val, priv->base + SSI_FC);
	447
	448	uniphier_spi_irq_disable(priv, SSI_IE_RCIE \| SSI_IE_RORIE);
	449	}
	450
5ba155a4 KH	451	static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
	452	{
	453	struct uniphier_spi_priv *priv = dev_id;
	454	u32 val, stat;
	455
	456	stat = readl(priv->base + SSI_IS);
	457	val = SSI_IC_TCIC \| SSI_IC_RCIC \| SSI_IC_RORIC;
	458	writel(val, priv->base + SSI_IC);
	459
	460	/* rx fifo overrun */
	461	if (stat & SSI_IS_RORID) {
	462	priv->error = -EIO;
	463	goto done;
	464	}
	465
	466	/* rx complete */
	467	if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
	468	while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
	469	(priv->rx_bytes - priv->tx_bytes) > 0)
	470	uniphier_spi_recv(priv);
	471
	472	if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) \|\|
	473	(priv->rx_bytes != priv->tx_bytes)) {
	474	priv->error = -EIO;
	475	goto done;
	476	} else if (priv->rx_bytes == 0)
	477	goto done;
	478
	479	/* next tx transfer */
	480	uniphier_spi_fill_tx_fifo(priv);
	481
	482	return IRQ_HANDLED;
	483	}
	484
	485	return IRQ_NONE;
	486
	487	done:
	488	complete(&priv->xfer_done);
	489	return IRQ_HANDLED;
	490	}
	491
	492	static int uniphier_spi_probe(struct platform_device *pdev)
	493	{
	494	struct uniphier_spi_priv *priv;
	495	struct spi_master *master;
5ba155a4 KH	496	unsigned long clk_rate;
	497	int irq;
	498	int ret;
	499
	500	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
	501	if (!master)
	502	return -ENOMEM;
	503
	504	platform_set_drvdata(pdev, master);
	505
	506	priv = spi_master_get_devdata(master);
	507	priv->master = master;
	508	priv->is_save_param = false;
	509
755f1a25	510	priv->base = devm_platform_ioremap_resource(pdev, 0);
5ba155a4 KH	511	if (IS_ERR(priv->base)) {
	512	ret = PTR_ERR(priv->base);
	513	goto out_master_put;
	514	}
	515
	516	priv->clk = devm_clk_get(&pdev->dev, NULL);
	517	if (IS_ERR(priv->clk)) {
	518	dev_err(&pdev->dev, "failed to get clock\n");
	519	ret = PTR_ERR(priv->clk);
	520	goto out_master_put;
	521	}
	522
	523	ret = clk_prepare_enable(priv->clk);
	524	if (ret)
	525	goto out_master_put;
	526
	527	irq = platform_get_irq(pdev, 0);
	528	if (irq < 0) {
5ba155a4 KH	529	ret = irq;
	530	goto out_disable_clk;
	531	}
	532
	533	ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
	534	0, "uniphier-spi", priv);
	535	if (ret) {
	536	dev_err(&pdev->dev, "failed to request IRQ\n");
	537	goto out_disable_clk;
	538	}
	539
	540	init_completion(&priv->xfer_done);
	541
	542	clk_rate = clk_get_rate(priv->clk);
	543
	544	master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
	545	master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
	546	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LSB_FIRST;
	547	master->dev.of_node = pdev->dev.of_node;
	548	master->bus_num = pdev->id;
	549	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
	550
	551	master->set_cs = uniphier_spi_set_cs;
	552	master->transfer_one = uniphier_spi_transfer_one;
	553	master->prepare_transfer_hardware
	554	= uniphier_spi_prepare_transfer_hardware;
	555	master->unprepare_transfer_hardware
	556	= uniphier_spi_unprepare_transfer_hardware;
11299c5c	557	master->handle_err = uniphier_spi_handle_err;
5ba155a4 KH	558	master->num_chipselect = 1;
	559
	560	ret = devm_spi_register_master(&pdev->dev, master);
	561	if (ret)
	562	goto out_disable_clk;
	563
	564	return 0;
	565
	566	out_disable_clk:
	567	clk_disable_unprepare(priv->clk);
	568
	569	out_master_put:
	570	spi_master_put(master);
	571	return ret;
	572	}
	573
	574	static int uniphier_spi_remove(struct platform_device *pdev)
	575	{
	576	struct uniphier_spi_priv *priv = platform_get_drvdata(pdev);
	577
	578	clk_disable_unprepare(priv->clk);
	579
	580	return 0;
	581	}
	582
	583	static const struct of_device_id uniphier_spi_match[] = {
	584	{ .compatible = "socionext,uniphier-scssi" },
	585	{ /* sentinel */ }
	586	};
	587	MODULE_DEVICE_TABLE(of, uniphier_spi_match);
	588
	589	static struct platform_driver uniphier_spi_driver = {
	590	.probe = uniphier_spi_probe,
	591	.remove = uniphier_spi_remove,
	592	.driver = {
	593	.name = "uniphier-spi",
	594	.of_match_table = uniphier_spi_match,
	595	},
	596	};
	597	module_platform_driver(uniphier_spi_driver);
	598
	599	MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
	600	MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
	601	MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
	602	MODULE_LICENSE("GPL v2");