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8e8e69d6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e8b17b5b MO |
2 | /* |
3 | * SPI bus driver for the Topcliff PCH used by Intel SoCs | |
65308c46 | 4 | * |
2b246283 | 5 | * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
e8b17b5b MO |
6 | */ |
7 | ||
65308c46 | 8 | #include <linux/delay.h> |
e8b17b5b MO |
9 | #include <linux/pci.h> |
10 | #include <linux/wait.h> | |
11 | #include <linux/spi/spi.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/spi/spidev.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
f016aeb6 | 17 | #include <linux/platform_device.h> |
e8b17b5b | 18 | |
c37f3c27 TM |
19 | #include <linux/dmaengine.h> |
20 | #include <linux/pch_dma.h> | |
21 | ||
e8b17b5b MO |
22 | /* Register offsets */ |
23 | #define PCH_SPCR 0x00 /* SPI control register */ | |
24 | #define PCH_SPBRR 0x04 /* SPI baud rate register */ | |
25 | #define PCH_SPSR 0x08 /* SPI status register */ | |
26 | #define PCH_SPDWR 0x0C /* SPI write data register */ | |
27 | #define PCH_SPDRR 0x10 /* SPI read data register */ | |
28 | #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ | |
29 | #define PCH_SRST 0x1C /* SPI reset register */ | |
c37f3c27 | 30 | #define PCH_ADDRESS_SIZE 0x20 |
e8b17b5b MO |
31 | |
32 | #define PCH_SPSR_TFD 0x000007C0 | |
33 | #define PCH_SPSR_RFD 0x0000F800 | |
34 | ||
35 | #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11) | |
36 | #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6) | |
37 | ||
38 | #define PCH_RX_THOLD 7 | |
39 | #define PCH_RX_THOLD_MAX 15 | |
e8b17b5b | 40 | |
f3e03e2e TM |
41 | #define PCH_TX_THOLD 2 |
42 | ||
e8b17b5b MO |
43 | #define PCH_MAX_BAUDRATE 5000000 |
44 | #define PCH_MAX_FIFO_DEPTH 16 | |
45 | ||
46 | #define STATUS_RUNNING 1 | |
47 | #define STATUS_EXITING 2 | |
48 | #define PCH_SLEEP_TIME 10 | |
49 | ||
e8b17b5b | 50 | #define SSN_LOW 0x02U |
8b7aa961 | 51 | #define SSN_HIGH 0x03U |
e8b17b5b MO |
52 | #define SSN_NO_CONTROL 0x00U |
53 | #define PCH_MAX_CS 0xFF | |
54 | #define PCI_DEVICE_ID_GE_SPI 0x8816 | |
55 | ||
56 | #define SPCR_SPE_BIT (1 << 0) | |
57 | #define SPCR_MSTR_BIT (1 << 1) | |
58 | #define SPCR_LSBF_BIT (1 << 4) | |
59 | #define SPCR_CPHA_BIT (1 << 5) | |
60 | #define SPCR_CPOL_BIT (1 << 6) | |
61 | #define SPCR_TFIE_BIT (1 << 8) | |
62 | #define SPCR_RFIE_BIT (1 << 9) | |
63 | #define SPCR_FIE_BIT (1 << 10) | |
64 | #define SPCR_ORIE_BIT (1 << 11) | |
65 | #define SPCR_MDFIE_BIT (1 << 12) | |
66 | #define SPCR_FICLR_BIT (1 << 24) | |
67 | #define SPSR_TFI_BIT (1 << 0) | |
68 | #define SPSR_RFI_BIT (1 << 1) | |
69 | #define SPSR_FI_BIT (1 << 2) | |
c37f3c27 | 70 | #define SPSR_ORF_BIT (1 << 3) |
e8b17b5b MO |
71 | #define SPBRR_SIZE_BIT (1 << 10) |
72 | ||
f016aeb6 TM |
73 | #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\ |
74 | SPCR_ORIE_BIT|SPCR_MDFIE_BIT) | |
65308c46 | 75 | |
e8b17b5b MO |
76 | #define SPCR_RFIC_FIELD 20 |
77 | #define SPCR_TFIC_FIELD 16 | |
78 | ||
c37f3c27 TM |
79 | #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) |
80 | #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) | |
81 | #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) | |
e8b17b5b MO |
82 | |
83 | #define PCH_CLOCK_HZ 50000000 | |
84 | #define PCH_MAX_SPBR 1023 | |
85 | ||
2b246283 | 86 | /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */ |
f016aeb6 | 87 | #define PCI_DEVICE_ID_ML7213_SPI 0x802c |
2e2de2e3 | 88 | #define PCI_DEVICE_ID_ML7223_SPI 0x800F |
92b3a5c1 | 89 | #define PCI_DEVICE_ID_ML7831_SPI 0x8816 |
f016aeb6 TM |
90 | |
91 | /* | |
92 | * Set the number of SPI instance max | |
93 | * Intel EG20T PCH : 1ch | |
2b246283 TM |
94 | * LAPIS Semiconductor ML7213 IOH : 2ch |
95 | * LAPIS Semiconductor ML7223 IOH : 1ch | |
96 | * LAPIS Semiconductor ML7831 IOH : 1ch | |
f016aeb6 TM |
97 | */ |
98 | #define PCH_SPI_MAX_DEV 2 | |
e8b17b5b | 99 | |
c37f3c27 TM |
100 | #define PCH_BUF_SIZE 4096 |
101 | #define PCH_DMA_TRANS_SIZE 12 | |
102 | ||
103 | static int use_dma = 1; | |
104 | ||
105 | struct pch_spi_dma_ctrl { | |
106 | struct dma_async_tx_descriptor *desc_tx; | |
107 | struct dma_async_tx_descriptor *desc_rx; | |
108 | struct pch_dma_slave param_tx; | |
109 | struct pch_dma_slave param_rx; | |
110 | struct dma_chan *chan_tx; | |
111 | struct dma_chan *chan_rx; | |
112 | struct scatterlist *sg_tx_p; | |
113 | struct scatterlist *sg_rx_p; | |
114 | struct scatterlist sg_tx; | |
115 | struct scatterlist sg_rx; | |
116 | int nent; | |
117 | void *tx_buf_virt; | |
118 | void *rx_buf_virt; | |
119 | dma_addr_t tx_buf_dma; | |
120 | dma_addr_t rx_buf_dma; | |
121 | }; | |
e8b17b5b MO |
122 | /** |
123 | * struct pch_spi_data - Holds the SPI channel specific details | |
124 | * @io_remap_addr: The remapped PCI base address | |
125 | * @master: Pointer to the SPI master structure | |
126 | * @work: Reference to work queue handler | |
e8b17b5b MO |
127 | * @wait: Wait queue for waking up upon receiving an |
128 | * interrupt. | |
129 | * @transfer_complete: Status of SPI Transfer | |
130 | * @bcurrent_msg_processing: Status flag for message processing | |
131 | * @lock: Lock for protecting this structure | |
132 | * @queue: SPI Message queue | |
133 | * @status: Status of the SPI driver | |
134 | * @bpw_len: Length of data to be transferred in bits per | |
135 | * word | |
136 | * @transfer_active: Flag showing active transfer | |
137 | * @tx_index: Transmit data count; for bookkeeping during | |
138 | * transfer | |
139 | * @rx_index: Receive data count; for bookkeeping during | |
140 | * transfer | |
141 | * @tx_buff: Buffer for data to be transmitted | |
142 | * @rx_index: Buffer for Received data | |
143 | * @n_curnt_chip: The chip number that this SPI driver currently | |
144 | * operates on | |
145 | * @current_chip: Reference to the current chip that this SPI | |
146 | * driver currently operates on | |
147 | * @current_msg: The current message that this SPI driver is | |
148 | * handling | |
149 | * @cur_trans: The current transfer that this SPI driver is | |
150 | * handling | |
151 | * @board_dat: Reference to the SPI device data structure | |
f016aeb6 TM |
152 | * @plat_dev: platform_device structure |
153 | * @ch: SPI channel number | |
154 | * @irq_reg_sts: Status of IRQ registration | |
e8b17b5b MO |
155 | */ |
156 | struct pch_spi_data { | |
157 | void __iomem *io_remap_addr; | |
c37f3c27 | 158 | unsigned long io_base_addr; |
e8b17b5b MO |
159 | struct spi_master *master; |
160 | struct work_struct work; | |
e8b17b5b MO |
161 | wait_queue_head_t wait; |
162 | u8 transfer_complete; | |
163 | u8 bcurrent_msg_processing; | |
164 | spinlock_t lock; | |
165 | struct list_head queue; | |
166 | u8 status; | |
167 | u32 bpw_len; | |
168 | u8 transfer_active; | |
169 | u32 tx_index; | |
170 | u32 rx_index; | |
171 | u16 *pkt_tx_buff; | |
172 | u16 *pkt_rx_buff; | |
173 | u8 n_curnt_chip; | |
174 | struct spi_device *current_chip; | |
175 | struct spi_message *current_msg; | |
176 | struct spi_transfer *cur_trans; | |
177 | struct pch_spi_board_data *board_dat; | |
f016aeb6 TM |
178 | struct platform_device *plat_dev; |
179 | int ch; | |
c37f3c27 TM |
180 | struct pch_spi_dma_ctrl dma; |
181 | int use_dma; | |
f016aeb6 | 182 | u8 irq_reg_sts; |
7d05b3e8 | 183 | int save_total_len; |
e8b17b5b MO |
184 | }; |
185 | ||
186 | /** | |
187 | * struct pch_spi_board_data - Holds the SPI device specific details | |
188 | * @pdev: Pointer to the PCI device | |
e8b17b5b | 189 | * @suspend_sts: Status of suspend |
f016aeb6 | 190 | * @num: The number of SPI device instance |
e8b17b5b MO |
191 | */ |
192 | struct pch_spi_board_data { | |
193 | struct pci_dev *pdev; | |
e8b17b5b | 194 | u8 suspend_sts; |
f016aeb6 TM |
195 | int num; |
196 | }; | |
197 | ||
198 | struct pch_pd_dev_save { | |
199 | int num; | |
200 | struct platform_device *pd_save[PCH_SPI_MAX_DEV]; | |
201 | struct pch_spi_board_data *board_dat; | |
e8b17b5b MO |
202 | }; |
203 | ||
9a21e477 | 204 | static const struct pci_device_id pch_spi_pcidev_id[] = { |
f016aeb6 TM |
205 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, |
206 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, | |
2e2de2e3 | 207 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, |
92b3a5c1 | 208 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, }, |
f016aeb6 | 209 | { } |
e8b17b5b MO |
210 | }; |
211 | ||
e8b17b5b MO |
212 | /** |
213 | * pch_spi_writereg() - Performs register writes | |
214 | * @master: Pointer to struct spi_master. | |
215 | * @idx: Register offset. | |
216 | * @val: Value to be written to register. | |
217 | */ | |
218 | static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val) | |
219 | { | |
e8b17b5b | 220 | struct pch_spi_data *data = spi_master_get_devdata(master); |
e8b17b5b MO |
221 | iowrite32(val, (data->io_remap_addr + idx)); |
222 | } | |
223 | ||
224 | /** | |
225 | * pch_spi_readreg() - Performs register reads | |
226 | * @master: Pointer to struct spi_master. | |
227 | * @idx: Register offset. | |
228 | */ | |
229 | static inline u32 pch_spi_readreg(struct spi_master *master, int idx) | |
230 | { | |
231 | struct pch_spi_data *data = spi_master_get_devdata(master); | |
e8b17b5b MO |
232 | return ioread32(data->io_remap_addr + idx); |
233 | } | |
234 | ||
e8b17b5b MO |
235 | static inline void pch_spi_setclr_reg(struct spi_master *master, int idx, |
236 | u32 set, u32 clr) | |
237 | { | |
238 | u32 tmp = pch_spi_readreg(master, idx); | |
239 | tmp = (tmp & ~clr) | set; | |
240 | pch_spi_writereg(master, idx, tmp); | |
241 | } | |
242 | ||
e8b17b5b MO |
243 | static void pch_spi_set_master_mode(struct spi_master *master) |
244 | { | |
245 | pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0); | |
246 | } | |
247 | ||
248 | /** | |
249 | * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs | |
250 | * @master: Pointer to struct spi_master. | |
251 | */ | |
252 | static void pch_spi_clear_fifo(struct spi_master *master) | |
253 | { | |
254 | pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0); | |
255 | pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT); | |
256 | } | |
257 | ||
e8b17b5b MO |
258 | static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val, |
259 | void __iomem *io_remap_addr) | |
260 | { | |
261 | u32 n_read, tx_index, rx_index, bpw_len; | |
262 | u16 *pkt_rx_buffer, *pkt_tx_buff; | |
263 | int read_cnt; | |
264 | u32 reg_spcr_val; | |
265 | void __iomem *spsr; | |
266 | void __iomem *spdrr; | |
267 | void __iomem *spdwr; | |
268 | ||
269 | spsr = io_remap_addr + PCH_SPSR; | |
270 | iowrite32(reg_spsr_val, spsr); | |
271 | ||
272 | if (data->transfer_active) { | |
273 | rx_index = data->rx_index; | |
274 | tx_index = data->tx_index; | |
275 | bpw_len = data->bpw_len; | |
276 | pkt_rx_buffer = data->pkt_rx_buff; | |
277 | pkt_tx_buff = data->pkt_tx_buff; | |
278 | ||
279 | spdrr = io_remap_addr + PCH_SPDRR; | |
280 | spdwr = io_remap_addr + PCH_SPDWR; | |
281 | ||
282 | n_read = PCH_READABLE(reg_spsr_val); | |
283 | ||
284 | for (read_cnt = 0; (read_cnt < n_read); read_cnt++) { | |
285 | pkt_rx_buffer[rx_index++] = ioread32(spdrr); | |
286 | if (tx_index < bpw_len) | |
287 | iowrite32(pkt_tx_buff[tx_index++], spdwr); | |
288 | } | |
289 | ||
290 | /* disable RFI if not needed */ | |
291 | if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) { | |
292 | reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR); | |
65308c46 | 293 | reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */ |
e8b17b5b MO |
294 | |
295 | /* reset rx threshold */ | |
c37f3c27 | 296 | reg_spcr_val &= ~MASK_RFIC_SPCR_BITS; |
e8b17b5b | 297 | reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD); |
c37f3c27 TM |
298 | |
299 | iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR)); | |
e8b17b5b MO |
300 | } |
301 | ||
302 | /* update counts */ | |
303 | data->tx_index = tx_index; | |
304 | data->rx_index = rx_index; | |
305 | ||
de3bd7e6 DK |
306 | /* if transfer complete interrupt */ |
307 | if (reg_spsr_val & SPSR_FI_BIT) { | |
308 | if ((tx_index == bpw_len) && (rx_index == tx_index)) { | |
309 | /* disable interrupts */ | |
310 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, | |
311 | PCH_ALL); | |
312 | ||
313 | /* transfer is completed; | |
314 | inform pch_spi_process_messages */ | |
315 | data->transfer_complete = true; | |
316 | data->transfer_active = false; | |
317 | wake_up(&data->wait); | |
318 | } else { | |
342451df | 319 | dev_vdbg(&data->master->dev, |
de3bd7e6 DK |
320 | "%s : Transfer is not completed", |
321 | __func__); | |
322 | } | |
373b0eb6 | 323 | } |
e8b17b5b MO |
324 | } |
325 | } | |
326 | ||
e8b17b5b MO |
327 | /** |
328 | * pch_spi_handler() - Interrupt handler | |
329 | * @irq: The interrupt number. | |
330 | * @dev_id: Pointer to struct pch_spi_board_data. | |
331 | */ | |
332 | static irqreturn_t pch_spi_handler(int irq, void *dev_id) | |
333 | { | |
334 | u32 reg_spsr_val; | |
e8b17b5b MO |
335 | void __iomem *spsr; |
336 | void __iomem *io_remap_addr; | |
337 | irqreturn_t ret = IRQ_NONE; | |
f016aeb6 TM |
338 | struct pch_spi_data *data = dev_id; |
339 | struct pch_spi_board_data *board_dat = data->board_dat; | |
e8b17b5b MO |
340 | |
341 | if (board_dat->suspend_sts) { | |
342 | dev_dbg(&board_dat->pdev->dev, | |
343 | "%s returning due to suspend\n", __func__); | |
344 | return IRQ_NONE; | |
345 | } | |
346 | ||
e8b17b5b MO |
347 | io_remap_addr = data->io_remap_addr; |
348 | spsr = io_remap_addr + PCH_SPSR; | |
349 | ||
350 | reg_spsr_val = ioread32(spsr); | |
351 | ||
25e803f9 TM |
352 | if (reg_spsr_val & SPSR_ORF_BIT) { |
353 | dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__); | |
f5d8ee3f | 354 | if (data->current_msg->complete) { |
25e803f9 TM |
355 | data->transfer_complete = true; |
356 | data->current_msg->status = -EIO; | |
357 | data->current_msg->complete(data->current_msg->context); | |
358 | data->bcurrent_msg_processing = false; | |
359 | data->current_msg = NULL; | |
360 | data->cur_trans = NULL; | |
361 | } | |
362 | } | |
363 | ||
364 | if (data->use_dma) | |
365 | return IRQ_NONE; | |
c37f3c27 | 366 | |
e8b17b5b | 367 | /* Check if the interrupt is for SPI device */ |
e8b17b5b MO |
368 | if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) { |
369 | pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr); | |
370 | ret = IRQ_HANDLED; | |
371 | } | |
372 | ||
373 | dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n", | |
374 | __func__, ret); | |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
379 | /** | |
380 | * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR | |
381 | * @master: Pointer to struct spi_master. | |
382 | * @speed_hz: Baud rate. | |
383 | */ | |
384 | static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz) | |
385 | { | |
65308c46 | 386 | u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2); |
e8b17b5b MO |
387 | |
388 | /* if baud rate is less than we can support limit it */ | |
e8b17b5b MO |
389 | if (n_spbr > PCH_MAX_SPBR) |
390 | n_spbr = PCH_MAX_SPBR; | |
391 | ||
c37f3c27 | 392 | pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS); |
e8b17b5b MO |
393 | } |
394 | ||
395 | /** | |
396 | * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR | |
397 | * @master: Pointer to struct spi_master. | |
398 | * @bits_per_word: Bits per word for SPI transfer. | |
399 | */ | |
400 | static void pch_spi_set_bits_per_word(struct spi_master *master, | |
401 | u8 bits_per_word) | |
402 | { | |
403 | if (bits_per_word == 8) | |
404 | pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT); | |
405 | else | |
406 | pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0); | |
407 | } | |
408 | ||
409 | /** | |
410 | * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer | |
411 | * @spi: Pointer to struct spi_device. | |
412 | */ | |
413 | static void pch_spi_setup_transfer(struct spi_device *spi) | |
414 | { | |
65308c46 | 415 | u32 flags = 0; |
e8b17b5b MO |
416 | |
417 | dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n", | |
418 | __func__, pch_spi_readreg(spi->master, PCH_SPBRR), | |
419 | spi->max_speed_hz); | |
e8b17b5b MO |
420 | pch_spi_set_baud_rate(spi->master, spi->max_speed_hz); |
421 | ||
422 | /* set bits per word */ | |
423 | pch_spi_set_bits_per_word(spi->master, spi->bits_per_word); | |
424 | ||
65308c46 GL |
425 | if (!(spi->mode & SPI_LSB_FIRST)) |
426 | flags |= SPCR_LSBF_BIT; | |
e8b17b5b | 427 | if (spi->mode & SPI_CPOL) |
65308c46 | 428 | flags |= SPCR_CPOL_BIT; |
e8b17b5b | 429 | if (spi->mode & SPI_CPHA) |
65308c46 GL |
430 | flags |= SPCR_CPHA_BIT; |
431 | pch_spi_setclr_reg(spi->master, PCH_SPCR, flags, | |
432 | (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT)); | |
e8b17b5b MO |
433 | |
434 | /* Clear the FIFO by toggling FICLR to 1 and back to 0 */ | |
435 | pch_spi_clear_fifo(spi->master); | |
436 | } | |
437 | ||
e8b17b5b MO |
438 | /** |
439 | * pch_spi_reset() - Clears SPI registers | |
440 | * @master: Pointer to struct spi_master. | |
441 | */ | |
442 | static void pch_spi_reset(struct spi_master *master) | |
443 | { | |
444 | /* write 1 to reset SPI */ | |
445 | pch_spi_writereg(master, PCH_SRST, 0x1); | |
446 | ||
447 | /* clear reset */ | |
448 | pch_spi_writereg(master, PCH_SRST, 0x0); | |
449 | } | |
450 | ||
e8b17b5b MO |
451 | static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) |
452 | { | |
453 | ||
454 | struct spi_transfer *transfer; | |
455 | struct pch_spi_data *data = spi_master_get_devdata(pspi->master); | |
456 | int retval; | |
457 | unsigned long flags; | |
458 | ||
c37f3c27 | 459 | spin_lock_irqsave(&data->lock, flags); |
e8b17b5b MO |
460 | /* validate Tx/Rx buffers and Transfer length */ |
461 | list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { | |
65308c46 | 462 | if (!transfer->tx_buf && !transfer->rx_buf) { |
e8b17b5b MO |
463 | dev_err(&pspi->dev, |
464 | "%s Tx and Rx buffer NULL\n", __func__); | |
465 | retval = -EINVAL; | |
c37f3c27 | 466 | goto err_return_spinlock; |
e8b17b5b MO |
467 | } |
468 | ||
65308c46 | 469 | if (!transfer->len) { |
e8b17b5b MO |
470 | dev_err(&pspi->dev, "%s Transfer length invalid\n", |
471 | __func__); | |
472 | retval = -EINVAL; | |
c37f3c27 | 473 | goto err_return_spinlock; |
e8b17b5b MO |
474 | } |
475 | ||
f6bd03a7 JN |
476 | dev_dbg(&pspi->dev, |
477 | "%s Tx/Rx buffer valid. Transfer length valid\n", | |
478 | __func__); | |
e8b17b5b | 479 | } |
c37f3c27 | 480 | spin_unlock_irqrestore(&data->lock, flags); |
e8b17b5b | 481 | |
65308c46 GL |
482 | /* We won't process any messages if we have been asked to terminate */ |
483 | if (data->status == STATUS_EXITING) { | |
e8b17b5b MO |
484 | dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__); |
485 | retval = -ESHUTDOWN; | |
c37f3c27 | 486 | goto err_out; |
e8b17b5b MO |
487 | } |
488 | ||
489 | /* If suspended ,return -EINVAL */ | |
490 | if (data->board_dat->suspend_sts) { | |
65308c46 | 491 | dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__); |
e8b17b5b | 492 | retval = -EINVAL; |
c37f3c27 | 493 | goto err_out; |
e8b17b5b MO |
494 | } |
495 | ||
496 | /* set status of message */ | |
497 | pmsg->actual_length = 0; | |
e8b17b5b MO |
498 | dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status); |
499 | ||
500 | pmsg->status = -EINPROGRESS; | |
c37f3c27 | 501 | spin_lock_irqsave(&data->lock, flags); |
e8b17b5b MO |
502 | /* add message to queue */ |
503 | list_add_tail(&pmsg->queue, &data->queue); | |
c37f3c27 TM |
504 | spin_unlock_irqrestore(&data->lock, flags); |
505 | ||
e8b17b5b MO |
506 | dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__); |
507 | ||
0d357739 | 508 | schedule_work(&data->work); |
e8b17b5b MO |
509 | dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__); |
510 | ||
511 | retval = 0; | |
512 | ||
e8b17b5b MO |
513 | err_out: |
514 | dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); | |
515 | return retval; | |
c37f3c27 TM |
516 | err_return_spinlock: |
517 | dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); | |
518 | spin_unlock_irqrestore(&data->lock, flags); | |
519 | return retval; | |
e8b17b5b MO |
520 | } |
521 | ||
522 | static inline void pch_spi_select_chip(struct pch_spi_data *data, | |
523 | struct spi_device *pspi) | |
524 | { | |
65308c46 GL |
525 | if (data->current_chip != NULL) { |
526 | if (pspi->chip_select != data->n_curnt_chip) { | |
527 | dev_dbg(&pspi->dev, "%s : different slave\n", __func__); | |
e8b17b5b MO |
528 | data->current_chip = NULL; |
529 | } | |
530 | } | |
531 | ||
532 | data->current_chip = pspi; | |
533 | ||
534 | data->n_curnt_chip = data->current_chip->chip_select; | |
535 | ||
536 | dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__); | |
537 | pch_spi_setup_transfer(pspi); | |
538 | } | |
539 | ||
c37f3c27 | 540 | static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw) |
e8b17b5b | 541 | { |
e8b17b5b MO |
542 | int size; |
543 | u32 n_writes; | |
544 | int j; | |
cd8d984f | 545 | struct spi_message *pmsg, *tmp; |
e8b17b5b MO |
546 | const u8 *tx_buf; |
547 | const u16 *tx_sbuf; | |
548 | ||
e8b17b5b MO |
549 | /* set baud rate if needed */ |
550 | if (data->cur_trans->speed_hz) { | |
65308c46 GL |
551 | dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); |
552 | pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); | |
e8b17b5b MO |
553 | } |
554 | ||
555 | /* set bits per word if needed */ | |
65308c46 GL |
556 | if (data->cur_trans->bits_per_word && |
557 | (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) { | |
558 | dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); | |
e8b17b5b | 559 | pch_spi_set_bits_per_word(data->master, |
65308c46 | 560 | data->cur_trans->bits_per_word); |
e8b17b5b MO |
561 | *bpw = data->cur_trans->bits_per_word; |
562 | } else { | |
563 | *bpw = data->current_msg->spi->bits_per_word; | |
564 | } | |
565 | ||
566 | /* reset Tx/Rx index */ | |
567 | data->tx_index = 0; | |
568 | data->rx_index = 0; | |
569 | ||
570 | data->bpw_len = data->cur_trans->len / (*bpw / 8); | |
e8b17b5b MO |
571 | |
572 | /* find alloc size */ | |
65308c46 GL |
573 | size = data->cur_trans->len * sizeof(*data->pkt_tx_buff); |
574 | ||
e8b17b5b MO |
575 | /* allocate memory for pkt_tx_buff & pkt_rx_buffer */ |
576 | data->pkt_tx_buff = kzalloc(size, GFP_KERNEL); | |
e8b17b5b MO |
577 | if (data->pkt_tx_buff != NULL) { |
578 | data->pkt_rx_buff = kzalloc(size, GFP_KERNEL); | |
65308c46 | 579 | if (!data->pkt_rx_buff) |
e8b17b5b | 580 | kfree(data->pkt_tx_buff); |
e8b17b5b MO |
581 | } |
582 | ||
65308c46 | 583 | if (!data->pkt_rx_buff) { |
e8b17b5b | 584 | /* flush queue and set status of all transfers to -ENOMEM */ |
cd8d984f | 585 | list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { |
e8b17b5b MO |
586 | pmsg->status = -ENOMEM; |
587 | ||
f5d8ee3f | 588 | if (pmsg->complete) |
e8b17b5b MO |
589 | pmsg->complete(pmsg->context); |
590 | ||
591 | /* delete from queue */ | |
592 | list_del_init(&pmsg->queue); | |
593 | } | |
e8b17b5b MO |
594 | return; |
595 | } | |
596 | ||
597 | /* copy Tx Data */ | |
65308c46 | 598 | if (data->cur_trans->tx_buf != NULL) { |
e8b17b5b | 599 | if (*bpw == 8) { |
65308c46 GL |
600 | tx_buf = data->cur_trans->tx_buf; |
601 | for (j = 0; j < data->bpw_len; j++) | |
602 | data->pkt_tx_buff[j] = *tx_buf++; | |
e8b17b5b | 603 | } else { |
65308c46 GL |
604 | tx_sbuf = data->cur_trans->tx_buf; |
605 | for (j = 0; j < data->bpw_len; j++) | |
606 | data->pkt_tx_buff[j] = *tx_sbuf++; | |
e8b17b5b MO |
607 | } |
608 | } | |
609 | ||
610 | /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */ | |
65308c46 GL |
611 | n_writes = data->bpw_len; |
612 | if (n_writes > PCH_MAX_FIFO_DEPTH) | |
e8b17b5b | 613 | n_writes = PCH_MAX_FIFO_DEPTH; |
e8b17b5b | 614 | |
b996356d ME |
615 | dev_dbg(&data->master->dev, |
616 | "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", | |
617 | __func__); | |
e8b17b5b MO |
618 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); |
619 | ||
65308c46 GL |
620 | for (j = 0; j < n_writes; j++) |
621 | pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]); | |
e8b17b5b MO |
622 | |
623 | /* update tx_index */ | |
624 | data->tx_index = j; | |
625 | ||
626 | /* reset transfer complete flag */ | |
627 | data->transfer_complete = false; | |
628 | data->transfer_active = true; | |
629 | } | |
630 | ||
c37f3c27 | 631 | static void pch_spi_nomore_transfer(struct pch_spi_data *data) |
e8b17b5b | 632 | { |
cd8d984f | 633 | struct spi_message *pmsg, *tmp; |
65308c46 | 634 | dev_dbg(&data->master->dev, "%s called\n", __func__); |
e8b17b5b | 635 | /* Invoke complete callback |
65308c46 | 636 | * [To the spi core..indicating end of transfer] */ |
e8b17b5b MO |
637 | data->current_msg->status = 0; |
638 | ||
f5d8ee3f | 639 | if (data->current_msg->complete) { |
e8b17b5b MO |
640 | dev_dbg(&data->master->dev, |
641 | "%s:Invoking callback of SPI core\n", __func__); | |
642 | data->current_msg->complete(data->current_msg->context); | |
643 | } | |
644 | ||
645 | /* update status in global variable */ | |
646 | data->bcurrent_msg_processing = false; | |
647 | ||
648 | dev_dbg(&data->master->dev, | |
649 | "%s:data->bcurrent_msg_processing = false\n", __func__); | |
650 | ||
651 | data->current_msg = NULL; | |
652 | data->cur_trans = NULL; | |
653 | ||
65308c46 GL |
654 | /* check if we have items in list and not suspending |
655 | * return 1 if list empty */ | |
e8b17b5b | 656 | if ((list_empty(&data->queue) == 0) && |
65308c46 GL |
657 | (!data->board_dat->suspend_sts) && |
658 | (data->status != STATUS_EXITING)) { | |
e8b17b5b | 659 | /* We have some more work to do (either there is more tranint |
65308c46 GL |
660 | * bpw;sfer requests in the current message or there are |
661 | *more messages) | |
662 | */ | |
663 | dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__); | |
0d357739 | 664 | schedule_work(&data->work); |
65308c46 GL |
665 | } else if (data->board_dat->suspend_sts || |
666 | data->status == STATUS_EXITING) { | |
e8b17b5b MO |
667 | dev_dbg(&data->master->dev, |
668 | "%s suspend/remove initiated, flushing queue\n", | |
669 | __func__); | |
cd8d984f | 670 | list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { |
e8b17b5b MO |
671 | pmsg->status = -EIO; |
672 | ||
65308c46 | 673 | if (pmsg->complete) |
e8b17b5b MO |
674 | pmsg->complete(pmsg->context); |
675 | ||
676 | /* delete from queue */ | |
677 | list_del_init(&pmsg->queue); | |
678 | } | |
679 | } | |
680 | } | |
681 | ||
682 | static void pch_spi_set_ir(struct pch_spi_data *data) | |
683 | { | |
c37f3c27 TM |
684 | /* enable interrupts, set threshold, enable SPI */ |
685 | if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) | |
77e58efd | 686 | /* set receive threshold to PCH_RX_THOLD */ |
65308c46 | 687 | pch_spi_setclr_reg(data->master, PCH_SPCR, |
c37f3c27 TM |
688 | PCH_RX_THOLD << SPCR_RFIC_FIELD | |
689 | SPCR_FIE_BIT | SPCR_RFIE_BIT | | |
690 | SPCR_ORIE_BIT | SPCR_SPE_BIT, | |
691 | MASK_RFIC_SPCR_BITS | PCH_ALL); | |
692 | else | |
77e58efd | 693 | /* set receive threshold to maximum */ |
65308c46 | 694 | pch_spi_setclr_reg(data->master, PCH_SPCR, |
c37f3c27 TM |
695 | PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD | |
696 | SPCR_FIE_BIT | SPCR_ORIE_BIT | | |
697 | SPCR_SPE_BIT, | |
698 | MASK_RFIC_SPCR_BITS | PCH_ALL); | |
e8b17b5b MO |
699 | |
700 | /* Wait until the transfer completes; go to sleep after | |
701 | initiating the transfer. */ | |
702 | dev_dbg(&data->master->dev, | |
703 | "%s:waiting for transfer to get over\n", __func__); | |
704 | ||
705 | wait_event_interruptible(data->wait, data->transfer_complete); | |
706 | ||
e8b17b5b MO |
707 | /* clear all interrupts */ |
708 | pch_spi_writereg(data->master, PCH_SPSR, | |
65308c46 | 709 | pch_spi_readreg(data->master, PCH_SPSR)); |
c37f3c27 TM |
710 | /* Disable interrupts and SPI transfer */ |
711 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT); | |
712 | /* clear FIFO */ | |
713 | pch_spi_clear_fifo(data->master); | |
e8b17b5b MO |
714 | } |
715 | ||
716 | static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw) | |
717 | { | |
718 | int j; | |
719 | u8 *rx_buf; | |
720 | u16 *rx_sbuf; | |
721 | ||
722 | /* copy Rx Data */ | |
65308c46 | 723 | if (!data->cur_trans->rx_buf) |
e8b17b5b MO |
724 | return; |
725 | ||
726 | if (bpw == 8) { | |
65308c46 GL |
727 | rx_buf = data->cur_trans->rx_buf; |
728 | for (j = 0; j < data->bpw_len; j++) | |
729 | *rx_buf++ = data->pkt_rx_buff[j] & 0xFF; | |
e8b17b5b | 730 | } else { |
65308c46 GL |
731 | rx_sbuf = data->cur_trans->rx_buf; |
732 | for (j = 0; j < data->bpw_len; j++) | |
733 | *rx_sbuf++ = data->pkt_rx_buff[j]; | |
e8b17b5b MO |
734 | } |
735 | } | |
736 | ||
c37f3c27 TM |
737 | static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw) |
738 | { | |
739 | int j; | |
740 | u8 *rx_buf; | |
741 | u16 *rx_sbuf; | |
742 | const u8 *rx_dma_buf; | |
743 | const u16 *rx_dma_sbuf; | |
744 | ||
745 | /* copy Rx Data */ | |
746 | if (!data->cur_trans->rx_buf) | |
747 | return; | |
748 | ||
749 | if (bpw == 8) { | |
750 | rx_buf = data->cur_trans->rx_buf; | |
751 | rx_dma_buf = data->dma.rx_buf_virt; | |
752 | for (j = 0; j < data->bpw_len; j++) | |
753 | *rx_buf++ = *rx_dma_buf++ & 0xFF; | |
7d05b3e8 | 754 | data->cur_trans->rx_buf = rx_buf; |
c37f3c27 TM |
755 | } else { |
756 | rx_sbuf = data->cur_trans->rx_buf; | |
757 | rx_dma_sbuf = data->dma.rx_buf_virt; | |
758 | for (j = 0; j < data->bpw_len; j++) | |
759 | *rx_sbuf++ = *rx_dma_sbuf++; | |
7d05b3e8 | 760 | data->cur_trans->rx_buf = rx_sbuf; |
c37f3c27 TM |
761 | } |
762 | } | |
763 | ||
25e803f9 | 764 | static int pch_spi_start_transfer(struct pch_spi_data *data) |
c37f3c27 TM |
765 | { |
766 | struct pch_spi_dma_ctrl *dma; | |
767 | unsigned long flags; | |
25e803f9 | 768 | int rtn; |
c37f3c27 TM |
769 | |
770 | dma = &data->dma; | |
771 | ||
772 | spin_lock_irqsave(&data->lock, flags); | |
773 | ||
774 | /* disable interrupts, SPI set enable */ | |
775 | pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL); | |
776 | ||
777 | spin_unlock_irqrestore(&data->lock, flags); | |
778 | ||
779 | /* Wait until the transfer completes; go to sleep after | |
780 | initiating the transfer. */ | |
781 | dev_dbg(&data->master->dev, | |
782 | "%s:waiting for transfer to get over\n", __func__); | |
25e803f9 TM |
783 | rtn = wait_event_interruptible_timeout(data->wait, |
784 | data->transfer_complete, | |
785 | msecs_to_jiffies(2 * HZ)); | |
7d05b3e8 TM |
786 | if (!rtn) |
787 | dev_err(&data->master->dev, | |
788 | "%s wait-event timeout\n", __func__); | |
c37f3c27 TM |
789 | |
790 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, | |
791 | DMA_FROM_DEVICE); | |
27504be5 TM |
792 | |
793 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent, | |
794 | DMA_FROM_DEVICE); | |
795 | memset(data->dma.tx_buf_virt, 0, PAGE_SIZE); | |
796 | ||
c37f3c27 TM |
797 | async_tx_ack(dma->desc_rx); |
798 | async_tx_ack(dma->desc_tx); | |
799 | kfree(dma->sg_tx_p); | |
800 | kfree(dma->sg_rx_p); | |
801 | ||
802 | spin_lock_irqsave(&data->lock, flags); | |
c37f3c27 TM |
803 | |
804 | /* clear fifo threshold, disable interrupts, disable SPI transfer */ | |
805 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, | |
806 | MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL | | |
807 | SPCR_SPE_BIT); | |
808 | /* clear all interrupts */ | |
809 | pch_spi_writereg(data->master, PCH_SPSR, | |
810 | pch_spi_readreg(data->master, PCH_SPSR)); | |
811 | /* clear FIFO */ | |
812 | pch_spi_clear_fifo(data->master); | |
813 | ||
814 | spin_unlock_irqrestore(&data->lock, flags); | |
25e803f9 TM |
815 | |
816 | return rtn; | |
c37f3c27 TM |
817 | } |
818 | ||
819 | static void pch_dma_rx_complete(void *arg) | |
820 | { | |
821 | struct pch_spi_data *data = arg; | |
822 | ||
823 | /* transfer is completed;inform pch_spi_process_messages_dma */ | |
824 | data->transfer_complete = true; | |
825 | wake_up_interruptible(&data->wait); | |
826 | } | |
827 | ||
828 | static bool pch_spi_filter(struct dma_chan *chan, void *slave) | |
829 | { | |
830 | struct pch_dma_slave *param = slave; | |
831 | ||
832 | if ((chan->chan_id == param->chan_id) && | |
833 | (param->dma_dev == chan->device->dev)) { | |
834 | chan->private = param; | |
835 | return true; | |
836 | } else { | |
837 | return false; | |
838 | } | |
839 | } | |
840 | ||
841 | static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) | |
842 | { | |
843 | dma_cap_mask_t mask; | |
844 | struct dma_chan *chan; | |
845 | struct pci_dev *dma_dev; | |
846 | struct pch_dma_slave *param; | |
847 | struct pch_spi_dma_ctrl *dma; | |
848 | unsigned int width; | |
849 | ||
850 | if (bpw == 8) | |
851 | width = PCH_DMA_WIDTH_1_BYTE; | |
852 | else | |
853 | width = PCH_DMA_WIDTH_2_BYTES; | |
854 | ||
855 | dma = &data->dma; | |
856 | dma_cap_zero(mask); | |
857 | dma_cap_set(DMA_SLAVE, mask); | |
858 | ||
859 | /* Get DMA's dev information */ | |
a9082105 AS |
860 | dma_dev = pci_get_slot(data->board_dat->pdev->bus, |
861 | PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0)); | |
c37f3c27 TM |
862 | |
863 | /* Set Tx DMA */ | |
864 | param = &dma->param_tx; | |
865 | param->dma_dev = &dma_dev->dev; | |
7611c7a5 | 866 | param->chan_id = data->ch * 2; /* Tx = 0, 2 */; |
c37f3c27 TM |
867 | param->tx_reg = data->io_base_addr + PCH_SPDWR; |
868 | param->width = width; | |
869 | chan = dma_request_channel(mask, pch_spi_filter, param); | |
870 | if (!chan) { | |
871 | dev_err(&data->master->dev, | |
872 | "ERROR: dma_request_channel FAILS(Tx)\n"); | |
873 | data->use_dma = 0; | |
874 | return; | |
875 | } | |
876 | dma->chan_tx = chan; | |
877 | ||
878 | /* Set Rx DMA */ | |
879 | param = &dma->param_rx; | |
880 | param->dma_dev = &dma_dev->dev; | |
7611c7a5 | 881 | param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */; |
c37f3c27 TM |
882 | param->rx_reg = data->io_base_addr + PCH_SPDRR; |
883 | param->width = width; | |
884 | chan = dma_request_channel(mask, pch_spi_filter, param); | |
885 | if (!chan) { | |
886 | dev_err(&data->master->dev, | |
887 | "ERROR: dma_request_channel FAILS(Rx)\n"); | |
888 | dma_release_channel(dma->chan_tx); | |
889 | dma->chan_tx = NULL; | |
890 | data->use_dma = 0; | |
891 | return; | |
892 | } | |
893 | dma->chan_rx = chan; | |
894 | } | |
895 | ||
896 | static void pch_spi_release_dma(struct pch_spi_data *data) | |
897 | { | |
898 | struct pch_spi_dma_ctrl *dma; | |
899 | ||
900 | dma = &data->dma; | |
901 | if (dma->chan_tx) { | |
902 | dma_release_channel(dma->chan_tx); | |
903 | dma->chan_tx = NULL; | |
904 | } | |
905 | if (dma->chan_rx) { | |
906 | dma_release_channel(dma->chan_rx); | |
907 | dma->chan_rx = NULL; | |
908 | } | |
c37f3c27 TM |
909 | } |
910 | ||
911 | static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |
912 | { | |
913 | const u8 *tx_buf; | |
914 | const u16 *tx_sbuf; | |
915 | u8 *tx_dma_buf; | |
916 | u16 *tx_dma_sbuf; | |
917 | struct scatterlist *sg; | |
918 | struct dma_async_tx_descriptor *desc_tx; | |
919 | struct dma_async_tx_descriptor *desc_rx; | |
920 | int num; | |
921 | int i; | |
922 | int size; | |
923 | int rem; | |
7d05b3e8 | 924 | int head; |
c37f3c27 TM |
925 | unsigned long flags; |
926 | struct pch_spi_dma_ctrl *dma; | |
927 | ||
928 | dma = &data->dma; | |
929 | ||
930 | /* set baud rate if needed */ | |
931 | if (data->cur_trans->speed_hz) { | |
932 | dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); | |
933 | spin_lock_irqsave(&data->lock, flags); | |
934 | pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); | |
935 | spin_unlock_irqrestore(&data->lock, flags); | |
936 | } | |
937 | ||
938 | /* set bits per word if needed */ | |
939 | if (data->cur_trans->bits_per_word && | |
940 | (data->current_msg->spi->bits_per_word != | |
941 | data->cur_trans->bits_per_word)) { | |
942 | dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); | |
943 | spin_lock_irqsave(&data->lock, flags); | |
944 | pch_spi_set_bits_per_word(data->master, | |
945 | data->cur_trans->bits_per_word); | |
946 | spin_unlock_irqrestore(&data->lock, flags); | |
947 | *bpw = data->cur_trans->bits_per_word; | |
948 | } else { | |
949 | *bpw = data->current_msg->spi->bits_per_word; | |
950 | } | |
951 | data->bpw_len = data->cur_trans->len / (*bpw / 8); | |
952 | ||
7d05b3e8 TM |
953 | if (data->bpw_len > PCH_BUF_SIZE) { |
954 | data->bpw_len = PCH_BUF_SIZE; | |
955 | data->cur_trans->len -= PCH_BUF_SIZE; | |
956 | } | |
957 | ||
c37f3c27 TM |
958 | /* copy Tx Data */ |
959 | if (data->cur_trans->tx_buf != NULL) { | |
960 | if (*bpw == 8) { | |
961 | tx_buf = data->cur_trans->tx_buf; | |
962 | tx_dma_buf = dma->tx_buf_virt; | |
963 | for (i = 0; i < data->bpw_len; i++) | |
964 | *tx_dma_buf++ = *tx_buf++; | |
965 | } else { | |
966 | tx_sbuf = data->cur_trans->tx_buf; | |
967 | tx_dma_sbuf = dma->tx_buf_virt; | |
968 | for (i = 0; i < data->bpw_len; i++) | |
969 | *tx_dma_sbuf++ = *tx_sbuf++; | |
970 | } | |
971 | } | |
7d05b3e8 TM |
972 | |
973 | /* Calculate Rx parameter for DMA transmitting */ | |
c37f3c27 | 974 | if (data->bpw_len > PCH_DMA_TRANS_SIZE) { |
7d05b3e8 TM |
975 | if (data->bpw_len % PCH_DMA_TRANS_SIZE) { |
976 | num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; | |
977 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE; | |
978 | } else { | |
979 | num = data->bpw_len / PCH_DMA_TRANS_SIZE; | |
980 | rem = PCH_DMA_TRANS_SIZE; | |
981 | } | |
c37f3c27 | 982 | size = PCH_DMA_TRANS_SIZE; |
c37f3c27 TM |
983 | } else { |
984 | num = 1; | |
985 | size = data->bpw_len; | |
986 | rem = data->bpw_len; | |
987 | } | |
988 | dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n", | |
989 | __func__, num, size, rem); | |
990 | spin_lock_irqsave(&data->lock, flags); | |
991 | ||
992 | /* set receive fifo threshold and transmit fifo threshold */ | |
993 | pch_spi_setclr_reg(data->master, PCH_SPCR, | |
994 | ((size - 1) << SPCR_RFIC_FIELD) | | |
f3e03e2e | 995 | (PCH_TX_THOLD << SPCR_TFIC_FIELD), |
c37f3c27 TM |
996 | MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS); |
997 | ||
998 | spin_unlock_irqrestore(&data->lock, flags); | |
999 | ||
1000 | /* RX */ | |
84aa0ba1 | 1001 | dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC); |
e902cdcb Y |
1002 | if (!dma->sg_rx_p) |
1003 | return; | |
1004 | ||
c37f3c27 TM |
1005 | sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ |
1006 | /* offset, length setting */ | |
1007 | sg = dma->sg_rx_p; | |
1008 | for (i = 0; i < num; i++, sg++) { | |
f3e03e2e TM |
1009 | if (i == (num - 2)) { |
1010 | sg->offset = size * i; | |
1011 | sg->offset = sg->offset * (*bpw / 8); | |
c37f3c27 TM |
1012 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem, |
1013 | sg->offset); | |
1014 | sg_dma_len(sg) = rem; | |
f3e03e2e TM |
1015 | } else if (i == (num - 1)) { |
1016 | sg->offset = size * (i - 1) + rem; | |
1017 | sg->offset = sg->offset * (*bpw / 8); | |
1018 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, | |
1019 | sg->offset); | |
1020 | sg_dma_len(sg) = size; | |
c37f3c27 | 1021 | } else { |
f3e03e2e | 1022 | sg->offset = size * i; |
c37f3c27 TM |
1023 | sg->offset = sg->offset * (*bpw / 8); |
1024 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, | |
1025 | sg->offset); | |
1026 | sg_dma_len(sg) = size; | |
1027 | } | |
1028 | sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; | |
1029 | } | |
1030 | sg = dma->sg_rx_p; | |
16052827 | 1031 | desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg, |
a485df4b | 1032 | num, DMA_DEV_TO_MEM, |
c37f3c27 TM |
1033 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1034 | if (!desc_rx) { | |
2857d80a GU |
1035 | dev_err(&data->master->dev, |
1036 | "%s:dmaengine_prep_slave_sg Failed\n", __func__); | |
c37f3c27 TM |
1037 | return; |
1038 | } | |
1039 | dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE); | |
1040 | desc_rx->callback = pch_dma_rx_complete; | |
1041 | desc_rx->callback_param = data; | |
1042 | dma->nent = num; | |
1043 | dma->desc_rx = desc_rx; | |
1044 | ||
7d05b3e8 TM |
1045 | /* Calculate Tx parameter for DMA transmitting */ |
1046 | if (data->bpw_len > PCH_MAX_FIFO_DEPTH) { | |
1047 | head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE; | |
1048 | if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) { | |
1049 | num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; | |
1050 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head; | |
1051 | } else { | |
1052 | num = data->bpw_len / PCH_DMA_TRANS_SIZE; | |
1053 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE + | |
1054 | PCH_DMA_TRANS_SIZE - head; | |
1055 | } | |
f3e03e2e | 1056 | size = PCH_DMA_TRANS_SIZE; |
f3e03e2e TM |
1057 | } else { |
1058 | num = 1; | |
1059 | size = data->bpw_len; | |
1060 | rem = data->bpw_len; | |
7d05b3e8 | 1061 | head = 0; |
f3e03e2e TM |
1062 | } |
1063 | ||
84aa0ba1 | 1064 | dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC); |
e902cdcb Y |
1065 | if (!dma->sg_tx_p) |
1066 | return; | |
1067 | ||
c37f3c27 TM |
1068 | sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ |
1069 | /* offset, length setting */ | |
1070 | sg = dma->sg_tx_p; | |
1071 | for (i = 0; i < num; i++, sg++) { | |
1072 | if (i == 0) { | |
1073 | sg->offset = 0; | |
7d05b3e8 TM |
1074 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head, |
1075 | sg->offset); | |
1076 | sg_dma_len(sg) = size + head; | |
1077 | } else if (i == (num - 1)) { | |
1078 | sg->offset = head + size * i; | |
1079 | sg->offset = sg->offset * (*bpw / 8); | |
c37f3c27 TM |
1080 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, |
1081 | sg->offset); | |
1082 | sg_dma_len(sg) = rem; | |
1083 | } else { | |
7d05b3e8 | 1084 | sg->offset = head + size * i; |
c37f3c27 TM |
1085 | sg->offset = sg->offset * (*bpw / 8); |
1086 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, | |
1087 | sg->offset); | |
1088 | sg_dma_len(sg) = size; | |
1089 | } | |
1090 | sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; | |
1091 | } | |
1092 | sg = dma->sg_tx_p; | |
16052827 | 1093 | desc_tx = dmaengine_prep_slave_sg(dma->chan_tx, |
a485df4b | 1094 | sg, num, DMA_MEM_TO_DEV, |
c37f3c27 TM |
1095 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1096 | if (!desc_tx) { | |
2857d80a GU |
1097 | dev_err(&data->master->dev, |
1098 | "%s:dmaengine_prep_slave_sg Failed\n", __func__); | |
c37f3c27 TM |
1099 | return; |
1100 | } | |
1101 | dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE); | |
1102 | desc_tx->callback = NULL; | |
1103 | desc_tx->callback_param = data; | |
1104 | dma->nent = num; | |
1105 | dma->desc_tx = desc_tx; | |
1106 | ||
c1b20aa5 | 1107 | dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__); |
c37f3c27 TM |
1108 | |
1109 | spin_lock_irqsave(&data->lock, flags); | |
1110 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); | |
1111 | desc_rx->tx_submit(desc_rx); | |
1112 | desc_tx->tx_submit(desc_tx); | |
1113 | spin_unlock_irqrestore(&data->lock, flags); | |
1114 | ||
1115 | /* reset transfer complete flag */ | |
1116 | data->transfer_complete = false; | |
1117 | } | |
e8b17b5b MO |
1118 | |
1119 | static void pch_spi_process_messages(struct work_struct *pwork) | |
1120 | { | |
cd8d984f | 1121 | struct spi_message *pmsg, *tmp; |
65308c46 | 1122 | struct pch_spi_data *data; |
e8b17b5b MO |
1123 | int bpw; |
1124 | ||
65308c46 | 1125 | data = container_of(pwork, struct pch_spi_data, work); |
8e41b527 | 1126 | dev_dbg(&data->master->dev, "%s data initialized\n", __func__); |
e8b17b5b MO |
1127 | |
1128 | spin_lock(&data->lock); | |
e8b17b5b | 1129 | /* check if suspend has been initiated;if yes flush queue */ |
65308c46 | 1130 | if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) { |
f6bd03a7 JN |
1131 | dev_dbg(&data->master->dev, |
1132 | "%s suspend/remove initiated, flushing queue\n", __func__); | |
cd8d984f | 1133 | list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { |
e8b17b5b MO |
1134 | pmsg->status = -EIO; |
1135 | ||
f5d8ee3f | 1136 | if (pmsg->complete) { |
e8b17b5b MO |
1137 | spin_unlock(&data->lock); |
1138 | pmsg->complete(pmsg->context); | |
1139 | spin_lock(&data->lock); | |
1140 | } | |
1141 | ||
1142 | /* delete from queue */ | |
1143 | list_del_init(&pmsg->queue); | |
1144 | } | |
1145 | ||
1146 | spin_unlock(&data->lock); | |
1147 | return; | |
1148 | } | |
1149 | ||
1150 | data->bcurrent_msg_processing = true; | |
1151 | dev_dbg(&data->master->dev, | |
1152 | "%s Set data->bcurrent_msg_processing= true\n", __func__); | |
1153 | ||
1154 | /* Get the message from the queue and delete it from there. */ | |
65308c46 GL |
1155 | data->current_msg = list_entry(data->queue.next, struct spi_message, |
1156 | queue); | |
e8b17b5b MO |
1157 | |
1158 | list_del_init(&data->current_msg->queue); | |
1159 | ||
1160 | data->current_msg->status = 0; | |
1161 | ||
1162 | pch_spi_select_chip(data, data->current_msg->spi); | |
1163 | ||
1164 | spin_unlock(&data->lock); | |
1165 | ||
c37f3c27 TM |
1166 | if (data->use_dma) |
1167 | pch_spi_request_dma(data, | |
1168 | data->current_msg->spi->bits_per_word); | |
8b7aa961 | 1169 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); |
e8b17b5b | 1170 | do { |
7d05b3e8 | 1171 | int cnt; |
e8b17b5b MO |
1172 | /* If we are already processing a message get the next |
1173 | transfer structure from the message otherwise retrieve | |
1174 | the 1st transfer request from the message. */ | |
1175 | spin_lock(&data->lock); | |
e8b17b5b MO |
1176 | if (data->cur_trans == NULL) { |
1177 | data->cur_trans = | |
c37f3c27 TM |
1178 | list_entry(data->current_msg->transfers.next, |
1179 | struct spi_transfer, transfer_list); | |
b996356d ME |
1180 | dev_dbg(&data->master->dev, |
1181 | "%s :Getting 1st transfer message\n", | |
1182 | __func__); | |
e8b17b5b MO |
1183 | } else { |
1184 | data->cur_trans = | |
c37f3c27 TM |
1185 | list_entry(data->cur_trans->transfer_list.next, |
1186 | struct spi_transfer, transfer_list); | |
b996356d ME |
1187 | dev_dbg(&data->master->dev, |
1188 | "%s :Getting next transfer message\n", | |
1189 | __func__); | |
e8b17b5b | 1190 | } |
e8b17b5b MO |
1191 | spin_unlock(&data->lock); |
1192 | ||
7d05b3e8 TM |
1193 | if (!data->cur_trans->len) |
1194 | goto out; | |
1195 | cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1; | |
1196 | data->save_total_len = data->cur_trans->len; | |
c37f3c27 | 1197 | if (data->use_dma) { |
7d05b3e8 TM |
1198 | int i; |
1199 | char *save_rx_buf = data->cur_trans->rx_buf; | |
1200 | for (i = 0; i < cnt; i ++) { | |
1201 | pch_spi_handle_dma(data, &bpw); | |
0f57e168 TM |
1202 | if (!pch_spi_start_transfer(data)) { |
1203 | data->transfer_complete = true; | |
1204 | data->current_msg->status = -EIO; | |
1205 | data->current_msg->complete | |
1206 | (data->current_msg->context); | |
1207 | data->bcurrent_msg_processing = false; | |
1208 | data->current_msg = NULL; | |
1209 | data->cur_trans = NULL; | |
7d05b3e8 | 1210 | goto out; |
0f57e168 | 1211 | } |
7d05b3e8 TM |
1212 | pch_spi_copy_rx_data_for_dma(data, bpw); |
1213 | } | |
1214 | data->cur_trans->rx_buf = save_rx_buf; | |
c37f3c27 TM |
1215 | } else { |
1216 | pch_spi_set_tx(data, &bpw); | |
1217 | pch_spi_set_ir(data); | |
1218 | pch_spi_copy_rx_data(data, bpw); | |
1219 | kfree(data->pkt_rx_buff); | |
1220 | data->pkt_rx_buff = NULL; | |
1221 | kfree(data->pkt_tx_buff); | |
1222 | data->pkt_tx_buff = NULL; | |
1223 | } | |
e8b17b5b | 1224 | /* increment message count */ |
7d05b3e8 | 1225 | data->cur_trans->len = data->save_total_len; |
e8b17b5b MO |
1226 | data->current_msg->actual_length += data->cur_trans->len; |
1227 | ||
1228 | dev_dbg(&data->master->dev, | |
1229 | "%s:data->current_msg->actual_length=%d\n", | |
1230 | __func__, data->current_msg->actual_length); | |
1231 | ||
1232 | /* check for delay */ | |
1233 | if (data->cur_trans->delay_usecs) { | |
b996356d ME |
1234 | dev_dbg(&data->master->dev, "%s:delay in usec=%d\n", |
1235 | __func__, data->cur_trans->delay_usecs); | |
e8b17b5b MO |
1236 | udelay(data->cur_trans->delay_usecs); |
1237 | } | |
1238 | ||
1239 | spin_lock(&data->lock); | |
1240 | ||
1241 | /* No more transfer in this message. */ | |
1242 | if ((data->cur_trans->transfer_list.next) == | |
1243 | &(data->current_msg->transfers)) { | |
c37f3c27 | 1244 | pch_spi_nomore_transfer(data); |
e8b17b5b MO |
1245 | } |
1246 | ||
1247 | spin_unlock(&data->lock); | |
1248 | ||
65308c46 | 1249 | } while (data->cur_trans != NULL); |
c37f3c27 | 1250 | |
25e803f9 | 1251 | out: |
8b7aa961 | 1252 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH); |
c37f3c27 TM |
1253 | if (data->use_dma) |
1254 | pch_spi_release_dma(data); | |
e8b17b5b MO |
1255 | } |
1256 | ||
f016aeb6 TM |
1257 | static void pch_spi_free_resources(struct pch_spi_board_data *board_dat, |
1258 | struct pch_spi_data *data) | |
e8b17b5b MO |
1259 | { |
1260 | dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); | |
1261 | ||
0d357739 | 1262 | flush_work(&data->work); |
e8b17b5b MO |
1263 | } |
1264 | ||
f016aeb6 TM |
1265 | static int pch_spi_get_resources(struct pch_spi_board_data *board_dat, |
1266 | struct pch_spi_data *data) | |
e8b17b5b | 1267 | { |
e8b17b5b MO |
1268 | dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); |
1269 | ||
e8b17b5b | 1270 | /* reset PCH SPI h/w */ |
f016aeb6 | 1271 | pch_spi_reset(data->master); |
e8b17b5b MO |
1272 | dev_dbg(&board_dat->pdev->dev, |
1273 | "%s pch_spi_reset invoked successfully\n", __func__); | |
1274 | ||
65308c46 | 1275 | dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__); |
e8b17b5b | 1276 | |
9677e7dd | 1277 | return 0; |
e8b17b5b MO |
1278 | } |
1279 | ||
c37f3c27 TM |
1280 | static void pch_free_dma_buf(struct pch_spi_board_data *board_dat, |
1281 | struct pch_spi_data *data) | |
1282 | { | |
1283 | struct pch_spi_dma_ctrl *dma; | |
1284 | ||
1285 | dma = &data->dma; | |
1286 | if (dma->tx_buf_dma) | |
1287 | dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, | |
1288 | dma->tx_buf_virt, dma->tx_buf_dma); | |
1289 | if (dma->rx_buf_dma) | |
1290 | dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, | |
1291 | dma->rx_buf_virt, dma->rx_buf_dma); | |
c37f3c27 TM |
1292 | } |
1293 | ||
f37d8e67 | 1294 | static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, |
c37f3c27 TM |
1295 | struct pch_spi_data *data) |
1296 | { | |
1297 | struct pch_spi_dma_ctrl *dma; | |
f37d8e67 | 1298 | int ret; |
c37f3c27 TM |
1299 | |
1300 | dma = &data->dma; | |
f37d8e67 | 1301 | ret = 0; |
c37f3c27 TM |
1302 | /* Get Consistent memory for Tx DMA */ |
1303 | dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, | |
1304 | PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL); | |
f37d8e67 AP |
1305 | if (!dma->tx_buf_virt) |
1306 | ret = -ENOMEM; | |
1307 | ||
c37f3c27 TM |
1308 | /* Get Consistent memory for Rx DMA */ |
1309 | dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, | |
1310 | PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); | |
f37d8e67 AP |
1311 | if (!dma->rx_buf_virt) |
1312 | ret = -ENOMEM; | |
1313 | ||
1314 | return ret; | |
c37f3c27 TM |
1315 | } |
1316 | ||
fd4a319b | 1317 | static int pch_spi_pd_probe(struct platform_device *plat_dev) |
e8b17b5b | 1318 | { |
f016aeb6 | 1319 | int ret; |
e8b17b5b | 1320 | struct spi_master *master; |
f016aeb6 TM |
1321 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); |
1322 | struct pch_spi_data *data; | |
e8b17b5b | 1323 | |
c37f3c27 TM |
1324 | dev_dbg(&plat_dev->dev, "%s:debug\n", __func__); |
1325 | ||
f016aeb6 TM |
1326 | master = spi_alloc_master(&board_dat->pdev->dev, |
1327 | sizeof(struct pch_spi_data)); | |
1328 | if (!master) { | |
1329 | dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n", | |
1330 | plat_dev->id); | |
1331 | return -ENOMEM; | |
e8b17b5b MO |
1332 | } |
1333 | ||
f016aeb6 TM |
1334 | data = spi_master_get_devdata(master); |
1335 | data->master = master; | |
e8b17b5b | 1336 | |
f016aeb6 | 1337 | platform_set_drvdata(plat_dev, data); |
e8b17b5b | 1338 | |
c37f3c27 TM |
1339 | /* baseaddress + address offset) */ |
1340 | data->io_base_addr = pci_resource_start(board_dat->pdev, 1) + | |
1341 | PCH_ADDRESS_SIZE * plat_dev->id; | |
9553821e | 1342 | data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0); |
f016aeb6 TM |
1343 | if (!data->io_remap_addr) { |
1344 | dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__); | |
1345 | ret = -ENOMEM; | |
1346 | goto err_pci_iomap; | |
e8b17b5b | 1347 | } |
9553821e | 1348 | data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id; |
e8b17b5b | 1349 | |
f016aeb6 TM |
1350 | dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n", |
1351 | plat_dev->id, data->io_remap_addr); | |
e8b17b5b MO |
1352 | |
1353 | /* initialize members of SPI master */ | |
e8b17b5b | 1354 | master->num_chipselect = PCH_MAX_CS; |
e8b17b5b | 1355 | master->transfer = pch_spi_transfer; |
f258b44e | 1356 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
24778be2 | 1357 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
fe3a1ad0 | 1358 | master->max_speed_hz = PCH_MAX_BAUDRATE; |
e8b17b5b | 1359 | |
f016aeb6 TM |
1360 | data->board_dat = board_dat; |
1361 | data->plat_dev = plat_dev; | |
1362 | data->n_curnt_chip = 255; | |
1363 | data->status = STATUS_RUNNING; | |
1364 | data->ch = plat_dev->id; | |
c37f3c27 | 1365 | data->use_dma = use_dma; |
e8b17b5b | 1366 | |
f016aeb6 TM |
1367 | INIT_LIST_HEAD(&data->queue); |
1368 | spin_lock_init(&data->lock); | |
1369 | INIT_WORK(&data->work, pch_spi_process_messages); | |
1370 | init_waitqueue_head(&data->wait); | |
65308c46 | 1371 | |
f016aeb6 TM |
1372 | ret = pch_spi_get_resources(board_dat, data); |
1373 | if (ret) { | |
1374 | dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret); | |
e8b17b5b MO |
1375 | goto err_spi_get_resources; |
1376 | } | |
1377 | ||
f016aeb6 TM |
1378 | ret = request_irq(board_dat->pdev->irq, pch_spi_handler, |
1379 | IRQF_SHARED, KBUILD_MODNAME, data); | |
1380 | if (ret) { | |
1381 | dev_err(&plat_dev->dev, | |
1382 | "%s request_irq failed\n", __func__); | |
1383 | goto err_request_irq; | |
1384 | } | |
1385 | data->irq_reg_sts = true; | |
e8b17b5b | 1386 | |
e8b17b5b | 1387 | pch_spi_set_master_mode(master); |
e8b17b5b | 1388 | |
7995d74a AS |
1389 | if (use_dma) { |
1390 | dev_info(&plat_dev->dev, "Use DMA for data transfers\n"); | |
f37d8e67 AP |
1391 | ret = pch_alloc_dma_buf(board_dat, data); |
1392 | if (ret) | |
1393 | goto err_spi_register_master; | |
7995d74a AS |
1394 | } |
1395 | ||
f016aeb6 TM |
1396 | ret = spi_register_master(master); |
1397 | if (ret != 0) { | |
1398 | dev_err(&plat_dev->dev, | |
e8b17b5b | 1399 | "%s spi_register_master FAILED\n", __func__); |
f016aeb6 | 1400 | goto err_spi_register_master; |
e8b17b5b MO |
1401 | } |
1402 | ||
e8b17b5b MO |
1403 | return 0; |
1404 | ||
f016aeb6 | 1405 | err_spi_register_master: |
7995d74a | 1406 | pch_free_dma_buf(board_dat, data); |
e1e57628 | 1407 | free_irq(board_dat->pdev->irq, data); |
f016aeb6 TM |
1408 | err_request_irq: |
1409 | pch_spi_free_resources(board_dat, data); | |
e8b17b5b | 1410 | err_spi_get_resources: |
f016aeb6 TM |
1411 | pci_iounmap(board_dat->pdev, data->io_remap_addr); |
1412 | err_pci_iomap: | |
e8b17b5b | 1413 | spi_master_put(master); |
f016aeb6 TM |
1414 | |
1415 | return ret; | |
e8b17b5b MO |
1416 | } |
1417 | ||
fd4a319b | 1418 | static int pch_spi_pd_remove(struct platform_device *plat_dev) |
e8b17b5b | 1419 | { |
f016aeb6 TM |
1420 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); |
1421 | struct pch_spi_data *data = platform_get_drvdata(plat_dev); | |
65308c46 | 1422 | int count; |
c37f3c27 | 1423 | unsigned long flags; |
e8b17b5b | 1424 | |
f016aeb6 TM |
1425 | dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n", |
1426 | __func__, plat_dev->id, board_dat->pdev->irq); | |
c37f3c27 TM |
1427 | |
1428 | if (use_dma) | |
1429 | pch_free_dma_buf(board_dat, data); | |
1430 | ||
65308c46 GL |
1431 | /* check for any pending messages; no action is taken if the queue |
1432 | * is still full; but at least we tried. Unload anyway */ | |
1433 | count = 500; | |
c37f3c27 | 1434 | spin_lock_irqsave(&data->lock, flags); |
f016aeb6 TM |
1435 | data->status = STATUS_EXITING; |
1436 | while ((list_empty(&data->queue) == 0) && --count) { | |
65308c46 GL |
1437 | dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n", |
1438 | __func__); | |
c37f3c27 | 1439 | spin_unlock_irqrestore(&data->lock, flags); |
65308c46 | 1440 | msleep(PCH_SLEEP_TIME); |
c37f3c27 | 1441 | spin_lock_irqsave(&data->lock, flags); |
e8b17b5b | 1442 | } |
c37f3c27 | 1443 | spin_unlock_irqrestore(&data->lock, flags); |
e8b17b5b | 1444 | |
f016aeb6 TM |
1445 | pch_spi_free_resources(board_dat, data); |
1446 | /* disable interrupts & free IRQ */ | |
1447 | if (data->irq_reg_sts) { | |
1448 | /* disable interrupts */ | |
1449 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); | |
1450 | data->irq_reg_sts = false; | |
1451 | free_irq(board_dat->pdev->irq, data); | |
1452 | } | |
e8b17b5b | 1453 | |
f016aeb6 TM |
1454 | pci_iounmap(board_dat->pdev, data->io_remap_addr); |
1455 | spi_unregister_master(data->master); | |
e8b17b5b | 1456 | |
f016aeb6 | 1457 | return 0; |
e8b17b5b | 1458 | } |
e8b17b5b | 1459 | #ifdef CONFIG_PM |
f016aeb6 TM |
1460 | static int pch_spi_pd_suspend(struct platform_device *pd_dev, |
1461 | pm_message_t state) | |
e8b17b5b MO |
1462 | { |
1463 | u8 count; | |
f016aeb6 TM |
1464 | struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); |
1465 | struct pch_spi_data *data = platform_get_drvdata(pd_dev); | |
e8b17b5b | 1466 | |
f016aeb6 | 1467 | dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__); |
e8b17b5b MO |
1468 | |
1469 | if (!board_dat) { | |
f016aeb6 | 1470 | dev_err(&pd_dev->dev, |
e8b17b5b MO |
1471 | "%s pci_get_drvdata returned NULL\n", __func__); |
1472 | return -EFAULT; | |
1473 | } | |
1474 | ||
e8b17b5b MO |
1475 | /* check if the current message is processed: |
1476 | Only after thats done the transfer will be suspended */ | |
1477 | count = 255; | |
c37f3c27 TM |
1478 | while ((--count) > 0) { |
1479 | if (!(data->bcurrent_msg_processing)) | |
e8b17b5b | 1480 | break; |
e8b17b5b MO |
1481 | msleep(PCH_SLEEP_TIME); |
1482 | } | |
1483 | ||
1484 | /* Free IRQ */ | |
f016aeb6 | 1485 | if (data->irq_reg_sts) { |
e8b17b5b | 1486 | /* disable all interrupts */ |
f016aeb6 TM |
1487 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); |
1488 | pch_spi_reset(data->master); | |
1489 | free_irq(board_dat->pdev->irq, data); | |
e8b17b5b | 1490 | |
f016aeb6 TM |
1491 | data->irq_reg_sts = false; |
1492 | dev_dbg(&pd_dev->dev, | |
e8b17b5b MO |
1493 | "%s free_irq invoked successfully.\n", __func__); |
1494 | } | |
1495 | ||
f016aeb6 TM |
1496 | return 0; |
1497 | } | |
1498 | ||
1499 | static int pch_spi_pd_resume(struct platform_device *pd_dev) | |
1500 | { | |
1501 | struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); | |
1502 | struct pch_spi_data *data = platform_get_drvdata(pd_dev); | |
1503 | int retval; | |
1504 | ||
1505 | if (!board_dat) { | |
1506 | dev_err(&pd_dev->dev, | |
1507 | "%s pci_get_drvdata returned NULL\n", __func__); | |
1508 | return -EFAULT; | |
1509 | } | |
1510 | ||
1511 | if (!data->irq_reg_sts) { | |
1512 | /* register IRQ */ | |
1513 | retval = request_irq(board_dat->pdev->irq, pch_spi_handler, | |
1514 | IRQF_SHARED, KBUILD_MODNAME, data); | |
1515 | if (retval < 0) { | |
1516 | dev_err(&pd_dev->dev, | |
1517 | "%s request_irq failed\n", __func__); | |
1518 | return retval; | |
1519 | } | |
1520 | ||
1521 | /* reset PCH SPI h/w */ | |
1522 | pch_spi_reset(data->master); | |
1523 | pch_spi_set_master_mode(data->master); | |
1524 | data->irq_reg_sts = true; | |
1525 | } | |
1526 | return 0; | |
1527 | } | |
1528 | #else | |
1529 | #define pch_spi_pd_suspend NULL | |
1530 | #define pch_spi_pd_resume NULL | |
1531 | #endif | |
1532 | ||
1533 | static struct platform_driver pch_spi_pd_driver = { | |
1534 | .driver = { | |
1535 | .name = "pch-spi", | |
f016aeb6 TM |
1536 | }, |
1537 | .probe = pch_spi_pd_probe, | |
fd4a319b | 1538 | .remove = pch_spi_pd_remove, |
f016aeb6 TM |
1539 | .suspend = pch_spi_pd_suspend, |
1540 | .resume = pch_spi_pd_resume | |
1541 | }; | |
1542 | ||
b86e81d9 | 1543 | static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
f016aeb6 TM |
1544 | { |
1545 | struct pch_spi_board_data *board_dat; | |
1546 | struct platform_device *pd_dev = NULL; | |
1547 | int retval; | |
1548 | int i; | |
1549 | struct pch_pd_dev_save *pd_dev_save; | |
1550 | ||
baa35f57 | 1551 | pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL); |
fe75cbc1 | 1552 | if (!pd_dev_save) |
f016aeb6 | 1553 | return -ENOMEM; |
f016aeb6 | 1554 | |
baa35f57 | 1555 | board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL); |
f016aeb6 | 1556 | if (!board_dat) { |
f016aeb6 TM |
1557 | retval = -ENOMEM; |
1558 | goto err_no_mem; | |
1559 | } | |
1560 | ||
1561 | retval = pci_request_regions(pdev, KBUILD_MODNAME); | |
1562 | if (retval) { | |
1563 | dev_err(&pdev->dev, "%s request_region failed\n", __func__); | |
1564 | goto pci_request_regions; | |
1565 | } | |
1566 | ||
1567 | board_dat->pdev = pdev; | |
1568 | board_dat->num = id->driver_data; | |
1569 | pd_dev_save->num = id->driver_data; | |
1570 | pd_dev_save->board_dat = board_dat; | |
1571 | ||
1572 | retval = pci_enable_device(pdev); | |
1573 | if (retval) { | |
1574 | dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__); | |
1575 | goto pci_enable_device; | |
1576 | } | |
1577 | ||
1578 | for (i = 0; i < board_dat->num; i++) { | |
1579 | pd_dev = platform_device_alloc("pch-spi", i); | |
1580 | if (!pd_dev) { | |
1581 | dev_err(&pdev->dev, "platform_device_alloc failed\n"); | |
bac902d5 | 1582 | retval = -ENOMEM; |
f016aeb6 TM |
1583 | goto err_platform_device; |
1584 | } | |
1585 | pd_dev_save->pd_save[i] = pd_dev; | |
1586 | pd_dev->dev.parent = &pdev->dev; | |
1587 | ||
1588 | retval = platform_device_add_data(pd_dev, board_dat, | |
1589 | sizeof(*board_dat)); | |
1590 | if (retval) { | |
1591 | dev_err(&pdev->dev, | |
1592 | "platform_device_add_data failed\n"); | |
1593 | platform_device_put(pd_dev); | |
1594 | goto err_platform_device; | |
1595 | } | |
1596 | ||
1597 | retval = platform_device_add(pd_dev); | |
1598 | if (retval) { | |
1599 | dev_err(&pdev->dev, "platform_device_add failed\n"); | |
1600 | platform_device_put(pd_dev); | |
1601 | goto err_platform_device; | |
1602 | } | |
1603 | } | |
1604 | ||
1605 | pci_set_drvdata(pdev, pd_dev_save); | |
1606 | ||
1607 | return 0; | |
1608 | ||
1609 | err_platform_device: | |
b86e81d9 AL |
1610 | while (--i >= 0) |
1611 | platform_device_unregister(pd_dev_save->pd_save[i]); | |
f016aeb6 TM |
1612 | pci_disable_device(pdev); |
1613 | pci_enable_device: | |
1614 | pci_release_regions(pdev); | |
1615 | pci_request_regions: | |
1616 | kfree(board_dat); | |
1617 | err_no_mem: | |
1618 | kfree(pd_dev_save); | |
1619 | ||
1620 | return retval; | |
1621 | } | |
1622 | ||
fd4a319b | 1623 | static void pch_spi_remove(struct pci_dev *pdev) |
f016aeb6 TM |
1624 | { |
1625 | int i; | |
1626 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); | |
1627 | ||
1628 | dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev); | |
1629 | ||
1630 | for (i = 0; i < pd_dev_save->num; i++) | |
1631 | platform_device_unregister(pd_dev_save->pd_save[i]); | |
1632 | ||
1633 | pci_disable_device(pdev); | |
1634 | pci_release_regions(pdev); | |
1635 | kfree(pd_dev_save->board_dat); | |
1636 | kfree(pd_dev_save); | |
1637 | } | |
1638 | ||
1639 | #ifdef CONFIG_PM | |
1640 | static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state) | |
1641 | { | |
1642 | int retval; | |
1643 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); | |
1644 | ||
1645 | dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); | |
1646 | ||
1647 | pd_dev_save->board_dat->suspend_sts = true; | |
1648 | ||
e8b17b5b MO |
1649 | /* save config space */ |
1650 | retval = pci_save_state(pdev); | |
e8b17b5b | 1651 | if (retval == 0) { |
e8b17b5b | 1652 | pci_enable_wake(pdev, PCI_D3hot, 0); |
e8b17b5b | 1653 | pci_disable_device(pdev); |
e8b17b5b | 1654 | pci_set_power_state(pdev, PCI_D3hot); |
e8b17b5b MO |
1655 | } else { |
1656 | dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__); | |
1657 | } | |
1658 | ||
e8b17b5b MO |
1659 | return retval; |
1660 | } | |
1661 | ||
1662 | static int pch_spi_resume(struct pci_dev *pdev) | |
1663 | { | |
1664 | int retval; | |
f016aeb6 | 1665 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); |
e8b17b5b MO |
1666 | dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); |
1667 | ||
e8b17b5b | 1668 | pci_set_power_state(pdev, PCI_D0); |
e8b17b5b MO |
1669 | pci_restore_state(pdev); |
1670 | ||
1671 | retval = pci_enable_device(pdev); | |
1672 | if (retval < 0) { | |
1673 | dev_err(&pdev->dev, | |
1674 | "%s pci_enable_device failed\n", __func__); | |
1675 | } else { | |
e8b17b5b MO |
1676 | pci_enable_wake(pdev, PCI_D3hot, 0); |
1677 | ||
f016aeb6 TM |
1678 | /* set suspend status to false */ |
1679 | pd_dev_save->board_dat->suspend_sts = false; | |
e8b17b5b MO |
1680 | } |
1681 | ||
e8b17b5b MO |
1682 | return retval; |
1683 | } | |
1684 | #else | |
1685 | #define pch_spi_suspend NULL | |
1686 | #define pch_spi_resume NULL | |
1687 | ||
1688 | #endif | |
1689 | ||
c88db233 | 1690 | static struct pci_driver pch_spi_pcidev_driver = { |
e8b17b5b MO |
1691 | .name = "pch_spi", |
1692 | .id_table = pch_spi_pcidev_id, | |
1693 | .probe = pch_spi_probe, | |
fd4a319b | 1694 | .remove = pch_spi_remove, |
e8b17b5b MO |
1695 | .suspend = pch_spi_suspend, |
1696 | .resume = pch_spi_resume, | |
1697 | }; | |
1698 | ||
1699 | static int __init pch_spi_init(void) | |
1700 | { | |
f016aeb6 TM |
1701 | int ret; |
1702 | ret = platform_driver_register(&pch_spi_pd_driver); | |
1703 | if (ret) | |
1704 | return ret; | |
1705 | ||
c88db233 | 1706 | ret = pci_register_driver(&pch_spi_pcidev_driver); |
0113f22e WY |
1707 | if (ret) { |
1708 | platform_driver_unregister(&pch_spi_pd_driver); | |
f016aeb6 | 1709 | return ret; |
0113f22e | 1710 | } |
f016aeb6 TM |
1711 | |
1712 | return 0; | |
e8b17b5b MO |
1713 | } |
1714 | module_init(pch_spi_init); | |
1715 | ||
e8b17b5b MO |
1716 | static void __exit pch_spi_exit(void) |
1717 | { | |
c88db233 | 1718 | pci_unregister_driver(&pch_spi_pcidev_driver); |
f016aeb6 | 1719 | platform_driver_unregister(&pch_spi_pd_driver); |
e8b17b5b MO |
1720 | } |
1721 | module_exit(pch_spi_exit); | |
1722 | ||
c37f3c27 TM |
1723 | module_param(use_dma, int, 0644); |
1724 | MODULE_PARM_DESC(use_dma, | |
1725 | "to use DMA for data transfers pass 1 else 0; default 1"); | |
1726 | ||
e8b17b5b | 1727 | MODULE_LICENSE("GPL"); |
2b246283 | 1728 | MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver"); |
2f1603c6 AS |
1729 | MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id); |
1730 |